break;
 
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra72x_dplls;
        *omap_vcores = &dra722_volts;
                *regs = &ioregs_dra7xx_es1;
                break;
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
                *regs = &ioregs_dra72x_es1;
                break;
 
 
        case DRA722_CONTROL_ID_CODE_ES1_0:
                *omap_si_rev = DRA722_ES1_0;
                break;
+       case DRA722_CONTROL_ID_CODE_ES2_0:
+               *omap_si_rev = DRA722_ES2_0;
+               break;
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
        }
 
                }
                break;
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
                *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
                *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
                break;
        case DRA752_ES1_1:
        case DRA752_ES2_0:
        case DRA722_ES1_0:
+       case DRA722_ES2_0:
                bug_00339_regs_ptr = dra_bug_00339_regs;
                *iterations = sizeof(dra_bug_00339_regs)/
                             sizeof(dra_bug_00339_regs[0]);
 
 #define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
 #define DRA752_CONTROL_ID_CODE_ES2_0           0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0           0x0B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_0           0x1B9BC02F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
 
 #define DRA752_ES1_1   0x07520110
 #define DRA752_ES2_0   0x07520200
 #define DRA722_ES1_0   0x07220100
+#define DRA722_ES2_0   0x07220200
 
 /*
  * SRAM scratch space entries