MX5: Add definitions for SATA controller

Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index e92f10623a92bb6e72c2d4c3e947f58dffcce78b..8f8d01c26e0ca68cfaa39c203e33ae33e82b3407 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -380,6 +380,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        case MXC_FEC_CLK:
                return decode_pll(mxc_plls[PLL1_CLOCK],
                                    CONFIG_SYS_MX5_HCLK);
+       case MXC_SATA_CLK:
+               return get_ahb_clk();
        default:
                break;
        }

diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index ea972a398545169e060924155bded2eebbf19cf5..f9f82f3918f4bbee7fa7a9cb7c9e3164cd68805b 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -32,6 +32,7 @@ enum mxc_clock {
        MXC_UART_CLK,
        MXC_CSPI_CLK,
        MXC_FEC_CLK,
+       MXC_SATA_CLK,
 };
 
 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 07296b5382a2b1b12f88812da9f8a12c20d35229..a4245a3cff3924d3d6f49b6d71b512a520f1d297 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -43,6 +43,7 @@
 #define NFC_BASE_ADDR_AXI       0xF7FF0000
 #define IRAM_BASE_ADDR          0xF8000000
 #define CS1_BASE_ADDR           0xF4000000
+#define SATA_BASE_ADDR         0x10000000
 #else
 #error "CPU_TYPE not defined"
 #endif