No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
/* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
*/
-Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Virtex2,
+ {xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) &fpga_fns,
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
- ret_val = Virtex2_ss_load (desc, buf, bsize);
+ ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
- ret_val = Virtex2_ssm_load (desc, buf, bsize);
+ ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
- ret_val = Virtex2_ss_dump (desc, buf, bsize);
+ ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
- ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+ ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
return ret_val;
}
-int Virtex2_info (Xilinx_desc * desc)
+int virtex2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
__FUNCTION__, __LINE__, fn);
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
return ret_val;
}
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
__FUNCTION__);
#endif
break;
- case Xilinx_Virtex2:
+ case xilinx_virtex2:
#if defined(CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n",
__FUNCTION__);
- ret_val = Virtex2_load (desc, buf, bsize);
+ ret_val = virtex2_load(desc, buf, bsize);
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
__FUNCTION__);
#endif
break;
- case Xilinx_Virtex2:
+ case xilinx_virtex2:
#if defined( CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n",
__FUNCTION__);
- ret_val = Virtex2_dump (desc, buf, bsize);
+ ret_val = virtex2_dump(desc, buf, bsize);
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
case xilinx_spartan3:
printf ("Spartan-III\n");
break;
- case Xilinx_Virtex2:
+ case xilinx_virtex2:
printf ("Virtex-II\n");
break;
case xilinx_zynq:
__FUNCTION__);
#endif
break;
- case Xilinx_Virtex2:
+ case xilinx_virtex2:
#if defined(CONFIG_FPGA_VIRTEX2)
- Virtex2_info (desc);
+ virtex2_info(desc);
#else
/* just in case */
printf ("%s: No support for Virtex-II devices.\n",
#include <xilinx.h>
-extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Virtex2_info(Xilinx_desc *desc);
+int virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
+int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+int virtex2_info(Xilinx_desc *desc);
/*
* Slave SelectMap Implementation function table.
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
-} Xilinx_Virtex2_Slave_SelectMap_fns;
+} xilinx_virtex2_slave_selectmap_fns;
/* Slave Serial Implementation function table */
typedef struct {
Xilinx_clk_fn clk;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
-} Xilinx_Virtex2_Slave_Serial_fns;
+} xilinx_virtex2_slave_serial_fns;
/* Device Image Sizes (in bytes)
*********************************************************************/
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
#endif /* _VIRTEX2_H_ */
min_xilinx_type, /* low range check value */
xilinx_spartan2, /* Spartan-II Family */
Xilinx_VirtexE, /* Virtex-E Family */
- Xilinx_Virtex2, /* Virtex2 Family */
+ xilinx_virtex2, /* Virtex2 Family */
xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
max_xilinx_type /* insert all new types before this */