Merge with /git/u-boot.git

diff --git a/CHANGELOG b/CHANGELOG
index 0211b02ee448d7e68e8d9768de5aa34775a77de9..d3f590ab41c79524c4feca7d2df170cb87f2087d 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Fix external IRQ configuration on Yellowstone & Yosemite
+  Patch by Stefan Roese, 28 Oct 2005
+
 * Add support for multiple PHYs.
   Tested on the following boards:
        cmcpu2      (at91rm9200/ether.c)

diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 4c0ae21ef34a866bfcbcd97cc1efce3d522b3d3f..c2b7cf17737c5af25c687468e3ef6877b5e1d3f4 100644 (file)
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -95,6 +95,11 @@ int board_early_init_f(void)
        out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
        out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
 
+       /* external interrupts IRQ0...3 */
+       out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
+       out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+       out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
 #if 0 /* test-only */
        /*setup USB 2.0 */
        out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 71907400234b198b0a40d43bdc420e4ce5e3edb6..03b412b82f8e631db68968063df7581a3a065a64 100644 (file)
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -95,6 +95,11 @@ int board_early_init_f(void)
        out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
        out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
 
+       /* external interrupts IRQ0...3 */
+       out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
+       out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+       out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
        /*setup USB 2.0 */
        out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
        out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);