--- /dev/null
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o
+SOBJS += lowlevel_init.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * TNETV107X: Asynchronous EMIF Configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
+#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
+
+#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
+#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
+#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
+#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
+#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
+#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
+#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
+#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
+#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
+#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
+
+#define NUM_CS 4
+
+#define set_config_field(reg, field, val) \
+ do { \
+ if (val != -1) { \
+ reg &= ~CONFIG_##field(0xffffffff); \
+ reg |= CONFIG_##field(val); \
+ } \
+ } while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+ unsigned long tmp;
+
+ if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+ tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
+ tmp |= (1 << cs);
+ __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
+
+ } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+ tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
+ tmp |= (1 << cs);
+ __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
+ }
+
+ tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
+
+ set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
+ set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
+ set_config_field(tmp, WR_SETUP, cfg->wr_setup);
+ set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
+ set_config_field(tmp, WR_HOLD, cfg->wr_hold);
+ set_config_field(tmp, RD_SETUP, cfg->rd_setup);
+ set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
+ set_config_field(tmp, RD_HOLD, cfg->rd_hold);
+ set_config_field(tmp, TURN_AROUND, cfg->turn_around);
+ set_config_field(tmp, WIDTH, cfg->width);
+
+ __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+ int cs;
+
+ clk_enable(TNETV107X_LPSC_AEMIF);
+
+ for (cs = 0; cs < num_cs; cs++)
+ configure_async_emif(cs, config + cs);
+}
--- /dev/null
+/*
+ * TNETV107X: Clock management APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+
+#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
+#define PSC_BASE TNETV107X_PSC_BASE
+
+#define BIT(x) (1 << (x))
+
+#define MAX_PREDIV 64
+#define MAX_POSTDIV 8
+#define MAX_MULT 512
+#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
+
+/* LPSC registers */
+#define PSC_PTCMD 0x120
+#define PSC_PTSTAT 0x128
+#define PSC_MDSTAT(n) (0x800 + (n) * 4)
+#define PSC_MDCTL(n) (0xA00 + (n) * 4)
+
+#define PSC_MDCTL_LRSTZ BIT(8)
+
+#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
+#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
+
+/* SSPLL registers */
+struct sspll_regs {
+ u32 modes;
+ u32 postdiv;
+ u32 prediv;
+ u32 mult_factor;
+ u32 divider_range;
+ u32 bw_divider;
+ u32 spr_amount;
+ u32 spr_rate_div;
+ u32 diag;
+};
+
+/* SSPLL base addresses */
+static struct sspll_regs *sspll_regs[] = {
+ (struct sspll_regs *)(CLOCK_BASE + 0x040),
+ (struct sspll_regs *)(CLOCK_BASE + 0x080),
+ (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
+};
+
+#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
+#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
+#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
+
+
+/* PLL Control Registers */
+struct pllctl_regs {
+ u32 ctl; /* 00 */
+ u32 ocsel; /* 04 */
+ u32 secctl; /* 08 */
+ u32 __pad0;
+ u32 mult; /* 10 */
+ u32 prediv; /* 14 */
+ u32 div1; /* 18 */
+ u32 div2; /* 1c */
+ u32 div3; /* 20 */
+ u32 oscdiv1; /* 24 */
+ u32 postdiv; /* 28 */
+ u32 bpdiv; /* 2c */
+ u32 wakeup; /* 30 */
+ u32 __pad1;
+ u32 cmd; /* 38 */
+ u32 stat; /* 3c */
+ u32 alnctl; /* 40 */
+ u32 dchange; /* 44 */
+ u32 cken; /* 48 */
+ u32 ckstat; /* 4c */
+ u32 systat; /* 50 */
+ u32 ckctl; /* 54 */
+ u32 __pad2[2];
+ u32 div4; /* 60 */
+ u32 div5; /* 64 */
+ u32 div6; /* 68 */
+ u32 div7; /* 6c */
+ u32 div8; /* 70 */
+};
+
+struct lpsc_map {
+ int pll, div;
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+ (struct pllctl_regs *)(CLOCK_BASE + 0x700),
+ (struct pllctl_regs *)(CLOCK_BASE + 0x300),
+ (struct pllctl_regs *)(CLOCK_BASE + 0x500),
+};
+
+#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val) \
+ pllctl_reg_write(pll, reg, \
+ (pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, mask, 0)
+
+/* PLLCTL Bits */
+#define PLLCTL_CLKMODE BIT(8)
+#define PLLCTL_PLLSELB BIT(7)
+#define PLLCTL_PLLENSRC BIT(5)
+#define PLLCTL_PLLDIS BIT(4)
+#define PLLCTL_PLLRST BIT(3)
+#define PLLCTL_PLLPWRDN BIT(1)
+#define PLLCTL_PLLEN BIT(0)
+
+#define PLLDIV_ENABLE BIT(15)
+
+static int pll_div_offset[] = {
+#define div_offset(reg) offsetof(struct pllctl_regs, reg)
+ div_offset(div1), div_offset(div2), div_offset(div3),
+ div_offset(div4), div_offset(div5), div_offset(div6),
+ div_offset(div7), div_offset(div8),
+};
+
+static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
+static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
+
+/* Mappings from PLL+DIV to subsystem clocks */
+#define sys_arm1176_clk {SYS_PLL, 0}
+#define sys_dsp_clk {SYS_PLL, 1}
+#define sys_ddr_clk {SYS_PLL, 2}
+#define sys_full_clk {SYS_PLL, 3}
+#define sys_lcd_clk {SYS_PLL, 4}
+#define sys_vlynq_ref_clk {SYS_PLL, 5}
+#define sys_tsc_clk {SYS_PLL, 6}
+#define sys_half_clk {SYS_PLL, 7}
+
+#define eth_clk_5 {ETH_PLL, 0}
+#define eth_clk_50 {ETH_PLL, 1}
+#define eth_clk_125 {ETH_PLL, 2}
+#define eth_clk_250 {ETH_PLL, 3}
+#define eth_clk_25 {ETH_PLL, 4}
+
+#define tdm_clk {TDM_PLL, 0}
+#define tdm_extra_clk {TDM_PLL, 1}
+#define tdm1_clk {TDM_PLL, 2}
+
+/* Optimization barrier */
+#define barrier() \
+ __asm__ __volatile__("mov r0, r0\n" : : : "memory");
+
+static const struct lpsc_map lpsc_clk_map[] = {
+ [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
+ [TNETV107X_LPSC_GEM] = sys_dsp_clk,
+ [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
+ [TNETV107X_LPSC_TPCC] = sys_full_clk,
+ [TNETV107X_LPSC_TPTC0] = sys_full_clk,
+ [TNETV107X_LPSC_TPTC1] = sys_full_clk,
+ [TNETV107X_LPSC_RAM] = sys_full_clk,
+ [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
+ [TNETV107X_LPSC_LCD] = sys_lcd_clk,
+ [TNETV107X_LPSC_ETHSS] = eth_clk_125,
+ [TNETV107X_LPSC_AEMIF] = sys_full_clk,
+ [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
+ [TNETV107X_LPSC_TSC] = sys_tsc_clk,
+ [TNETV107X_LPSC_ROM] = sys_half_clk,
+ [TNETV107X_LPSC_UART2] = sys_half_clk,
+ [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
+ [TNETV107X_LPSC_SECCTL] = sys_half_clk,
+ [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
+ [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
+ [TNETV107X_LPSC_GPIO] = sys_half_clk,
+ [TNETV107X_LPSC_MDIO] = sys_half_clk,
+ [TNETV107X_LPSC_SDIO0] = sys_half_clk,
+ [TNETV107X_LPSC_UART0] = sys_half_clk,
+ [TNETV107X_LPSC_UART1] = sys_half_clk,
+ [TNETV107X_LPSC_TIMER0] = sys_half_clk,
+ [TNETV107X_LPSC_TIMER1] = sys_half_clk,
+ [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
+ [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
+ [TNETV107X_LPSC_SSP] = sys_half_clk,
+ [TNETV107X_LPSC_TDM0] = tdm_clk,
+ [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
+ [TNETV107X_LPSC_MCDMA] = sys_half_clk,
+ [TNETV107X_LPSC_USB0] = sys_half_clk,
+ [TNETV107X_LPSC_TDM1] = tdm1_clk,
+ [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
+ [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
+ [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
+ [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
+ [TNETV107X_LPSC_SPARE] = sys_half_clk,
+ [TNETV107X_LPSC_SDIO1] = sys_half_clk,
+ [TNETV107X_LPSC_USB1] = sys_half_clk,
+ [TNETV107X_LPSC_USBSS] = sys_half_clk,
+ [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
+ [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
+};
+
+static const unsigned long pll_ext_freq[] = {
+ [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
+ [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
+ [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
+};
+
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, postdiv = 1;
+ unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
+ unsigned long ret;
+ u32 bypass;
+
+ bypass = __raw_readl((u32 *)(CLOCK_BASE));
+ if (!(bypass & pll_bypass_mask[pll])) {
+ mult = sspll_reg_read(pll, mult_factor);
+ prediv = sspll_reg_read(pll, prediv) + 1;
+ postdiv = sspll_reg_read(pll, postdiv) + 1;
+ }
+
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
+ ref = pll_ext_freq[pll];
+
+ if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
+ return ref;
+
+ ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
+ ret /= (prediv * postdiv);
+
+ return ret;
+}
+
+static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
+ int div)
+{
+ int divider = 1;
+ unsigned long divreg;
+
+ divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
+
+ if (divreg & PLLDIV_ENABLE)
+ divider = (divreg & pll_div_mask[pll]) + 1;
+
+ return fpll / divider;
+}
+
+static unsigned long pll_div_freq_get(int pll, int div)
+{
+ unsigned int fpll = pll_freq_get(pll);
+
+ return __pll_div_freq_get(pll, fpll, div);
+}
+
+static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
+ unsigned long hz)
+{
+ int divider = (fpll / hz - 1);
+
+ divider &= pll_div_mask[pll];
+ divider |= PLLDIV_ENABLE;
+
+ __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
+ pllctl_reg_setbits(pll, alnctl, (1 << div));
+ pllctl_reg_setbits(pll, dchange, (1 << div));
+}
+
+static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
+{
+ unsigned int fpll = pll_freq_get(pll);
+
+ __pll_div_freq_set(pll, fpll, div, hz);
+
+ pllctl_reg_write(pll, cmd, 1);
+
+ /* Wait until new divider takes effect */
+ while (pllctl_reg_read(pll, stat) & 0x01);
+
+ return __pll_div_freq_get(pll, fpll, div);
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
+}
+
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
+{
+ unsigned long fpll, divider, pll;
+
+ pll = lpsc_clk_map[clk].pll;
+ fpll = pll_freq_get(pll);
+ divider = (fpll / hz - 1);
+ divider &= pll_div_mask[pll];
+
+ return fpll / (divider + 1);
+}
+
+int clk_set_rate(unsigned int clk, unsigned long _hz)
+{
+ unsigned long hz;
+
+ hz = clk_round_rate(clk, _hz);
+ if (hz != _hz)
+ return -EINVAL; /* Cannot set to target freq */
+
+ pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
+ return 0;
+}
+
+void lpsc_control(int mod, unsigned long state, int lrstz)
+{
+ u32 mdctl;
+
+ mdctl = psc_reg_read(PSC_MDCTL(mod));
+ mdctl &= ~0x1f;
+ mdctl |= state;
+
+ if (lrstz == 0)
+ mdctl &= ~PSC_MDCTL_LRSTZ;
+ else if (lrstz == 1)
+ mdctl |= PSC_MDCTL_LRSTZ;
+
+ psc_reg_write(PSC_MDCTL(mod), mdctl);
+
+ psc_reg_write(PSC_PTCMD, 1);
+
+ /* wait for power domain transition to end */
+ while (psc_reg_read(PSC_PTSTAT) & 1);
+
+ /* Wait for module state change */
+ while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
+}
+
+int lpsc_status(unsigned int id)
+{
+ return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
+}
+
+static void init_pll(const struct pll_init_data *data)
+{
+ unsigned long fpll;
+ unsigned long best_pre = 0, best_post = 0, best_mult = 0;
+ unsigned long div, prediv, postdiv, mult;
+ unsigned long delta, actual;
+ long best_delta = -1;
+ int i;
+ u32 tmp;
+
+ if (data->pll == SYS_PLL)
+ return; /* cannot reconfigure system pll on the fly */
+
+ tmp = pllctl_reg_read(data->pll, ctl);
+ if (data->internal_osc) {
+ tmp &= ~PLLCTL_CLKMODE;
+ fpll = CONFIG_SYS_INT_OSC_FREQ;
+ } else {
+ tmp |= PLLCTL_CLKMODE;
+ fpll = pll_ext_freq[data->pll];
+ }
+ pllctl_reg_write(data->pll, ctl, tmp);
+
+ mult = data->pll_freq / fpll;
+ for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+ div = (fpll * mult) / data->pll_freq;
+ if (div < 1 || div > MAX_DIV)
+ continue;
+
+ for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
+ prediv = div / postdiv;
+ if (prediv < 1 || prediv > MAX_PREDIV)
+ continue;
+
+ actual = (fpll / prediv) * (mult / postdiv);
+ delta = (actual - data->pll_freq);
+ if (delta < 0)
+ delta = -delta;
+ if ((delta < best_delta) || (best_delta == -1)) {
+ best_delta = delta;
+ best_mult = mult;
+ best_pre = prediv;
+ best_post = postdiv;
+ if (delta == 0)
+ goto done;
+ }
+ }
+ }
+done:
+
+ if (best_delta == -1) {
+ printf("pll cannot derive %lu from %lu\n",
+ data->pll_freq, fpll);
+ return;
+ }
+
+ fpll = fpll * best_mult;
+ fpll /= best_pre * best_post;
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
+
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
+
+ sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
+ sspll_reg_write(data->pll, prediv, best_pre - 1);
+ sspll_reg_write(data->pll, postdiv, best_post - 1);
+
+ for (i = 0; i < 10; i++)
+ if (data->div_freq[i])
+ __pll_div_freq_set(data->pll, fpll, i,
+ data->div_freq[i]);
+
+ pllctl_reg_write(data->pll, cmd, 1);
+
+ /* Wait until pll "go" operation completes */
+ while (pllctl_reg_read(data->pll, stat) & 0x01);
+
+ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+ int i;
+
+ for (i = 0; i < num_pll; i++)
+ init_pll(&config[i]);
+}
--- /dev/null
+/*
+ * TNETV107X: Architecture initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void chip_configuration_unlock(void)
+{
+ __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
+ __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+ icache_enable();
+ chip_configuration_unlock();
+
+ return 0;
+}
--- /dev/null
+/*
+ * TNETV107X: Low-level pre-relocation initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* nothing for now, maybe needed for more exotic boot modes */
+ mov pc, lr
--- /dev/null
+/*
+ * TNETV107X: Pinmux configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define MUX_MODE_1 0x00
+#define MUX_MODE_2 0x04
+#define MUX_MODE_3 0x0c
+#define MUX_MODE_4 0x1c
+
+#define MUX_DEBUG 0
+
+static const struct pin_config pin_table[] = {
+ /* reg shift mode */
+ TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
+ TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
+ TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
+ TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
+ TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
+ TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
+ TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
+ TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
+ TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
+ TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
+ TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
+ TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
+ TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
+ TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
+ TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
+ TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
+ TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
+ TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
+ TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
+ TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
+ TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
+ TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
+ TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
+ TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
+ TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
+ TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
+ TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
+ TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
+ TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
+ TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
+ TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
+ TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
+ TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
+ TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
+ TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
+ TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
+ TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
+ TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
+ TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
+ TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
+ TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
+ TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
+ TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
+ TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
+ TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
+ TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
+ TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
+ TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
+ TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
+ TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
+ TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
+ TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
+ TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
+ TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
+ TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
+ TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
+ TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
+ TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
+ TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
+ TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
+ TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
+ TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
+ TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
+};
+
+const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
+
+int mux_select_pin(short index)
+{
+ const struct pin_config *cfg;
+ unsigned long mask, mode, reg;
+
+ if (index >= pin_table_size)
+ return 0;
+
+ cfg = &pin_table[index];
+
+ mask = 0x1f << cfg->mask_offset;
+ mode = cfg->mode << cfg->mask_offset;
+
+ reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
+ reg = (reg & ~mask) | mode;
+ __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
+
+ return 1;
+}
+
+int mux_select_pins(const short *pins)
+{
+ int i, ret = 1;
+
+ for (i = 0; pins[i] >= 0; i++)
+ ret &= mux_select_pin(pins[i]);
+
+ return ret;
+}
--- /dev/null
+/*
+ * TNETV107X: Timer implementation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+struct timer_regs {
+ u_int32_t pid12;
+ u_int32_t pad[3];
+ u_int32_t tim12;
+ u_int32_t tim34;
+ u_int32_t prd12;
+ u_int32_t prd34;
+ u_int32_t tcr;
+ u_int32_t tgcr;
+ u_int32_t wdtcr;
+};
+
+#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
+
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define TIM_CLK_DIV 16
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init(void)
+{
+ clk_enable(TNETV107X_LPSC_TIMER0);
+
+ lastinc = timestamp = 0;
+
+ /* We are using timer34 in unchained 32-bit mode, full speed */
+ __raw_writel(0x0, ®s->tcr);
+ __raw_writel(0x0, ®s->tgcr);
+ __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), ®s->tgcr);
+ __raw_writel(0x0, ®s->tim34);
+ __raw_writel(TIMER_LOAD_VAL, ®s->prd34);
+ __raw_writel(2 << 22, ®s->tcr);
+
+ return 0;
+}
+
+void reset_timer(void)
+{
+ lastinc = timestamp = 0;
+
+ __raw_writel(0, ®s->tcr);
+ __raw_writel(0, ®s->tim34);
+ __raw_writel(2 << 22, ®s->tcr);
+}
+
+static ulong get_timer_raw(void)
+{
+ ulong now = __raw_readl(®s->tim34);
+
+ if (now >= lastinc)
+ timestamp += now - lastinc;
+ else
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
+
+ lastinc = now;
+
+ return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+ return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+ tmo *= usec;
+ tmo /= (1000 * TIM_CLK_DIV);
+
+ endtime = get_timer_raw() + tmo;
+
+ do {
+ ulong now = get_timer_raw();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--- /dev/null
+/*
+ * TNETV107X: Watchdog timer implementation (for reset)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define MAX_DIV 0xFFFE0001
+
+struct wdt_regs {
+ u32 kick_lock;
+#define KICK_LOCK_1 0x5555
+#define KICK_LOCK_2 0xaaaa
+ u32 kick;
+
+ u32 change_lock;
+#define CHANGE_LOCK_1 0x6666
+#define CHANGE_LOCK_2 0xbbbb
+ u32 change;
+
+ u32 disable_lock;
+#define DISABLE_LOCK_1 0x7777
+#define DISABLE_LOCK_2 0xcccc
+#define DISABLE_LOCK_3 0xdddd
+ u32 disable;
+
+ u32 prescale_lock;
+#define PRESCALE_LOCK_1 0x5a5a
+#define PRESCALE_LOCK_2 0xa5a5
+ u32 prescale;
+};
+
+static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
+
+#define wdt_reg_read(reg) __raw_readl(®s->reg)
+#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg)
+
+static int write_prescale_reg(unsigned long prescale_value)
+{
+ wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
+ if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
+ if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(prescale, prescale_value);
+
+ return 0;
+}
+
+static int write_change_reg(unsigned long initial_timer_value)
+{
+ wdt_reg_write(change_lock, CHANGE_LOCK_1);
+ if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(change_lock, CHANGE_LOCK_2);
+ if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(change, initial_timer_value);
+
+ return 0;
+}
+
+static int wdt_control(unsigned long disable_value)
+{
+ wdt_reg_write(disable_lock, DISABLE_LOCK_1);
+ if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(disable_lock, DISABLE_LOCK_2);
+ if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
+ return -1;
+
+ wdt_reg_write(disable_lock, DISABLE_LOCK_3);
+ if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(disable, disable_value);
+ return 0;
+}
+
+static int wdt_set_period(unsigned long msec)
+{
+ unsigned long change_value, count_value;
+ unsigned long prescale_value = 1;
+ unsigned long refclk_khz, maxdiv;
+ int ret;
+
+ refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
+ maxdiv = (MAX_DIV / refclk_khz);
+
+ if ((!msec) || (msec > maxdiv))
+ return -1;
+
+ count_value = refclk_khz * msec;
+ if (count_value > 0xffff) {
+ change_value = count_value / 0xffff + 1;
+ prescale_value = count_value / change_value;
+ } else {
+ change_value = count_value;
+ }
+
+ ret = write_prescale_reg(prescale_value - 1);
+ if (ret)
+ return ret;
+
+ ret = write_change_reg(change_value);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+unsigned long last_wdt = -1;
+
+int wdt_start(unsigned long msecs)
+{
+ int ret;
+ ret = wdt_control(0);
+ if (ret)
+ return ret;
+ ret = wdt_set_period(msecs);
+ if (ret)
+ return ret;
+ ret = wdt_control(1);
+ if (ret)
+ return ret;
+ ret = wdt_kick();
+ last_wdt = msecs;
+ return ret;
+}
+
+int wdt_stop(void)
+{
+ last_wdt = -1;
+ return wdt_control(0);
+}
+
+int wdt_kick(void)
+{
+ wdt_reg_write(kick_lock, KICK_LOCK_1);
+ if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(kick_lock, KICK_LOCK_2);
+ if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(kick, 1);
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ clk_enable(TNETV107X_LPSC_WDT_ARM);
+ wdt_start(1);
+ wdt_kick();
+}
--- /dev/null
+/*
+ * TNETV107X: Clock APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
+#define PSC_MDCTL_NEXT_SYNCRST 0x1
+#define PSC_MDCTL_NEXT_DISABLE 0x2
+#define PSC_MDCTL_NEXT_ENABLE 0x3
+
+#define CONFIG_SYS_INT_OSC_FREQ 24000000
+
+#ifndef __ASSEMBLY__
+
+/* PLL identifiers */
+enum pll_type_e {
+ SYS_PLL,
+ TDM_PLL,
+ ETH_PLL
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+ int pll;
+ int internal_osc;
+ unsigned long pll_freq;
+ unsigned long div_freq[10];
+};
+
+void init_plls(int num_pll, struct pll_init_data *config);
+int lpsc_status(unsigned int mod);
+void lpsc_control(int mod, unsigned long state, int lrstz);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+static inline void clk_enable(unsigned int mod)
+{
+ lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
+}
+
+static inline void clk_disable(unsigned int mod)
+{
+ lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
+}
+
+#endif
+
+#endif
--- /dev/null
+#include <asm/arch-davinci/emif_defs.h>
--- /dev/null
+/*
+ * TNETV107X: Hardware information
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sizes.h>
+
+#define ASYNC_EMIF_NUM_CS 4
+#define ASYNC_EMIF_MODE_NOR 0
+#define ASYNC_EMIF_MODE_NAND 1
+#define ASYNC_EMIF_MODE_ONENAND 2
+#define ASYNC_EMIF_PRESERVE -1
+
+struct async_emif_config {
+ unsigned mode;
+ unsigned select_strobe;
+ unsigned extend_wait;
+ unsigned wr_setup;
+ unsigned wr_strobe;
+ unsigned wr_hold;
+ unsigned rd_setup;
+ unsigned rd_strobe;
+ unsigned rd_hold;
+ unsigned turn_around;
+ enum {
+ ASYNC_EMIF_8 = 0,
+ ASYNC_EMIF_16 = 1,
+ ASYNC_EMIF_32 = 2,
+ } width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+int wdt_start(unsigned long msecs);
+int wdt_stop(void);
+int wdt_kick(void);
+
+#endif
+
+/* Chip configuration unlock codes and registers */
+#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
+#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
+#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
+#define TNETV107X_KICK0_MAGIC 0x83e70b13
+#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
+
+/* Module base addresses */
+#define TNETV107X_TPCC_BASE 0x01C00000
+#define TNETV107X_TPTC0_BASE 0x01C10000
+#define TNETV107X_TPTC1_BASE 0x01C10400
+#define TNETV107X_INTC_BASE 0x03000000
+#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
+#define TNETV107X_INTD_BASE 0x08038000
+#define TNETV107X_INTD_IPC_BASE 0x08038000
+#define TNETV107X_INTD_FAST_BASE 0x08039000
+#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
+#define TNETV107X_INTD_SLOW_BASE 0x0803B000
+#define TNETV107X_PKA_BASE 0x08040000
+#define TNETV107X_RNG_BASE 0x08044000
+#define TNETV107X_TIMER0_BASE 0x08086500
+#define TNETV107X_TIMER1_BASE 0x08086600
+#define TNETV107X_WDT0_ARM_BASE 0x08086700
+#define TNETV107X_WDT1_DSP_BASE 0x08086800
+#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
+#define TNETV107X_GPIO_BASE 0x08088000
+#define TNETV107X_UART1_BASE 0x08088400
+#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
+#define TNETV107X_SDIO0_BASE 0x08088700
+#define TNETV107X_SDIO1_BASE 0x08088800
+#define TNETV107X_MDIO_BASE 0x08088900
+#define TNETV107X_KEYPAD_BASE 0x08088A00
+#define TNETV107X_SSP_BASE 0x08088C00
+#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
+#define TNETV107X_PSC_BASE 0x0808B000
+#define TNETV107X_TDM0_BASE 0x08100000
+#define TNETV107X_TDM1_BASE 0x08100100
+#define TNETV107X_MCDMA_BASE 0x08108000
+#define TNETV107X_UART0_DMA_BASE 0x08108200
+#define TNETV107X_USBSS_BASE 0x08120000
+#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
+#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
+#define TNETV107X_IMCOP_BASE 0x01CC0000
+#define TNETV107X_MBX_LITE_BASE 0x07000000
+#define TNETV107X_ETHSS_BASE 0x0803C000
+#define TNETV107X_CPSW_BASE 0x0803C000
+#define TNETV107X_SPF_BASE 0x0803C800
+#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
+#define TNETV107X_VTP_CNTRL_0 0x0803D800
+#define TNETV107X_VTP_CNTRL_1 0x0803D900
+#define TNETV107X_UART2_DMA_BASE 0x08108400
+#define TNETV107X_INTERNAL_MEMORY 0x20000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
+#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
+#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
+
+/* LPSC module definitions */
+#define TNETV107X_LPSC_ARM 0
+#define TNETV107X_LPSC_GEM 1
+#define TNETV107X_LPSC_DDR2_PHY 2
+#define TNETV107X_LPSC_TPCC 3
+#define TNETV107X_LPSC_TPTC0 4
+#define TNETV107X_LPSC_TPTC1 5
+#define TNETV107X_LPSC_RAM 6
+#define TNETV107X_LPSC_MBX_LITE 7
+#define TNETV107X_LPSC_LCD 8
+#define TNETV107X_LPSC_ETHSS 9
+#define TNETV107X_LPSC_AEMIF 10
+#define TNETV107X_LPSC_CHIP_CFG 11
+#define TNETV107X_LPSC_TSC 12
+#define TNETV107X_LPSC_ROM 13
+#define TNETV107X_LPSC_UART2 14
+#define TNETV107X_LPSC_PKTSEC 15
+#define TNETV107X_LPSC_SECCTL 16
+#define TNETV107X_LPSC_KEYMGR 17
+#define TNETV107X_LPSC_KEYPAD 18
+#define TNETV107X_LPSC_GPIO 19
+#define TNETV107X_LPSC_MDIO 20
+#define TNETV107X_LPSC_SDIO0 21
+#define TNETV107X_LPSC_UART0 22
+#define TNETV107X_LPSC_UART1 23
+#define TNETV107X_LPSC_TIMER0 24
+#define TNETV107X_LPSC_TIMER1 25
+#define TNETV107X_LPSC_WDT_ARM 26
+#define TNETV107X_LPSC_WDT_DSP 27
+#define TNETV107X_LPSC_SSP 28
+#define TNETV107X_LPSC_TDM0 29
+#define TNETV107X_LPSC_VLYNQ 30
+#define TNETV107X_LPSC_MCDMA 31
+#define TNETV107X_LPSC_USB0 32
+#define TNETV107X_LPSC_TDM1 33
+#define TNETV107X_LPSC_DEBUGSS 34
+#define TNETV107X_LPSC_ETHSS_RGMII 35
+#define TNETV107X_LPSC_SYSTEM 36
+#define TNETV107X_LPSC_IMCOP 37
+#define TNETV107X_LPSC_SPARE 38
+#define TNETV107X_LPSC_SDIO1 39
+#define TNETV107X_LPSC_USB1 40
+#define TNETV107X_LPSC_USBSS 41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
+#define TNETV107X_LPSC_MAX 44
+
+/* Interrupt controller */
+#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
+#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * TNETV107X: Pinmux APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+struct pin_config {
+ unsigned char reg_index;
+ unsigned char mask_offset;
+ unsigned char mode;
+};
+
+#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
+ { reg, offset, mux_mode }
+
+int mux_select_pin(short index);
+int mux_select_pins(const short *pins);
+
+enum tnetv107x_pin_mux_index {
+ TNETV107X_PIN_ASR_A00,
+ TNETV107X_PIN_GPIO32,
+ TNETV107X_PIN_ASR_A01,
+ TNETV107X_PIN_GPIO33,
+ TNETV107X_PIN_ASR_A02,
+ TNETV107X_PIN_GPIO34,
+ TNETV107X_PIN_ASR_A03,
+ TNETV107X_PIN_GPIO35,
+ TNETV107X_PIN_ASR_A04,
+ TNETV107X_PIN_GPIO36,
+ TNETV107X_PIN_ASR_A05,
+ TNETV107X_PIN_GPIO37,
+ TNETV107X_PIN_ASR_A06,
+ TNETV107X_PIN_GPIO38,
+ TNETV107X_PIN_ASR_A07,
+ TNETV107X_PIN_GPIO39,
+ TNETV107X_PIN_ASR_A08,
+ TNETV107X_PIN_GPIO40,
+ TNETV107X_PIN_ASR_A09,
+ TNETV107X_PIN_GPIO41,
+ TNETV107X_PIN_ASR_A10,
+ TNETV107X_PIN_GPIO42,
+ TNETV107X_PIN_ASR_A11,
+ TNETV107X_PIN_BOOT_STRP_0,
+ TNETV107X_PIN_ASR_A12,
+ TNETV107X_PIN_BOOT_STRP_1,
+ TNETV107X_PIN_ASR_A13,
+ TNETV107X_PIN_GPIO43,
+ TNETV107X_PIN_ASR_A14,
+ TNETV107X_PIN_GPIO44,
+ TNETV107X_PIN_ASR_A15,
+ TNETV107X_PIN_GPIO45,
+ TNETV107X_PIN_ASR_A16,
+ TNETV107X_PIN_GPIO46,
+ TNETV107X_PIN_ASR_A17,
+ TNETV107X_PIN_GPIO47,
+ TNETV107X_PIN_ASR_A18,
+ TNETV107X_PIN_GPIO48,
+ TNETV107X_PIN_SDIO1_DATA3_0,
+ TNETV107X_PIN_ASR_A19,
+ TNETV107X_PIN_GPIO49,
+ TNETV107X_PIN_SDIO1_DATA2_0,
+ TNETV107X_PIN_ASR_A20,
+ TNETV107X_PIN_GPIO50,
+ TNETV107X_PIN_SDIO1_DATA1_0,
+ TNETV107X_PIN_ASR_A21,
+ TNETV107X_PIN_GPIO51,
+ TNETV107X_PIN_SDIO1_DATA0_0,
+ TNETV107X_PIN_ASR_A22,
+ TNETV107X_PIN_GPIO52,
+ TNETV107X_PIN_SDIO1_CMD_0,
+ TNETV107X_PIN_ASR_A23,
+ TNETV107X_PIN_GPIO53,
+ TNETV107X_PIN_SDIO1_CLK_0,
+ TNETV107X_PIN_ASR_BA_1,
+ TNETV107X_PIN_GPIO54,
+ TNETV107X_PIN_SYS_PLL_CLK,
+ TNETV107X_PIN_ASR_CS0,
+ TNETV107X_PIN_ASR_CS1,
+ TNETV107X_PIN_ASR_CS2,
+ TNETV107X_PIN_TDM_PLL_CLK,
+ TNETV107X_PIN_ASR_CS3,
+ TNETV107X_PIN_ETH_PHY_CLK,
+ TNETV107X_PIN_ASR_D00,
+ TNETV107X_PIN_GPIO55,
+ TNETV107X_PIN_ASR_D01,
+ TNETV107X_PIN_GPIO56,
+ TNETV107X_PIN_ASR_D02,
+ TNETV107X_PIN_GPIO57,
+ TNETV107X_PIN_ASR_D03,
+ TNETV107X_PIN_GPIO58,
+ TNETV107X_PIN_ASR_D04,
+ TNETV107X_PIN_GPIO59_0,
+ TNETV107X_PIN_ASR_D05,
+ TNETV107X_PIN_GPIO60_0,
+ TNETV107X_PIN_ASR_D06,
+ TNETV107X_PIN_GPIO61_0,
+ TNETV107X_PIN_ASR_D07,
+ TNETV107X_PIN_GPIO62_0,
+ TNETV107X_PIN_ASR_D08,
+ TNETV107X_PIN_GPIO63_0,
+ TNETV107X_PIN_ASR_D09,
+ TNETV107X_PIN_GPIO64_0,
+ TNETV107X_PIN_ASR_D10,
+ TNETV107X_PIN_SDIO1_DATA3_1,
+ TNETV107X_PIN_ASR_D11,
+ TNETV107X_PIN_SDIO1_DATA2_1,
+ TNETV107X_PIN_ASR_D12,
+ TNETV107X_PIN_SDIO1_DATA1_1,
+ TNETV107X_PIN_ASR_D13,
+ TNETV107X_PIN_SDIO1_DATA0_1,
+ TNETV107X_PIN_ASR_D14,
+ TNETV107X_PIN_SDIO1_CMD_1,
+ TNETV107X_PIN_ASR_D15,
+ TNETV107X_PIN_SDIO1_CLK_1,
+ TNETV107X_PIN_ASR_OE,
+ TNETV107X_PIN_BOOT_STRP_2,
+ TNETV107X_PIN_ASR_RNW,
+ TNETV107X_PIN_GPIO29_0,
+ TNETV107X_PIN_ASR_WAIT,
+ TNETV107X_PIN_GPIO30_0,
+ TNETV107X_PIN_ASR_WE,
+ TNETV107X_PIN_BOOT_STRP_3,
+ TNETV107X_PIN_ASR_WE_DQM0,
+ TNETV107X_PIN_GPIO31,
+ TNETV107X_PIN_LCD_PD17_0,
+ TNETV107X_PIN_ASR_WE_DQM1,
+ TNETV107X_PIN_ASR_BA0_0,
+ TNETV107X_PIN_VLYNQ_CLK,
+ TNETV107X_PIN_GPIO14,
+ TNETV107X_PIN_LCD_PD19_0,
+ TNETV107X_PIN_VLYNQ_RXD0,
+ TNETV107X_PIN_GPIO15,
+ TNETV107X_PIN_LCD_PD20_0,
+ TNETV107X_PIN_VLYNQ_RXD1,
+ TNETV107X_PIN_GPIO16,
+ TNETV107X_PIN_LCD_PD21_0,
+ TNETV107X_PIN_VLYNQ_TXD0,
+ TNETV107X_PIN_GPIO17,
+ TNETV107X_PIN_LCD_PD22_0,
+ TNETV107X_PIN_VLYNQ_TXD1,
+ TNETV107X_PIN_GPIO18,
+ TNETV107X_PIN_LCD_PD23_0,
+ TNETV107X_PIN_SDIO0_CLK,
+ TNETV107X_PIN_GPIO19,
+ TNETV107X_PIN_SDIO0_CMD,
+ TNETV107X_PIN_GPIO20,
+ TNETV107X_PIN_SDIO0_DATA0,
+ TNETV107X_PIN_GPIO21,
+ TNETV107X_PIN_SDIO0_DATA1,
+ TNETV107X_PIN_GPIO22,
+ TNETV107X_PIN_SDIO0_DATA2,
+ TNETV107X_PIN_GPIO23,
+ TNETV107X_PIN_SDIO0_DATA3,
+ TNETV107X_PIN_GPIO24,
+ TNETV107X_PIN_EMU0,
+ TNETV107X_PIN_EMU1,
+ TNETV107X_PIN_RTCK,
+ TNETV107X_PIN_TRST_N,
+ TNETV107X_PIN_TCK,
+ TNETV107X_PIN_TDI,
+ TNETV107X_PIN_TDO,
+ TNETV107X_PIN_TMS,
+ TNETV107X_PIN_TDM1_CLK,
+ TNETV107X_PIN_TDM1_RX,
+ TNETV107X_PIN_TDM1_TX,
+ TNETV107X_PIN_TDM1_FS,
+ TNETV107X_PIN_KEYPAD_R0,
+ TNETV107X_PIN_KEYPAD_R1,
+ TNETV107X_PIN_KEYPAD_R2,
+ TNETV107X_PIN_KEYPAD_R3,
+ TNETV107X_PIN_KEYPAD_R4,
+ TNETV107X_PIN_KEYPAD_R5,
+ TNETV107X_PIN_KEYPAD_R6,
+ TNETV107X_PIN_GPIO12,
+ TNETV107X_PIN_KEYPAD_R7,
+ TNETV107X_PIN_GPIO10,
+ TNETV107X_PIN_KEYPAD_C0,
+ TNETV107X_PIN_KEYPAD_C1,
+ TNETV107X_PIN_KEYPAD_C2,
+ TNETV107X_PIN_KEYPAD_C3,
+ TNETV107X_PIN_KEYPAD_C4,
+ TNETV107X_PIN_KEYPAD_C5,
+ TNETV107X_PIN_KEYPAD_C6,
+ TNETV107X_PIN_GPIO13,
+ TNETV107X_PIN_TEST_CLK_IN,
+ TNETV107X_PIN_KEYPAD_C7,
+ TNETV107X_PIN_GPIO11,
+ TNETV107X_PIN_SSP0_0,
+ TNETV107X_PIN_SCC_DCLK,
+ TNETV107X_PIN_LCD_PD20_1,
+ TNETV107X_PIN_SSP0_1,
+ TNETV107X_PIN_SCC_CS_N,
+ TNETV107X_PIN_LCD_PD21_1,
+ TNETV107X_PIN_SSP0_2,
+ TNETV107X_PIN_SCC_D,
+ TNETV107X_PIN_LCD_PD22_1,
+ TNETV107X_PIN_SSP0_3,
+ TNETV107X_PIN_SCC_RESETN,
+ TNETV107X_PIN_LCD_PD23_1,
+ TNETV107X_PIN_SSP1_0,
+ TNETV107X_PIN_GPIO25,
+ TNETV107X_PIN_UART2_CTS,
+ TNETV107X_PIN_SSP1_1,
+ TNETV107X_PIN_GPIO26,
+ TNETV107X_PIN_UART2_RD,
+ TNETV107X_PIN_SSP1_2,
+ TNETV107X_PIN_GPIO27,
+ TNETV107X_PIN_UART2_RTS,
+ TNETV107X_PIN_SSP1_3,
+ TNETV107X_PIN_GPIO28,
+ TNETV107X_PIN_UART2_TD,
+ TNETV107X_PIN_UART0_CTS,
+ TNETV107X_PIN_UART0_RD,
+ TNETV107X_PIN_UART0_RTS,
+ TNETV107X_PIN_UART0_TD,
+ TNETV107X_PIN_UART1_RD,
+ TNETV107X_PIN_UART1_TD,
+ TNETV107X_PIN_LCD_AC_NCS,
+ TNETV107X_PIN_LCD_HSYNC_RNW,
+ TNETV107X_PIN_LCD_VSYNC_A0,
+ TNETV107X_PIN_LCD_MCLK,
+ TNETV107X_PIN_LCD_PD16_0,
+ TNETV107X_PIN_LCD_PCLK_E,
+ TNETV107X_PIN_LCD_PD00,
+ TNETV107X_PIN_LCD_PD01,
+ TNETV107X_PIN_LCD_PD02,
+ TNETV107X_PIN_LCD_PD03,
+ TNETV107X_PIN_LCD_PD04,
+ TNETV107X_PIN_LCD_PD05,
+ TNETV107X_PIN_LCD_PD06,
+ TNETV107X_PIN_LCD_PD07,
+ TNETV107X_PIN_LCD_PD08,
+ TNETV107X_PIN_GPIO59_1,
+ TNETV107X_PIN_LCD_PD09,
+ TNETV107X_PIN_GPIO60_1,
+ TNETV107X_PIN_LCD_PD10,
+ TNETV107X_PIN_ASR_BA0_1,
+ TNETV107X_PIN_GPIO61_1,
+ TNETV107X_PIN_LCD_PD11,
+ TNETV107X_PIN_GPIO62_1,
+ TNETV107X_PIN_LCD_PD12,
+ TNETV107X_PIN_GPIO63_1,
+ TNETV107X_PIN_LCD_PD13,
+ TNETV107X_PIN_GPIO64_1,
+ TNETV107X_PIN_LCD_PD14,
+ TNETV107X_PIN_GPIO29_1,
+ TNETV107X_PIN_LCD_PD15,
+ TNETV107X_PIN_GPIO30_1,
+ TNETV107X_PIN_EINT0,
+ TNETV107X_PIN_GPIO08,
+ TNETV107X_PIN_EINT1,
+ TNETV107X_PIN_GPIO09,
+ TNETV107X_PIN_GPIO00,
+ TNETV107X_PIN_LCD_PD20_2,
+ TNETV107X_PIN_TDM_CLK_IN_2,
+ TNETV107X_PIN_GPIO01,
+ TNETV107X_PIN_LCD_PD21_2,
+ TNETV107X_PIN_24M_CLK_OUT_1,
+ TNETV107X_PIN_GPIO02,
+ TNETV107X_PIN_LCD_PD22_2,
+ TNETV107X_PIN_GPIO03,
+ TNETV107X_PIN_LCD_PD23_2,
+ TNETV107X_PIN_GPIO04,
+ TNETV107X_PIN_LCD_PD16_1,
+ TNETV107X_PIN_USB0_RXERR,
+ TNETV107X_PIN_GPIO05,
+ TNETV107X_PIN_LCD_PD17_1,
+ TNETV107X_PIN_TDM_CLK_IN_1,
+ TNETV107X_PIN_GPIO06,
+ TNETV107X_PIN_LCD_PD18,
+ TNETV107X_PIN_24M_CLK_OUT_2,
+ TNETV107X_PIN_GPIO07,
+ TNETV107X_PIN_LCD_PD19_1,
+ TNETV107X_PIN_USB1_RXERR,
+ TNETV107X_PIN_ETH_PLL_CLK,
+ TNETV107X_PIN_MDIO,
+ TNETV107X_PIN_MDC,
+ TNETV107X_PIN_AIC_MUTE_STAT_N,
+ TNETV107X_PIN_TDM0_CLK,
+ TNETV107X_PIN_AIC_HNS_EN_N,
+ TNETV107X_PIN_TDM0_FS,
+ TNETV107X_PIN_AIC_HDS_EN_STAT_N,
+ TNETV107X_PIN_TDM0_TX,
+ TNETV107X_PIN_AIC_HNF_EN_STAT_N,
+ TNETV107X_PIN_TDM0_RX,
+};
+
+#endif
--- /dev/null
+/*
+ * TNETV107X: NAND definitions
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
+
+#define MASK_CLE 0x4000
+#define MASK_ALE 0x2000
+
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
+
+extern void davinci_nand_init(struct nand_chip *nand);
+
+#endif
projects / u-boot / commitdiff