powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005

SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 05648169ad41f9cd272617fb6b3fac90b1fb0a46..7b9f77362c4af7f7e2f6ad3f69a30c7d39ff92c5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -47,6 +47,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
        puts("Work-around for Erratum SERDES9 enabled\n");
 #endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
+       puts("Work-around for Erratum SERDES-A005 enabled\n");
+#endif
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
        puts("Work-around for Erratum CPU22 enabled\n");
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index d39f96352ef9d9c839fc879d9ef41c7df0323035..edacdb813f54c373627b84a880f411e384670bbd 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -386,6 +386,52 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
 }
 #endif
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+/*
+ * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
+ * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
+ */
+static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
+{
+       enum srds_prtcl device;
+
+       switch (cfg) {
+       case 0x13:
+       case 0x16:
+               /*
+                * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
+                * to 0.
+                */
+               clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
+                            SRDS_PLLCR1_PLL_BWSEL);
+               break;
+       case 0x19:
+               /*
+                * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
+                * SRDSB3PLLCR1[PLLBW_SEL] to 1.
+                */
+               clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
+                            SRDS_PLLCR1_PLL_BWSEL);
+               setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
+                            SRDS_PLLCR1_PLL_BWSEL);
+               break;
+       }
+
+       /*
+        * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
+        * before XAUI is initialized.
+        */
+       for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
+               if (is_serdes_configured(device)) {
+                       int bank = serdes_get_bank_by_device(cfg, device);
+
+                       clrbits_be32(&regs->bank[bank].pllcr1,
+                                    SRDS_PLLCR1_PLL_BWSEL);
+               }
+       }
+}
+#endif
+
 void fsl_serdes_init(void)
 {
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -570,6 +616,8 @@ void fsl_serdes_init(void)
        puts("\n");
 #endif
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+       p4080_erratum_serdes_a005(srds_regs, cfg);
 #endif
 
        for (idx = 0; idx < SRDS_MAX_BANK; idx++) {

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index da2e99804d1ec7fea4db8c32a8af90a03baa799b..b8b8914c44284241a3e81e6713bd12f94f876fd5 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -311,6 +311,7 @@
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
+#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 
 /* P5010 is single core version of P5020 */
 #elif defined(CONFIG_PPC_P5010)