/* Just in case... */
disable_interrupts();
-#ifdef CONFIG_SYS_PCAT_INTERRUPTS
+#ifdef CONFIG_I8259_PIC
/* Initialize the master/slave i8259 pic */
i8259_init();
#endif
int register_timer_isr (timer_fnc_t *isr_func);
unsigned long get_tbclk_mhz(void);
void timer_set_base(uint64_t base);
-int pcat_timer_init(void);
+int i8254_init(void);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
obj-y += mpspec.o
obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-y += cmd_mtrr.o
-obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
-obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
+obj-$(CONFIG_I8259_PIC) += i8259.o
+obj-$(CONFIG_I8254_TIMER) += i8254.o
ifndef CONFIG_DM_PCI
obj-$(CONFIG_PCI) += pci_type1.o
endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/i8254.h>
+
+#define TIMER1_VALUE 18 /* 15.6us */
+#define TIMER2_VALUE 0x0a8e /* 440Hz */
+
+int i8254_init(void)
+{
+ /*
+ * Initialize counter 1, used to refresh request signal.
+ * This is required for legacy purpose as some codes like
+ * vgabios utilizes counter 1 to provide delay functionality.
+ */
+ outb(PIT_CMD_CTR1 | PIT_CMD_LOW | PIT_CMD_MODE2,
+ PIT_BASE + PIT_COMMAND);
+ outb(TIMER1_VALUE, PIT_BASE + PIT_T1);
+
+ /*
+ * Initialize counter 2, used to drive the speaker.
+ * To start a beep, set both bit0 and bit1 of port 0x61.
+ * To stop it, clear both bit0 and bit1 of port 0x61.
+ */
+ outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
+ PIT_BASE + PIT_COMMAND);
+ outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
+ outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file provides the interrupt handling functionality for systems
+ * based on the standard PC/AT architecture using two cascaded i8259
+ * Programmable Interrupt Controllers.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/i8259.h>
+#include <asm/ibmpc.h>
+#include <asm/interrupt.h>
+
+int i8259_init(void)
+{
+ u8 i;
+
+ /* Mask all interrupts */
+ outb(0xff, MASTER_PIC + IMR);
+ outb(0xff, SLAVE_PIC + IMR);
+
+ /*
+ * Master PIC
+ * Place master PIC interrupts at INT20
+ */
+ outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
+ outb(0x20, MASTER_PIC + ICW2);
+ outb(IR2, MASTER_PIC + ICW3);
+ outb(ICW4_PM, MASTER_PIC + ICW4);
+
+ for (i = 0; i < 8; i++)
+ outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
+
+ /*
+ * Slave PIC
+ * Place slave PIC interrupts at INT28
+ */
+ outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
+ outb(0x28, SLAVE_PIC + ICW2);
+ outb(0x02, SLAVE_PIC + ICW3);
+ outb(ICW4_PM, SLAVE_PIC + ICW4);
+
+ for (i = 0; i < 8; i++)
+ outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
+
+ /*
+ * Enable cascaded interrupts by unmasking the cascade IRQ pin of
+ * the master PIC
+ */
+ unmask_irq(2);
+
+ /* Interrupt 9 should be level triggered (SCI). The OS might do this */
+ configure_irq_trigger(9, true);
+
+ return 0;
+}
+
+void mask_irq(int irq)
+{
+ int imr_port;
+
+ if (irq >= SYS_NUM_IRQS)
+ return;
+
+ if (irq > 7)
+ imr_port = SLAVE_PIC + IMR;
+ else
+ imr_port = MASTER_PIC + IMR;
+
+ outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
+}
+
+void unmask_irq(int irq)
+{
+ int imr_port;
+
+ if (irq >= SYS_NUM_IRQS)
+ return;
+
+ if (irq > 7)
+ imr_port = SLAVE_PIC + IMR;
+ else
+ imr_port = MASTER_PIC + IMR;
+
+ outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
+}
+
+void specific_eoi(int irq)
+{
+ if (irq >= SYS_NUM_IRQS)
+ return;
+
+ if (irq > 7) {
+ /*
+ * IRQ is on the slave - Issue a corresponding EOI to the
+ * slave PIC and an EOI for IRQ2 (the cascade interrupt)
+ * on the master PIC
+ */
+ outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
+ irq = SEOI_IR2;
+ }
+
+ outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
+}
+
+void configure_irq_trigger(int int_num, bool is_level_triggered)
+{
+ u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
+
+ debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
+ if (is_level_triggered)
+ int_bits |= (1 << int_num);
+ else
+ int_bits &= ~(1 << int_num);
+
+ /* Write new values */
+ debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
+ outb((u8)(int_bits & 0xff), ELCR1);
+ outb((u8)(int_bits >> 8), ELCR2);
+}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file provides the interrupt handling functionality for systems
- * based on the standard PC/AT architecture using two cascaded i8259
- * Programmable Interrupt Controllers.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/i8259.h>
-#include <asm/ibmpc.h>
-#include <asm/interrupt.h>
-
-int i8259_init(void)
-{
- u8 i;
-
- /* Mask all interrupts */
- outb(0xff, MASTER_PIC + IMR);
- outb(0xff, SLAVE_PIC + IMR);
-
- /*
- * Master PIC
- * Place master PIC interrupts at INT20
- */
- outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
- outb(0x20, MASTER_PIC + ICW2);
- outb(IR2, MASTER_PIC + ICW3);
- outb(ICW4_PM, MASTER_PIC + ICW4);
-
- for (i = 0; i < 8; i++)
- outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
-
- /*
- * Slave PIC
- * Place slave PIC interrupts at INT28
- */
- outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
- outb(0x28, SLAVE_PIC + ICW2);
- outb(0x02, SLAVE_PIC + ICW3);
- outb(ICW4_PM, SLAVE_PIC + ICW4);
-
- for (i = 0; i < 8; i++)
- outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
-
- /*
- * Enable cascaded interrupts by unmasking the cascade IRQ pin of
- * the master PIC
- */
- unmask_irq(2);
-
- /* Interrupt 9 should be level triggered (SCI). The OS might do this */
- configure_irq_trigger(9, true);
-
- return 0;
-}
-
-void mask_irq(int irq)
-{
- int imr_port;
-
- if (irq >= SYS_NUM_IRQS)
- return;
-
- if (irq > 7)
- imr_port = SLAVE_PIC + IMR;
- else
- imr_port = MASTER_PIC + IMR;
-
- outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
-}
-
-void unmask_irq(int irq)
-{
- int imr_port;
-
- if (irq >= SYS_NUM_IRQS)
- return;
-
- if (irq > 7)
- imr_port = SLAVE_PIC + IMR;
- else
- imr_port = MASTER_PIC + IMR;
-
- outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
-}
-
-void specific_eoi(int irq)
-{
- if (irq >= SYS_NUM_IRQS)
- return;
-
- if (irq > 7) {
- /*
- * IRQ is on the slave - Issue a corresponding EOI to the
- * slave PIC and an EOI for IRQ2 (the cascade interrupt)
- * on the master PIC
- */
- outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
- irq = SEOI_IR2;
- }
-
- outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
-}
-
-void configure_irq_trigger(int int_num, bool is_level_triggered)
-{
- u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
-
- debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
- if (is_level_triggered)
- int_bits |= (1 << int_num);
- else
- int_bits &= ~(1 << int_num);
-
- /* Write new values */
- debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
- outb((u8)(int_bits & 0xff), ELCR1);
- outb((u8)(int_bits >> 8), ELCR2);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/i8254.h>
-
-#define TIMER1_VALUE 18 /* 15.6us */
-#define TIMER2_VALUE 0x0a8e /* 440Hz */
-
-int pcat_timer_init(void)
-{
- /*
- * Initialize counter 1, used to refresh request signal.
- * This is required for legacy purpose as some codes like
- * vgabios utilizes counter 1 to provide delay functionality.
- */
- outb(PIT_CMD_CTR1 | PIT_CMD_LOW | PIT_CMD_MODE2,
- PIT_BASE + PIT_COMMAND);
- outb(TIMER1_VALUE, PIT_BASE + PIT_T1);
-
- /*
- * Initialize counter 2, used to drive the speaker.
- * To start a beep, set both bit0 and bit1 of port 0x61.
- * To stop it, clear both bit0 and bit1 of port 0x61.
- */
- outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
- PIT_BASE + PIT_COMMAND);
- outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
- outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
-
- return 0;
-}
int timer_init(void)
{
-#ifdef CONFIG_SYS_PCAT_TIMER
- /* Set up the PCAT timer if required */
- pcat_timer_init();
+#ifdef CONFIG_I8254_TIMER
+ /* Set up the i8254 timer if required */
+ i8254_init();
#endif
return 0;
*/
#define CONFIG_SYS_X86_TSC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_PCAT_TIMER
+#define CONFIG_I8259_PIC
+#define CONFIG_I8254_TIMER
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
projects / u-boot / commitdiff