armv8: fsl_lsch2: Add SerDes 2 support

New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index fe3444a91e36c9e3321bbda0ec523c829b05ebdd..f73092ae3e44aaec50234084625e6add4e138ef8 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
 
 int is_serdes_configured(enum srds_prtcl device)
 {
@@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
 #ifdef CONFIG_SYS_FSL_SRDS_1
        ret |= serdes1_prtcl_map[device];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       ret |= serdes2_prtcl_map[device];
+#endif
 
        return !!ret;
 }
@@ -37,6 +43,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
                cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
                cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
                break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       case FSL_SRDS_2:
+               cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+               cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+               break;
 #endif
        default:
                printf("invalid SerDes%d\n", sd);
@@ -114,4 +126,11 @@ void fsl_serdes_init(void)
                    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
                    serdes1_prtcl_map);
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       serdes_init(FSL_SRDS_2,
+                   CONFIG_SYS_FSL_SERDES_ADDR,
+                   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
+                   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
+                   serdes2_prtcl_map);
+#endif
 }

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 487cba80803f64c9f520e7c15e08d65542c06abe..1f3340442caf6e77d0ad22851aa5e98338a24372 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -140,6 +140,7 @@ enum srds_prtcl {
 
 enum srds {
        FSL_SRDS_1  = 0,
+       FSL_SRDS_2  = 1,
 };
 
 #endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 97136a011ecb265e5017394a114f0ca6c7a3aa5a..95a42935cac9c20b29f9c2e21802b1d264562b2c 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -228,6 +228,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK   0xffff0000
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK   0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT  0
 #define RCW_SB_EN_REG_INDEX    7
 #define RCW_SB_EN_MASK         0x00200000