sun9i: Add sun9i (A80) clock setup support

Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 1720f7db01ddf7594a53acf43aed660caf178705..1c4b7633f92308b28fb48ef5df9e29888cacb052 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_MACH_SUN5I)      += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)       += clock_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)       += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN8I)       += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN9I)       += clock_sun9i.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
new file mode 100644 (file)
index 0000000..27179ba
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
@@ -0,0 +1,68 @@
+/*
+ * sun9i specific clock code
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       /* open the clock for uart */
+       setbits_le32(&ccm->apb1_gate,
+                    CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
+                                      CONFIG_CONS_INDEX - 1));
+       /* deassert uart reset */
+       setbits_le32(&ccm->apb1_reset_cfg,
+                    1 << (APB1_RESET_UART_SHIFT +
+                          CONFIG_CONS_INDEX - 1));
+
+       /* Dup with clock_init_safe(), drop once sun9i SPL support lands */
+       writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       if (port > 4)
+               return -1;
+
+       /* set the apb reset and clock gate for twi */
+       if (state) {
+               setbits_le32(&ccm->apb1_gate,
+                            CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+               setbits_le32(&ccm->apb1_reset_cfg,
+                            1 << (APB1_RESET_UART_SHIFT + port));
+       } else {
+               clrbits_le32(&ccm->apb1_reset_cfg,
+                            1 << (APB1_RESET_UART_SHIFT + port));
+               clrbits_le32(&ccm->apb1_gate,
+                            CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+       }
+
+       return 0;
+}
+
+unsigned int clock_get_pll4_periph0(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->pll4_periph0_cfg);
+       int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
+       int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
+       int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
+       const int k = 1;
+
+       return ((24000000 * n * k) >> p) / m;
+}