]> git.sur5r.net Git - u-boot/commitdiff
imx: ventana: add pci fixup for PLX PEX860x switch GPIO
authorTim Harvey <tharvey@gateworks.com>
Fri, 8 Aug 2014 05:49:57 +0000 (22:49 -0700)
committerStefano Babic <sbabic@denx.de>
Tue, 9 Sep 2014 14:15:03 +0000 (16:15 +0200)
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
board/gateworks/gw_ventana/gw_ventana.c
include/configs/gw_ventana.h

index 452a9053f51c0e9915d05078a73effb58ee18a8b..9a1b6dd9ce3173ddad3511cc626d57f35903fa59 100644 (file)
@@ -31,6 +31,7 @@
 #include <mmc.h>
 #include <mtd_node.h>
 #include <netdev.h>
+#include <pci.h>
 #include <power/pmic.h>
 #include <power/ltc3676_pmic.h>
 #include <power/pfuze100_pmic.h>
@@ -1157,6 +1158,35 @@ int imx6_pcie_toggle_reset(void)
        }
        return 0;
 }
+
+/*
+ * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
+ * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
+ * properly and assert reset for 100ms.
+ */
+void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+                        unsigned short vendor, unsigned short device,
+                        unsigned short class)
+{
+       u32 dw;
+
+       debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
+             PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+       if (vendor == PCI_VENDOR_ID_PLX &&
+           (device & 0xfff0) == 0x8600 &&
+           PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
+               debug("configuring PLX 860X downstream PERST#\n");
+               pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
+               dw |= 0xaaa8; /* GPIO1-7 outputs */
+               pci_hose_write_config_dword(hose, dev, 0x62c, dw);
+
+               pci_hose_read_config_dword(hose, dev, 0x644, &dw);
+               dw |= 0xfe;   /* GPIO1-7 output high */
+               pci_hose_write_config_dword(hose, dev, 0x644, dw);
+
+               mdelay(100);
+       }
+}
 #endif /* CONFIG_CMD_PCI */
 
 #ifdef CONFIG_SERIAL_TAG
index b991b093cb6977b24cff29fced71aa1e39f3a7e4..0e5c20097d1cfd0781e68d2883fcac031921664b 100644 (file)
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCI_FIXUP_DEV
 #define CONFIG_PCIE_IMX
 #endif