#include <common.h>
 #include <netdev.h>
+#include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
 
 #include "../common/fman.h"
 
        struct memac_mdio_info memac_mdio_info;
        unsigned int i;
        int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+       phy_interface_t phy_int;
+       struct mii_dev *bus;
+#endif
+
        printf("Initializing Fman\n");
 
        memac_mdio_info.regs =
                                                        DEFAULT_FM_MDIO_NAME));
        }
 
+#ifdef CONFIG_VSC9953
+       /* SerDes configured for QSGMII */
+       if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+               for (i = 0; i < 4; i++) {
+                       bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+                       phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+                       phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+                       vsc9953_port_info_set_mdio(i, bus);
+                       vsc9953_port_info_set_phy_address(i, phy_addr);
+                       vsc9953_port_info_set_phy_int(i, phy_int);
+                       vsc9953_port_enable(i);
+               }
+       }
+       if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+               for (i = 4; i < 8; i++) {
+                       bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+                       phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+                       phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+                       vsc9953_port_info_set_mdio(i, bus);
+                       vsc9953_port_info_set_phy_address(i, phy_addr);
+                       vsc9953_port_info_set_phy_int(i, phy_int);
+                       vsc9953_port_enable(i);
+               }
+       }
+
+       /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+       if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+               vsc9953_port_enable(8);
+
+       /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+       if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+               /* Enable L2 On MAC2 using SCFG */
+               struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+                               CONFIG_SYS_MPC85xx_SCFG;
+
+               out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+                        (0x80000000));
+               vsc9953_port_enable(9);
+       }
+#endif
+
        cpu_eth_init(bis);
 #endif
 
 
 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 #define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
 
+/* Enable VSC9953 L2 Switch driver on T1040 SoC */
+#ifdef CONFIG_T1040RDB
+#define CONFIG_VSC9953
+#define CONFIG_VSC9953_CMD
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR       0x04
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR       0x08
+#endif
+
 #define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC4"
 #define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */