The fifo size of ep0 is 64 bytes, and if the packet size grater than
64 bytes, the driver would have to fill up the fifo multiple times,
and before filling up the fifo, the driver should make sure the fifo
is empty by checking fifo empty indication.
However there is a hardware bug that the fifo empty indication is
somehow a bit earlier than fifo reset. So if I don't add an extra
delay here, the data might be corrupted. (i.e., 1 byte missing)
After a couple of tests, it truns out that 1 usec is good enough.
This workaround should be applied to all hardware revisions.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
if (ep->id == 0) {
/* Wait until cx/ep0 fifo empty */
fotg210_cxwait(chip, CXFIFO_CXFIFOE);
+ udelay(1);
writel(DMAFIFO_CX, ®s->dma_fifo);
} else {
/* Wait until epx fifo empty */