return -EINVAL;
}
- ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
- if (ret == -1)
- return ret;
- priv->link_base = ret;
+ cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
+ if (!cell || len != 8)
+ return -EINVAL;
+ priv->link_base = fdt_addr_to_cpu(cell[0]);
+ priv->link_num = fdt_addr_to_cpu(cell[1]);
+ if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
+ debug("Limiting supported PIRQ link number from %d to %d\n",
+ priv->link_num, CONFIG_MAX_PIRQ_LINKS);
+ priv->link_num = CONFIG_MAX_PIRQ_LINKS;
+ }
priv->irq_mask = fdtdec_get_int(blob, node,
"intel,pirq-mask", PIRQ_BITMAP);
*
* @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
* @link_base: link value base number
+ * @link_num: number of PIRQ links supported
* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
struct irq_router {
int config;
u32 link_base;
+ int link_num;
u16 irq_mask;
u32 bdf;
u32 ibase;