that work for multiple fs types
CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENV saveenv
- CONFIG_CMD_FAT * FAT command support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
CONFIG_CMD_GO * the 'go' command (exec code)
- Partition Labels (disklabels) Supported:
Zero or more of the following:
CONFIG_MAC_PARTITION Apple's MacOS partition table.
- CONFIG_DOS_PARTITION MS Dos partition table, traditional on the
- Intel architecture, USB sticks, etc.
CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc.
CONFIG_EFI_PARTITION GPT partition table, common when EFI is the
bootloader. Note 2TB partition limit; see
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
-- FAT(File Allocation Table) filesystem write function support:
- CONFIG_FAT_WRITE
-
- Define this to enable support for saving memory data as a
- file in FAT formatted partition.
-
- This will also enable the command "fatwrite" enabling the
- user to write files to FAT.
-
-- FAT(File Allocation Table) filesystem cluster size:
- CONFIG_FS_FAT_MAX_CLUSTSIZE
-
- Define the max cluster size for fat operations else
- a default value of 65536 will be defined.
-
- Keyboard Support:
See Kconfig help for available keyboard drivers.
environment.
- CONFIG_FAT_WRITE:
- This should be defined. Otherwise it cannot save the environment file.
+ This must be enabled. Otherwise it cannot save the environment file.
- CONFIG_ENV_IS_IN_MMC:
select DM_SPI
select DM_GPIO
select DM_MMC
- imply CRC32_VERIFY
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
imply CMD_IOTRACE
- imply LZMA
imply CMD_LZMADEC
+ imply CRC32_VERIFY
+ imply FAT_WRITE
imply HASH_VERIFY
+ imply LZMA
config SH
bool "SuperH architecture"
select DM_SERIAL
select DM_GPIO
select OF_CONTROL
+ imply FAT_WRITE
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
bool "Support bcm23550_w1d"
select CPU_V7
imply CRC32_VERIFY
+ imply FAT_WRITE
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
select CPU_V7
imply CRC32_VERIFY
+ imply FAT_WRITE
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7
imply CRC32_VERIFY
imply CMD_HASH
+ imply FAT_WRITE
imply HASH_VERIFY
config TARGET_BCMNSP
select DM_SPI
select DM_GPIO
select DM_KEYBOARD
+ imply FAT_WRITE
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
select DM
select DM_SERIAL
select BOARD_EARLY_INIT_F
+ imply FAT_WRITE
imply SYS_THUMB_BUILD
config TARGET_S32V234EVB
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SYS_THUMB_BUILD
imply CRC32_VERIFY
+ imply FAT_WRITE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
+ imply FAT_WRITE
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO_SUPPORT
imply SPL_LIBCOMMON_SUPPORT
select SPL_CLK
select CLK_ZYNQ
imply CMD_CLK
+ imply FAT_WRITE
config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
select SPL_BOARD_INIT if SPL
select SPL_CLK
select DM_USB if USB
+ imply FAT_WRITE
config TEGRA
bool "NVIDIA Tegra"
+ imply FAT_WRITE
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select SPL_OF_CONTROL if SPL
select SPL_PINCTRL if SPL
select SUPPORT_SPL
+ imply FAT_WRITE
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
+ imply FAT_WRITE
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
which is loaded during boot stage, and then remains resident in RAM
and runs in the TrustZone after boot.
Say y to enable it.
+
+config SPL_FSL_LS_PPA
+ bool "FSL Layerscape PPA firmware support for SPL build"
+ depends on !ARMV8_PSCI
+ select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+ select SEC_FIRMWARE_ARMV8_PSCI
+ select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
+ help
+ The FSL Primary Protected Application (PPA) is a software component
+ which is loaded during boot stage, and then remains resident in RAM
+ and runs in the TrustZone after boot. This is to load PPA during SPL
+ stage instead of the RAM version of U-Boot. Once PPA is initialized,
+ the rest of U-Boot (including RAM version) runs at EL2.
choice
prompt "FSL Layerscape PPA firmware loading-media select"
depends on FSL_LS_PPA
int arch_cpu_init(void)
{
+ /*
+ * This function is called before U-Boot relocates itself to speed up
+ * on system running. It is not necessary to run if performance is not
+ * critical. Skip if MMU is already enabled by SPL or other means.
+ */
+ if (get_sctlr() & CR_M)
+ return 0;
+
icache_enable();
__asm_invalidate_dcache_all();
__asm_invalidate_tlb_all();
{
int error = 0;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
/* Update with accurate clock frequency */
- asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+ if (current_el() == 3)
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
#endif
#ifdef CONFIG_FSL_LSCH3
{
phys_size_t ram_top = ram_size;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* The start address of MC reserved memory needs to be aligned. */
ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
}
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int xfi_dpmac[XFI8 + 1];
int sgmii_dpmac[SGMII16 + 1];
#endif
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
else {
serdes_prtcl_map[lane_prtcl] = 1;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
switch (lane_prtcl) {
case QSGMII_A:
case QSGMII_B:
void fsl_serdes_init(void)
{
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int i , j;
for (i = XFI1, j = 1; i <= XFI8; i++, j++)
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
+ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
+1:
+
#ifdef CONFIG_FSL_LSCH3
/* Set Wuo bit for RN-I 20 */
#endif
#endif
+100:
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
#endif
2:
+ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
+1:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
isb
dsb sy
#endif
+100:
1:
#ifdef CONFIG_ARCH_LS1046A
+ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
+1:
/* Initialize the L2 RAM latency */
mrs x1, S3_1_c11_c0_2
mov x0, #0x1C7
orr x1, x1, #0x80
msr S3_1_c11_c0_2, x1
isb
+100:
#endif
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
/*
* Return status in x0
* success 0
- * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
+ * timeout 1 for setting SFONLY, 2 for FAM, 3 for both
*/
mov x29, lr
mov x8, #0
+ switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
+
+1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
+100:
1:
mov x0, x8
mov lr, x29
int ppa_init(void)
{
+ unsigned int el = current_el();
void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
int ret;
#endif
#endif
+ /* Skip if running at lower exception level */
+ if (el < 3) {
+ debug("Skipping PPA init, running at EL%d\n", el);
+ return 0;
+ }
+
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
debug("%s: PPA image load from XIP\n", __func__);
static void erratum_rcw_src(void)
{
-#if defined(CONFIG_SPL)
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
u32 val;
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ /* Skip if running at lower exception level */
+ if (current_el() < 3)
+ return;
+
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
+ /* Skip if running at lower exception level */
+ if (current_el() < 3)
+ return;
+
/* enable propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A53 core cluster)
*/
- out_le32(&cci->slave[4].snoop_ctrl,
- CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+ if (current_el() == 3) {
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+ }
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */
#include <asm/io.h>
#include <fsl_ifc.h>
#include <i2c.h>
+#include <fsl_csu.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/ppa.h>
DECLARE_GLOBAL_DATA_PTR;
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+#ifdef CONFIG_SPL_FSL_LS_PPA
+ ppa_init();
+#endif
}
void board_init_f(ulong dummy)
i2c_init_all();
#endif
dram_init();
-}
+#ifdef CONFIG_SPL_FSL_LS_PPA
+#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
+#error Need secure RAM for PPA
#endif
+ /*
+ * Secure memory location is determined in dram_init_banksize().
+ * gd->ram_size is deducted by the size of secure ram.
+ */
+ dram_init_banksize();
+
+ /*
+ * After dram_init_bank_size(), we know U-Boot only uses the first
+ * memory bank regardless how big the memory is.
+ */
+ gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+
+ /*
+ * If PPA is loaded, U-Boot will resume running at EL2.
+ * Cache and MMU will be enabled. Need a place for TLB.
+ * U-Boot will be relocated to the end of available memory
+ * in first bank. At this point, we cannot know how much
+ * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
+ * to avoid overlapping. As soon as the RAM version U-Boot sets
+ * up new MMU, this space is no longer needed.
+ */
+ gd->ram_top -= SPL_TLB_SETBACK;
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
+ gd->arch.tlb_allocated = gd->arch.tlb_addr;
+#endif /* CONFIG_SPL_FSL_LS_PPA */
+}
+#endif /* CONFIG_SPL_BUILD */
*/
unsigned int sec_firmware_support_psci_version(void)
{
- if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
+ if (current_el() == SEC_FIRMWARE_TARGET_EL)
return _sec_firmware_support_psci_version();
return PSCI_INVALID_VER;
* this bit should be set for A53/A57/A72.
*/
#ifdef CONFIG_ARMV8_SET_SMPEN
+ switch_el x1, 3f, 1f, 1f
+3:
mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
+1:
#endif
/* Apply ARM core specific erratas */
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
+ sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
- sun50i-h5-orangepi-pc2.dtb
+ sun50i-h5-orangepi-pc2.dtb \
+ sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
+ sun50i-a64-bananapi-m64.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
--- /dev/null
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BananaPi-M64";
+ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c1_pins {
+ bias-pull-up;
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ status = "okay";
+};
+++ /dev/null
-/*
- * Copyright (c) 2016 ARM Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "sun50i-a64.dtsi"
-
-/ {
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &emac;
- };
-
- soc {
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- };
-};
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
- vmmc-supply = <®_vcc3v3>;
- cd-gpios = <&pio 5 6 0>;
- cd-inverted;
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-&usbphy {
- status = "okay";
-};
-
-&ohci1 {
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
--- /dev/null
+/ {
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ soc {
+ emac: ethernet@01c30000 {
+ compatible = "allwinner,sun50i-a64-emac";
+ reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
+ reg-names = "emac", "syscon";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "ahb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+ };
+};
+
+&pio {
+ rmii_pins: rmii_pins {
+ allwinner,pins = "PD10", "PD11", "PD13", "PD14",
+ "PD17", "PD18", "PD19", "PD20",
+ "PD22", "PD23";
+ allwinner,function = "emac";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ rgmii_pins: rgmii_pins {
+ allwinner,pins = "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23";
+ allwinner,function = "emac";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/dts-v1/;
-
-#include "sun50i-a64-pine64-common.dtsi"
+#include "sun50i-a64-pine64.dts"
/ {
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
- memory {
- reg = <0x40000000 0x40000000>;
- };
-};
-
-&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
- phy = <&phy1>;
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
+ /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
};
-
/dts-v1/;
-#include "sun50i-a64-pine64-common.dtsi"
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Pine64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
+ aliases {
+ serial0 = &uart0;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
- memory {
- reg = <0x40000000 0x20000000>;
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c1_pins {
+ bias-pull-up;
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
};
};
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
};
- memory {
- device_type = "memory";
- reg = <0x40000000 0>;
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-accuracy = <300000000>;
+ clock-output-names = "iosc";
};
- gic: interrupt-controller@1c81000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
-
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x2000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
};
timer {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- pll1: pll1_clk@1c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun8i-a23-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll6: pll6_clk@1c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6", "pll6x2";
- };
-
- pll6d2: pll6d2_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <2>;
- clock-mult = <1>;
- clocks = <&pll6 0>;
- clock-output-names = "pll6d2";
- };
-
- pll7: pll7_clk@1c2002c {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-pll6-clk";
- reg = <0x01c2002c 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll7", "pll7x2";
- };
-
- cpu: cpu_clk@1c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20050 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
- clock-output-names = "cpu";
- critical-clocks = <0>;
- };
-
- axi: axi_clk@1c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20050 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- ahb1: ahb1_clk@1c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-ahb1-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
- clock-output-names = "ahb1";
- };
-
- ahb2: ahb2_clk@1c2005c {
- #clock-cells = <0>;
- compatible = "allwinner,sun8i-h3-ahb2-clk";
- reg = <0x01c2005c 0x4>;
- clocks = <&ahb1>, <&pll6d2>;
- clock-output-names = "ahb2";
- };
-
- apb1: apb1_clk@1c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1>;
- clock-output-names = "apb1";
- };
-
- apb2: apb2_clk@1c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
- clock-output-names = "apb2";
- };
-
- bus_gates: bus_gates_clk@1c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun50i-a64-bus-gates-clk",
- "allwinner,sunxi-multi-bus-gates-clk";
- reg = <0x01c20060 0x14>;
- ahb1_parent {
- clocks = <&ahb1>;
- clock-indices = <1>, <5>,
- <6>, <8>,
- <9>, <10>,
- <13>, <14>,
- <18>, <19>,
- <20>, <21>,
- <23>, <24>,
- <25>, <28>,
- <32>, <35>,
- <36>, <37>,
- <40>, <43>,
- <44>, <52>,
- <53>, <54>,
- <135>;
- clock-output-names = "bus_mipidsi", "bus_ce",
- "bus_dma", "bus_mmc0",
- "bus_mmc1", "bus_mmc2",
- "bus_nand", "bus_sdram",
- "bus_ts", "bus_hstimer",
- "bus_spi0", "bus_spi1",
- "bus_otg", "bus_otg_ehci0",
- "bus_ehci0", "bus_otg_ohci0",
- "bus_ve", "bus_lcd0",
- "bus_lcd1", "bus_deint",
- "bus_csi", "bus_hdmi",
- "bus_de", "bus_gpu",
- "bus_msgbox", "bus_spinlock",
- "bus_dbg";
- };
- ahb2_parent {
- clocks = <&ahb2>;
- clock-indices = <17>, <29>;
- clock-output-names = "bus_gmac", "bus_ohci0";
- };
- apb1_parent {
- clocks = <&apb1>;
- clock-indices = <64>, <65>,
- <69>, <72>,
- <76>, <77>,
- <78>;
- clock-output-names = "bus_codec", "bus_spdif",
- "bus_pio", "bus_ths",
- "bus_i2s0", "bus_i2s1",
- "bus_i2s2";
- };
- abp2_parent {
- clocks = <&apb2>;
- clock-indices = <96>, <97>,
- <98>, <101>,
- <112>, <113>,
- <114>, <115>,
- <116>;
- clock-output-names = "bus_i2c0", "bus_i2c1",
- "bus_i2c2", "bus_scr",
- "bus_uart0", "bus_uart1",
- "bus_uart2", "bus_uart3",
- "bus_uart4";
- };
- };
-
- mmc0_clk: mmc0_clk@1c20088 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
- clock-output-names = "mmc0";
- };
-
- mmc1_clk: mmc1_clk@1c2008c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
- clock-output-names = "mmc1";
- };
-
- mmc2_clk: mmc2_clk@1c20090 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
- clock-output-names = "mmc2";
- };
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
ranges;
mmc0: mmc@1c0f000 {
- compatible = "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&bus_gates 8>, <&mmc0_clk>,
- <&mmc0_clk>, <&mmc0_clk>;
- clock-names = "ahb", "mmc",
- "output", "sample";
- resets = <&ahb_rst 8>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
- compatible = "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&bus_gates 9>, <&mmc1_clk>,
- <&mmc1_clk>, <&mmc1_clk>;
- clock-names = "ahb", "mmc",
- "output", "sample";
- resets = <&ahb_rst 9>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@1c11000 {
- compatible = "allwinner,sun50i-a64-mmc",
- "allwinner,sun5i-a13-mmc";
+ compatible = "allwinner,sun50i-a64-emmc";
reg = <0x01c11000 0x1000>;
- clocks = <&bus_gates 10>, <&mmc2_clk>,
- <&mmc2_clk>, <&mmc2_clk>;
- clock-names = "ahb", "mmc",
- "output", "sample";
- resets = <&ahb_rst 10>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
+ usb_otg: usb@01c19000 {
+ compatible = "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun50i-a64-usb-phy";
+ reg = <0x01c19400 0x14>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1b400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ccu: clock@01c20000 {
+ compatible = "allwinner,sun50i-a64-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun50i-a64-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bus_gates 69>;
+ clocks = <&ccu 58>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
- #interrupt-cells = <2>;
-
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PB8", "PB9";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart0_pins_b: uart0@1 {
- allwinner,pins = "PF2", "PF3";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_2pins: uart1_2@0 {
- allwinner,pins = "PG6", "PG7";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_4pins: uart1_4@0 {
- allwinner,pins = "PG6", "PG7", "PG8", "PG9";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart2_2pins: uart2_2@0 {
- allwinner,pins = "PB0", "PB1";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart2_4pins: uart2_4@0 {
- allwinner,pins = "PB0", "PB1", "PB2", "PB3";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart3_pins_a: uart3@0 {
- allwinner,pins = "PD0", "PD1";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart3_2pins_b: uart3_2@1 {
- allwinner,pins = "PH4", "PH5";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
+ #interrupt-cells = <3>;
- uart3_4pins_b: uart3_4@1 {
- allwinner,pins = "PH4", "PH5", "PH6", "PH7";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart4_2pins: uart4_2@0 {
- allwinner,pins = "PD2", "PD3";
- allwinner,function = "uart4";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart4_4pins: uart4_4@0 {
- allwinner,pins = "PD2", "PD3", "PD4", "PD5";
- allwinner,function = "uart4";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_pins: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_default_cd_pin: mmc0_cd_pin@0 {
- allwinner,pins = "PF6";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- mmc1_pins: mmc1@0 {
- allwinner,pins = "PG0", "PG1", "PG2", "PG3",
- "PG4", "PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ i2c1_pins: i2c1_pins {
+ pins = "PH2", "PH3";
+ function = "i2c1";
};
- mmc2_pins: mmc2@0 {
- allwinner,pins = "PC1", "PC5", "PC6", "PC8",
- "PC9", "PC10";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
- i2c0_pins: i2c0_pins {
- allwinner,pins = "PH0", "PH1";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
};
- i2c1_pins: i2c1_pins {
- allwinner,pins = "PH2", "PH3";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ mmc2_pins: mmc2-pins {
+ pins = "PC1", "PC5", "PC6", "PC8", "PC9",
+ "PC10","PC11", "PC12", "PC13",
+ "PC14", "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
};
- i2c2_pins: i2c2_pins {
- allwinner,pins = "PE14", "PE15";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart0_pins_a: uart0@0 {
+ pins = "PB8", "PB9";
+ function = "uart0";
};
- rmii_pins: rmii_pins {
- allwinner,pins = "PD10", "PD11", "PD13", "PD14",
- "PD17", "PD18", "PD19", "PD20",
- "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart1_pins: uart1_pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
};
- rgmii_pins: rgmii_pins {
- allwinner,pins = "PD8", "PD9", "PD10", "PD11",
- "PD12", "PD13", "PD15",
- "PD16", "PD17", "PD18", "PD19",
- "PD20", "PD21", "PD22", "PD23";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart1_rts_cts_pins: uart1_rts_cts_pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
};
};
- ahb_rst: reset@1c202c0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202c0 0xc>;
- };
-
- apb1_rst: reset@1c202d0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202d0 0x4>;
- };
-
- apb2_rst: reset@1c202d8 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202d8 0x4>;
- };
-
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&bus_gates 112>;
- resets = <&apb2_rst 16>;
+ clocks = <&ccu 67>;
+ resets = <&ccu 46>;
status = "disabled";
};
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&bus_gates 113>;
- resets = <&apb2_rst 17>;
+ clocks = <&ccu 68>;
+ resets = <&ccu 47>;
status = "disabled";
};
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&bus_gates 114>;
- resets = <&apb2_rst 18>;
+ clocks = <&ccu 69>;
+ resets = <&ccu 48>;
status = "disabled";
};
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&bus_gates 115>;
- resets = <&apb2_rst 19>;
+ clocks = <&ccu 70>;
+ resets = <&ccu 49>;
status = "disabled";
};
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&bus_gates 116>;
- resets = <&apb2_rst 20>;
+ clocks = <&ccu 71>;
+ resets = <&ccu 50>;
status = "disabled";
};
- rtc: rtc@1f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
-
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bus_gates 96>;
- resets = <&apb2_rst 0>;
+ clocks = <&ccu 63>;
+ resets = <&ccu 42>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bus_gates 97>;
- resets = <&apb2_rst 1>;
+ clocks = <&ccu 64>;
+ resets = <&ccu 43>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bus_gates 98>;
- resets = <&apb2_rst 2>;
+ clocks = <&ccu 65>;
+ resets = <&ccu 44>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- emac: ethernet@01c30000 {
- compatible = "allwinner,sun50i-a64-emac";
- reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
- reg-names = "emac", "syscon";
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ahb_rst 17>;
- reset-names = "ahb";
- clocks = <&bus_gates 17>;
- clock-names = "ahb";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
- usbphy: phy@1c1b810 {
- compatible = "allwinner,sun50i-a64-usb-phy",
- "allwinner,sun8i-a33-usb-phy";
- reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
- reg-names = "phy_ctrl", "pmu1";
- status = "disabled";
- #phy-cells = <1>;
+ rtc: rtc@1f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
- ehci1: usb@01c1b000 {
- compatible = "allwinner,sun50i-a64-ehci",
- "generic-ehci";
- reg = <0x01c1b000 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
+ r_ccu: clock@1f01400 {
+ compatible = "allwinner,sun50i-a64-r-ccu";
+ reg = <0x01f01400 0x100>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
- ohci1: usb@01c1b400 {
- compatible = "allwinner,sun50i-a64-ohci",
- "generic-ohci";
- reg = <0x01c1b400 0x100>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "enabled";
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
};
};
/dts-v1/;
-#include "sun8i-h3.dtsi"
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi PC 2";
compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
- cpus {
- cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
- enable-method = "psci";
- };
- cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
- enable-method = "psci";
- };
- cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
- enable-method = "psci";
- };
- cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
- enable-method = "psci";
- };
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
};
};
-&gic {
- compatible = "arm,gic-400";
-};
-
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 5 6 0>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
status = "okay";
};
--- /dev/null
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi Prime";
+ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ soc {
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3.dtsi"
+
+/ {
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ };
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ };
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ };
+};
+
+&gic {
+ compatible = "arm,gic-400";
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyArm NanoPi M1";
+ compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/dts-v1/;
-#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sun8i-h3-nanopi.dtsi"
/ {
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
-
- pwr {
- label = "nanopi:green:pwr";
- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
- default-state = "on";
- };
-
- status {
- label = "nanopi:blue:status";
- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
- };
- };
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&pio {
- leds_opc: led-pins {
- allwinner,pins = "PA10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-&r_pio {
- leds_r_opc: led-pins {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
-&usbphy {
- /* USB VBUS is always on */
- status = "okay";
};
&emac {
--- /dev/null
+/*
+ * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "k1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_npi>;
+
+ k1@0 {
+ label = "k1";
+ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ leds_npi: led_pins@0 {
+ pins = "PA10";
+ function = "gpio_out";
+ };
+};
+
+&r_pio {
+ leds_r_npi: led_pins@0 {
+ pins = "PL10";
+ function = "gpio_out";
+ };
+
+ sw_r_npi: key_pins@0 {
+ pins = "PL3";
+ function = "gpio_in";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
* To be aligned with MMU block size
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
+#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
void enable_layerscape_ns_access(void)
{
- enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#ifdef CONFIG_ARM64
+ if (current_el() == 3)
+#endif
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
}
void set_pcie_ns_access(int pcie, u16 val)
error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = cpu_eth_init(bis);
#endif
return error;
}
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
int offset;
fdt_fixup_memory_banks(blob, base, size, 2);
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(blob);
#endif
return 0;
}
#endif
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+}
+#endif
F: configs/ls2080aqds_defconfig
F: configs/ls2080aqds_nand_defconfig
F: configs/ls2080aqds_qspi_defconfig
+F: configs/ls2080aqds_sdcard_defconfig
LS2080A_SECURE_BOOT BOARD
M: Saksham Jain <saksham.jain@nxp.freescale.com>
DPAA2 DPC 0x00E00000
Kernel.itb 0x01000000
+Memory map for SD boot
+-------------------------
+Image Flash Offset SD Card
+ Start Block No.
+RCW+PBI 0x00000000 0x00008
+Boot firmware (U-Boot) 0x00100000 0x00800
+Boot firmware Environment 0x00300000 0x01800
+PPA firmware 0x00400000 0x02000
+DPAA2 MC 0x00A00000 0x05000
+DPAA2 DPL 0x00D00000 0x06800
+DPAA2 DPC 0x00E00000 0x07000
+Kernel.itb 0x01000000 0x08000
+
Environment Variables
---------------------
- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
#include <fm_eth.h>
#include <i2c.h>
#include <miiphy.h>
+#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
#include "../common/qixis.h"
#define MC_BOOT_ENV_VAR "mcinitcmd"
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
* Bank 2 -> Lanes A,B, C, D, E, F, G, H
int board_eth_init(bd_t *bis)
{
int error;
- char *mc_boot_env_var;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
}
}
- mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
- if (mc_boot_env_var)
- run_command_list(mc_boot_env_var, -1, 0);
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
return error;
}
-#ifdef CONFIG_FSL_MC_ENET
-
-#endif
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+ mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
}
#endif
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
int offset;
fsl_fdt_fixup_dr_usb(blob, bd);
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(blob);
#endif
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
-#define MC_BOOT_ENV_VAR "mcinitcmd"
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
- char *mc_boot_env_var;
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
}
}
- mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
- if (mc_boot_env_var)
- run_command_list(mc_boot_env_var, -1, 0);
cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
+#endif /* CONFIG_FSL_MC_ENET */
#ifdef CONFIG_PHY_AQUANTIA
/*
#endif
return pci_eth_init(bis);
}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+ mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
F: configs/Bananapi_M2_Ultra_defconfig
F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+BANANAPI M64
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/bananapi_m64_defconfig
+
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@free-electrons.com>
S: Maintained
S: Maintained
F: configs/MSI_Primo81_defconfig
+NANOPI-M1 BOARD
+M: Mylène Josserand <mylene.josserand@free-electrons.com>
+S: Maintained
+F: configs/nanopi_m1_defconfig
+
NANOPI-NEO BOARD
M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
S: Maintained
F: configs/orangepi_pc2_defconfig
+ORANGEPI PRIME BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/orangepi_prime_defconfig
+
PINE64 BOARDS
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
imply CMD_EXT4_WRITE
imply CMD_FASTBOOT if FASTBOOT
imply CMD_FAT
+ imply FAT_WRITE if CMD_FAT
imply CMD_FS_GENERIC
imply CMD_GPIO
imply CMD_GPT
config CMD_FAT
bool "FAT command support"
+ select FS_FAT
help
Support for the FAT fs
config SPL_FAT_SUPPORT
bool "Support FAT filesystems"
depends on SPL
+ select FS_FAT
help
Enable support for FAT and VFAT filesystems with SPL. This
permits U-Boot (or Linux in Falcon mode) to be loaded from a FAT
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_CONS_INDEX=1
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_ISO_PARTITION is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_FAT_WRITE=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_OMAP_WATCHDOG=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_OMAP_WATCHDOG=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
CONFIG_OMAP_WATCHDOG=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
-CONFIG_DOS_PARTITION=y
+CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MMC_DW_K3=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_GPT=y
-CONFIG_DOS_PARTITION=y
+CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_CMD_GPT=y
-CONFIG_DOS_PARTITION=y
+CONFIG_CMD_FAT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_NAND_BOOT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SPL=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_NAND_BOOT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="TI"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_UBI=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_PIC32=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_G_DNL_MANUFACTURER="Samsung"
CONFIG_G_DNL_VENDOR_NUM=0x04e8
CONFIG_G_DNL_PRODUCT_NUM=0x6601
+CONFIG_FAT_WRITE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_FAT_WRITE=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_SPI=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_FAT_WRITE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_FAT_WRITE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
+CONFIG_FAT_WRITE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
if NETDEVICES
+config PHY_GIGE
+ bool "Enable GbE PHY status parsing and configuration"
+ help
+ Enables support for parsing the status output and for
+ configuring GbE PHYs (affects the inner workings of some
+ commands and miiphyutil.c).
+
config AG7XXX
bool "Atheros AG7xxx Ethernet MAC support"
depends on DM_ETH && ARCH_ATH79
bool "Allwinner Sun8i Ethernet MAC support"
depends on DM_ETH
select PHYLIB
+ select PHY_GIGE
help
This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC.
It can be found in H3/A64/A83T based SoCs and compatible with both
#endif
}
-static void cpsw_slave_update_link(struct cpsw_slave *slave,
+static int cpsw_slave_update_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, int *link)
{
struct phy_device *phy;
u32 mac_control = 0;
+ int ret = -ENODEV;
phy = priv->phydev;
-
if (!phy)
- return;
+ goto out;
+
+ ret = phy_startup(phy);
+ if (ret)
+ goto out;
- phy_startup(phy);
- *link = phy->link;
+ if (link)
+ *link = phy->link;
- if (*link) { /* link up */
+ if (phy->link) { /* link up */
mac_control = priv->data.mac_control;
if (phy->speed == 1000)
mac_control |= GIGABITEN;
}
if (mac_control == slave->mac_control)
- return;
+ goto out;
if (mac_control) {
printf("link up on port %d, speed %d, %s duplex\n",
__raw_writel(mac_control, &slave->sliver->mac_control);
slave->mac_control = mac_control;
+
+out:
+ return ret;
}
static int cpsw_update_link(struct cpsw_priv *priv)
{
- int link = 0;
+ int ret = -ENODEV;
struct cpsw_slave *slave;
for_active_slave(slave, priv)
- cpsw_slave_update_link(slave, priv, &link);
+ ret = cpsw_slave_update_link(slave, priv, NULL);
- return link;
+ return ret;
}
static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
for_active_slave(slave, priv)
cpsw_slave_init(slave, priv);
- cpsw_update_link(priv);
+ ret = cpsw_update_link(priv);
+ if (ret)
+ goto out;
/* init descriptor pool */
for (i = 0; i < NUM_DESCS; i++) {
}
}
- return 0;
+out:
+ return ret;
}
static void _cpsw_halt(struct cpsw_priv *priv)
#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
+#include <power/regulator.h>
#include "designware.h"
DECLARE_GLOBAL_DATA_PTR;
ulong ioaddr;
int ret;
+#if defined(CONFIG_DM_REGULATOR)
+ struct udevice *phy_supply;
+
+ ret = device_get_supply_regulator(dev, "phy-supply",
+ &phy_supply);
+ if (ret) {
+ debug("%s: No phy supply\n", dev->name);
+ } else {
+ ret = regulator_set_enable(phy_supply, true);
+ if (ret) {
+ puts("Error enabling phy supply\n");
+ return ret;
+ }
+ }
+#endif
+
#ifdef CONFIG_DM_PCI
/*
* If we are on PCI bus, either directly attached to a PCI root port,
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
- return PHY_INTERFACE_MODE_RGMII;
+ return PHY_INTERFACE_MODE_RGMII_TXID;
}
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
- return PHY_INTERFACE_MODE_RGMII;
+ return PHY_INTERFACE_MODE_RGMII_TXID;
}
/* handle SGMII */
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
- return PHY_INTERFACE_MODE_RGMII;
+ return PHY_INTERFACE_MODE_RGMII_TXID;
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
- return PHY_INTERFACE_MODE_RGMII;
+ return PHY_INTERFACE_MODE_RGMII_TXID;
/* handle SGMII, only MAC 2/5/6/9/10 available */
switch (port) {
#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
+#define MC_BOOT_ENV_VAR "mcinitcmd"
DECLARE_GLOBAL_DATA_PTR;
static int mc_boot_status = -1;
}
#endif
-static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
- struct eth_device *eth_dev)
+#define MC_DT_INCREASE_SIZE 64
+
+enum mc_fixup_type {
+ MC_FIXUP_DPL,
+ MC_FIXUP_DPC
+};
+
+static int mc_fixup_mac_addr(void *blob, int nodeoffset,
+ const char *propname, struct eth_device *eth_dev,
+ enum mc_fixup_type type)
{
- int nodeoffset, err = 0;
+ int err = 0, len = 0, size, i;
+ unsigned char env_enetaddr[ARP_HLEN];
+ unsigned int enetaddr_32[ARP_HLEN];
+ void *val = NULL;
+
+ switch (type) {
+ case MC_FIXUP_DPL:
+ /* DPL likes its addresses on 32 * ARP_HLEN bits */
+ for (i = 0; i < ARP_HLEN; i++)
+ enetaddr_32[i] = cpu_to_fdt32(eth_dev->enetaddr[i]);
+ val = enetaddr_32;
+ len = sizeof(enetaddr_32);
+ break;
+
+ case MC_FIXUP_DPC:
+ val = eth_dev->enetaddr;
+ len = ARP_HLEN;
+ break;
+ }
+
+ /* MAC address property present */
+ if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
+ /* u-boot MAC addr randomly assigned - leave the present one */
+ if (!eth_getenv_enetaddr_by_index("eth", eth_dev->index,
+ env_enetaddr))
+ return err;
+ } else {
+ size = MC_DT_INCREASE_SIZE + strlen(propname) + len;
+ /* make room for mac address property */
+ err = fdt_increase_size(blob, size);
+ if (err) {
+ printf("fdt_increase_size: err=%s\n",
+ fdt_strerror(err));
+ return err;
+ }
+ }
+
+ err = fdt_setprop(blob, nodeoffset, propname, val, len);
+ if (err) {
+ printf("fdt_setprop: err=%s\n", fdt_strerror(err));
+ return err;
+ }
+
+ return err;
+}
+
+#define is_dpni(s) (s != NULL ? !strncmp(s, "dpni@", 5) : 0)
+
+const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
+{
+ int connoffset = fdt_path_offset(blob, "/connections"), off;
+ const char *s1, *s2;
+
+ for (off = fdt_first_subnode(blob, connoffset);
+ off >= 0;
+ off = fdt_next_subnode(blob, off)) {
+ s1 = fdt_stringlist_get(blob, off, "endpoint1", 0, NULL);
+ s2 = fdt_stringlist_get(blob, off, "endpoint2", 0, NULL);
+
+ if (!s1 || !s2)
+ continue;
+
+ if (strcmp(endpoint, s1) == 0)
+ return s2;
+
+ if (strcmp(endpoint, s2) == 0)
+ return s1;
+ }
+
+ return NULL;
+}
+
+static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
+ struct eth_device *eth_dev)
+{
+ int objoff = fdt_path_offset(blob, "/objects");
+ int dpmacoff = -1, dpnioff = -1;
+ const char *endpoint;
char mac_name[10];
- const char link_type_mode[] = "FIXED_LINK";
- unsigned char env_enetaddr[6];
+ int err;
+
+ sprintf(mac_name, "dpmac@%d", dpmac_id);
+ dpmacoff = fdt_subnode_offset(blob, objoff, mac_name);
+ if (dpmacoff < 0)
+ /* dpmac not defined in DPL, so skip it. */
+ return 0;
+
+ err = mc_fixup_mac_addr(blob, dpmacoff, "mac_addr", eth_dev,
+ MC_FIXUP_DPL);
+ if (err) {
+ printf("Error fixing up dpmac mac_addr in DPL\n");
+ return err;
+ }
+
+ /* now we need to figure out if there is any
+ * DPNI connected to this MAC, so we walk the
+ * connection list
+ */
+ endpoint = dpl_get_connection_endpoint(blob, mac_name);
+ if (!is_dpni(endpoint))
+ return 0;
+
+ /* let's see if we can fixup the DPNI as well */
+ dpnioff = fdt_subnode_offset(blob, objoff, endpoint);
+ if (dpnioff < 0)
+ /* DPNI not defined in DPL in the objects area */
+ return 0;
+
+ return mc_fixup_mac_addr(blob, dpnioff, "mac_addr", eth_dev,
+ MC_FIXUP_DPL);
+}
+
+static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
+ struct eth_device *eth_dev)
+{
+ int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
+ int err = 0;
+ char mac_name[10];
+ const char link_type_mode[] = "MAC_LINK_TYPE_FIXED";
sprintf(mac_name, "mac@%d", dpmac_id);
/* node not found - create it */
- nodeoffset = fdt_subnode_offset(blob, noff, (const char *) mac_name);
- if (nodeoffset < 0) {
+ noff = fdt_subnode_offset(blob, nodeoffset, (const char *)mac_name);
+ if (noff < 0) {
err = fdt_increase_size(blob, 200);
if (err) {
printf("fdt_increase_size: err=%s\n",
return err;
}
- nodeoffset = fdt_add_subnode(blob, noff, mac_name);
+ noff = fdt_add_subnode(blob, nodeoffset, mac_name);
+ if (noff < 0) {
+ printf("fdt_add_subnode: err=%s\n",
+ fdt_strerror(err));
+ return err;
+ }
/* add default property of fixed link */
- err = fdt_appendprop_string(blob, nodeoffset,
+ err = fdt_appendprop_string(blob, noff,
"link_type", link_type_mode);
if (err) {
printf("fdt_appendprop_string: err=%s\n",
}
}
- /* port_mac_address property present in DPC */
- if (fdt_get_property(blob, nodeoffset, "port_mac_address", NULL)) {
- /* MAC addr randomly assigned - leave the one in DPC */
- eth_getenv_enetaddr_by_index("eth", eth_dev->index,
- env_enetaddr);
- if (is_zero_ethaddr(env_enetaddr))
- return err;
+ return mc_fixup_mac_addr(blob, noff, "port_mac_address", eth_dev,
+ MC_FIXUP_DPC);
+}
- /* replace DPC MAC address with u-boot env one */
- err = fdt_setprop(blob, nodeoffset, "port_mac_address",
- eth_dev->enetaddr, 6);
- if (err) {
- printf("fdt_setprop mac: err=%s\n", fdt_strerror(err));
- return err;
- }
+static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
+{
+ int i, err = 0, ret = 0;
+ char ethname[10];
+ struct eth_device *eth_dev;
- return 0;
- }
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+ /* port not enabled */
+ if ((wriop_is_enabled_dpmac(i) != 1) ||
+ (wriop_get_phy_address(i) == -1))
+ continue;
- /* append port_mac_address property to mac node in DPC */
- err = fdt_increase_size(blob, 80);
- if (err) {
- printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
- return err;
- }
+ sprintf(ethname, "DPMAC%d@%s", i,
+ phy_interface_strings[wriop_get_enet_if(i)]);
- err = fdt_appendprop(blob, nodeoffset,
- "port_mac_address", eth_dev->enetaddr, 6);
- if (err) {
- printf("fdt_appendprop: err=%s\n", fdt_strerror(err));
- return err;
+ eth_dev = eth_get_dev_by_name(ethname);
+ if (eth_dev == NULL)
+ continue;
+
+ switch (type) {
+ case MC_FIXUP_DPL:
+ err = mc_fixup_dpl_mac_addr(blob, i, eth_dev);
+ break;
+ case MC_FIXUP_DPC:
+ err = mc_fixup_dpc_mac_addr(blob, i, eth_dev);
+ break;
+ default:
+ break;
+ }
+
+ if (err)
+ printf("fsl-mc: ERROR fixing mac address for %s\n",
+ ethname);
+ ret |= err;
}
- return err;
+ return ret;
}
static int mc_fixup_dpc(u64 dpc_addr)
{
void *blob = (void *)dpc_addr;
int nodeoffset, err = 0;
- char ethname[10];
- struct eth_device *eth_dev;
- int i;
/* delete any existing ICID pools */
nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
/* fixup MAC addresses for dpmac ports */
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
if (nodeoffset < 0)
- goto out;
-
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- /* port not enabled */
- if ((wriop_is_enabled_dpmac(i) != 1) ||
- (wriop_get_phy_address(i) == -1))
- continue;
-
- sprintf(ethname, "DPMAC%d@%s", i,
- phy_interface_strings[wriop_get_enet_if(i)]);
-
- eth_dev = eth_get_dev_by_name(ethname);
- if (eth_dev == NULL)
- continue;
-
- err = mc_fixup_dpc_mac_addr(blob, nodeoffset, i, eth_dev);
- if (err) {
- printf("mc_fixup_dpc_mac_addr failed: err=%s\n",
- fdt_strerror(err));
- goto out;
- }
- }
+ return 0;
-out:
+ err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
return err;
return 0;
}
+
+static int mc_fixup_dpl(u64 dpl_addr)
+{
+ void *blob = (void *)dpl_addr;
+ u32 ver = fdt_getprop_u32_default(blob, "/", "dpl-version", 0);
+ int err = 0;
+
+ /* The DPL fixup for mac addresses is only relevant
+ * for old-style DPLs
+ */
+ if (ver >= 10)
+ return 0;
+
+ err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPL);
+ flush_dcache_range(dpl_addr, dpl_addr + fdt_totalsize(blob));
+
+ return err;
+}
+
static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
{
u64 mc_dpl_offset;
(u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
+ if (mc_fixup_dpl(mc_ram_addr + mc_dpl_offset))
+ return -EINVAL;
dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
return 0;
}
"fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
"fsl_mc start aiop [FW_addr] - Start AIOP\n"
);
+
+void mc_env_boot(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ char *mc_boot_env_var;
+ /* The MC may only be initialized in the reset PHY function
+ * because otherwise U-Boot has not yet set up all the MAC
+ * address info properly. Without MAC addresses, the MC code
+ * can not properly initialize the DPC.
+ */
+ mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
+#endif /* CONFIG_FSL_MC_ENET */
+}
name, status);
}
-#ifdef CONFIG_MACB_SEARCH_PHY
static int macb_phy_find(struct macb_device *macb, const char *name)
{
int i;
return 0;
}
-#endif /* CONFIG_MACB_SEARCH_PHY */
#ifdef CONFIG_DM_ETH
static int macb_phy_init(struct udevice *dev, const char *name)
int i;
arch_get_mdio_control(name);
-#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb, name))
return 0;
-#endif /* CONFIG_MACB_SEARCH_PHY */
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
* to select interface between RMII and MII.
*/
#ifdef CONFIG_DM_ETH
- if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
+ if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
+ (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
gem_writel(macb, UR, GEM_BIT(RGMII));
else
gem_writel(macb, UR, 0);
/* MPCS registers */
#define PCS40G_COMMON_CONTROL 0x14
-#define FORWARD_ERROR_CORRECTION_MASK BIT(1)
+#define FORWARD_ERROR_CORRECTION_MASK BIT(10)
#define PCS_CLOCK_RESET 0x14c
#define TX_SD_CLK_RESET_MASK BIT(0)
/* configure XG MAC mode */
val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
- val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+ val &= ~MVPP22_XPCS_PCSMODE_MASK;
val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
/* Set hw internals when starting port */
static void mvpp2_start_dev(struct mvpp2_port *port)
{
- mvpp2_gmac_max_rx_size_set(port);
+ switch (port->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_SGMII:
+ mvpp2_gmac_max_rx_size_set(port);
+ default:
+ break;
+ }
+
mvpp2_txp_max_tx_size_set(port);
if (port->priv->hw_version == MVPP21)
return err;
}
- err = mvpp2_phy_connect(dev, port);
- if (err < 0)
- return err;
+ if (port->phy_node) {
+ err = mvpp2_phy_connect(dev, port);
+ if (err < 0)
+ return err;
- mvpp2_link_event(port);
+ mvpp2_link_event(port);
+ } else {
+ mvpp2_egress_enable(port);
+ mvpp2_ingress_enable(port);
+ }
mvpp2_start_dev(port);
const char *phy_mode_str;
int phy_node;
u32 id;
- u32 phyaddr;
+ u32 phyaddr = 0;
int phy_mode = -1;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
- if (phy_node < 0) {
- dev_err(&pdev->dev, "missing phy\n");
- return -ENODEV;
+
+ if (phy_node > 0) {
+ phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
+ if (phyaddr < 0) {
+ dev_err(&pdev->dev, "could not find phy address\n");
+ return -1;
+ }
+ } else {
+ phy_node = 0;
}
phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
"phy-speed", 1000);
- phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
-
port->id = id;
if (port->priv->hw_version == MVPP21)
port->first_rxq = port->id * rxq_number;
/* Reconfigure parser accept the original MAC address */
mvpp2_prs_update_mac_da(port, port->dev_addr);
- mvpp2_port_power_up(port);
+ switch (port->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_SGMII:
+ mvpp2_port_power_up(port);
+ default:
+ break;
+ }
mvpp2_open(dev, port);
port->gop_id * MVPP22_PORT_OFFSET;
/* Set phy address of the port */
- mvpp22_smi_phy_addr_cfg(port);
+ if(port->phy_node)
+ mvpp22_smi_phy_addr_cfg(port);
/* GoP Init */
gop_port_init(port);
memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
for (i = 0; i < PCH_GBE_DESC_NUM; i++)
- rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev,
- (ulong)(priv->rx_buff[i]));
+ rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
+ priv->rx_buff[i]);
- writel(dm_pci_phys_to_mem(priv->dev, (ulong)rx_desc),
+ flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
+
+ writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
&mac_regs->rx_dsc_base);
writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->rx_dsc_size);
- writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_desc + 1)),
+ writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
&mac_regs->rx_dsc_sw_p);
}
memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
- writel(dm_pci_phys_to_mem(priv->dev, (ulong)tx_desc),
+ flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
+
+ writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
&mac_regs->tx_dsc_base);
writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->tx_dsc_size);
- writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_desc + 1)),
+ writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
&mac_regs->tx_dsc_sw_p);
}
u32 int_st;
ulong start;
+ flush_dcache_range((ulong)packet, (ulong)packet + length);
+
tx_head = &priv->tx_desc[0];
tx_desc = &priv->tx_desc[priv->tx_idx];
if (length < 64)
frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
- tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (ulong)packet);
+ tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
tx_desc->length = length;
tx_desc->tx_words_eob = length + 3;
tx_desc->tx_frame_ctrl = frame_ctrl;
tx_desc->dma_status = 0;
tx_desc->gbec_status = 0;
+ flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
+
/* Test the wrap-around condition */
if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
priv->tx_idx = 0;
- writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_head + priv->tx_idx)),
+ writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
&mac_regs->tx_dsc_sw_p);
start = get_timer(0);
struct pch_gbe_priv *priv = dev_get_priv(dev);
struct pch_gbe_regs *mac_regs = priv->mac_regs;
struct pch_gbe_rx_desc *rx_desc;
- ulong hw_desc, buffer_addr, length;
+ ulong hw_desc, length;
+ void *buffer;
rx_desc = &priv->rx_desc[priv->rx_idx];
hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
/* Just return if not receiving any packet */
- if ((ulong)rx_desc == hw_desc)
+ if (virt_to_phys(rx_desc) == hw_desc)
return -EAGAIN;
- buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr);
- *packetp = (uchar *)buffer_addr;
+ /* Invalidate the descriptor */
+ invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
+
length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
+ buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
+ invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
+ *packetp = (uchar *)buffer;
return length;
}
if (++rx_swp >= PCH_GBE_DESC_NUM)
rx_swp = 0;
- writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_head + rx_swp)),
+ writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
&mac_regs->rx_dsc_sw_p);
return 0;
struct pch_gbe_priv *priv;
struct eth_pdata *plat = dev_get_platdata(dev);
void *iobase;
+ int err;
/*
* The priv structure contains the descriptors and frame buffers which
pch_gbe_mdio_init(dev->name, priv->mac_regs);
priv->bus = miiphy_get_dev_by_name(dev->name);
+ err = pch_gbe_reset(dev);
+ if (err)
+ return err;
+
return pch_gbe_phy_init(dev);
}
config PHY_MICREL
bool "Micrel Ethernet PHYs support"
+ help
+ Enable support for the GbE PHYs manufactured by Micrel (now
+ a part of Microchip). This includes drivers for the KSZ804,
+ KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, KSZ8721
+ either/or KSZ9021 (see the "Micrel KSZ9021 family support"
+ config option for details), and KSZ9031 (if configured).
+
+if PHY_MICREL
+
+config PHY_MICREL_KSZ9021
+ bool "Micrel KSZ9021 family support"
+ select PHY_GIGE
+ help
+ Enable support for the Micrel KSZ9021 GbE PHY family. If
+ enabled, the extended register read/write for KSZ9021 PHYs
+ is supported through the 'mdio' command and any RGMII signal
+ delays configured in the device tree will be applied to the
+ PHY during initialisation.
+
+ Note that the KSZ9021 uses the same part number os the
+ KSZ8921BL, so enabling this option disables support for the
+ KSZ8721BL.
+
+config PHY_MICREL_KSZ9031
+ bool "Micrel KSZ9031 family support"
+ select PHY_GIGE
+ help
+ Enable support for the Micrel KSZ9031 GbE PHY family. If
+ enabled, the extended register read/write for KSZ9021 PHYs
+ is supported through the 'mdio' command and any RGMII signal
+ delays configured in the device tree will be applied to the
+ PHY during initialisatioin.
+
+endif # PHY_MICREL
config PHY_MSCC
bool "Microsemi Corp Ethernet PHYs support"
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+#define MII_MARVELL_PHY_PAGE 22
+
/* 88E1011 PHY Status Register */
#define MIIM_88E1xxx_PHY_STATUS 0x11
#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
#define MIIM_88E1310_PHY_PAGE 22
/* 88E151x PHY defines */
+/* Page 2 registers */
+#define MIIM_88E151x_PHY_MSCR 21
+#define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
+#define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
+#define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
/* Page 3 registers */
#define MIIM_88E151x_LED_FUNC_CTRL 16
#define MIIM_88E151x_LED_FLD_SZ 4
static int m88e1518_config(struct phy_device *phydev)
{
+ u16 reg;
+
/*
* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
* /88E1514 Rev A0, Errata Section 3.1
udelay(100);
}
- return m88e1111s_config(phydev);
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ reg = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR);
+
+ reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
+ reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
+ reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR, reg);
+ }
+
+ if (phy_interface_is_rgmii(phydev)) {
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
+ reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
+ else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ reg |= MIIM_88E151x_RGMII_RX_DELAY;
+ else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ reg |= MIIM_88E151x_RGMII_TX_DELAY;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
+ }
+
+ /* soft reset */
+ phy_reset(phydev);
+
+ genphy_config_aneg(phydev);
+ genphy_restart_aneg(phydev);
+
+ return 0;
}
/* Marvell 88E1510 */
int err;
err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, true);
+ true, 20000, false);
if (err)
return err;
writel(mgtcr, ®s->phymntnc);
err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, true);
+ true, 20000, false);
if (err)
return err;
dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
ZYNQ_GEM_RXBUF_NEW_MASK;
dummy_rx_bd->status = 0;
- flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
- sizeof(dummy_tx_bd));
- flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
- sizeof(dummy_rx_bd));
writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
static int zynq_gem_read_rom_mac(struct udevice *dev)
{
- int retval;
struct eth_pdata *pdata = dev_get_platdata(dev);
- retval = zynq_board_read_rom_ethaddr(pdata->enetaddr);
- if (retval == -ENOSYS)
- retval = 0;
+ if (!pdata)
+ return -ENOSYS;
- return retval;
+ return zynq_board_read_rom_ethaddr(pdata->enetaddr);
}
static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
*/
#include <common.h>
+#include <malloc.h>
#include <command.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#endif
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#include <mmc.h>
+#endif
+
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
qe_map_t *qe_immr = NULL;
{
qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
- u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+ void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+ if (mmc_initialize(gd->bd)) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return;
+ }
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ free(addr);
+ printf("\nMMC cannot find device for ucode\n");
+ } else {
+ printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
+ dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
+ /* flush cache after read */
+ flush_cache((ulong)addr, cnt * 512);
+ }
+#endif
+ u_qe_upload_firmware(addr);
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
+ free(addr);
+#endif
}
#endif
+config FS_FAT
+ bool "Enable FAT filesystem support"
+ help
+ This provides support for reading images from File Allocation Table
+ (FAT) filesystem. FAT filesystem is a legacy, lightweight filesystem.
+ It is useful mainly for its wide compatibility with various operating
+ systems. You can also enable CMD_FAT to get access to fat commands.
+
+config FAT_WRITE
+ bool "Enable FAT filesystem write support"
+ depends on FS_FAT
+ help
+ This provides support for creating and writing new files to an
+ existing FAT filesystem partition.
+
+config FS_FAT_MAX_CLUSTSIZE
+ int "Set maximum possible clusersize"
+ default 65536
+ depends on FS_FAT
+ help
+ Set the maximum possible clustersize for the FAT filesytem. This
+ is the smallest amount of disk space that can be used to hold a
+ file. Unless you have an extremely tight memory memory constraints,
+ leave the default.
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
-#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)
+#if defined(CONFIG_ENV_IS_IN_FAT) && !defined(CONFIG_FS_FAT)
#define CONFIG_FS_FAT
#endif
+#if defined(CONFIG_ENV_IS_IN_FAT) && !defined(CONFIG_FAT_WRITE)
+#define CONFIG_FAT_WRITE
+#endif
+
#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
!defined(CONFIG_FS_EXT4)
#define CONFIG_FS_EXT4
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
-/* Miscellaneous commands */
-#define CONFIG_FAT_WRITE
-
#undef CONFIG_IPADDR
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FAT_WRITE
#ifdef CONFIG_MX6Q
#define CONFIG_CMD_SATA
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
-/* Miscellaneous commands */
-#define CONFIG_FAT_WRITE
-
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
#else
/* u-boot env in sd/mmc card */
#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_FAT_WRITE
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_FAT_WRITE
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
#else
/* Use file in FAT file to save environment */
#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_FAT_WRITE
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_FAT_WRITE
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_FAT_WRITE
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_FILE "uboot.env"
#define FAT_ENV_DEVICE_AND_PART "0"
/* Initial upstream - boot to cmd prompt only */
#define CONFIG_BOOTCOMMAND ""
-/* Commands */
-#define CONFIG_FAT_WRITE
-
#undef CONFIG_USB_GADGET_VBUS_DRAW
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USBID_ADDR 0x34052c46
/* Initial upstream - boot to cmd prompt only */
#define CONFIG_BOOTCOMMAND ""
-/* Commands */
-#define CONFIG_FAT_WRITE
-
#define CONFIG_USBID_ADDR 0x34052c46
#endif /* __BCM28155_AP_H */
#define CONFIG_MX_CYCLIC
-/* Commands */
-#define CONFIG_FAT_WRITE
-
/* Enable Time Command */
/* Misc utility code */
* enabled a number of useful commands and support.
*/
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#endif /* CONFIG_MMC, ... */
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-/*
- * Common filesystems support. When we have removable storage we
- * enabled a number of useful commands and support.
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_FAT_WRITE
-#endif /* CONFIG_MMC, ... */
#endif /* __CONFIG_BRXRE1_H__ */
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FAT_WRITE
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_LZO
#define CONFIG_RBTREE
-/* Debug commands */
-
-/* Miscellaneous commands */
-#define CONFIG_FAT_WRITE
#define BOARD_EXTRA_ENV_SETTINGS \
"mtdparts=" MTDPARTS_DEFAULT "\0"
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
-/* Miscellaneous commands */
-#define CONFIG_FAT_WRITE
-
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
#undef CONFIG_SUPPORT_RAW_INITRD
-#undef CONFIG_FAT_WRITE
/* BOOTP/DHCP options */
#define CONFIG_BOOTP_SUBNETMASK
* Commands configuration
*/
#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
/*
* mv-plug-common.h should be defined after CMD configs since it used them
"led4=60,0,1\0" \
"led5=63,0,1\0"
-#undef CONFIG_CMD_FAT
-
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* PWM */
#define CONFIG_PWM
-/* Command definition*/
-#define CONFIG_FAT_WRITE
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "1:1"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
/* Monitor Command Prompt */
"name_uboot=u-boot-spi-k2e-evm.gph\0" \
"name_fs=arago-console-image-k2e-evm.cpio.gz\0"
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x100000
+
#include <configs/ti_armv7_keystone2.h>
/* SPL SPI Loader Configuration */
"get_pmmc_${boot} run_pmmc get_mon_${boot} run_mon " \
"get_fdt_${boot} get_kern_${boot} run_kern"
-#include <configs/ti_armv7_keystone2.h>
-
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c080000
#define CONFIG_PHY_MICREL
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
-#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_FAT
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#endif
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
+
+#include <configs/ti_armv7_keystone2.h>
+
#endif /* __CONFIG_K2G_EVM_H */
"name_uboot=u-boot-spi-k2hk-evm.gph\0" \
"name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x100000
+
#include <configs/ti_armv7_keystone2.h>
/* SPL SPI Loader Configuration */
"name_uboot=u-boot-spi-k2l-evm.gph\0" \
"name_fs=arago-console-image-k2l-evm.cpio.gz\0"
+#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x100000
+
#include <configs/ti_armv7_keystone2.h>
/* SPL SPI Loader Configuration */
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_FAT
-
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SPI_FLASH_SPANSION
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif
/*
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif
/*
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
+#define CONFIG_SYS_QE_FW_ADDR 0x60940000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
/* QE */
#ifndef SPL_NO_QE
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
- !defined(CONFIG_QSPI_BOOT)
+#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x60940000
#endif
/* USB */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_CMD_SCSI
-#ifndef CONFIG_CMD_FAT
-#define CONFIG_CMD_FAT
-#endif
#ifndef CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT2
#endif
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
/*
* Carve out a DDR region which will not be used by u-boot/Linux
*
"earlycon=uart8250,mmio,0x21c0500 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
+ " fsl_mc apply dpl 0x80200000 &&" \
+ " mmc read $kernel_load $kernel_start" \
+ " $kernel_size && bootm $kernel_load"
+#else
#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
+#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
+#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#endif
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_LBMAP_SD 0x00
#define QIXIS_LBMAP_QSPI 0x0f
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_SD 0x40
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_FORCE_MEM 0x01
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#if defined(CONFIG_SPL)
+#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET 0x200000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x20000
+#endif
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
"esbc_validate 0x580740000;" \
"fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x90100000\0" \
+ "kernel_addr=0x800\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x8000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x14000\0" \
+ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0" \
+ "mcmemsize=0x70000000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
#endif /* CONFIG_SECURE_BOOT */
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
-
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
/*
* U-Boot Commands
*/
-#define CONFIG_FAT_WRITE
-
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_SATA
#undef CONFIG_BOOTARGS
#define CONFIG_SYS_USE_SERIALFLASH 1
-/*
- * U-Boot Commands
- */
-#define CONFIG_FAT_WRITE
-
/*
* Memory configurations
*/
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE SZ_8K
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
#include "mx6_common.h"
/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SATA
*/
/* FAT FS */
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_FAT
-#define CONFIG_FAT_WRITE
/* EXT4 FS */
#define CONFIG_FS_EXT4
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_FAT_WRITE
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
#define CONFIG_CMD_SDRAM
/* Support File sytems */
-#define CONFIG_FAT_WRITE
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_SUPPORT_RAW_INITRD
/* Support File sytems */
-#define CONFIG_FAT_WRITE
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FAT_WRITE
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define SDRAM_BANK_SIZE (512UL << 20UL)
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FAT_WRITE
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define SDRAM_BANK_SIZE (2UL << 30)
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FAT_WRITE
-
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_FAT
-#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
/* RAW SD card / eMMC locations. */
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_FS_FAT
-#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
/* RAW SD card / eMMC locations. */
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_PREBOOT "usb start"
#define CONFIG_SYS_ONENAND_BASE 0xB0000000
/* write support for filesystems */
-#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
/* GPT */
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC"
-#if defined(CONFIG_CMD_USB)
-#define CONFIG_CMD_FAT
-#endif
-
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_FAT_WRITE
-#endif
-
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#if CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
#endif
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_FAT_WRITE
-#endif
-
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_CMD_PCI
-#define CONFIG_FS_FAT
-#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#define CONFIG_HOST_MAX_DEVICES 4
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_FS_FAT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Command line configuration */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define __CONFIG_SOCFGPA_ARRIA10_H__
#include <asm/arch/base_addr_a10.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
+
#define CONFIG_HW_WATCHDOG
/* Booting Linux */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_FAT_WRITE
-
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#include <asm/arch/base_addr_ac5.h>
-/* U-Boot Commands */
-#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
/* Memory configurations */
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
-#define CONFIG_FAT_WRITE /* enable write access */
-
#define CONFIG_SPL_FRAMEWORK
#ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */
#ifdef CONFIG_FS_EXT4
#undef CONFIG_FS_EXT4
#endif
-#ifdef CONFIG_FS_FAT
-#undef CONFIG_FS_FAT
-#endif
/* remove USB */
#ifdef CONFIG_USB_EHCI_TEGRA
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
-#define CONFIG_FAT_WRITE
#endif
#endif /* _TEGRA_COMMON_H_ */
#define CONFIG_CMD_ASKENV
-#define CONFIG_FS_FAT
-
/*
* Only one of the following two options (DDR3/DDR2) should be enabled
* CONFIG_TI816X_EVM_DDR2
#define CONFIG_SUPPORT_RAW_INITRD
-/*
- * Common filesystems support. When we have removable storage we
- * enabled a number of useful commands and support.
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_FAT_WRITE
-#endif
-
/*
* Our platforms make use of SPL to initalize the hardware (primarily
* memory) enough for full U-Boot to be loaded. We make use of the general
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_FS_FAT
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
/* USB */
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
-#define CONFIG_FAT_WRITE
/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
# define FAT_ENV_INTERFACE "mmc"
#endif
-#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQMP_USB)
-# define CONFIG_FAT_WRITE
-#endif
-
#ifdef CONFIG_NAND_ARASAN
# define CONFIG_CMD_NAND_LOCK_UNLOCK
# define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MMC_SDHCI_ZYNQ) || defined(CONFIG_ZYNQ_USB)
# define CONFIG_SUPPORT_VFAT
-# define CONFIG_FAT_WRITE
#endif
#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
--- /dev/null
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_BUS_MIPI_DSI 28
+#define CLK_BUS_CE 29
+#define CLK_BUS_DMA 30
+#define CLK_BUS_MMC0 31
+#define CLK_BUS_MMC1 32
+#define CLK_BUS_MMC2 33
+#define CLK_BUS_NAND 34
+#define CLK_BUS_DRAM 35
+#define CLK_BUS_EMAC 36
+#define CLK_BUS_TS 37
+#define CLK_BUS_HSTIMER 38
+#define CLK_BUS_SPI0 39
+#define CLK_BUS_SPI1 40
+#define CLK_BUS_OTG 41
+#define CLK_BUS_EHCI0 42
+#define CLK_BUS_EHCI1 43
+#define CLK_BUS_OHCI0 44
+#define CLK_BUS_OHCI1 45
+#define CLK_BUS_VE 46
+#define CLK_BUS_TCON0 47
+#define CLK_BUS_TCON1 48
+#define CLK_BUS_DEINTERLACE 49
+#define CLK_BUS_CSI 50
+#define CLK_BUS_HDMI 51
+#define CLK_BUS_DE 52
+#define CLK_BUS_GPU 53
+#define CLK_BUS_MSGBOX 54
+#define CLK_BUS_SPINLOCK 55
+#define CLK_BUS_CODEC 56
+#define CLK_BUS_SPDIF 57
+#define CLK_BUS_PIO 58
+#define CLK_BUS_THS 59
+#define CLK_BUS_I2S0 60
+#define CLK_BUS_I2S1 61
+#define CLK_BUS_I2S2 62
+#define CLK_BUS_I2C0 63
+#define CLK_BUS_I2C1 64
+#define CLK_BUS_I2C2 65
+#define CLK_BUS_SCR 66
+#define CLK_BUS_UART0 67
+#define CLK_BUS_UART1 68
+#define CLK_BUS_UART2 69
+#define CLK_BUS_UART3 70
+#define CLK_BUS_UART4 71
+#define CLK_BUS_DBG 72
+#define CLK_THS 73
+#define CLK_NAND 74
+#define CLK_MMC0 75
+#define CLK_MMC1 76
+#define CLK_MMC2 77
+#define CLK_TS 78
+#define CLK_CE 79
+#define CLK_SPI0 80
+#define CLK_SPI1 81
+#define CLK_I2S0 82
+#define CLK_I2S1 83
+#define CLK_I2S2 84
+#define CLK_SPDIF 85
+#define CLK_USB_PHY0 86
+#define CLK_USB_PHY1 87
+#define CLK_USB_HSIC 88
+#define CLK_USB_HSIC_12M 89
+
+#define CLK_USB_OHCI0 91
+
+#define CLK_USB_OHCI1 93
+
+#define CLK_DRAM_VE 95
+#define CLK_DRAM_CSI 96
+#define CLK_DRAM_DEINTERLACE 97
+#define CLK_DRAM_TS 98
+#define CLK_DE 99
+#define CLK_TCON0 100
+#define CLK_TCON1 101
+#define CLK_DEINTERLACE 102
+#define CLK_CSI_MISC 103
+#define CLK_CSI_SCLK 104
+#define CLK_CSI_MCLK 105
+#define CLK_VE 106
+#define CLK_AC_DIG 107
+#define CLK_AC_DIG_4X 108
+#define CLK_AVS 109
+#define CLK_HDMI 110
+#define CLK_HDMI_DDC 111
+
+#define CLK_DSI_DPHY 113
+#define CLK_GPU 114
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_HSIC 2
+#define RST_DRAM 3
+#define RST_MBUS 4
+#define RST_BUS_MIPI_DSI 5
+#define RST_BUS_CE 6
+#define RST_BUS_DMA 7
+#define RST_BUS_MMC0 8
+#define RST_BUS_MMC1 9
+#define RST_BUS_MMC2 10
+#define RST_BUS_NAND 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_EMAC 13
+#define RST_BUS_TS 14
+#define RST_BUS_HSTIMER 15
+#define RST_BUS_SPI0 16
+#define RST_BUS_SPI1 17
+#define RST_BUS_OTG 18
+#define RST_BUS_EHCI0 19
+#define RST_BUS_EHCI1 20
+#define RST_BUS_OHCI0 21
+#define RST_BUS_OHCI1 22
+#define RST_BUS_VE 23
+#define RST_BUS_TCON0 24
+#define RST_BUS_TCON1 25
+#define RST_BUS_DEINTERLACE 26
+#define RST_BUS_CSI 27
+#define RST_BUS_HDMI0 28
+#define RST_BUS_HDMI1 29
+#define RST_BUS_DE 30
+#define RST_BUS_GPU 31
+#define RST_BUS_MSGBOX 32
+#define RST_BUS_SPINLOCK 33
+#define RST_BUS_DBG 34
+#define RST_BUS_LVDS 35
+#define RST_BUS_CODEC 36
+#define RST_BUS_SPDIF 37
+#define RST_BUS_THS 38
+#define RST_BUS_I2S0 39
+#define RST_BUS_I2S1 40
+#define RST_BUS_I2S2 41
+#define RST_BUS_I2C0 42
+#define RST_BUS_I2C1 43
+#define RST_BUS_I2C2 44
+#define RST_BUS_SCR 45
+#define RST_BUS_UART0 46
+#define RST_BUS_UART1 47
+#define RST_BUS_UART2 48
+#define RST_BUS_UART3 49
+#define RST_BUS_UART4 50
+
+#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
#define PREFETCH_BLOCKS 2
-#ifndef CONFIG_FS_FAT_MAX_CLUSTSIZE
-#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
-#endif
#define MAX_CLUSTSIZE CONFIG_FS_FAT_MAX_CLUSTSIZE
#define DIRENTSPERBLOCK (mydata->sect_size / sizeof(dir_entry))
unsigned long mc_get_dram_block_size(void);
int fsl_mc_ldpaa_init(bd_t *bis);
int fsl_mc_ldpaa_exit(bd_t *bd);
+void mc_env_boot(void);
#endif
static int eth_write_hwaddr(struct udevice *dev)
{
- struct eth_pdata *pdata = dev->platdata;
+ struct eth_pdata *pdata;
int ret = 0;
if (!dev || !device_active(dev))
/* seq is valid since the device is active */
if (eth_get_ops(dev)->write_hwaddr && !eth_mac_skip(dev->seq)) {
+ pdata = dev->platdata;
if (!is_valid_ethaddr(pdata->enetaddr)) {
printf("\nError: %s address %pM illegal value\n",
dev->name, pdata->enetaddr);
CONFIG_FASTBOOT_FLASH_NAND_DEV
CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS
CONFIG_FAST_FLASH_BIT
-CONFIG_FAT_WRITE
CONFIG_FB_ADDR
CONFIG_FB_BACKLIGHT
CONFIG_FB_DEFERRED_IO
CONFIG_FSMTDBLK
CONFIG_FSNOTIFY
CONFIG_FS_EXT4
-CONFIG_FS_FAT
-CONFIG_FS_FAT_MAX_CLUSTSIZE
CONFIG_FS_POSIX_ACL
CONFIG_FTAHBC020S
CONFIG_FTAHBC020S_BASE
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