struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_pin_io io;
 };
 
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,               \
                        PMUX_FUNC_ ## f1,               \
 
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_pin_io io;
 };
 
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,               \
                        PMUX_FUNC_ ## f1,               \
 
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_ctlid ctl_id;
        enum pmux_pullid pull_id;
 };
 /* Convenient macro for defining pin group properties */
 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd)                \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,                       \
                        PMUX_FUNC_ ## f1,                       \
 
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_pin_io io;
 };
 
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,               \
                        PMUX_FUNC_ ## f1,               \
 
                                (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
                                ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE -1
 #define PGRP_SLWF_MAX  3
 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
 
                                (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
                                ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE -1
 #define PGRP_SLWF_MAX  3
 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
 
        PMUX_TRI_TRISTATE = 1,
 };
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-
-       PMUX_VDDIO_NONE
-};
-
 enum {
        PMUX_TRISTATE_REGS      = 4,
        PMUX_MUX_REGS           = 7,
 
                                (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
                                ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE -1
 #define PGRP_SLWF_MAX  3
 #define        PGRP_SLWR_NONE  PGRP_SLWF_NONE