]> git.sur5r.net Git - u-boot/commitdiff
ARM: tegra: pinctrl: remove vddio
authorStephen Warren <swarren@nvidia.com>
Fri, 21 Mar 2014 18:28:50 +0000 (12:28 -0600)
committerTom Warren <twarren@nvidia.com>
Thu, 17 Apr 2014 15:41:05 +0000 (08:41 -0700)
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/tegra114-common/pinmux.c
arch/arm/cpu/tegra124-common/pinmux.c
arch/arm/cpu/tegra20-common/pinmux.c
arch/arm/cpu/tegra30-common/pinmux.c
arch/arm/include/asm/arch-tegra114/pinmux.h
arch/arm/include/asm/arch-tegra124/pinmux.h
arch/arm/include/asm/arch-tegra20/pinmux.h
arch/arm/include/asm/arch-tegra30/pinmux.h

index 7bf494c49a4d476a270bb5c71cc00b8cb5e30cc2..e83a29f43a5f641be597a227ca43bab5c7943a8f 100644 (file)
@@ -24,7 +24,6 @@
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_pin_io io;
 };
 
@@ -54,7 +53,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,               \
                        PMUX_FUNC_ ## f1,               \
index b1ac59e5b3c93ca3ce1f73faee0a799cff7f6eca..921dd2119b10c1f84255516fe37c8b169f0ad105 100644 (file)
@@ -15,7 +15,6 @@
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_pin_io io;
 };
 
@@ -45,7 +44,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,               \
                        PMUX_FUNC_ ## f1,               \
index 1f04d9c7ff7d1ade2f645920a479230da9afd34d..40301e13c29df3019da84e858aff5f645bb87046 100644 (file)
@@ -259,7 +259,6 @@ enum pmux_pullid {
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_ctlid ctl_id;
        enum pmux_pullid pull_id;
 };
@@ -286,7 +285,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd)                \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,                       \
                        PMUX_FUNC_ ## f1,                       \
index 6fd424981c23795ef01892b19bfac907327f0ee4..8eca0dd65485eb8910dbb9c327425263048d5bb5 100644 (file)
@@ -24,7 +24,6 @@
 struct tegra_pingroup_desc {
        const char *name;
        enum pmux_func funcs[4];
-       enum pmux_vddio vddio;
        enum pmux_pin_io io;
 };
 
@@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
                        PMUX_FUNC_ ## f0,               \
                        PMUX_FUNC_ ## f1,               \
index edf1a89ce1112027ed30602e80f412c783fd91e1..93d2ca525cec26b7415281af2d4543794c860c79 100644 (file)
@@ -449,27 +449,6 @@ enum pmux_pin_rcv_sel {
                                (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
                                ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE -1
 #define PGRP_SLWF_MAX  3
 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
index f51f44a54a24315d1159c2647b84a5d4ba86aacc..2042f1f7e5a394288a5f882d2f40a0239fd3184f 100644 (file)
@@ -458,27 +458,6 @@ enum pmux_pin_rcv_sel {
                                (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
                                ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE -1
 #define PGRP_SLWF_MAX  3
 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
index 3374d9c40f129dcffa76a5411a02570042d34c94..2bfaf53d349d9543864f8846f8bba797b94fa52c 100644 (file)
@@ -257,21 +257,6 @@ enum pmux_tristate {
        PMUX_TRI_TRISTATE = 1,
 };
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-
-       PMUX_VDDIO_NONE
-};
-
 enum {
        PMUX_TRISTATE_REGS      = 4,
        PMUX_MUX_REGS           = 7,
index ff2511e8774f3bb0817e5935b2e7198b88a09b5d..0704e4d4d4a1d0a76f488e6a84a3f66430628a41 100644 (file)
@@ -509,27 +509,6 @@ enum pmux_pin_ioreset {
                                (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
                                ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
 
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
 #define PGRP_SLWF_NONE -1
 #define PGRP_SLWF_MAX  3
 #define        PGRP_SLWR_NONE  PGRP_SLWF_NONE