]> git.sur5r.net Git - u-boot/commitdiff
ppc_4xx: Apply new HW register names
authorNiklaus Giger <niklaus.giger@member.fsf.org>
Sun, 4 Oct 2009 18:04:20 +0000 (20:04 +0200)
committerStefan Roese <sr@denx.de>
Wed, 7 Oct 2009 07:15:20 +0000 (09:15 +0200)
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
34 files changed:
board/amcc/bamboo/bamboo.c
board/amcc/canyonlands/canyonlands.c
board/amcc/ebony/ebony.c
board/amcc/katmai/katmai.c
board/amcc/luan/epld.h
board/amcc/luan/luan.c
board/amcc/ocotea/ocotea.c
board/amcc/sequoia/sequoia.c
board/amcc/taishan/showinfo.c
board/amcc/taishan/taishan.c
board/amcc/yosemite/yosemite.c
board/amcc/yucca/yucca.c
board/esd/common/cmd_loadpci.c
board/esd/du440/du440.c
board/esd/pmc440/cmd_pmc440.c
board/esd/pmc440/pmc440.c
board/exbitgen/init.S
board/gdsys/gdppc440etx/gdppc440etx.c
board/gdsys/intip/intip.c
board/korat/korat.c
board/lwmon5/lwmon5.c
board/netstal/hcu5/hcu5.c
board/pcs440ep/pcs440ep.c
board/prodrive/alpr/alpr.c
board/prodrive/p3p440/p3p440.c
board/sandburst/common/ppc440gx_i2c.h
board/sandburst/common/sb_common.c
board/xes/xpedite1000/xpedite1000.c
cpu/ppc4xx/4xx_pci.c
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/miiphy.c
cpu/ppc4xx/speed.c
drivers/net/4xx_enet.c
post/cpu/ppc4xx/ether.c

index 38186a5d37894a77008cc8ec22e012bb37961f45..2598f2cf41d703abeb210c487144bc098b9e9b3a 100644 (file)
@@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers
index 9495b621aca6948542c6fd151832155b4d172129..91fae1917dd12fdbd7587b60fec8410e41707e00 100644 (file)
@@ -339,27 +339,27 @@ void pci_target_init(struct pci_controller * hose )
        /*
         * Disable everything
         */
-       out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-       out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
        /*
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         */
-       out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out_le32((void *)PCIX0_PIM0LAH, 0);
-       out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-       out_le32((void *)PCIX0_BAR0, 0);
+       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out_le32((void *)PCIL0_PIM0LAH, 0);
+       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out_le32((void *)PCIL0_BAR0, 0);
 
        /*
         * Program the board's subsystem id/vendor id
         */
-       out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index e61b5de2d84b5261807eb2d58fea98302484226b..0ca1accec8d86dc9f9b9ec15034101614714758b 100644 (file)
@@ -210,28 +210,28 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0SA, 0);        /* disable */
-       out32r(PCIX0_PIM1SA, 0);        /* disable */
-       out32r(PCIX0_PIM2SA, 0);        /* disable */
-       out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
+       out32r(PCIL0_PIM0SA, 0);        /* disable */
+       out32r(PCIL0_PIM1SA, 0);        /* disable */
+       out32r(PCIL0_PIM2SA, 0);        /* disable */
+       out32r(PCIL0_EROMBA, 0);        /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
      * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIX0_PIM0LAH, 0);
-       out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out32r(PCIL0_PIM0LAH, 0);
+       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-       out32r(PCIX0_BAR0, 0);
+       out32r(PCIL0_BAR0, 0);
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index aa6d0abddb8a5445614a015368e28ba61455a4b3..908f1a5953c423ec457ecc7784fe358e44879a6a 100644 (file)
@@ -305,27 +305,27 @@ void pci_target_init(struct pci_controller * hose )
        /*-------------------------------------------------------------------+
         * Disable everything
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*-------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*-------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *-------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 05362e06d78fbaf42a0ea5f7a9d5ba3556d98fe9..569d78c46227a08abcf2c2a66580e8c5cab2e8b6 100644 (file)
@@ -8,8 +8,8 @@
 #define EPLD0_FLASH_SRAM_SEL_N 0x01    /* 0 SRAM at mem top, 1 small flash at mem top */
 
 #define EPLD1_CLK_CNTL0                0x80    /* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIX0_CNTL1      0x40    /* S*0 of 9531 */
-#define EPLD1_PCIX0_CNTL2      0x20    /* S*1 of 9531 */
+#define EPLD1_PCIL0_CNTL1      0x40    /* S*0 of 9531 */
+#define EPLD1_PCIL0_CNTL2      0x20    /* S*1 of 9531 */
 #define EPLD1_CLK_CNTL3                0x10    /* FSEL-B1 of MPC9772 */
 #define EPLD1_CLK_CNTL4                0x08    /* FSEL-B0 of MPC9772 */
 #define EPLD1_MASTER_CLOCK6    0x04    /* clock source select 6 */
 #define EPLD3_STATUS_LED2      0x02    /* status LED 2 (1 = LED on) */
 #define EPLD3_STATUS_LED1      0x01    /* status LED 1 (1 = LED on) */
 
-#define EPLD4_PCIX0_VTH1       0x80    /* PCI-X 0 VTH1 status */
-#define EPLD4_PCIX0_VTH2       0x40    /* PCI-X 0 VTH2 status */
-#define EPLD4_PCIX0_VTH3       0x20    /* PCI-X 0 VTH3 status */
-#define EPLD4_PCIX0_VTH4       0x10    /* PCI-X 0 VTH4 status */
+#define EPLD4_PCIL0_VTH1       0x80    /* PCI-X 0 VTH1 status */
+#define EPLD4_PCIL0_VTH2       0x40    /* PCI-X 0 VTH2 status */
+#define EPLD4_PCIL0_VTH3       0x20    /* PCI-X 0 VTH3 status */
+#define EPLD4_PCIL0_VTH4       0x10    /* PCI-X 0 VTH4 status */
 #define EPLD4_PCIX1_VTH1       0x08    /* PCI-X 1 VTH1 status */
 #define EPLD4_PCIX1_VTH2       0x04    /* PCI-X 1 VTH2 status */
 #define EPLD4_PCIX1_VTH3       0x02    /* PCI-X 1 VTH3 status */
 #define EPLD4_PCIX1_VTH4       0x01    /* PCI-X 1 VTH4 status */
 
-#define EPLD5_PCIX0_INT0       0x80    /* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIX0_INT1       0x40    /* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIX0_INT2       0x20    /* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIX0_INT3       0x10    /* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIL0_INT0       0x80    /* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIL0_INT1       0x40    /* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIL0_INT2       0x20    /* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIL0_INT3       0x10    /* PCIX0 INT3 status, write 0 to reset */
 #define EPLD5_PCIX1_INT0       0x08    /* PCIX1 INT0 status, write 0 to reset */
 #define EPLD5_PCIX1_INT1       0x04    /* PCIX1 INT1 status, write 0 to reset */
 #define EPLD5_PCIX1_INT2       0x02    /* PCIX1 INT2 status, write 0 to reset */
 #define EPLD5_PCIX1_INT3       0x01    /* PCIX1 INT3 status, write 0 to reset */
 
-#define EPLD6_PCIX0_RESET_CTL  0x80    /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIL0_RESET_CTL  0x80    /* 0=enable slot reset, 1=disable slot reset */
 #define EPLD6_PCIX1_RESET_CTL  0x40    /* 0=enable slot reset, 1=disable slot reset */
 #define EPLD6_ETH_INT_MODE     0x20    /* 0=IRQ5 recv's external eth int */
 #define EPLD6_PCIX2_RESET_CTL  0x10    /* 0=enable slot reset, 1=disable slot reset */
index 5f76672fb522a04e77c34a6710ed98ef908d6271..a04f2af3b8dc02834b3f8959859dcd6b3fbde24d 100644 (file)
@@ -173,28 +173,28 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index d776edabcda75543842997197cefa9bd1ddc9ae4..0aa317ec0e4e7403deb1b29aa011b1c4752b96a3 100644 (file)
@@ -321,28 +321,28 @@ void pci_target_init(struct pci_controller * hose )
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 17f831c3f41f1999f5868c8ff81d9758abf2cc8a..d42c802538c87bf75e201406b676840d15879d1e 100644 (file)
@@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index e4e441b319d4f838f83bd7eca81ba5d45c7135c6..a9a80e5b6e3baeebb5643ec7da76cc75d68597e2 100644 (file)
@@ -39,13 +39,13 @@ void show_reset_reg(void)
        mfcpr(CPR0_PLLD,reg);
        printf("cpr_plld   = %#010lx\n",reg);
 
-       mfcpr(CPR0_PRIMAD,reg);
+       mfcpr(CPR0_PRIMAD0,reg);
        printf("cpr_primad = %#010lx\n",reg);
 
-       mfcpr(CPR0_PRIMBD,reg);
+       mfcpr(CPR0_PRIMBD0,reg);
        printf("cpr_primbd = %#010lx\n",reg);
 
-       mfcpr(CPR0_OPBD,reg);
+       mfcpr(CPR0_OPBD0,reg);
        printf("cpr_opbd   = %#010lx\n",reg);
 
        mfcpr(CPR0_PERD,reg);
@@ -106,59 +106,59 @@ void show_xbridge_info(void)
        printf("SDR0_XPLLD  = %#010lx\n", reg);
 
        printf("PCI-X Bridge Configure registers\n");
-       printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
-       printf("PCIX0_DEVID             = %#06x\n", in16r(PCIX0_DEVID));
-       printf("PCIX0_CMD               = %#06x\n", in16r(PCIX0_CMD));
-       printf("PCIX0_STATUS            = %#06x\n", in16r(PCIX0_STATUS));
-       printf("PCIX0_REVID             = %#04x\n", in8(PCIX0_REVID));
-       printf("PCIX0_CACHELS           = %#04x\n", in8(PCIX0_CACHELS));
-       printf("PCIX0_LATTIM            = %#04x\n", in8(PCIX0_LATTIM));
-       printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
-       printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));
-
-       printf("PCIX0_BAR0              = %#010lx\n", in32r(PCIX0_BAR0));
-       printf("PCIX0_BAR1              = %#010lx\n", in32r(PCIX0_BAR1));
-       printf("PCIX0_BAR2              = %#010lx\n", in32r(PCIX0_BAR2));
-       printf("PCIX0_BAR3              = %#010lx\n", in32r(PCIX0_BAR3));
-       printf("PCIX0_BAR4              = %#010lx\n", in32r(PCIX0_BAR4));
-       printf("PCIX0_BAR5              = %#010lx\n", in32r(PCIX0_BAR5));
-
-       printf("PCIX0_CISPTR            = %#010lx\n", in32r(PCIX0_CISPTR));
-       printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
-       printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
-       printf("PCIX0_EROMBA            = %#010lx\n", in32r(PCIX0_EROMBA));
-       printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
-       printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
-       printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
-       printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
-       printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));
-
-       printf("PCIX0_BRDGOPT1          = %#010lx\n", in32r(PCIX0_BRDGOPT1));
-       printf("PCIX0_BRDGOPT2          = %#010lx\n", in32r(PCIX0_BRDGOPT2));
-
-       printf("PCIX0_POM0LAL           = %#010lx\n", in32r(PCIX0_POM0LAL));
-       printf("PCIX0_POM0LAH           = %#010lx\n", in32r(PCIX0_POM0LAH));
-       printf("PCIX0_POM0SA            = %#010lx\n", in32r(PCIX0_POM0SA));
-       printf("PCIX0_POM0PCILAL        = %#010lx\n", in32r(PCIX0_POM0PCIAL));
-       printf("PCIX0_POM0PCILAH        = %#010lx\n", in32r(PCIX0_POM0PCIAH));
-       printf("PCIX0_POM1LAL           = %#010lx\n", in32r(PCIX0_POM1LAL));
-       printf("PCIX0_POM1LAH           = %#010lx\n", in32r(PCIX0_POM1LAH));
-       printf("PCIX0_POM1SA            = %#010lx\n", in32r(PCIX0_POM1SA));
-       printf("PCIX0_POM1PCILAL        = %#010lx\n", in32r(PCIX0_POM1PCIAL));
-       printf("PCIX0_POM1PCILAH        = %#010lx\n", in32r(PCIX0_POM1PCIAH));
-       printf("PCIX0_POM2SA            = %#010lx\n", in32r(PCIX0_POM2SA));
-
-       printf("PCIX0_PIM0SA            = %#010lx\n", in32r(PCIX0_PIM0SA));
-       printf("PCIX0_PIM0LAL           = %#010lx\n", in32r(PCIX0_PIM0LAL));
-       printf("PCIX0_PIM0LAH           = %#010lx\n", in32r(PCIX0_PIM0LAH));
-       printf("PCIX0_PIM1SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
-       printf("PCIX0_PIM1LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
-       printf("PCIX0_PIM1LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
-       printf("PCIX0_PIM2SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
-       printf("PCIX0_PIM2LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
-       printf("PCIX0_PIM2LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
-
-       printf("PCIX0_XSTS              = %#010lx\n", in32r(PCIX0_STS));
+       printf("PCIL0_VENDID            = %#06x\n", in16r(PCIL0_VENDID));
+       printf("PCIL0_DEVID             = %#06x\n", in16r(PCIL0_DEVID));
+       printf("PCIL0_CMD               = %#06x\n", in16r(PCIL0_CMD));
+       printf("PCIL0_STATUS            = %#06x\n", in16r(PCIL0_STATUS));
+       printf("PCIL0_REVID             = %#04x\n", in8(PCIL0_REVID));
+       printf("PCIL0_CACHELS           = %#04x\n", in8(PCIL0_CACHELS));
+       printf("PCIL0_LATTIM            = %#04x\n", in8(PCIL0_LATTIM));
+       printf("PCIL0_HDTYPE            = %#04x\n", in8(PCIL0_HDTYPE));
+       printf("PCIL0_BIST              = %#04x\n", in8(PCIL0_BIST));
+
+       printf("PCIL0_BAR0              = %#010lx\n", in32r(PCIL0_BAR0));
+       printf("PCIL0_BAR1              = %#010lx\n", in32r(PCIL0_BAR1));
+       printf("PCIL0_BAR2              = %#010lx\n", in32r(PCIL0_BAR2));
+       printf("PCIL0_BAR3              = %#010lx\n", in32r(PCIL0_BAR3));
+       printf("PCIL0_BAR4              = %#010lx\n", in32r(PCIL0_BAR4));
+       printf("PCIL0_BAR5              = %#010lx\n", in32r(PCIL0_BAR5));
+
+       printf("PCIL0_CISPTR            = %#010lx\n", in32r(PCIL0_CISPTR));
+       printf("PCIL0_SBSSYSVID         = %#010x\n", in16r(PCIL0_SBSYSVID));
+       printf("PCIL0_SBSSYSID          = %#010x\n", in16r(PCIL0_SBSYSID));
+       printf("PCIL0_EROMBA            = %#010lx\n", in32r(PCIL0_EROMBA));
+       printf("PCIL0_CAP               = %#04x\n", in8(PCIL0_CAP));
+       printf("PCIL0_INTLN             = %#04x\n", in8(PCIL0_INTLN));
+       printf("PCIL0_INTPN             = %#04x\n", in8(PCIL0_INTPN));
+       printf("PCIL0_MINGNT            = %#04x\n", in8(PCIL0_MINGNT));
+       printf("PCIL0_MAXLTNCY          = %#04x\n", in8(PCIL0_MAXLTNCY));
+
+       printf("PCIL0_BRDGOPT1          = %#010lx\n", in32r(PCIL0_BRDGOPT1));
+       printf("PCIL0_BRDGOPT2          = %#010lx\n", in32r(PCIL0_BRDGOPT2));
+
+       printf("PCIL0_POM0LAL           = %#010lx\n", in32r(PCIL0_POM0LAL));
+       printf("PCIL0_POM0LAH           = %#010lx\n", in32r(PCIL0_POM0LAH));
+       printf("PCIL0_POM0SA            = %#010lx\n", in32r(PCIL0_POM0SA));
+       printf("PCIL0_POM0PCILAL        = %#010lx\n", in32r(PCIL0_POM0PCIAL));
+       printf("PCIL0_POM0PCILAH        = %#010lx\n", in32r(PCIL0_POM0PCIAH));
+       printf("PCIL0_POM1LAL           = %#010lx\n", in32r(PCIL0_POM1LAL));
+       printf("PCIL0_POM1LAH           = %#010lx\n", in32r(PCIL0_POM1LAH));
+       printf("PCIL0_POM1SA            = %#010lx\n", in32r(PCIL0_POM1SA));
+       printf("PCIL0_POM1PCILAL        = %#010lx\n", in32r(PCIL0_POM1PCIAL));
+       printf("PCIL0_POM1PCILAH        = %#010lx\n", in32r(PCIL0_POM1PCIAH));
+       printf("PCIL0_POM2SA            = %#010lx\n", in32r(PCIL0_POM2SA));
+
+       printf("PCIL0_PIM0SA            = %#010lx\n", in32r(PCIL0_PIM0SA));
+       printf("PCIL0_PIM0LAL           = %#010lx\n", in32r(PCIL0_PIM0LAL));
+       printf("PCIL0_PIM0LAH           = %#010lx\n", in32r(PCIL0_PIM0LAH));
+       printf("PCIL0_PIM1SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+       printf("PCIL0_PIM1LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+       printf("PCIL0_PIM1LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+       printf("PCIL0_PIM2SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+       printf("PCIL0_PIM2LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+       printf("PCIL0_PIM2LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+
+       printf("PCIL0_XSTS              = %#010lx\n", in32r(PCIL0_STS));
 }
 
 int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
index 4a0573eb3804b5cc5eb4c909d0d37f995395f66a..0c20faf9ab6804f1bd2424a839db595c941be52c 100644 (file)
@@ -254,28 +254,28 @@ void pci_target_init(struct pci_controller * hose )
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 1ec13eb6b56d19772b4d0e4c280c73096da67724..7ceccfa9b90e6f259a88677ea9e3f41e35ea281c 100644 (file)
@@ -408,22 +408,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers
index 5c9d49178cf61c8ea0543a9d7d326bbddd333cb4..d8f4bcbb17ddf9812b9cbb2c465ff355b24db586 100644 (file)
@@ -633,27 +633,27 @@ void pci_target_init(struct pci_controller * hose )
        /*-------------------------------------------------------------------+
         * Disable everything
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*-------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*-------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *-------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 47e946f116a32ea46228a9fc21a4b21027280755..eecae0a7fd1803864f6a3146bcde3b0d919afa97 100644 (file)
@@ -48,7 +48,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        u32 la, ptm1la;
 
 #if defined(CONFIG_440)
-       ptm1la = in32r(PCIX0_PTM1LA);
+       ptm1la = in32r(PCIL0_PTM1LA);
 #else
        ptm1la = in32r(PTM1LA);
 #endif
index 056f455d687ba27a9aa34fe4470ffd999bc07f74..d0e52cbab3911a0464af3b32d756be322dab29f0 100644 (file)
@@ -435,26 +435,26 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index 1af431bd7d135e342279bb634d692ce85c8861ae..476e94096291855806cd46cc04adbb558c07429a 100644 (file)
@@ -497,15 +497,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                /* map PCI address at 0xc0000000 in PLB space */
 
                /* PMM1 Mask/Attribute - disabled b4 setting */
-               out32r(PCIX0_PMM1MA, 0x00000000);
+               out32r(PCIL0_PMM1MA, 0x00000000);
                /* PMM1 Local Address */
-               out32r(PCIX0_PMM1LA, 0xc0000000);
+               out32r(PCIL0_PMM1LA, 0xc0000000);
                /* PMM1 PCI Low Address */
-               out32r(PCIX0_PMM1PCILA, pciaddr);
+               out32r(PCIL0_PMM1PCILA, pciaddr);
                /* PMM1 PCI High Address */
-               out32r(PCIX0_PMM1PCIHA, 0x00000000);
+               out32r(PCIL0_PMM1PCIHA, 0x00000000);
                /* 256MB + No prefetching, and enable region */
-               out32r(PCIX0_PMM1MA, 0xf0000001);
+               out32r(PCIL0_PMM1MA, 0xf0000001);
        } else {
                printf("Usage:\npmm %s\n", cmdtp->help);
        }
index f0f9bff3eb2d9f05b9e705f49394391720f977b2..ec9255243c472c18014a3f5b303695472e717689 100644 (file)
@@ -208,7 +208,7 @@ int misc_init_f(void)
 
        if (getenv("pciearly") && (!is_monarch())) {
                printf("PCI:   early target init\n");
-               pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+               pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
                pci_target_init(&hose);
        }
        return 0;
@@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
                                                /* and enable region */
 
        if (!is_monarch()) {
                ptmla_str = getenv("ptm1la");
                ptmms_str = getenv("ptm1ms");
                if(NULL != ptmla_str && NULL != ptmms_str ) {
-                       out32r(PCIX0_PTM1MS,
+                       out32r(PCIL0_PTM1MS,
                               simple_strtoul(ptmms_str, NULL, 16));
-                       out32r(PCIX0_PTM1LA,
+                       out32r(PCIL0_PTM1LA,
                               simple_strtoul(ptmla_str, NULL, 16));
                } else {
                        /* BAR1: default top 64MB of RAM */
-                       out32r(PCIX0_PTM1MS, 0xfc000001);
-                       out32r(PCIX0_PTM1LA, 0x0c000000);
+                       out32r(PCIL0_PTM1MS, 0xfc000001);
+                       out32r(PCIL0_PTM1LA, 0x0c000000);
                }
        } else {
                /* BAR1: default: complete 256MB RAM */
-               out32r(PCIX0_PTM1MS, 0xf0000001);
-               out32r(PCIX0_PTM1LA, 0x00000000);
+               out32r(PCIL0_PTM1MS, 0xf0000001);
+               out32r(PCIL0_PTM1LA, 0x00000000);
        }
 
        ptmla_str = getenv("ptm2la");           /* Local Addr. Reg */
        ptmms_str = getenv("ptm2ms");           /* Memory Size/Attribute */
        if(NULL != ptmla_str && NULL != ptmms_str ) {
-               out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
-               out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+               out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+               out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
        } else {
                /* BAR2: default: 4MB FPGA */
-               out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
-               out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+               out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+               out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
        }
 
        if (is_monarch()) {
index 7a9726fe78e591980efcb9046547f654ba5a5319..721aaac3e741c9a8c9523190628cdb9ea6531fdd 100644 (file)
@@ -52,7 +52,7 @@
 #define    IIC_EXTSTS  (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
 #define    IIC_LSADR   (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
 #define    IIC_HSADR   (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV  (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_CLKDIV  (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
 #define    IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
 #define    IIC_XFRCNT  (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
 #define    IIC_XTCNTLSS        (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
@@ -537,7 +537,7 @@ read_spd:
        WRITE_I2C(IICHSADR, 0x00)       /* clear hi slave address */
        WRITE_I2C(IICSTS, 0x08)         /* update status register */
        WRITE_I2C(IICEXTSTS, 0x8f)
-       WRITE_I2C(IICCLKDIV, 0x05)
+       WRITE_I2C(IIC0_CLKDIV, 0x05)
        WRITE_I2C(IICINTRMSK, 0x00)     /* no interrupts */
        WRITE_I2C(IICXFRCNT, 0x00)      /* clear transfer count */
        WRITE_I2C(IICXTCNTLSS, 0xf0)    /* clear extended control & stat */
index 7cc1bf26783d6432b6cbd73499b01b1ed4befe61..90dbe52aa283f0f30c2ac3e90009a46a5a988954 100644 (file)
@@ -239,22 +239,22 @@ void pci_target_init(struct pci_controller *hose)
         *   Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);
-       out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);
-       out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);
-       out32r(PCIX0_PTM1LA, 0);
-       out32r(PCIX0_PTM2MS, 0);
-       out32r(PCIX0_PTM2LA, 0);
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);
+       out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);
+       out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);
+       out32r(PCIL0_PTM1LA, 0);
+       out32r(PCIL0_PTM2MS, 0);
+       out32r(PCIL0_PTM2LA, 0);
 
        /*
         * Set up Configuration registers
index 2cd2e6d4503741504cf19ddee6db8715acd72194..b42e90853f4bc97a680876d8f46b66313a166881 100644 (file)
@@ -154,27 +154,27 @@ void pci_target_init(struct pci_controller *hose)
        /*
         * Disable everything
         */
-       out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-       out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-       out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+       out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+       out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+       out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
        /*
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
         * strapping options to not support sizes such as 128/256 MB.
         */
-       out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out_le32((void *)PCIX0_PIM0LAH, 0);
-       out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-       out_le32((void *)PCIX0_BAR0, 0);
+       out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out_le32((void *)PCIL0_PIM0LAH, 0);
+       out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out_le32((void *)PCIL0_BAR0, 0);
 
        /*
         * Program the board's subsystem id/vendor id
         */
-       out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 40a097cef59ef010d09857f49471f4db01535a54..8c674a20953bd9330bf30c9884ce0e3ec8bab89f 100644 (file)
@@ -679,29 +679,29 @@ void pci_target_init(struct pci_controller *hose)
         * Use byte reversed out routines to handle endianess.
         * Make this region non-prefetchable.
         */
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA,
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA,
               CONFIG_SYS_PCI_MEMBASE);         /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute */
                                                /* - disabled b4 setting */
-       out32r(PCIX0_PMM1LA,
+       out32r(PCIL0_PMM1LA,
               CONFIG_SYS_PCI_MEMBASE + 0x20000000);    /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA,
+       out32r(PCIL0_PMM1PCILA,
               CONFIG_SYS_PCI_MEMBASE + 0x20000000);    /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, */
                                                /* and enable region */
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);                /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);                /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);                /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);                /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);                /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index f4090f40dd3f1bf5a0d9d6584c43e9aba29cd00e..ef7f2e8dc5778a231a0c25c4449c5c17222abc63 100644 (file)
@@ -351,22 +351,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers
index 4522612daef16ed4acf6e981c03a96d754cc6e45..946c3f3a4dd304a97e6b7a727241db3b84178f4a 100644 (file)
@@ -398,27 +398,27 @@ void pci_target_init(struct pci_controller *hose)
         * Make this region non-prefetchable.
         */
        /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0MA, 0x00000000);
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0MA, 0x00000000);
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        /* 512M + No prefetching, and enable region */
-       out32r(PCIX0_PMM0MA, 0xE0000001);
+       out32r(PCIL0_PMM0MA, 0xE0000001);
 
        /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1MA, 0x00000000);
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
+       out32r(PCIL0_PMM1MA, 0x00000000);
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        /* 512M + No prefetching, and enable region */
-       out32r(PCIX0_PMM1MA, 0xE0000001);
+       out32r(PCIL0_PMM1MA, 0xE0000001);
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers
index ac059a903b1946d7f6894f21dcad7a77384337b6..b70827e0cc29b9933fd01c738f0c563bdc34b61d 100644 (file)
@@ -626,22 +626,22 @@ void pci_target_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
-
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
+
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*--------------------------------------------------------------------------+
         * Set up Configuration registers
index cdb91ac36b44d0c285ef2bfb9749ef31248a1c76..51335c4d9c82503f33d987e6787a395cb31f95ea 100644 (file)
@@ -192,28 +192,28 @@ void pci_target_init(struct pci_controller * hose )
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
@@ -270,21 +270,21 @@ void pci_master_init(struct pci_controller *hose)
          |   Use byte reversed out routines to handle endianess.
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
-       out32r( PCIX0_POM0SA, 0 ); /* disable */
-       out32r( PCIX0_POM1SA, 0 ); /* disable */
-       out32r( PCIX0_POM2SA, 0 ); /* disable */
-
-       out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);  /* PMM0 Local Address */
-       out32r(PCIX0_POM0LAH, 0x00000003);      /* PMM0 Local Address */
-       out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
-       out32r(PCIX0_POM0PCIAH, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
-
-       out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_POM1LAH, 0x00000003);      /* PMM0 Local Address */
-       out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
-       out32r(PCIX0_POM1PCIAH, 0x00000000);    /* PMM0 PCI High Address */
-       out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
+       out32r( PCIL0_POM0SA, 0 ); /* disable */
+       out32r( PCIL0_POM1SA, 0 ); /* disable */
+       out32r( PCIL0_POM2SA, 0 ); /* disable */
+
+       out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);  /* PMM0 Local Address */
+       out32r(PCIL0_POM0LAH, 0x00000003);      /* PMM0 Local Address */
+       out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
+       out32r(PCIL0_POM0PCIAH, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
+
+       out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIL0_POM1LAH, 0x00000003);      /* PMM0 Local Address */
+       out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
+       out32r(PCIL0_POM1PCIAH, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 }
 #endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
index 20fd4dc2769cfa623c1b721dfcd08d0fc490ad76..9a078527609ea71caf505a1726902dc7c479c70e 100644 (file)
@@ -209,28 +209,28 @@ void pci_target_init(struct pci_controller *hose)
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0SA, 0);        /* disable */
-       out32r(PCIX0_PIM1SA, 0);        /* disable */
-       out32r(PCIX0_PIM2SA, 0);        /* disable */
-       out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
+       out32r(PCIL0_PIM0SA, 0);        /* disable */
+       out32r(PCIL0_PIM1SA, 0);        /* disable */
+       out32r(PCIL0_PIM2SA, 0);        /* disable */
+       out32r(PCIL0_EROMBA, 0);        /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIX0_PIM0LAH, 0);
-       out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out32r(PCIL0_PIM0LAH, 0);
+       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-       out32r(PCIX0_BAR0, 0);
+       out32r(PCIL0_BAR0, 0);
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 328abd64b8975a8b42653ea94f75e5b97b2f9628..90f27caa0dad331ca4be3db887aadd5bc100f124 100644 (file)
@@ -44,7 +44,7 @@
 #define    IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
 #define    IIC_LSADR1  (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
 #define    IIC_HSADR1  (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV)
 #define    IIC_INTRMSK1        (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
 #define    IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
 #define    IIC_XTCNTLSS1       (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
index e1c61463dd2e7a1ae41e5091366f2dc9038c47ca..a484874ea3561891f56ca871d7197222d6574d60 100644 (file)
@@ -346,28 +346,28 @@ void pci_target_init(struct pci_controller * hose )
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+       out32r( PCIL0_PIM0SA, 0 ); /* disable */
+       out32r( PCIL0_PIM1SA, 0 ); /* disable */
+       out32r( PCIL0_PIM2SA, 0 ); /* disable */
+       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
        /*--------------------------------------------------------------------------+
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         *--------------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+       out32r( PCIL0_PIM0LAH, 0 );
+       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-       out32r( PCIX0_BAR0, 0 );
+       out32r( PCIL0_BAR0, 0 );
 
        /*--------------------------------------------------------------------------+
         * Program the board's subsystem id/vendor id
         *--------------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index 011fb94bb63234d147a507de669097c91b0bee7e..04949bb2d464b95c3bc0caa351abbe7f2c066bda 100644 (file)
@@ -156,7 +156,7 @@ int pci_pre_init(struct pci_controller * hose)
                return 0;
 
 #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
-       /* Setup System Device Register PCIX0_XCR */
+       /* Setup System Device Register PCIL0_XCR */
        mfsdr(SDR0_XCR, strap);
        strap &= 0x0f000000;
        mtsdr(SDR0_XCR, strap);
@@ -175,26 +175,26 @@ int pci_pre_init(struct pci_controller * hose)
 void pci_target_init(struct pci_controller * hose)
 {
        /* Disable everything */
-       out32r(PCIX0_PIM0SA, 0);
-       out32r(PCIX0_PIM1SA, 0);
-       out32r(PCIX0_PIM2SA, 0);
-       out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+       out32r(PCIL0_PIM0SA, 0);
+       out32r(PCIL0_PIM1SA, 0);
+       out32r(PCIL0_PIM2SA, 0);
+       out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
 
        /*
         * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
         * options to not support sizes such as 128/256 MB.
         */
-       out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-       out32r(PCIX0_PIM0LAH, 0);
-       out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+       out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+       out32r(PCIL0_PIM0LAH, 0);
+       out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-       out32r(PCIX0_BAR0, 0);
+       out32r(PCIL0_BAR0, 0);
 
        /* Program the board's subsystem id/vendor id */
-       out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-       out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+       out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-       out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+       out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
index e97f32c7b0781c823c7d55e908b210861f67598b..fa521f0415c12fe80f1782988a1cdf5fa05ee5e3 100644 (file)
@@ -518,7 +518,7 @@ int pci_440_init (struct pci_controller *hose)
        /* PCI I/O space */
        pci_set_region(hose->regions + reg_num++,
                       0x00000000,
-                      PCIX0_IOBASE,
+                      PCIL0_IOBASE,
                       0x10000,
                       PCI_REGION_IO);
 
@@ -545,7 +545,7 @@ int pci_440_init (struct pci_controller *hose)
 
        hose->region_count = reg_num;
 
-       pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+       pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 
        /* Let board change/modify hose & do initial checks */
        if (pci_pre_init (hose) == 0) {
@@ -562,18 +562,18 @@ int pci_440_init (struct pci_controller *hose)
 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
        pci_target_init(hose);                /* Let board setup pci target */
 #else
-       out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
-       out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
+       out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-       out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
-       out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
-#elif defined(PCIX0_BRDGOPT1)
-       out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
-       out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
+       out32r( PCIL0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
+       out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
+#elif defined(PCIL0_BRDGOPT1)
+       out32r( PCIL0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
+       out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config   */
 #endif
 
        /*--------------------------------------------------------------------------+
@@ -583,23 +583,23 @@ int pci_440_init (struct pci_controller *hose)
 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
        pci_master_init(hose);          /* Let board setup pci master */
 #else
-       out32r( PCIX0_POM0SA, 0 ); /* disable */
-       out32r( PCIX0_POM1SA, 0 ); /* disable */
-       out32r( PCIX0_POM2SA, 0 ); /* disable */
+       out32r( PCIL0_POM0SA, 0 ); /* disable */
+       out32r( PCIL0_POM1SA, 0 ); /* disable */
+       out32r( PCIL0_POM2SA, 0 ); /* disable */
 #if defined(CONFIG_440SPE)
-       out32r( PCIX0_POM0LAL, 0x10000000 );
-       out32r( PCIX0_POM0LAH, 0x0000000c );
+       out32r( PCIL0_POM0LAL, 0x10000000 );
+       out32r( PCIL0_POM0LAH, 0x0000000c );
 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-       out32r( PCIX0_POM0LAL, 0x20000000 );
-       out32r( PCIX0_POM0LAH, 0x0000000c );
+       out32r( PCIL0_POM0LAL, 0x20000000 );
+       out32r( PCIL0_POM0LAH, 0x0000000c );
 #else
-       out32r( PCIX0_POM0LAL, 0x00000000 );
-       out32r( PCIX0_POM0LAH, 0x00000003 );
+       out32r( PCIL0_POM0LAL, 0x00000000 );
+       out32r( PCIL0_POM0LAH, 0x00000003 );
 #endif
-       out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
-       out32r( PCIX0_POM0PCIAH, 0x00000000 );
-       out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
-       out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+       out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
+       out32r( PCIL0_POM0PCIAH, 0x00000000 );
+       out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
+       out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
 #endif
 
        /*--------------------------------------------------------------------------+
@@ -614,7 +614,7 @@ int pci_440_init (struct pci_controller *hose)
 #endif
 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
     !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
-               out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+               out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
 #endif
                hose->last_busno = pci_hose_scan(hose);
        }
index bd06b9bc22c9466eb36d446bd54310de575d2c9f..a00da408c90cd0557e31373028da7419d2227c30 100644 (file)
@@ -58,13 +58,13 @@ void reconfigure_pll(u32 new_cpu_freq)
                target_perdv0 = 4;
                target_spcid0 = 4;
 
-               mfcpr(CPR0_PRIMBD, reg);
+               mfcpr(CPR0_PRIMBD0, reg);
                temp = (reg & PRBDV_MASK) >> 24;
                prbdv0 = temp ? temp : 8;
                if (prbdv0 != target_prbdv0) {
                        reg &= ~PRBDV_MASK;
                        reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
-                       mtcpr(CPR0_PRIMBD, reg);
+                       mtcpr(CPR0_PRIMBD0, reg);
                        reset_needed = 1;
                }
 
index fa3bfc8d9f51f4e438613c9462424e18e39774d7..22ed5c25ea14969b93767bef27f670b1076108b5 100644 (file)
@@ -195,7 +195,7 @@ unsigned int miiphy_getemac_offset(u8 addr)
        unsigned long eoffset;
 
        /* Need to find out which mdi port we're using */
-       zmii = in_be32((void *)ZMII_FER);
+       zmii = in_be32((void *)ZMII0_FER);
 
        if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
                /* using port 0 */
@@ -217,12 +217,12 @@ unsigned int miiphy_getemac_offset(u8 addr)
                /* None of the mdi ports are enabled! */
                /* enable port 0 */
                zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
-               out_be32((void *)ZMII_FER, zmii);
+               out_be32((void *)ZMII0_FER, zmii);
                eoffset = 0;
                /* need to soft reset port 0 */
-               zmii = in_be32((void *)EMAC_M0);
-               zmii |= EMAC_M0_SRST;
-               out_be32((void *)EMAC_M0, zmii);
+               zmii = in_be32((void *)EMAC0_MR0);
+               zmii |= EMAC_MR0_SRST;
+               out_be32((void *)EMAC0_MR0, zmii);
        }
 
        return (eoffset);
@@ -243,19 +243,19 @@ unsigned int miiphy_getemac_offset(u8 addr)
        switch (addr) {
 #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
        case CONFIG_GPCS_PHY1_ADDR:
-               if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
+               if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
                        eoffset = 0x100;
                break;
 #endif
 #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
        case CONFIG_GPCS_PHY2_ADDR:
-               if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
+               if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
                        eoffset = 0x300;
                break;
 #endif
 #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
        case CONFIG_GPCS_PHY3_ADDR:
-               if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
+               if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
                        eoffset = 0x400;
                break;
 #endif
@@ -278,9 +278,9 @@ static int emac_miiphy_wait(u32 emac_reg)
        /* wait for completion */
        i = 0;
        do {
-               sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
+               sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
                if (i++ > 5) {
-                       debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__,
+                       debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
                              __LINE__, sta_reg);
                        return -1;
                }
@@ -324,7 +324,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
        if (cmd == EMAC_STACR_WRITE)
                memcpy(&sta_reg, &value, 2);    /* put in data */
 
-       out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
+       out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
        debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
 
        /* wait for completion */
@@ -349,7 +349,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
        if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
                return -1;
 
-       sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
+       sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
        *value = sta_reg >> 16;
 
        return 0;
index 988ba9742d2492c5f2755bb951f9bdefeeb47439..906face033030fac18bad2a77b17daca13f39b70 100644 (file)
@@ -334,7 +334,7 @@ void get_sys_info (sys_info_t *sysInfo)
        sysInfo->pllFbkDiv = temp ? temp : 32;
        lfdiv = reg & PLLD_LFBDV_MASK;
 
-       mfcpr(CPR0_OPBD, reg);
+       mfcpr(CPR0_OPBD0, reg);
        temp = (reg & OPBDDV_MASK) >> 24;
        sysInfo->pllOpbDiv = temp ? temp : 4;
 
@@ -342,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo)
        temp = (reg & PERDV_MASK) >> 24;
        sysInfo->pllExtBusDiv = temp ? temp : 8;
 
-       mfcpr(CPR0_PRIMBD, reg);
+       mfcpr(CPR0_PRIMBD0, reg);
        temp = (reg & PRBDV_MASK) >> 24;
        prbdv0 = temp ? temp : 8;
 
@@ -1050,7 +1050,7 @@ void get_sys_info (sys_info_t * sysInfo)
        /*
         * Determine OPBDV0
         */
-       mfcpr(CPR0_OPBD, tmp);
+       mfcpr(CPR0_OPBD0, tmp);
        tmp = (tmp >> 24) & 0x03;
        sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
 
index f2c9be0dd3f4d03a6523c9643f87780f68142af1..2fac64167b9fd418f9a649f137ae0c11cfcc55b1 100644 (file)
@@ -44,7 +44,7 @@
  *             RX descriptor address up to the next cache line boundary.
  *  16-Jan-00  Added support for booting with IP of 0x0                    MKW
  *  15-Mar-00  Updated enetInit() to enable broadcast addresses in the
- *             EMAC_RXM register.                                          JWB
+ *             EMAC0_RXM register.                                         JWB
  *  12-Mar-01  anne-sophie.harnois@nextream.fr
  *              - Variables are compatible with those already defined in
  *               include/net.h
@@ -58,7 +58,7 @@
  *  08-May-01  stefan.roese@esd-electronics.com
  *             - MAL error handling added (eth_init called again)
  *  13-Nov-01  stefan.roese@esd-electronics.com
- *             - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ *             - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
  *  04-Jan-02  stefan.roese@esd-electronics.com
  *             - Wait for PHY auto negotiation to complete added
  *  06-Feb-02  stefan.roese@esd-electronics.com
@@ -359,7 +359,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
        EMAC_4XX_HW_PST hw_p = dev->priv;
        u32 val = 10000;
 
-       out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
+       out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000);        /* disable emac interrupts */
 
        /* 1st reset MAL channel */
        /* Note: writing a 0 to a channel has no effect */
@@ -382,7 +382,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
        emac_loopback_enable(hw_p);
 
        /* EMAC RESET */
-       out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+       out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
 
        /* remove clocks for EMAC internal loopback  */
        emac_loopback_disable(hw_p);
@@ -485,7 +485,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
        /* Ensure we setup mdio for this devnum and ONLY this devnum */
        zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
 
-       out_be32((void *)ZMII_FER, zmiifer);
+       out_be32((void *)ZMII0_FER, zmiifer);
        out_be32((void *)RGMII_FER, rmiifer);
 
        return ((int)pfc1);
@@ -504,21 +504,21 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
        switch (pfc1) {
        case SDR0_PFC1_SELECT_CONFIG_2:
                /* 1 x GMII port */
-               out_be32((void *)ZMII_FER, 0x00);
+               out_be32((void *)ZMII0_FER, 0x00);
                out_be32((void *)RGMII_FER, 0x00000037);
                bis->bi_phymode[0] = BI_PHYMODE_GMII;
                bis->bi_phymode[1] = BI_PHYMODE_NONE;
                break;
        case SDR0_PFC1_SELECT_CONFIG_4:
                /* 2 x RGMII ports */
-               out_be32((void *)ZMII_FER, 0x00);
+               out_be32((void *)ZMII0_FER, 0x00);
                out_be32((void *)RGMII_FER, 0x00000055);
                bis->bi_phymode[0] = BI_PHYMODE_RGMII;
                bis->bi_phymode[1] = BI_PHYMODE_RGMII;
                break;
        case SDR0_PFC1_SELECT_CONFIG_6:
                /* 2 x SMII ports */
-               out_be32((void *)ZMII_FER,
+               out_be32((void *)ZMII0_FER,
                         ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
                         ((ZMII_FER_SMII) << ZMII_FER_V(1)));
                out_be32((void *)RGMII_FER, 0x00000000);
@@ -527,7 +527,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
                break;
        case SDR0_PFC1_SELECT_CONFIG_1_2:
                /* only 1 x MII supported */
-               out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+               out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
                out_be32((void *)RGMII_FER, 0x00000000);
                bis->bi_phymode[0] = BI_PHYMODE_MII;
                bis->bi_phymode[1] = BI_PHYMODE_NONE;
@@ -537,9 +537,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
        }
 
        /* Ensure we setup mdio for this devnum and ONLY this devnum */
-       zmiifer = in_be32((void *)ZMII_FER);
+       zmiifer = in_be32((void *)ZMII0_FER);
        zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-       out_be32((void *)ZMII_FER, zmiifer);
+       out_be32((void *)ZMII0_FER, zmiifer);
 
        return ((int)0x0);
 }
@@ -953,18 +953,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        /* NOTE: Therefore, disable all other EMACS, since we handle */
        /* NOTE: only one emac at a time */
        reg = 0;
-       out_be32((void *)ZMII_FER, 0);
+       out_be32((void *)ZMII0_FER, 0);
        udelay (100);
 
 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-       out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+       out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
 #elif defined(CONFIG_440GX) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
        ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
 #endif
 
-       out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+       out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
 #if defined(CONFIG_405EX)
        ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
@@ -976,13 +976,13 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        emac_loopback_enable(hw_p);
 
        /* EMAC RESET */
-       out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+       out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
 
        /* remove clocks for EMAC internal loopback  */
        emac_loopback_disable(hw_p);
 
        failsafe = 1000;
-       while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
+       while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
                udelay (1000);
                failsafe--;
        }
@@ -1000,15 +1000,15 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        opbfreq = sysinfo.freqOPB / 1000000;
        if (opbfreq <= 50);
        else if (opbfreq <= 66)
-               mode_reg |= EMAC_M1_OBCI_66;
+               mode_reg |= EMAC_MR1_OBCI_66;
        else if (opbfreq <= 83)
-               mode_reg |= EMAC_M1_OBCI_83;
+               mode_reg |= EMAC_MR1_OBCI_83;
        else if (opbfreq <= 100)
-               mode_reg |= EMAC_M1_OBCI_100;
+               mode_reg |= EMAC_MR1_OBCI_100;
        else
-               mode_reg |= EMAC_M1_OBCI_GT100;
+               mode_reg |= EMAC_MR1_OBCI_GT100;
 
-       out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+       out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 
 #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
@@ -1041,9 +1041,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif
                }
 
-               mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
-               mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg);
-               out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+               mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
+               mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
+               out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
 
                /* Configure GPCS interface to recommended setting for SGMII */
                miiphy_reset(dev->name, reg);
@@ -1250,11 +1250,11 @@ get_speed:
 #endif
 
        /* Set ZMII/RGMII speed according to the phy link speed */
-       reg = in_be32((void *)ZMII_SSR);
+       reg = in_be32((void *)ZMII0_SSR);
        if ( (speed == 100) || (speed == 1000) )
-               out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
+               out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
        else
-               out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+               out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
 
        if ((devnum == 2) || (devnum == 3)) {
                if (speed == 1000)
@@ -1381,7 +1381,7 @@ get_speed:
        reg = reg << 8;
        reg |= dev->enetaddr[1];
 
-       out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
+       out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
 
        reg = 0x00000000;
        reg |= dev->enetaddr[2];        /* set low address  */
@@ -1392,7 +1392,7 @@ get_speed:
        reg = reg << 8;
        reg |= dev->enetaddr[5];
 
-       out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
+       out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
 
        switch (devnum) {
        case 1:
@@ -1480,9 +1480,9 @@ get_speed:
        mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
 
        /* set transmit enable & receive enable */
-       out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+       out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
 
-       mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
+       mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
 
        /* set rx-/tx-fifo size */
        mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
@@ -1497,47 +1497,47 @@ get_speed:
                pfc1 |= SDR0_PFC1_EM_1000;
                mtsdr (SDR0_PFC1, pfc1);
 #endif
-               mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
+               mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
        } else if (speed == _100BASET)
-               mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
+               mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
        else
                mode_reg = mode_reg & ~0x00C00000;      /* 10 MBPS */
        if (duplex == FULL)
-               mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
+               mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
 
-       out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+       out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
 
        /* Enable broadcast and indvidual address */
        /* TBS: enabling runts as some misbehaved nics will send runts */
-       out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
+       out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
 
        /* we probably need to set the tx mode1 reg? maybe at tx time */
 
        /* set transmit request threshold register */
-       out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000);        /* 256 byte threshold */
+       out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000);       /* 256 byte threshold */
 
        /* set receive  low/high water mark register */
 #if defined(CONFIG_440)
        /* 440s has a 64 byte burst length */
-       out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+       out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
 #else
        /* 405s have a 16 byte burst length */
-       out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
+       out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
 #endif /* defined(CONFIG_440) */
-       out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
+       out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
 
        /* Set fifo limit entry in tx mode 0 */
-       out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
+       out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
        /* Frame gap set */
-       out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
+       out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
 
        /* Set EMAC IER */
        hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
        if (speed == _100BASET)
                hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
 
-       out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
-       out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
+       out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff);        /* clear pending interrupts */
+       out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
 
        if (hw_p->first_init == 0) {
                /*
@@ -1596,8 +1596,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
 
        sync();
 
-       out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
-                in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
+       out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
+                in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
 #ifdef INFO_4XX_ENET
        hw_p->stats.pkts_tx++;
 #endif
@@ -1607,9 +1607,9 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
         *-----------------------------------------------------------------------*/
        time_start = get_timer (0);
        while (1) {
-               temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
+               temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
                /* loop until either TINT turns on or 3 seconds elapse */
-               if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
+               if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
                        /* transmit is done, so now check for errors
                         * If there is an error, an interrupt should
                         * happen when we return
@@ -1678,7 +1678,7 @@ int enetInt (struct eth_device *dev)
 
                /* look for EMAC errors */
                if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
-                       emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
+                       emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
                        emac_err(dev, emac_isr);
 
                        /* clear EMAC error interrupt status bits */
@@ -1761,7 +1761,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr)
        EMAC_4XX_HW_PST hw_p = dev->priv;
 
        printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
-       out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
+       out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
 }
 
 /*-----------------------------------------------------------------------------+
index c3665da94a6ffbc8af0d8f749263387b2dcbc491..a58db04e49924697b462fb98e6fc0052f43d0506 100644 (file)
@@ -115,11 +115,11 @@ static void ether_post_init (int devnum, int hw_addr)
        sync ();
 #endif
        /* reset emac */
-       out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
+       out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
        sync ();
 
        for (i = 0;; i++) {
-               if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
+               if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
                        break;
                if (i >= 1000) {
                        printf ("Timeout resetting EMAC\n");
@@ -134,15 +134,15 @@ static void ether_post_init (int devnum, int hw_addr)
        mode_reg = 0x0;
        if (sysinfo.freqOPB <= 50000000);
        else if (sysinfo.freqOPB <= 66666667)
-               mode_reg |= EMAC_M1_OBCI_66;
+               mode_reg |= EMAC_MR1_OBCI_66;
        else if (sysinfo.freqOPB <= 83333333)
-               mode_reg |= EMAC_M1_OBCI_83;
+               mode_reg |= EMAC_MR1_OBCI_83;
        else if (sysinfo.freqOPB <= 100000000)
-               mode_reg |= EMAC_M1_OBCI_100;
+               mode_reg |= EMAC_MR1_OBCI_100;
        else
-               mode_reg |= EMAC_M1_OBCI_GT100;
+               mode_reg |= EMAC_MR1_OBCI_GT100;
 
-       out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
+       out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
 
 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 
@@ -210,40 +210,40 @@ static void ether_post_init (int devnum, int hw_addr)
 
        /* set internal loopback mode */
 #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
-       out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
-                 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
-                 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
-                 in_be32 ((void*)(EMAC_M1 + hw_addr)));
+       out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
+                 EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+                 EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+                 in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
 #else
-       out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
-                 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
-                 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
-                 in_be32 ((void*)(EMAC_M1 + hw_addr)));
+       out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
+                 EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+                 EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+                 in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
 #endif
 
        /* set transmit enable & receive enable */
-       out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
+       out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
 
        /* enable broadcast address */
-       out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
+       out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
 
        /* set transmit request threshold register */
-       out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000);    /* 256 byte threshold */
+       out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000);   /* 256 byte threshold */
 
        /* set receive  low/high water mark register */
 #if defined(CONFIG_440)
        /* 440s has a 64 byte burst length */
-       out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
+       out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
 #else
        /* 405s have a 16 byte burst length */
-       out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
+       out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
 #endif /* defined(CONFIG_440) */
-       out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
+       out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
 
        /* Set fifo limit entry in tx mode 0 */
-       out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
+       out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
        /* Frame gap set */
-       out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
+       out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
        sync ();
 }
 
@@ -270,7 +270,7 @@ static void ether_post_halt (int devnum, int hw_addr)
                udelay (1000);
        }
        /* emac reset */
-       out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
+       out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
 
 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        /* remove clocks for EMAC internal loopback  */
@@ -300,7 +300,7 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
        flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
        sync ();
 
-       out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
+       out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
        sync ();
 }