/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
* (C) Copyright 2009
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
*/
#include <common.h>
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy SoC access. Please update!
-#endif
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
-/*
- * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
- * to keep track of the bootcount.
- */
-#define AT91_GPBR_BOOTCOUNT_REGISTER 3
-#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
-
int arch_cpu_init(void)
{
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
+void arch_preboot_os(void)
+{
+ ulong cpiv;
+ at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
+
+ cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+ /*
+ * Disable PITC
+ * Add 0x1000 to current counter to stop it faster
+ * without waiting for wrapping back to 0
+ */
+ writel(cpiv + 0x1000, &pit->mr);
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
#ifdef CONFIG_BOOTCOUNT_LIMIT
/*
- * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
- * in one 32-bit register. This is done, as the AT91SAM9260 only has
- * 4 GPBR.
+ * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register.
+ * This is done so we need to use only one of the four GPBR registers.
*/
void bootcount_store (ulong a)
{
- volatile ulong *save_addr =
- (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+ at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
- *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
+ writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff),
+ &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
}
ulong bootcount_load (void)
{
- volatile ulong *save_addr =
- (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+ at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE;
- if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+ ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
+ if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
return 0;
else
- return (*save_addr & 0x0000ffff);
+ return val & 0x0000ffff;
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */
u32 reserved2[3];
u32 hsh;
u32 hsl;
- u32 sh1l;
+ u32 sa1l;
u32 sa1h;
u32 sa2l;
u32 sa2h;
int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
unsigned char reg, unsigned short *value)
{
+ unsigned long netstat;
at91emac_EnableMDIO(at91mac);
writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
AT91_EMAC_MAN_PHYA(addr),
&at91mac->man);
- udelay(10000);
+
+ do {
+ netstat = readl(&at91mac->sr);
+ DEBUG_AT91PHY("poll SR %08lx\n", netstat);
+ } while (!(netstat & AT91_EMAC_SR_IDLE));
+
*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
at91emac_DisableMDIO(at91mac);
int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
unsigned char reg, unsigned short value)
{
+ unsigned long netstat;
DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value)
at91emac_EnableMDIO(at91mac);
AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
&at91mac->man);
- udelay(10000);
+
+ do {
+ netstat = readl(&at91mac->sr);
+ DEBUG_AT91PHY("poll SR %08lx\n", netstat);
+ } while (!(netstat & AT91_EMAC_SR_IDLE));
at91emac_DisableMDIO(at91mac);
+
return 0;
}
memset(emacfix, 0, sizeof(emac_device));
memset(dev, 0, sizeof(*dev));
-#ifndef CONFIG_RMII
- sprintf(dev->name, "AT91 EMAC");
-#else
- sprintf(dev->name, "AT91 EMAC RMII");
-#endif
+ sprintf(dev->name, "emac");
dev->iobase = iobase;
dev->priv = emacfix;
dev->init = at91emac_init;
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
+ * Modified to support C structur SoC access by
+ * Andreas Bießmann <biessmann@corscience.de>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
-#ifndef CONFIG_AT91_LEGACY
-#define CONFIG_AT91_LEGACY
-#warning Please update to use C structur SoC access !
-#endif
#include <watchdog.h>
#include <asm/io.h>
void serial_setbrg(void)
{
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
unsigned long divisor;
unsigned long usart_hz;
*/
usart_hz = get_usart_clk_rate(USART_ID);
divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
- usart3_writel(BRGR, USART3_BF(CD, divisor));
+ writel(USART3_BF(CD, divisor), &usart->brgr);
}
int serial_init(void)
{
- usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+
+ writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
- usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN));
- usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
+ writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
+ writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
- | USART3_BF(NBSTOP, USART3_NBSTOP_1)));
+ | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
+ &usart->mr);
return 0;
}
void serial_putc(char c)
{
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+
if (c == '\n')
serial_putc('\r');
- while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ;
- usart3_writel(THR, c);
+ while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
+ writel(c, &usart->thr);
}
void serial_puts(const char *s)
int serial_getc(void)
{
- while (!(usart3_readl(CSR) & USART3_BIT(RXRDY)))
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+
+ while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
WATCHDOG_RESET();
- return usart3_readl(RHR);
+ return readl(&usart->rhr);
}
int serial_tstc(void)
{
- return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0;
+ atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE;
+ return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
*
* Copyright (C) 2005-2006 Atmel Corporation
*
+ * Modified to support C structure SoC access by
+ * Andreas Bießmann <biessmann@corscience.de>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
#ifndef __DRIVERS_ATMEL_USART_H__
#define __DRIVERS_ATMEL_USART_H__
-/* USART3 register offsets */
-#define USART3_CR 0x0000
-#define USART3_MR 0x0004
-#define USART3_IER 0x0008
-#define USART3_IDR 0x000c
-#define USART3_IMR 0x0010
-#define USART3_CSR 0x0014
-#define USART3_RHR 0x0018
-#define USART3_THR 0x001c
-#define USART3_BRGR 0x0020
-#define USART3_RTOR 0x0024
-#define USART3_TTGR 0x0028
-#define USART3_FIDI 0x0040
-#define USART3_NER 0x0044
-#define USART3_XXR 0x0048
-#define USART3_IFR 0x004c
-#define USART3_RPR 0x0100
-#define USART3_RCR 0x0104
-#define USART3_TPR 0x0108
-#define USART3_TCR 0x010c
-#define USART3_RNPR 0x0110
-#define USART3_RNCR 0x0114
-#define USART3_TNPR 0x0118
-#define USART3_TNCR 0x011c
-#define USART3_PTCR 0x0120
-#define USART3_PTSR 0x0124
+/* USART3 register footprint */
+typedef struct atmel_usart3 {
+ u32 cr;
+ u32 mr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 csr;
+ u32 rhr;
+ u32 thr;
+ u32 brgr;
+ u32 rtor;
+ u32 ttgr;
+ u32 reserved0[5];
+ u32 fidi;
+ u32 ner;
+ u32 reserved1;
+ u32 ifr;
+ u32 man;
+ u32 reserved2[54]; // version and PDC not needed
+} atmel_usart3_t;
/* Bitfields in CR */
#define USART3_RSTRX_OFFSET 2
<< USART3_##name##_OFFSET)) \
| USART3_BF(name,value))
-/* Register access macros */
-#define usart3_readl(reg) \
- readl((void *)USART_BASE + USART3_##reg)
-#define usart3_writel(reg,value) \
- writel((value), (void *)USART_BASE + USART3_##reg)
-
#endif /* __DRIVERS_ATMEL_USART_H__ */
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