phy: marvell: a3700: Set USB3 RX wait depending on ref clock

According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 4fb23bb54734238cd001b4a742389f19da0d7d1b..3da9eedc231c1cbd4fd09ad4d8b890d2cfdb02f9 100644 (file)
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -382,20 +382,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
        /*
         * 3. Check crystal jumper setting and program the Power and PLL
         * Control accordingly
+        * 4. Change RX wait
         */
        if (get_ref_clk() == 40) {
                /* 40 MHz */
                usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
+               usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
        } else {
                /* 25 MHz */
                usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
+               usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);
        }
 
-       /*
-        * 4. Change RX wait
-        */
-       usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
-
        /*
         * 5. Enable idle sync
         */