#ifdef CONFIG_SOC_DA8XX
        gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
        /* DDR PHY uses an x2 input clock */
-       gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
+       gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+                               (clk_get(DAVINCI_DDR_CLKID) / 1000000);
 #else
 
        unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
 
        DAVINCI_PLL0_SYSCLK2                    = DAVINCI_PLLC0_FLAG | 2,
        DAVINCI_PLL0_SYSCLK4                    = DAVINCI_PLLC0_FLAG | 4,
        DAVINCI_PLL0_SYSCLK6                    = DAVINCI_PLLC0_FLAG | 6,
+       DAVINCI_PLL1_SYSCLK1                    = DAVINCI_PLLC1_FLAG | 1,
        DAVINCI_PLL1_SYSCLK2                    = DAVINCI_PLLC1_FLAG | 2,
 
        /* map peripherals to clock IDs */
        DAVINCI_ARM_CLKID                       = DAVINCI_PLL0_SYSCLK6,
+       DAVINCI_DDR_CLKID                       = DAVINCI_PLL1_SYSCLK1,
        DAVINCI_MDIO_CLKID                      = DAVINCI_PLL0_SYSCLK4,
        DAVINCI_MMC_CLKID                       = DAVINCI_PLL0_SYSCLK2,
        DAVINCI_SPI0_CLKID                      = DAVINCI_PLL0_SYSCLK2,