]> git.sur5r.net Git - u-boot/commitdiff
MX35: add support for flea3 board
authorStefano Babic <sbabic@denx.de>
Sun, 23 Oct 2011 23:58:20 +0000 (23:58 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 3 Nov 2011 21:56:20 +0000 (22:56 +0100)
The flea3 board is a custom board by CarMediaLab used
in automotive.
Network (FEC), NOR, NAND and SPI are supported.

Signed-off-by: Stefano Babic <sbabic@denx.de>
MAINTAINERS
board/CarMediaLab/flea3/Makefile [new file with mode: 0644]
board/CarMediaLab/flea3/flea3.c [new file with mode: 0644]
board/CarMediaLab/flea3/lowlevel_init.S [new file with mode: 0644]
boards.cfg
include/configs/flea3.h [new file with mode: 0644]

index 576fea83099bf7409936c72d0d8b5714782972ad..54b917c042b3dbdf76068965c5904ebd0c16a34a 100644 (file)
@@ -560,6 +560,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
 Stefano Babic <sbabic@denx.de>
 
        ea20            davinci
+       flea3           i.MX35
        mx35pdk         i.MX35
        mx51evk         i.MX51
        polaris         xscale/pxa
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
new file mode 100644 (file)
index 0000000..f5ad494
--- /dev/null
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := flea3.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
new file mode 100644 (file)
index 0000000..64f4b57
--- /dev/null
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG                0x003F4208
+
+#define ESDCTL_DDR2_CONFIG     0x007FFC3F
+#define ESDCTL_0x92220000      0x92220000
+#define ESDCTL_0xA2220000      0xA2220000
+#define ESDCTL_0xB2220000      0xB2220000
+#define ESDCTL_0x82228080      0x82228080
+#define ESDCTL_DDR2_EMR2       0x04000000
+#define ESDCTL_DDR2_EMR3       0x06000000
+#define ESDCTL_PRECHARGE       0x00000400
+#define ESDCTL_DDR2_EN_DLL     0x02000400
+#define ESDCTL_DDR2_RESET_DLL  0x00000333
+#define ESDCTL_DDR2_MR         0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5     0x00F49F00
+
+static inline void dram_wait(unsigned int count)
+{
+       volatile unsigned int wait = count;
+
+       while (wait--)
+               ;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+               PHYS_SDRAM_1_SIZE);
+
+       return 0;
+}
+
+static void board_setup_sdram_bank(u32 start_address)
+
+{
+       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+       u32 *cfg_reg, *ctl_reg;
+       u32 val;
+
+       switch (start_address) {
+       case CSD0_BASE_ADDR:
+               cfg_reg = &esdc->esdcfg0;
+               ctl_reg = &esdc->esdctl0;
+               break;
+       case CSD1_BASE_ADDR:
+               cfg_reg = &esdc->esdcfg1;
+               ctl_reg = &esdc->esdctl1;
+               break;
+       default:
+               return;
+       }
+
+       /* Initialize MISC register for DDR2 */
+       val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+               ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+       writel(val, &esdc->esdmisc);
+       val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+       writel(val, &esdc->esdmisc);
+
+       /*
+        * according to DDR2 specs, wait a while before
+        * the PRECHARGE_ALL command
+        */
+       dram_wait(0x20000);
+
+       /* Load DDR2 config and timing */
+       writel(ESDCTL_DDR2_CONFIG, cfg_reg);
+
+       /* Precharge ALL */
+       writel(ESDCTL_0x92220000,
+               ctl_reg);
+       writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+       /* Load mode */
+       writel(ESDCTL_0xB2220000,
+               ctl_reg);
+       writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+       writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+       writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+       /* Precharge ALL */
+       writel(ESDCTL_0x92220000,
+               ctl_reg);
+       writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+       /* Set mode auto refresh : at least two refresh are required */
+       writel(ESDCTL_0xA2220000,
+               ctl_reg);
+       writel(0xda, start_address);
+       writel(0xda, start_address);
+
+       writel(ESDCTL_0xB2220000,
+               ctl_reg);
+       writeb(0xda, start_address + ESDCTL_DDR2_MR);
+       writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+       /* OCD mode exit */
+       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+       /* Set normal mode */
+       writel(ESDCTL_0x82228080,
+               ctl_reg);
+
+       dram_wait(0x20000);
+
+       /* Do not set delay lines, only for MDDR */
+}
+
+static void board_setup_sdram(void)
+{
+       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+       /* Initialize with default values both CSD0/1 */
+       writel(0x2000, &esdc->esdctl0);
+       writel(0x2000, &esdc->esdctl1);
+
+       board_setup_sdram_bank(CSD1_BASE_ADDR);
+}
+
+static void setup_iomux_uart3(void)
+{
+       mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+       mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+       int pad;
+
+       mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+       mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+       pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+                       | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+       mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+       mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+       mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+       mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+       mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+       mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+       mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+       mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+       mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+       mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+       mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+       /* setup pins for FEC */
+       mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+       struct ccm_regs *ccm =
+               (struct ccm_regs *)IMX_CCM_BASE;
+
+       /* setup GPIO3_1 to set HighVCore signal */
+       mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5);
+       gpio_direction_output(65, 1);
+
+       /* initialize PLL and clock configuration */
+       writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+       writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+       writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+       /* Set the core to run at 532 Mhz */
+       writel(0x00001000, &ccm->pdr0);
+
+       /* Set-up RAM */
+       board_setup_sdram();
+
+       /* enable clocks */
+       writel(readl(&ccm->cgr0) |
+               MXC_CCM_CGR0_EMI_MASK |
+               MXC_CCM_CGR0_EDI0_MASK |
+               MXC_CCM_CGR0_EPIT1_MASK,
+               &ccm->cgr0);
+
+       writel(readl(&ccm->cgr1) |
+               MXC_CCM_CGR1_FEC_MASK |
+               MXC_CCM_CGR1_GPIO1_MASK |
+               MXC_CCM_CGR1_GPIO2_MASK |
+               MXC_CCM_CGR1_GPIO3_MASK |
+               MXC_CCM_CGR1_I2C1_MASK |
+               MXC_CCM_CGR1_I2C2_MASK |
+               MXC_CCM_CGR1_I2C3_MASK,
+               &ccm->cgr1);
+
+       /* Set-up NAND */
+       __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+       /* Set pinmux for the required peripherals */
+       setup_iomux_uart3();
+       setup_iomux_i2c();
+       setup_iomux_fec();
+       setup_iomux_spi();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       return 0;
+}
+
+u32 get_board_rev(void)
+{
+       int rev = 0;
+
+       return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644 (file)
index 0000000..2f42fc9
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG                0x77777777
+#define AIPS_OPACR_CONFIG      0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG         0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG       0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG       0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG            0x00000040
+
+#define CCM_PDR0_CONFIG                0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+       core_init
+
+       init_aips
+
+       init_max
+
+       init_m3if
+
+       mov pc, lr
index 604becfb44d2311d0b967781b8a433f510634829..555bd63a37487591745475c86f4e68649cbc6109 100644 (file)
@@ -42,6 +42,7 @@ imx31_litekit                arm         arm1136     -                   logicpd
 imx31_phycore                arm         arm1136     -                   -              mx31
 imx31_phycore_eet            arm         arm1136     imx31_phycore       -              mx31         imx31_phycore:IMX31_PHYCORE_EET
 mx31pdk                      arm         arm1136     -                   freescale      mx31         mx31pdk:NAND_U_BOOT
+flea3                        arm         arm1136     -                   CarMediaLab    mx35
 mx35pdk                      arm         arm1136     -                   freescale      mx35
 omap2420h4                   arm         arm1136     -                   ti             omap24xx
 tnetv107x_evm                arm         arm1176     tnetv107xevm        ti             tnetv107x
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644 (file)
index 0000000..d88c578
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+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ  24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3                3668
+#endif
+
+#define CONFIG_MACH_TYPE               MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE   0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX      1
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY       3
+
+#define CONFIG_LOADADDR                0x90800000      /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE   FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP    /* undef to save memory */
+#define CONFIG_SYS_PROMPT      "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define        CONFIG_SYS_PROMPT_HUSH_PS2      "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE      256     /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS     16      /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0       /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ   /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ                          1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128 * 1024)    /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   1
+#define PHYS_SDRAM_1           CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE      (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE          CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR       (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE               (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
+                                       GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+                                       CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT         "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT       "mtdparts=mxc_nand:196m(root1)," \
+                               "196m(root2),-(user);"  \
+                               "physmap-flash.0:512k(u-boot),64k(env1)," \
+                               "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE          CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1   /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512  /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE   (64 * 1024)
+#define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector    */
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + \
+                               CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI           /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION    /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE      (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s)        str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "netdev=eth0\0"                                                 \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "addip_sta=setenv bootargs ${bootargs} "                        \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"               \
+       "addip=if test -n ${ipdyn};then run addip_dyn;"                 \
+               "else run addip_sta;fi\0"       \
+       "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
+       "addtty=setenv bootargs ${bootargs}"                            \
+               " console=ttymxc0,${baudrate}\0"                        \
+       "addmisc=setenv bootargs ${bootargs} ${misc}\0"                 \
+       "loadaddr=90800000\0"                                           \
+       "kernel_addr_r=90800000\0"                                      \
+       "hostname=" xstr(CONFIG_HOSTNAME) "\0"                          \
+       "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"                   \
+       "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"             \
+       "flash_self=run ramargs addip addtty addmtd addmisc;"           \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
+               "bootm ${kernel_addr}\0"                                \
+       "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
+               "run nfsargs addip addtty addmtd addmisc;"              \
+               "bootm ${kernel_addr_r}\0"                              \
+       "net_self_load=tftp ${kernel_addr_r} ${bootfile};"              \
+               "tftp ${ramdisk_addr_r} ${ramdisk_file};\0"             \
+       "net_self=if run net_self_load;then "                           \
+               "run ramargs addip addtty addmtd addmisc;"              \
+               "bootm ${kernel_addr_r} ${ramdisk_addr_r};"             \
+               "else echo Images not loades;fi\0"                      \
+       "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"                 \
+       "load=tftp ${loadaddr} ${u-boot}\0"                             \
+       "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"                \
+       "update=protect off ${uboot_addr} +40000;"                      \
+               "erase ${uboot_addr} +40000;"                           \
+               "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"          \
+       "upd=if run load;then echo Updating u-boot;if run update;"      \
+               "then echo U-Boot updated;"                             \
+                       "else echo Error updating u-boot !;"            \
+                       "echo Board without bootloader !!;"             \
+               "fi;"                                                   \
+               "else echo U-Boot not downloaded..exiting;fi\0"         \
+       "bootcmd=run net_nfs\0"
+
+#endif                         /* __CONFIG_H */