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</storageModule>\r
<tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.archiver.base.310362498" name="GNU ARM Archiver" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.archiver.base"/>\r
</toolChain>\r
</folderInfo>\r
+ <folderInfo id="com.silabs.ide.si32.gcc.debug#com.silabs.ide.si32.gcc:4.8.3.20131129@5.1008127701" name="/" resourcePath="Source/SilLabs_Code/kits/SLSTK3401A_EFM32PG">\r
+ <toolChain id="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.exe.2026080801" name="Si32 GNU ARM" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.exe" unusedChildren="">\r
+ <option id="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.debug.level.860218153.408368925" name="Debug Level" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.toolchain.debug.level.860218153"/>\r
+ <tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base.276729238" name="GNU ARM C Compiler" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.compiler.base.637949526"/>\r
+ <tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base.289631977" name="GNU ARM C++ Compiler" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.compiler.base.607108724"/>\r
+ <tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.assembler.base.1946889243" name="GNU ARM Assembler" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.assembler.base.599397077"/>\r
+ <tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base.364942885" name="GNU ARM C Linker" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base.1895173662"/>\r
+ <tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base.915572947" name="GNU ARM C++ Linker" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.cpp.linker.base.1027397459"/>\r
+ <tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.archiver.base.1439736431" name="GNU ARM Archiver" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.archiver.base.310362498"/>\r
+ </toolChain>\r
+ </folderInfo>\r
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+ <entry excluding="Source/SilLabs_Code/kits/SLSTK3401A_EFM32PG|Source/SilLabs_Code/Device/SiliconLabs/EFM32PG1B|Source/SilLabs_Code/CMSIS/efm32pg1b|Source/FreeRTOS_Source/portable/GCC/ARM_CM3|Source/SilLabs_Code/Device/SiliconLabs/EFM32WG/Source|Source/SilLabs_Code/kits/EFM32GG_STK3700|Source/SilLabs_Code/Device/SiliconLabs/EFM32GG|Source/SilLabs_Code/CMSIS/efm32gg|CMSIS/efm32gg" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
</sourceEntries>\r
</configuration>\r
</storageModule>\r
#include "em_burtc.h"\r
#include "em_rmu.h"\r
#include "em_int.h"\r
+#include "em_rtc.h"\r
#include "sleep.h"\r
\r
/* SEE THE COMMENTS ABOVE THE DEFINITION OF configCREATE_LOW_POWER_DEMO IN\r
--- /dev/null
+/* @file startup_efm32pg1b.S\r
+ * @brief startup file for Silicon Labs EFM32PG1B devices.\r
+ * For use with GCC for ARM Embedded Processors\r
+ * @version 4.2.1\r
+ * Date: 12 June 2014\r
+ *\r
+ */\r
+/* Copyright (c) 2011 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+ .syntax unified\r
+ .arch armv7-m\r
+ .section .stack\r
+ .align 3\r
+#ifdef __STACK_SIZE\r
+ .equ Stack_Size, __STACK_SIZE\r
+#else\r
+ .equ Stack_Size, 0x00000400\r
+#endif\r
+ .globl __StackTop\r
+ .globl __StackLimit\r
+__StackLimit:\r
+ .space Stack_Size\r
+ .size __StackLimit, . - __StackLimit\r
+__StackTop:\r
+ .size __StackTop, . - __StackTop\r
+\r
+ .section .heap\r
+ .align 3\r
+#ifdef __HEAP_SIZE\r
+ .equ Heap_Size, __HEAP_SIZE\r
+#else\r
+ .equ Heap_Size, 0x00000C00\r
+#endif\r
+ .globl __HeapBase\r
+ .globl __HeapLimit\r
+__HeapBase:\r
+ .if Heap_Size\r
+ .space Heap_Size\r
+ .endif\r
+ .size __HeapBase, . - __HeapBase\r
+__HeapLimit:\r
+ .size __HeapLimit, . - __HeapLimit\r
+\r
+ .section .vectors\r
+ .align 2\r
+ .globl __Vectors\r
+__Vectors:\r
+ .long __StackTop /* Top of Stack */\r
+ .long Reset_Handler /* Reset Handler */\r
+ .long NMI_Handler /* NMI Handler */\r
+ .long HardFault_Handler /* Hard Fault Handler */\r
+ .long MemManage_Handler /* MPU Fault Handler */\r
+ .long BusFault_Handler /* Bus Fault Handler */\r
+ .long UsageFault_Handler /* Usage Fault Handler */\r
+ .long Default_Handler /* Reserved */\r
+ .long Default_Handler /* Reserved */\r
+ .long Default_Handler /* Reserved */\r
+ .long Default_Handler /* Reserved */\r
+ .long SVC_Handler /* SVCall Handler */\r
+ .long DebugMon_Handler /* Debug Monitor Handler */\r
+ .long Default_Handler /* Reserved */\r
+ .long PendSV_Handler /* PendSV Handler */\r
+ .long SysTick_Handler /* SysTick Handler */\r
+\r
+ /* External interrupts */\r
+ .long EMU_IRQHandler /* 0 - EMU */\r
+ .long Default_Handler /* 1 - Reserved */\r
+ .long WDOG0_IRQHandler /* 2 - WDOG0 */\r
+ .long Default_Handler /* 3 - Reserved */\r
+ .long Default_Handler /* 4 - Reserved */\r
+ .long Default_Handler /* 5 - Reserved */\r
+ .long Default_Handler /* 6 - Reserved */\r
+ .long Default_Handler /* 7 - Reserved */\r
+ .long LDMA_IRQHandler /* 8 - LDMA */\r
+ .long GPIO_EVEN_IRQHandler /* 9 - GPIO_EVEN */\r
+ .long TIMER0_IRQHandler /* 10 - TIMER0 */\r
+ .long USART0_RX_IRQHandler /* 11 - USART0_RX */\r
+ .long USART0_TX_IRQHandler /* 12 - USART0_TX */\r
+ .long ACMP0_IRQHandler /* 13 - ACMP0 */\r
+ .long ADC0_IRQHandler /* 14 - ADC0 */\r
+ .long IDAC0_IRQHandler /* 15 - IDAC0 */\r
+ .long I2C0_IRQHandler /* 16 - I2C0 */\r
+ .long GPIO_ODD_IRQHandler /* 17 - GPIO_ODD */\r
+ .long TIMER1_IRQHandler /* 18 - TIMER1 */\r
+ .long USART1_RX_IRQHandler /* 19 - USART1_RX */\r
+ .long USART1_TX_IRQHandler /* 20 - USART1_TX */\r
+ .long LEUART0_IRQHandler /* 21 - LEUART0 */\r
+ .long PCNT0_IRQHandler /* 22 - PCNT0 */\r
+ .long CMU_IRQHandler /* 23 - CMU */\r
+ .long MSC_IRQHandler /* 24 - MSC */\r
+ .long CRYPTO_IRQHandler /* 25 - CRYPTO */\r
+ .long LETIMER0_IRQHandler /* 26 - LETIMER0 */\r
+ .long Default_Handler /* 27 - Reserved */\r
+ .long Default_Handler /* 28 - Reserved */\r
+ .long RTCC_IRQHandler /* 29 - RTCC */\r
+ .long Default_Handler /* 30 - Reserved */\r
+ .long CRYOTIMER_IRQHandler /* 31 - CRYOTIMER */\r
+ .long Default_Handler /* 32 - Reserved */\r
+ .long FPUEH_IRQHandler /* 33 - FPUEH */\r
+\r
+\r
+ .size __Vectors, . - __Vectors\r
+\r
+ .text\r
+ .thumb\r
+ .thumb_func\r
+ .align 2\r
+ .globl Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+#ifndef __NO_SYSTEM_INIT\r
+ ldr r0, =SystemInit\r
+ blx r0\r
+#endif\r
+\r
+/* Firstly it copies data from read only memory to RAM. There are two schemes\r
+ * to copy. One can copy more than one sections. Another can only copy\r
+ * one section. The former scheme needs more instructions and read-only\r
+ * data to implement than the latter.\r
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */\r
+\r
+#ifdef __STARTUP_COPY_MULTIPLE\r
+/* Multiple sections scheme.\r
+ *\r
+ * Between symbol address __copy_table_start__ and __copy_table_end__,\r
+ * there are array of triplets, each of which specify:\r
+ * offset 0: LMA of start of a section to copy from\r
+ * offset 4: VMA of start of a section to copy to\r
+ * offset 8: size of the section to copy. Must be multiply of 4\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r4, =__copy_table_start__\r
+ ldr r5, =__copy_table_end__\r
+\r
+.L_loop0:\r
+ cmp r4, r5\r
+ bge .L_loop0_done\r
+ ldr r1, [r4]\r
+ ldr r2, [r4, #4]\r
+ ldr r3, [r4, #8]\r
+\r
+.L_loop0_0:\r
+ subs r3, #4\r
+ ittt ge\r
+ ldrge r0, [r1, r3]\r
+ strge r0, [r2, r3]\r
+ bge .L_loop0_0\r
+\r
+ adds r4, #12\r
+ b .L_loop0\r
+\r
+.L_loop0_done:\r
+#else\r
+/* Single section scheme.\r
+ *\r
+ * The ranges of copy from/to are specified by following symbols\r
+ * __etext: LMA of start of the section to copy from. Usually end of text\r
+ * __data_start__: VMA of start of the section to copy to\r
+ * __data_end__: VMA of end of the section to copy to\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r1, =__etext\r
+ ldr r2, =__data_start__\r
+ ldr r3, =__data_end__\r
+\r
+.L_loop1:\r
+ cmp r2, r3\r
+ ittt lt\r
+ ldrlt r0, [r1], #4\r
+ strlt r0, [r2], #4\r
+ blt .L_loop1\r
+#endif /*__STARTUP_COPY_MULTIPLE */\r
+\r
+/* This part of work usually is done in C library startup code. Otherwise,\r
+ * define this macro to enable it in this startup.\r
+ *\r
+ * There are two schemes too. One can clear multiple BSS sections. Another\r
+ * can only clear one section. The former is more size expensive than the\r
+ * latter.\r
+ *\r
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.\r
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.\r
+ */\r
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE\r
+/* Multiple sections scheme.\r
+ *\r
+ * Between symbol address __copy_table_start__ and __copy_table_end__,\r
+ * there are array of tuples specifying:\r
+ * offset 0: Start of a BSS section\r
+ * offset 4: Size of this BSS section. Must be multiply of 4\r
+ */\r
+ ldr r3, =__zero_table_start__\r
+ ldr r4, =__zero_table_end__\r
+\r
+.L_loop2:\r
+ cmp r3, r4\r
+ bge .L_loop2_done\r
+ ldr r1, [r3]\r
+ ldr r2, [r3, #4]\r
+ movs r0, 0\r
+\r
+.L_loop2_0:\r
+ subs r2, #4\r
+ itt ge\r
+ strge r0, [r1, r2]\r
+ bge .L_loop2_0\r
+ adds r3, #8\r
+ b .L_loop2\r
+.L_loop2_done:\r
+#elif defined (__STARTUP_CLEAR_BSS)\r
+/* Single BSS section scheme.\r
+ *\r
+ * The BSS section is specified by following symbols\r
+ * __bss_start__: start of the BSS section.\r
+ * __bss_end__: end of the BSS section.\r
+ *\r
+ * Both addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r1, =__bss_start__\r
+ ldr r2, =__bss_end__\r
+\r
+ movs r0, 0\r
+.L_loop3:\r
+ cmp r1, r2\r
+ itt lt\r
+ strlt r0, [r1], #4\r
+ blt .L_loop3\r
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */\r
+\r
+#ifndef __START\r
+#define __START _start\r
+#endif\r
+ bl __START\r
+\r
+ .pool\r
+ .size Reset_Handler, . - Reset_Handler\r
+\r
+ .align 1\r
+ .thumb_func\r
+ .weak Default_Handler\r
+ .type Default_Handler, %function\r
+Default_Handler:\r
+ b .\r
+ .size Default_Handler, . - Default_Handler\r
+\r
+/* Macro to define default handlers. Default handler\r
+ * will be weak symbol and just dead loops. They can be\r
+ * overwritten by other handlers */\r
+ .macro def_irq_handler handler_name\r
+ .weak \handler_name\r
+ .set \handler_name, Default_Handler\r
+ .endm\r
+\r
+ def_irq_handler NMI_Handler\r
+ def_irq_handler HardFault_Handler\r
+ def_irq_handler MemManage_Handler\r
+ def_irq_handler BusFault_Handler\r
+ def_irq_handler UsageFault_Handler\r
+ def_irq_handler SVC_Handler\r
+ def_irq_handler DebugMon_Handler\r
+ def_irq_handler PendSV_Handler\r
+ def_irq_handler SysTick_Handler\r
+\r
+\r
+ def_irq_handler EMU_IRQHandler\r
+ def_irq_handler WDOG0_IRQHandler\r
+ def_irq_handler LDMA_IRQHandler\r
+ def_irq_handler GPIO_EVEN_IRQHandler\r
+ def_irq_handler TIMER0_IRQHandler\r
+ def_irq_handler USART0_RX_IRQHandler\r
+ def_irq_handler USART0_TX_IRQHandler\r
+ def_irq_handler ACMP0_IRQHandler\r
+ def_irq_handler ADC0_IRQHandler\r
+ def_irq_handler IDAC0_IRQHandler\r
+ def_irq_handler I2C0_IRQHandler\r
+ def_irq_handler GPIO_ODD_IRQHandler\r
+ def_irq_handler TIMER1_IRQHandler\r
+ def_irq_handler USART1_RX_IRQHandler\r
+ def_irq_handler USART1_TX_IRQHandler\r
+ def_irq_handler LEUART0_IRQHandler\r
+ def_irq_handler PCNT0_IRQHandler\r
+ def_irq_handler CMU_IRQHandler\r
+ def_irq_handler MSC_IRQHandler\r
+ def_irq_handler CRYPTO_IRQHandler\r
+ def_irq_handler LETIMER0_IRQHandler\r
+ def_irq_handler RTCC_IRQHandler\r
+ def_irq_handler CRYOTIMER_IRQHandler\r
+ def_irq_handler FPUEH_IRQHandler\r
+\r
+ .end\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file system_efm32pg1b.c\r
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#include <stdint.h>\r
+#include "em_device.h"\r
+\r
+/*******************************************************************************\r
+ ****************************** DEFINES ************************************\r
+ ******************************************************************************/\r
+\r
+/** LFRCO frequency, tuned to below frequency during manufacturing. */\r
+#define EFM32_LFRCO_FREQ (32768UL)\r
+#define EFM32_ULFRCO_FREQ (1000UL)\r
+\r
+/*******************************************************************************\r
+ ************************** LOCAL VARIABLES ********************************\r
+ ******************************************************************************/\r
+\r
+/* System oscillator frequencies. These frequencies are normally constant */\r
+/* for a target, but they are made configurable in order to allow run-time */\r
+/* handling of different boards. The crystal oscillator clocks can be set */\r
+/* compile time to a non-default value by defining respective EFM_nFXO_FREQ */\r
+/* values according to board design. By defining the EFM_nFXO_FREQ to 0, */\r
+/* one indicates that the oscillator is not present, in order to save some */\r
+/* SW footprint. */\r
+\r
+#ifndef EFM32_HFRCO_MAX_FREQ\r
+#define EFM32_HFRCO_MAX_FREQ (38000000UL)\r
+#endif\r
+\r
+#ifndef EFM32_HFXO_FREQ\r
+#define EFM32_HFXO_FREQ (40000000UL)\r
+#endif\r
+\r
+#ifndef EFM32_HFRCO_STARTUP_FREQ\r
+#define EFM32_HFRCO_STARTUP_FREQ (19000000UL)\r
+#endif\r
+\r
+\r
+/* Do not define variable if HF crystal oscillator not present */\r
+#if (EFM32_HFXO_FREQ > 0UL)\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/** System HFXO clock. */\r
+static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;\r
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
+#endif\r
+\r
+#ifndef EFM32_LFXO_FREQ\r
+#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)\r
+#endif\r
+/* Do not define variable if LF crystal oscillator not present */\r
+#if (EFM32_LFXO_FREQ > 0UL)\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/** System LFXO clock. */\r
+static uint32_t SystemLFXOClock = 32768UL;\r
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+ ************************** GLOBAL VARIABLES *******************************\r
+ ******************************************************************************/\r
+\r
+/**\r
+ * @brief\r
+ * System System Clock Frequency (Core Clock).\r
+ *\r
+ * @details\r
+ * Required CMSIS global variable that must be kept up-to-date.\r
+ */\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief\r
+ * System HFRCO frequency\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary variable, not part of the CMSIS definition.\r
+ *\r
+ * @details\r
+ * Frequency of the system HFRCO oscillator\r
+ */\r
+uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;\r
+\r
+\r
+/*******************************************************************************\r
+ ************************** GLOBAL FUNCTIONS *******************************\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the current core clock frequency.\r
+ *\r
+ * @details\r
+ * Calculate and get the current core clock frequency based on the current\r
+ * configuration. Assuming that the SystemCoreClock global variable is\r
+ * maintained, the core clock frequency is stored in that variable as well.\r
+ * This function will however calculate the core clock based on actual HW\r
+ * configuration. It will also update the SystemCoreClock global variable.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The current core clock frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemCoreClockGet(void)\r
+{\r
+ uint32_t ret;\r
+ uint32_t presc;\r
+\r
+ ret = SystemHFClockGet();\r
+ presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >>\r
+ _CMU_HFCOREPRESC_PRESC_SHIFT;\r
+ ret /= (presc + 1);\r
+\r
+ /* Keep CMSIS system clock variable up-to-date */\r
+ SystemCoreClock = ret;\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the maximum core clock frequency.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The maximum core clock frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemMaxCoreClockGet(void)\r
+{\r
+ return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \\r
+ EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the current HFCLK frequency.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The current HFCLK frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemHFClockGet(void)\r
+{\r
+ uint32_t ret;\r
+\r
+ switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)\r
+ {\r
+ case CMU_HFCLKSTATUS_SELECTED_LFXO:\r
+#if (EFM32_LFXO_FREQ > 0)\r
+ ret = SystemLFXOClock;\r
+#else\r
+ /* We should not get here, since core should not be clocked. May */\r
+ /* be caused by a misconfiguration though. */\r
+ ret = 0;\r
+#endif\r
+ break;\r
+\r
+ case CMU_HFCLKSTATUS_SELECTED_LFRCO:\r
+ ret = EFM32_LFRCO_FREQ;\r
+ break;\r
+\r
+ case CMU_HFCLKSTATUS_SELECTED_HFXO:\r
+#if (EFM32_HFXO_FREQ > 0)\r
+ ret = SystemHFXOClock;\r
+#else\r
+ /* We should not get here, since core should not be clocked. May */\r
+ /* be caused by a misconfiguration though. */\r
+ ret = 0;\r
+#endif\r
+ break;\r
+\r
+ default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */\r
+ ret = SystemHfrcoFreq;\r
+ break;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get high frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * HFXO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemHFXOClockGet(void)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_HFXO_FREQ > 0)\r
+ return SystemHFXOClock;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Set high frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This function is mainly provided for being able to handle target systems\r
+ * with different HF crystal oscillator frequencies run-time. If used, it\r
+ * should probably only be used once during system startup.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @param[in] freq\r
+ * HFXO frequency in Hz used for target.\r
+ *****************************************************************************/\r
+void SystemHFXOClockSet(uint32_t freq)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_HFXO_FREQ > 0)\r
+ SystemHFXOClock = freq;\r
+\r
+ /* Update core clock frequency if HFXO is used to clock core */\r
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO)\r
+ {\r
+ /* The function will update the global variable */\r
+ SystemCoreClockGet();\r
+ }\r
+#else\r
+ (void)freq; /* Unused parameter */\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Initialize the system.\r
+ *\r
+ * @details\r
+ * Do required generic HW system init.\r
+ *\r
+ * @note\r
+ * This function is invoked during system init, before the main() routine\r
+ * and any data has been initialized. For this reason, it cannot do any\r
+ * initialization of variables etc.\r
+ *****************************************************************************/\r
+void SystemInit(void)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ /* Set floating point coprosessor access mode. */\r
+ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */\r
+ (3UL << 11 * 2)); /* set CP11 Full Access */\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get low frequency RC oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * LFRCO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemLFRCOClockGet(void)\r
+{\r
+ /* Currently we assume that this frequency is properly tuned during */\r
+ /* manufacturing and is not changed after reset. If future requirements */\r
+ /* for re-tuning by user, we can add support for that. */\r
+ return EFM32_LFRCO_FREQ;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get ultra low frequency RC oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * ULFRCO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemULFRCOClockGet(void)\r
+{\r
+ /* The ULFRCO frequency is not tuned, and can be very inaccurate */\r
+ return EFM32_ULFRCO_FREQ;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get low frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * LFXO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemLFXOClockGet(void)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_LFXO_FREQ > 0)\r
+ return SystemLFXOClock;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Set low frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This function is mainly provided for being able to handle target systems\r
+ * with different HF crystal oscillator frequencies run-time. If used, it\r
+ * should probably only be used once during system startup.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @param[in] freq\r
+ * LFXO frequency in Hz used for target.\r
+ *****************************************************************************/\r
+void SystemLFXOClockSet(uint32_t freq)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_LFXO_FREQ > 0)\r
+ SystemLFXOClock = freq;\r
+\r
+ /* Update core clock frequency if LFXO is used to clock core */\r
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO)\r
+ {\r
+ /* The function will update the global variable */\r
+ SystemCoreClockGet();\r
+ }\r
+#else\r
+ (void)freq; /* Unused parameter */\r
+#endif\r
+}\r
================ Revision history ============================================\r
+4.2.1:\r
+ - No changes.\r
+\r
+4.2.0:\r
+ - Various corrections and improvements of Jade/Pearl/EFR family files.\r
+\r
+4.1.1:\r
+ - Added CRYPTO module (cryptographic engine) to Jade/Pearl/EFR families.\r
+\r
+4.1.0:\r
+ - Added device headers for new families EZR32HG (EZR Happy Gecko), EFM32JG\r
+ (Jade Gecko) and EFM32PG (Pearl Gecko)\r
+ - Bugfixes in EZR32 LG and WG system/startup files.\r
+ - Added support for new EZR32HG family.\r
+\r
4.0.0:\r
- Use ARM CMSIS version 4.2.0.\r
- emlib: New style version macros in em_version.h.\r
* @file efm32gg990f1024.h\r
* @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
* for EFM32GG990F1024\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
*****************************************************************************/\r
\r
-#ifndef __SILICON_LABS_EFM32GG990F1024_H__\r
-#define __SILICON_LABS_EFM32GG990F1024_H__\r
+#ifndef EFM32GG990F1024_H\r
+#define EFM32GG990F1024_H\r
\r
#ifdef __cplusplus\r
extern "C" {\r
#ifdef __cplusplus\r
}\r
#endif\r
-#endif /* __SILICON_LABS_EFM32GG990F1024_H__ */\r
+#endif /* EFM32GG990F1024_H */\r
/**************************************************************************//**\r
* @file efm32gg_acmp.h\r
* @brief EFM32GG_ACMP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_ACMP\r
* @{\r
#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */\r
\r
/** @} End of group EFM32GG_ACMP */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_adc.h\r
* @brief EFM32GG_ADC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_ADC\r
* @{\r
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
\r
/** @} End of group EFM32GG_ADC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_aes.h\r
* @brief EFM32GG_AES register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_AES\r
* @{\r
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */\r
\r
/** @} End of group EFM32GG_AES */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_af_pins.h\r
* @brief EFM32GG_AF_PINS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_AF_Pins\r
* @{\r
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : -1)\r
\r
/** @} End of group EFM32GG_AF_Pins */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_af_ports.h\r
* @brief EFM32GG_AF_PORTS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_AF_Ports\r
* @{\r
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : -1)\r
\r
/** @} End of group EFM32GG_AF_Ports */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_burtc.h\r
* @brief EFM32GG_BURTC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_BURTC\r
* @{\r
#define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */\r
\r
/** @} End of group EFM32GG_BURTC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_burtc_ret.h\r
* @brief EFM32GG_BURTC_RET register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief BURTC_RET EFM32GG BURTC RET\r
*****************************************************************************/\r
__IO uint32_t REG; /**< Retention Register */\r
} BURTC_RET_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_calibrate.h\r
* @brief EFM32GG_CALIBRATE register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_CALIBRATE\r
* @{\r
__I uint32_t VALUE; /**< Default value for calibration register */\r
} CALIBRATE_TypeDef; /** @} */\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_cmu.h\r
* @brief EFM32GG_CMU register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_CMU\r
* @{\r
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
\r
/** @} End of group EFM32GG_CMU */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_dac.h\r
* @brief EFM32GG_DAC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_DAC\r
* @{\r
#define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */\r
\r
/** @} End of group EFM32GG_DAC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_devinfo.h\r
* @brief EFM32GG_DEVINFO register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_DEVINFO\r
* @{\r
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */\r
\r
/** @} End of group EFM32GG_DEVINFO */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_dma.h\r
* @brief EFM32GG_DMA register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_DMA\r
* @{\r
#define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for DMA_CH_CTRL */\r
\r
/** @} End of group EFM32GG_DMA */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_dma_ch.h\r
* @brief EFM32GG_DMA_CH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief DMA_CH EFM32GG DMA CH\r
*****************************************************************************/\r
__IO uint32_t CTRL; /**< Channel Control Register */\r
} DMA_CH_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_dma_descriptor.h\r
* @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_DMA_DESCRIPTOR\r
* @{\r
__IO uint32_t USER; /**< DMA padding register, available for user */\r
} DMA_DESCRIPTOR_TypeDef; /** @} */\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_dmactrl.h\r
* @brief EFM32GG_DMACTRL register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
\r
/**************************************************************************//**\r
* @defgroup EFM32GG_DMACTRL_BitFields\r
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */\r
\r
/** @} End of group EFM32GG_DMA */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_dmareq.h\r
* @brief EFM32GG_DMAREQ register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
\r
/**************************************************************************//**\r
* @defgroup EFM32GG_DMAREQ_BitFields\r
#define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */\r
\r
/** @} End of group EFM32GG_DMAREQ */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_ebi.h\r
* @brief EFM32GG_EBI register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_EBI\r
* @{\r
#define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */\r
\r
/** @} End of group EFM32GG_EBI */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_emu.h\r
* @brief EFM32GG_EMU register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_EMU\r
* @{\r
#define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */\r
\r
/** @} End of group EFM32GG_EMU */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_etm.h\r
* @brief EFM32GG_ETM register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_ETM\r
* @{\r
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */\r
\r
/** @} End of group EFM32GG_ETM */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_gpio.h\r
* @brief EFM32GG_GPIO register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_GPIO\r
* @{\r
#define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUCAUSE */\r
\r
/** @} End of group EFM32GG_GPIO */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_gpio_p.h\r
* @brief EFM32GG_GPIO_P register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief GPIO_P EFM32GG GPIO P\r
*****************************************************************************/\r
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */\r
} GPIO_P_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_i2c.h\r
* @brief EFM32GG_I2C register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_I2C\r
* @{\r
#define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */\r
\r
/** @} End of group EFM32GG_I2C */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_lcd.h\r
* @brief EFM32GG_LCD register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_LCD\r
* @{\r
#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */\r
\r
/** @} End of group EFM32GG_LCD */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_lesense.h\r
* @brief EFM32GG_LESENSE register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_LESENSE\r
* @{\r
#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */\r
\r
/** @} End of group EFM32GG_LESENSE */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_lesense_buf.h\r
* @brief EFM32GG_LESENSE_BUF register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief LESENSE_BUF EFM32GG LESENSE BUF\r
*****************************************************************************/\r
__IO uint32_t DATA; /**< Scan results */\r
} LESENSE_BUF_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_lesense_ch.h\r
* @brief EFM32GG_LESENSE_CH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief LESENSE_CH EFM32GG LESENSE CH\r
*****************************************************************************/\r
uint32_t RESERVED0[1]; /**< Reserved future */\r
} LESENSE_CH_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_lesense_st.h\r
* @brief EFM32GG_LESENSE_ST register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief LESENSE_ST EFM32GG LESENSE ST\r
*****************************************************************************/\r
__IO uint32_t TCONFB; /**< State transition configuration B */\r
} LESENSE_ST_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_letimer.h\r
* @brief EFM32GG_LETIMER register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_LETIMER\r
* @{\r
#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */\r
\r
/** @} End of group EFM32GG_LETIMER */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_leuart.h\r
* @brief EFM32GG_LEUART register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_LEUART\r
* @{\r
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */\r
\r
/** @} End of group EFM32GG_LEUART */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_msc.h\r
* @brief EFM32GG_MSC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_MSC\r
* @{\r
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */\r
\r
/** @} End of group EFM32GG_MSC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_pcnt.h\r
* @brief EFM32GG_PCNT register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_PCNT\r
* @{\r
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */\r
\r
/** @} End of group EFM32GG_PCNT */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_prs.h\r
* @brief EFM32GG_PRS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_PRS\r
* @{\r
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
\r
/** @} End of group EFM32GG_PRS */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_prs_ch.h\r
* @brief EFM32GG_PRS_CH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief PRS_CH EFM32GG PRS CH\r
*****************************************************************************/\r
__IO uint32_t CTRL; /**< Channel Control Register */\r
} PRS_CH_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_prs_signals.h\r
* @brief EFM32GG_PRS_SIGNALS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @addtogroup EFM32GG_PRS_Signals\r
* @{\r
#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
\r
/** @} End of group EFM32GG_PRS */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_rmu.h\r
* @brief EFM32GG_RMU register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_RMU\r
* @{\r
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */\r
\r
/** @} End of group EFM32GG_RMU */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_romtable.h\r
* @brief EFM32GG_ROMTABLE register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_ROMTABLE\r
* @{\r
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */\r
\r
/** @} End of group EFM32GG_ROMTABLE */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_rtc.h\r
* @brief EFM32GG_RTC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_RTC\r
* @{\r
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */\r
\r
/** @} End of group EFM32GG_RTC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_timer.h\r
* @brief EFM32GG_TIMER register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_TIMER\r
* @{\r
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */\r
\r
/** @} End of group EFM32GG_TIMER */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_timer_cc.h\r
* @brief EFM32GG_TIMER_CC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief TIMER_CC EFM32GG TIMER CC\r
*****************************************************************************/\r
__IO uint32_t CCVB; /**< CC Channel Buffer Register */\r
} TIMER_CC_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_uart.h\r
* @brief EFM32GG_UART register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
\r
/**************************************************************************//**\r
* @defgroup EFM32GG_UART_BitFields\r
#define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */\r
\r
/** @} End of group EFM32GG_UART */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_usart.h\r
* @brief EFM32GG_USART register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_USART\r
* @{\r
#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */\r
\r
/** @} End of group EFM32GG_USART */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_usb.h\r
* @brief EFM32GG_USB register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_USB\r
* @{\r
#define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */\r
\r
/** @} End of group EFM32GG_USB */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_usb_diep.h\r
* @brief EFM32GG_USB_DIEP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief USB_DIEP EFM32GG USB DIEP\r
*****************************************************************************/\r
uint32_t RESERVED2[1]; /**< Reserved future */\r
} USB_DIEP_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_usb_doep.h\r
* @brief EFM32GG_USB_DOEP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief USB_DOEP EFM32GG USB DOEP\r
*****************************************************************************/\r
uint32_t RESERVED2[2]; /**< Reserved future */\r
} USB_DOEP_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_usb_hc.h\r
* @brief EFM32GG_USB_HC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief USB_HC EFM32GG USB HC\r
*****************************************************************************/\r
uint32_t RESERVED1[2]; /**< Reserved future */\r
} USB_HC_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32gg_vcmp.h\r
* @brief EFM32GG_VCMP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_VCMP\r
* @{\r
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */\r
\r
/** @} End of group EFM32GG_VCMP */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32gg_wdog.h\r
* @brief EFM32GG_WDOG register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32GG_WDOG\r
* @{\r
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
\r
/** @} End of group EFM32GG_WDOG */\r
-\r
+/** @} End of group Parts */\r
\r
*\r
*\r
* @endverbatim\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
*****************************************************************************/\r
\r
-#ifndef __SILICON_LABS_EM_DEVICE_H__\r
-#define __SILICON_LABS_EM_DEVICE_H__\r
+#ifndef EM_DEVICE_H\r
+#define EM_DEVICE_H\r
\r
#if defined(EFM32GG230F1024)\r
#include "efm32gg230f1024.h"\r
#else\r
#error "em_device.h: PART NUMBER undefined"\r
#endif\r
-#endif /* __SILICON_LABS_EM_DEVICE_H__ */\r
+#endif /* EM_DEVICE_H */\r
/***************************************************************************//**\r
* @file system_efm32gg.h\r
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
*****************************************************************************/\r
\r
-#ifndef __SILICON_LABS_SYSTEM_EFM32GG_H__\r
-#define __SILICON_LABS_SYSTEM_EFM32GG_H__\r
+#ifndef SYSTEM_EFM32GG_H\r
+#define SYSTEM_EFM32GG_H\r
\r
#ifdef __cplusplus\r
extern "C" {\r
******************************************************************************/\r
\r
/* Interrupt routines - prototypes */\r
-#if defined(_EFM32_GIANT_FAMILY)\r
void Reset_Handler(void);\r
void NMI_Handler(void);\r
void HardFault_Handler(void);\r
void DebugMon_Handler(void);\r
void PendSV_Handler(void);\r
void SysTick_Handler(void);\r
+\r
void DMA_IRQHandler(void);\r
void GPIO_EVEN_IRQHandler(void);\r
void TIMER0_IRQHandler(void);\r
void AES_IRQHandler(void);\r
void EBI_IRQHandler(void);\r
void EMU_IRQHandler(void);\r
-#endif\r
\r
uint32_t SystemCoreClockGet(void);\r
+uint32_t SystemMaxCoreClockGet(void);\r
\r
/**************************************************************************//**\r
* @brief\r
#ifdef __cplusplus\r
}\r
#endif\r
-#endif /* __SILICON_LABS_SYSTEM_EFM32GG_H__ */\r
+#endif /* SYSTEM_EFM32GG_H */\r
/* */\r
/* Silicon Laboratories, Inc. 2015 */\r
/* */\r
-/* Version 4.0.0 */\r
+/* Version 4.2.0 */\r
/* */\r
\r
MEMORY\r
/* @file startup_efm32gg.S\r
* @brief startup file for Silicon Labs EFM32GG devices.\r
* For use with GCC for ARM Embedded Processors\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
* Date: 12 June 2014\r
*\r
*/\r
.long SysTick_Handler /* SysTick Handler */\r
\r
/* External interrupts */\r
+\r
.long DMA_IRQHandler /* 0 - DMA */\r
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */\r
.long TIMER0_IRQHandler /* 2 - TIMER0 */\r
* @file startup_efm32gg.c\r
* @brief CMSIS Compatible EFM32GG startup file in C.\r
* Should be used with GCC 'GNU Tools ARM Embedded'\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
* Date: 12 June 2014\r
*\r
*/\r
SysTick_Handler, /* SysTick Handler */\r
\r
/* External interrupts */\r
+\r
DMA_IRQHandler, /* 0 - DMA */\r
GPIO_EVEN_IRQHandler, /* 1 - GPIO_EVEN */\r
TIMER0_IRQHandler, /* 2 - TIMER0 */\r
/***************************************************************************//**\r
* @file system_efm32gg.c\r
* @brief CMSIS Cortex-M3 System Layer for EFM32GG devices.\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
/* SW footprint. */\r
\r
#ifndef EFM32_HFXO_FREQ\r
-#ifdef _EFM32_GIANT_FAMILY\r
#define EFM32_HFXO_FREQ (48000000UL)\r
-#else\r
-#define EFM32_HFXO_FREQ (32000000UL)\r
-#endif\r
#endif\r
+\r
+#define EFM32_HFRCO_MAX_FREQ (28000000UL)\r
+\r
/* Do not define variable if HF crystal oscillator not present */\r
#if (EFM32_HFXO_FREQ > 0)\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
-/** System HFXO clock. */ \r
+/** System HFXO clock. */\r
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;\r
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
#endif\r
\r
-#ifndef EFM32_LFXO_FREQ \r
+#ifndef EFM32_LFXO_FREQ\r
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)\r
#endif\r
+\r
/* Do not define variable if LF crystal oscillator not present */\r
#if (EFM32_LFXO_FREQ > 0)\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
-/** System LFXO clock. */ \r
+/** System LFXO clock. */\r
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;\r
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
#endif\r
uint32_t SystemCoreClockGet(void)\r
{\r
uint32_t ret;\r
- \r
+\r
ret = SystemHFClockGet();\r
-#if defined (_EFM32_GIANT_FAMILY)\r
/* Leopard/Giant Gecko has an additional divider */\r
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));\r
-#endif\r
- ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> \r
+ ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>\r
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;\r
\r
/* Keep CMSIS variable up-to-date just in case */\r
}\r
\r
\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the maximum core clock frequency.\r
+ *\r
+ * @note\r
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The maximum core clock frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemMaxCoreClockGet(void)\r
+{\r
+ return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \\r
+ EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);\r
+}\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Get the current HFCLK frequency.\r
uint32_t SystemHFClockGet(void)\r
{\r
uint32_t ret;\r
- \r
+\r
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |\r
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))\r
{\r
ret = 0;\r
#endif\r
break;\r
- \r
+\r
case CMU_STATUS_LFRCOSEL:\r
ret = EFM32_LFRCO_FREQ;\r
break;\r
- \r
+\r
case CMU_STATUS_HFXOSEL:\r
#if (EFM32_HFXO_FREQ > 0)\r
ret = SystemHFXOClock;\r
ret = 0;\r
#endif\r
break;\r
- \r
+\r
default: /* CMU_STATUS_HFRCOSEL */\r
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)\r
{\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b100f128gm32.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
+ * for EFM32PG1B100F128GM32\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SILICON_LABS_EFM32PG1B100F128GM32_H\r
+#define SILICON_LABS_EFM32PG1B100F128GM32_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************//**\r
+ * @addtogroup Parts\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32 EFM32PG1B100F128GM32\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers *******************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+\r
+/****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/\r
+\r
+ EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */\r
+ WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */\r
+ LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */\r
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */\r
+ ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */\r
+ ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */\r
+ IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */\r
+ I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */\r
+ USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */\r
+ LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */\r
+ PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */\r
+ CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */\r
+ MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */\r
+ CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */\r
+ LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
+ RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */\r
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */\r
+ FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_Core EFM32PG1B100F128GM32 Core\r
+ * @{\r
+ * @brief Processor and Core Peripheral Section\r
+ *****************************************************************************/\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __FPU_PRESENT 1 /**< Presence of FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Core */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32PG1B100F128GM32_Part EFM32PG1B100F128GM32 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+/** Part family */\r
+#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */\r
+#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
+#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */\r
+#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */\r
+\r
+/* If part number is not defined as compiler option, define it */\r
+#if !defined(EFM32PG1B100F128GM32)\r
+#define EFM32PG1B100F128GM32 1 /**< PEARL Gecko Part */\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32PG1B100F128GM32" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */\r
+#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */\r
+#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */\r
+#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */\r
+#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */\r
+#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */\r
+#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */\r
+#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */\r
+#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */\r
+#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */\r
+#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */\r
+#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */\r
+#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */\r
+#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */\r
+#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */\r
+#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */\r
+#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */\r
+#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */\r
+#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */\r
+#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */\r
+#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+\r
+/** Bit banding area */\r
+#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
+#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
+\r
+/** Flash and SRAM limits for EFM32PG1B100F128GM32 */\r
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
+#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */\r
+#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */\r
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
+#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */\r
+#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */\r
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 72\r
+#define AFCHANLOC_MAX 32\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 61\r
+\r
+/* Part number capabilities */\r
+\r
+#define TIMER_PRESENT /**< TIMER is available in this part */\r
+#define TIMER_COUNT 2 /**< 2 TIMERs available */\r
+#define USART_PRESENT /**< USART is available in this part */\r
+#define USART_COUNT 2 /**< 2 USARTs available */\r
+#define LEUART_PRESENT /**< LEUART is available in this part */\r
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */\r
+#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
+#define PCNT_PRESENT /**< PCNT is available in this part */\r
+#define PCNT_COUNT 1 /**< 1 PCNTs available */\r
+#define I2C_PRESENT /**< I2C is available in this part */\r
+#define I2C_COUNT 1 /**< 1 I2Cs available */\r
+#define ADC_PRESENT /**< ADC is available in this part */\r
+#define ADC_COUNT 1 /**< 1 ADCs available */\r
+#define ACMP_PRESENT /**< ACMP is available in this part */\r
+#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
+#define IDAC_PRESENT /**< IDAC is available in this part */\r
+#define IDAC_COUNT 1 /**< 1 IDACs available */\r
+#define WDOG_PRESENT /**< WDOG is available in this part */\r
+#define WDOG_COUNT 1 /**< 1 WDOGs available */\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define CRYPTO_PRESENT\r
+#define CRYPTO_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define LDMA_PRESENT\r
+#define LDMA_COUNT 1\r
+#define FPUEH_PRESENT\r
+#define FPUEH_COUNT 1\r
+#define GPCRC_PRESENT\r
+#define GPCRC_COUNT 1\r
+#define CRYOTIMER_PRESENT\r
+#define CRYOTIMER_COUNT 1\r
+#define RTCC_PRESENT\r
+#define RTCC_COUNT 1\r
+#define BOOTLOADER_PRESENT\r
+#define BOOTLOADER_COUNT 1\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_efm32pg1b.h" /* System Header File */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Part */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_TypeDefs EFM32PG1B100F128GM32 Peripheral TypeDefs\r
+ * @{\r
+ * @brief Device Specific Peripheral Register Structures\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_msc.h"\r
+#include "efm32pg1b_emu.h"\r
+#include "efm32pg1b_rmu.h"\r
+#include "efm32pg1b_cmu.h"\r
+#include "efm32pg1b_crypto.h"\r
+#include "efm32pg1b_gpio_p.h"\r
+#include "efm32pg1b_gpio.h"\r
+#include "efm32pg1b_prs_ch.h"\r
+#include "efm32pg1b_prs.h"\r
+#include "efm32pg1b_ldma_ch.h"\r
+#include "efm32pg1b_ldma.h"\r
+#include "efm32pg1b_fpueh.h"\r
+#include "efm32pg1b_gpcrc.h"\r
+#include "efm32pg1b_timer_cc.h"\r
+#include "efm32pg1b_timer.h"\r
+#include "efm32pg1b_usart.h"\r
+#include "efm32pg1b_leuart.h"\r
+#include "efm32pg1b_letimer.h"\r
+#include "efm32pg1b_cryotimer.h"\r
+#include "efm32pg1b_pcnt.h"\r
+#include "efm32pg1b_i2c.h"\r
+#include "efm32pg1b_adc.h"\r
+#include "efm32pg1b_acmp.h"\r
+#include "efm32pg1b_idac.h"\r
+#include "efm32pg1b_rtcc_cc.h"\r
+#include "efm32pg1b_rtcc_ret.h"\r
+#include "efm32pg1b_rtcc.h"\r
+#include "efm32pg1b_wdog_pch.h"\r
+#include "efm32pg1b_wdog.h"\r
+#include "efm32pg1b_dma_descriptor.h"\r
+#include "efm32pg1b_devinfo.h"\r
+#include "efm32pg1b_romtable.h"\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_TypeDefs */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_Base EFM32PG1B100F128GM32 Peripheral Memory Map\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */\r
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */\r
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */\r
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */\r
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */\r
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */\r
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */\r
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */\r
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */\r
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */\r
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */\r
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */\r
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */\r
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */\r
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */\r
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */\r
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */\r
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */\r
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */\r
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */\r
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */\r
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_Base */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_Declaration EFM32PG1B100F128GM32 Peripheral Declarations\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */\r
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */\r
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */\r
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */\r
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_Declaration */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_Peripheral_Offsets EFM32PG1B100F128GM32 Peripheral Offsets\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */\r
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */\r
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */\r
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */\r
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */\r
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */\r
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */\r
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */\r
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */\r
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Peripheral_Offsets */\r
+\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_BitFields EFM32PG1B100F128GM32 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_prs_signals.h"\r
+#include "efm32pg1b_dmareq.h"\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_UNLOCK EFM32PG1B100F128GM32 Unlock Codes\r
+ * @{\r
+ *****************************************************************************/\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_UNLOCK */\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_BitFields */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F128GM32_Alternate_Function EFM32PG1B100F128GM32 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_af_ports.h"\r
+#include "efm32pg1b_af_pins.h"\r
+\r
+/** @} End of group EFM32PG1B100F128GM32_Alternate_Function */\r
+\r
+/**************************************************************************//**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ *****************************************************************************/\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/** @} End of group EFM32PG1B100F128GM32 */\r
+\r
+/** @} End of group Parts */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SILICON_LABS_EFM32PG1B100F128GM32_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b100f256gm32.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
+ * for EFM32PG1B100F256GM32\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SILICON_LABS_EFM32PG1B100F256GM32_H\r
+#define SILICON_LABS_EFM32PG1B100F256GM32_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************//**\r
+ * @addtogroup Parts\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32 EFM32PG1B100F256GM32\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers *******************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+\r
+/****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/\r
+\r
+ EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */\r
+ WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */\r
+ LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */\r
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */\r
+ ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */\r
+ ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */\r
+ IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */\r
+ I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */\r
+ USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */\r
+ LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */\r
+ PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */\r
+ CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */\r
+ MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */\r
+ CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */\r
+ LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
+ RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */\r
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */\r
+ FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_Core EFM32PG1B100F256GM32 Core\r
+ * @{\r
+ * @brief Processor and Core Peripheral Section\r
+ *****************************************************************************/\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __FPU_PRESENT 1 /**< Presence of FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Core */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32PG1B100F256GM32_Part EFM32PG1B100F256GM32 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+/** Part family */\r
+#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */\r
+#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
+#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */\r
+#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */\r
+\r
+/* If part number is not defined as compiler option, define it */\r
+#if !defined(EFM32PG1B100F256GM32)\r
+#define EFM32PG1B100F256GM32 1 /**< PEARL Gecko Part */\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32PG1B100F256GM32" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */\r
+#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */\r
+#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */\r
+#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */\r
+#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */\r
+#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */\r
+#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */\r
+#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */\r
+#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */\r
+#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */\r
+#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */\r
+#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */\r
+#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */\r
+#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */\r
+#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */\r
+#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */\r
+#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */\r
+#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */\r
+#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */\r
+#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */\r
+#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+\r
+/** Bit banding area */\r
+#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
+#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
+\r
+/** Flash and SRAM limits for EFM32PG1B100F256GM32 */\r
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */\r
+#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */\r
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
+#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */\r
+#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */\r
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 72\r
+#define AFCHANLOC_MAX 32\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 61\r
+\r
+/* Part number capabilities */\r
+\r
+#define TIMER_PRESENT /**< TIMER is available in this part */\r
+#define TIMER_COUNT 2 /**< 2 TIMERs available */\r
+#define USART_PRESENT /**< USART is available in this part */\r
+#define USART_COUNT 2 /**< 2 USARTs available */\r
+#define LEUART_PRESENT /**< LEUART is available in this part */\r
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */\r
+#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
+#define PCNT_PRESENT /**< PCNT is available in this part */\r
+#define PCNT_COUNT 1 /**< 1 PCNTs available */\r
+#define I2C_PRESENT /**< I2C is available in this part */\r
+#define I2C_COUNT 1 /**< 1 I2Cs available */\r
+#define ADC_PRESENT /**< ADC is available in this part */\r
+#define ADC_COUNT 1 /**< 1 ADCs available */\r
+#define ACMP_PRESENT /**< ACMP is available in this part */\r
+#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
+#define IDAC_PRESENT /**< IDAC is available in this part */\r
+#define IDAC_COUNT 1 /**< 1 IDACs available */\r
+#define WDOG_PRESENT /**< WDOG is available in this part */\r
+#define WDOG_COUNT 1 /**< 1 WDOGs available */\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define CRYPTO_PRESENT\r
+#define CRYPTO_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define LDMA_PRESENT\r
+#define LDMA_COUNT 1\r
+#define FPUEH_PRESENT\r
+#define FPUEH_COUNT 1\r
+#define GPCRC_PRESENT\r
+#define GPCRC_COUNT 1\r
+#define CRYOTIMER_PRESENT\r
+#define CRYOTIMER_COUNT 1\r
+#define RTCC_PRESENT\r
+#define RTCC_COUNT 1\r
+#define BOOTLOADER_PRESENT\r
+#define BOOTLOADER_COUNT 1\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_efm32pg1b.h" /* System Header File */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Part */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_TypeDefs EFM32PG1B100F256GM32 Peripheral TypeDefs\r
+ * @{\r
+ * @brief Device Specific Peripheral Register Structures\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_msc.h"\r
+#include "efm32pg1b_emu.h"\r
+#include "efm32pg1b_rmu.h"\r
+#include "efm32pg1b_cmu.h"\r
+#include "efm32pg1b_crypto.h"\r
+#include "efm32pg1b_gpio_p.h"\r
+#include "efm32pg1b_gpio.h"\r
+#include "efm32pg1b_prs_ch.h"\r
+#include "efm32pg1b_prs.h"\r
+#include "efm32pg1b_ldma_ch.h"\r
+#include "efm32pg1b_ldma.h"\r
+#include "efm32pg1b_fpueh.h"\r
+#include "efm32pg1b_gpcrc.h"\r
+#include "efm32pg1b_timer_cc.h"\r
+#include "efm32pg1b_timer.h"\r
+#include "efm32pg1b_usart.h"\r
+#include "efm32pg1b_leuart.h"\r
+#include "efm32pg1b_letimer.h"\r
+#include "efm32pg1b_cryotimer.h"\r
+#include "efm32pg1b_pcnt.h"\r
+#include "efm32pg1b_i2c.h"\r
+#include "efm32pg1b_adc.h"\r
+#include "efm32pg1b_acmp.h"\r
+#include "efm32pg1b_idac.h"\r
+#include "efm32pg1b_rtcc_cc.h"\r
+#include "efm32pg1b_rtcc_ret.h"\r
+#include "efm32pg1b_rtcc.h"\r
+#include "efm32pg1b_wdog_pch.h"\r
+#include "efm32pg1b_wdog.h"\r
+#include "efm32pg1b_dma_descriptor.h"\r
+#include "efm32pg1b_devinfo.h"\r
+#include "efm32pg1b_romtable.h"\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_TypeDefs */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_Base EFM32PG1B100F256GM32 Peripheral Memory Map\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */\r
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */\r
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */\r
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */\r
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */\r
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */\r
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */\r
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */\r
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */\r
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */\r
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */\r
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */\r
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */\r
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */\r
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */\r
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */\r
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */\r
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */\r
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */\r
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */\r
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */\r
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_Base */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_Declaration EFM32PG1B100F256GM32 Peripheral Declarations\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */\r
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */\r
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */\r
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */\r
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_Declaration */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_Peripheral_Offsets EFM32PG1B100F256GM32 Peripheral Offsets\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */\r
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */\r
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */\r
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */\r
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */\r
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */\r
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */\r
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */\r
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */\r
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Peripheral_Offsets */\r
+\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_BitFields EFM32PG1B100F256GM32 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_prs_signals.h"\r
+#include "efm32pg1b_dmareq.h"\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_UNLOCK EFM32PG1B100F256GM32 Unlock Codes\r
+ * @{\r
+ *****************************************************************************/\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_UNLOCK */\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_BitFields */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B100F256GM32_Alternate_Function EFM32PG1B100F256GM32 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_af_ports.h"\r
+#include "efm32pg1b_af_pins.h"\r
+\r
+/** @} End of group EFM32PG1B100F256GM32_Alternate_Function */\r
+\r
+/**************************************************************************//**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ *****************************************************************************/\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/** @} End of group EFM32PG1B100F256GM32 */\r
+\r
+/** @} End of group Parts */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SILICON_LABS_EFM32PG1B100F256GM32_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b200f128gm32.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
+ * for EFM32PG1B200F128GM32\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SILICON_LABS_EFM32PG1B200F128GM32_H\r
+#define SILICON_LABS_EFM32PG1B200F128GM32_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************//**\r
+ * @addtogroup Parts\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32 EFM32PG1B200F128GM32\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers *******************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+\r
+/****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/\r
+\r
+ EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */\r
+ WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */\r
+ LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */\r
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */\r
+ ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */\r
+ ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */\r
+ IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */\r
+ I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */\r
+ USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */\r
+ LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */\r
+ PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */\r
+ CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */\r
+ MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */\r
+ CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */\r
+ LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
+ RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */\r
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */\r
+ FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_Core EFM32PG1B200F128GM32 Core\r
+ * @{\r
+ * @brief Processor and Core Peripheral Section\r
+ *****************************************************************************/\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __FPU_PRESENT 1 /**< Presence of FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Core */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32PG1B200F128GM32_Part EFM32PG1B200F128GM32 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+/** Part family */\r
+#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */\r
+#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
+#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */\r
+#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */\r
+\r
+/* If part number is not defined as compiler option, define it */\r
+#if !defined(EFM32PG1B200F128GM32)\r
+#define EFM32PG1B200F128GM32 1 /**< PEARL Gecko Part */\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32PG1B200F128GM32" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */\r
+#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */\r
+#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */\r
+#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */\r
+#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */\r
+#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */\r
+#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */\r
+#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */\r
+#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */\r
+#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */\r
+#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */\r
+#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */\r
+#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */\r
+#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */\r
+#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */\r
+#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */\r
+#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */\r
+#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */\r
+#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */\r
+#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */\r
+#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+\r
+/** Bit banding area */\r
+#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
+#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
+\r
+/** Flash and SRAM limits for EFM32PG1B200F128GM32 */\r
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
+#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */\r
+#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */\r
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
+#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */\r
+#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */\r
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 72\r
+#define AFCHANLOC_MAX 32\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 61\r
+\r
+/* Part number capabilities */\r
+\r
+#define TIMER_PRESENT /**< TIMER is available in this part */\r
+#define TIMER_COUNT 2 /**< 2 TIMERs available */\r
+#define USART_PRESENT /**< USART is available in this part */\r
+#define USART_COUNT 2 /**< 2 USARTs available */\r
+#define LEUART_PRESENT /**< LEUART is available in this part */\r
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */\r
+#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
+#define PCNT_PRESENT /**< PCNT is available in this part */\r
+#define PCNT_COUNT 1 /**< 1 PCNTs available */\r
+#define I2C_PRESENT /**< I2C is available in this part */\r
+#define I2C_COUNT 1 /**< 1 I2Cs available */\r
+#define ADC_PRESENT /**< ADC is available in this part */\r
+#define ADC_COUNT 1 /**< 1 ADCs available */\r
+#define ACMP_PRESENT /**< ACMP is available in this part */\r
+#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
+#define IDAC_PRESENT /**< IDAC is available in this part */\r
+#define IDAC_COUNT 1 /**< 1 IDACs available */\r
+#define WDOG_PRESENT /**< WDOG is available in this part */\r
+#define WDOG_COUNT 1 /**< 1 WDOGs available */\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define CRYPTO_PRESENT\r
+#define CRYPTO_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define LDMA_PRESENT\r
+#define LDMA_COUNT 1\r
+#define FPUEH_PRESENT\r
+#define FPUEH_COUNT 1\r
+#define GPCRC_PRESENT\r
+#define GPCRC_COUNT 1\r
+#define CRYOTIMER_PRESENT\r
+#define CRYOTIMER_COUNT 1\r
+#define RTCC_PRESENT\r
+#define RTCC_COUNT 1\r
+#define BOOTLOADER_PRESENT\r
+#define BOOTLOADER_COUNT 1\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_efm32pg1b.h" /* System Header File */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Part */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_TypeDefs EFM32PG1B200F128GM32 Peripheral TypeDefs\r
+ * @{\r
+ * @brief Device Specific Peripheral Register Structures\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_msc.h"\r
+#include "efm32pg1b_emu.h"\r
+#include "efm32pg1b_rmu.h"\r
+#include "efm32pg1b_cmu.h"\r
+#include "efm32pg1b_crypto.h"\r
+#include "efm32pg1b_gpio_p.h"\r
+#include "efm32pg1b_gpio.h"\r
+#include "efm32pg1b_prs_ch.h"\r
+#include "efm32pg1b_prs.h"\r
+#include "efm32pg1b_ldma_ch.h"\r
+#include "efm32pg1b_ldma.h"\r
+#include "efm32pg1b_fpueh.h"\r
+#include "efm32pg1b_gpcrc.h"\r
+#include "efm32pg1b_timer_cc.h"\r
+#include "efm32pg1b_timer.h"\r
+#include "efm32pg1b_usart.h"\r
+#include "efm32pg1b_leuart.h"\r
+#include "efm32pg1b_letimer.h"\r
+#include "efm32pg1b_cryotimer.h"\r
+#include "efm32pg1b_pcnt.h"\r
+#include "efm32pg1b_i2c.h"\r
+#include "efm32pg1b_adc.h"\r
+#include "efm32pg1b_acmp.h"\r
+#include "efm32pg1b_idac.h"\r
+#include "efm32pg1b_rtcc_cc.h"\r
+#include "efm32pg1b_rtcc_ret.h"\r
+#include "efm32pg1b_rtcc.h"\r
+#include "efm32pg1b_wdog_pch.h"\r
+#include "efm32pg1b_wdog.h"\r
+#include "efm32pg1b_dma_descriptor.h"\r
+#include "efm32pg1b_devinfo.h"\r
+#include "efm32pg1b_romtable.h"\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_TypeDefs */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_Base EFM32PG1B200F128GM32 Peripheral Memory Map\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */\r
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */\r
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */\r
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */\r
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */\r
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */\r
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */\r
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */\r
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */\r
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */\r
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */\r
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */\r
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */\r
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */\r
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */\r
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */\r
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */\r
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */\r
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */\r
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */\r
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */\r
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_Base */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_Declaration EFM32PG1B200F128GM32 Peripheral Declarations\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */\r
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */\r
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */\r
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */\r
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_Declaration */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_Peripheral_Offsets EFM32PG1B200F128GM32 Peripheral Offsets\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */\r
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */\r
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */\r
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */\r
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */\r
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */\r
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */\r
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */\r
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */\r
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Peripheral_Offsets */\r
+\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_BitFields EFM32PG1B200F128GM32 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_prs_signals.h"\r
+#include "efm32pg1b_dmareq.h"\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_UNLOCK EFM32PG1B200F128GM32 Unlock Codes\r
+ * @{\r
+ *****************************************************************************/\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_UNLOCK */\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_BitFields */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM32_Alternate_Function EFM32PG1B200F128GM32 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_af_ports.h"\r
+#include "efm32pg1b_af_pins.h"\r
+\r
+/** @} End of group EFM32PG1B200F128GM32_Alternate_Function */\r
+\r
+/**************************************************************************//**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ *****************************************************************************/\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/** @} End of group EFM32PG1B200F128GM32 */\r
+\r
+/** @} End of group Parts */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SILICON_LABS_EFM32PG1B200F128GM32_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b200f128gm48.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
+ * for EFM32PG1B200F128GM48\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SILICON_LABS_EFM32PG1B200F128GM48_H\r
+#define SILICON_LABS_EFM32PG1B200F128GM48_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************//**\r
+ * @addtogroup Parts\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48 EFM32PG1B200F128GM48\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers *******************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+\r
+/****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/\r
+\r
+ EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */\r
+ WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */\r
+ LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */\r
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */\r
+ ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */\r
+ ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */\r
+ IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */\r
+ I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */\r
+ USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */\r
+ LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */\r
+ PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */\r
+ CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */\r
+ MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */\r
+ CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */\r
+ LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
+ RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */\r
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */\r
+ FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_Core EFM32PG1B200F128GM48 Core\r
+ * @{\r
+ * @brief Processor and Core Peripheral Section\r
+ *****************************************************************************/\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __FPU_PRESENT 1 /**< Presence of FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Core */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32PG1B200F128GM48_Part EFM32PG1B200F128GM48 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+/** Part family */\r
+#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */\r
+#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
+#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */\r
+#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */\r
+\r
+/* If part number is not defined as compiler option, define it */\r
+#if !defined(EFM32PG1B200F128GM48)\r
+#define EFM32PG1B200F128GM48 1 /**< PEARL Gecko Part */\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32PG1B200F128GM48" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */\r
+#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */\r
+#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */\r
+#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */\r
+#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */\r
+#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */\r
+#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */\r
+#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */\r
+#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */\r
+#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */\r
+#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */\r
+#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */\r
+#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */\r
+#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */\r
+#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */\r
+#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */\r
+#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */\r
+#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */\r
+#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */\r
+#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */\r
+#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+\r
+/** Bit banding area */\r
+#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
+#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
+\r
+/** Flash and SRAM limits for EFM32PG1B200F128GM48 */\r
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
+#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */\r
+#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */\r
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
+#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */\r
+#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */\r
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 72\r
+#define AFCHANLOC_MAX 32\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 61\r
+\r
+/* Part number capabilities */\r
+\r
+#define TIMER_PRESENT /**< TIMER is available in this part */\r
+#define TIMER_COUNT 2 /**< 2 TIMERs available */\r
+#define USART_PRESENT /**< USART is available in this part */\r
+#define USART_COUNT 2 /**< 2 USARTs available */\r
+#define LEUART_PRESENT /**< LEUART is available in this part */\r
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */\r
+#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
+#define PCNT_PRESENT /**< PCNT is available in this part */\r
+#define PCNT_COUNT 1 /**< 1 PCNTs available */\r
+#define I2C_PRESENT /**< I2C is available in this part */\r
+#define I2C_COUNT 1 /**< 1 I2Cs available */\r
+#define ADC_PRESENT /**< ADC is available in this part */\r
+#define ADC_COUNT 1 /**< 1 ADCs available */\r
+#define ACMP_PRESENT /**< ACMP is available in this part */\r
+#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
+#define IDAC_PRESENT /**< IDAC is available in this part */\r
+#define IDAC_COUNT 1 /**< 1 IDACs available */\r
+#define WDOG_PRESENT /**< WDOG is available in this part */\r
+#define WDOG_COUNT 1 /**< 1 WDOGs available */\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define CRYPTO_PRESENT\r
+#define CRYPTO_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define LDMA_PRESENT\r
+#define LDMA_COUNT 1\r
+#define FPUEH_PRESENT\r
+#define FPUEH_COUNT 1\r
+#define GPCRC_PRESENT\r
+#define GPCRC_COUNT 1\r
+#define CRYOTIMER_PRESENT\r
+#define CRYOTIMER_COUNT 1\r
+#define RTCC_PRESENT\r
+#define RTCC_COUNT 1\r
+#define BOOTLOADER_PRESENT\r
+#define BOOTLOADER_COUNT 1\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_efm32pg1b.h" /* System Header File */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Part */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_TypeDefs EFM32PG1B200F128GM48 Peripheral TypeDefs\r
+ * @{\r
+ * @brief Device Specific Peripheral Register Structures\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_msc.h"\r
+#include "efm32pg1b_emu.h"\r
+#include "efm32pg1b_rmu.h"\r
+#include "efm32pg1b_cmu.h"\r
+#include "efm32pg1b_crypto.h"\r
+#include "efm32pg1b_gpio_p.h"\r
+#include "efm32pg1b_gpio.h"\r
+#include "efm32pg1b_prs_ch.h"\r
+#include "efm32pg1b_prs.h"\r
+#include "efm32pg1b_ldma_ch.h"\r
+#include "efm32pg1b_ldma.h"\r
+#include "efm32pg1b_fpueh.h"\r
+#include "efm32pg1b_gpcrc.h"\r
+#include "efm32pg1b_timer_cc.h"\r
+#include "efm32pg1b_timer.h"\r
+#include "efm32pg1b_usart.h"\r
+#include "efm32pg1b_leuart.h"\r
+#include "efm32pg1b_letimer.h"\r
+#include "efm32pg1b_cryotimer.h"\r
+#include "efm32pg1b_pcnt.h"\r
+#include "efm32pg1b_i2c.h"\r
+#include "efm32pg1b_adc.h"\r
+#include "efm32pg1b_acmp.h"\r
+#include "efm32pg1b_idac.h"\r
+#include "efm32pg1b_rtcc_cc.h"\r
+#include "efm32pg1b_rtcc_ret.h"\r
+#include "efm32pg1b_rtcc.h"\r
+#include "efm32pg1b_wdog_pch.h"\r
+#include "efm32pg1b_wdog.h"\r
+#include "efm32pg1b_dma_descriptor.h"\r
+#include "efm32pg1b_devinfo.h"\r
+#include "efm32pg1b_romtable.h"\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_TypeDefs */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_Base EFM32PG1B200F128GM48 Peripheral Memory Map\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */\r
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */\r
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */\r
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */\r
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */\r
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */\r
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */\r
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */\r
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */\r
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */\r
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */\r
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */\r
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */\r
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */\r
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */\r
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */\r
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */\r
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */\r
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */\r
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */\r
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */\r
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_Base */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_Declaration EFM32PG1B200F128GM48 Peripheral Declarations\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */\r
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */\r
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */\r
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */\r
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_Declaration */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_Peripheral_Offsets EFM32PG1B200F128GM48 Peripheral Offsets\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */\r
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */\r
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */\r
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */\r
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */\r
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */\r
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */\r
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */\r
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */\r
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Peripheral_Offsets */\r
+\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_BitFields EFM32PG1B200F128GM48 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_prs_signals.h"\r
+#include "efm32pg1b_dmareq.h"\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_UNLOCK EFM32PG1B200F128GM48 Unlock Codes\r
+ * @{\r
+ *****************************************************************************/\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_UNLOCK */\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_BitFields */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F128GM48_Alternate_Function EFM32PG1B200F128GM48 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_af_ports.h"\r
+#include "efm32pg1b_af_pins.h"\r
+\r
+/** @} End of group EFM32PG1B200F128GM48_Alternate_Function */\r
+\r
+/**************************************************************************//**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ *****************************************************************************/\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/** @} End of group EFM32PG1B200F128GM48 */\r
+\r
+/** @} End of group Parts */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SILICON_LABS_EFM32PG1B200F128GM48_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b200f256gm32.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
+ * for EFM32PG1B200F256GM32\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SILICON_LABS_EFM32PG1B200F256GM32_H\r
+#define SILICON_LABS_EFM32PG1B200F256GM32_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************//**\r
+ * @addtogroup Parts\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32 EFM32PG1B200F256GM32\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers *******************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+\r
+/****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/\r
+\r
+ EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */\r
+ WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */\r
+ LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */\r
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */\r
+ ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */\r
+ ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */\r
+ IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */\r
+ I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */\r
+ USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */\r
+ LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */\r
+ PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */\r
+ CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */\r
+ MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */\r
+ CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */\r
+ LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
+ RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */\r
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */\r
+ FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_Core EFM32PG1B200F256GM32 Core\r
+ * @{\r
+ * @brief Processor and Core Peripheral Section\r
+ *****************************************************************************/\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __FPU_PRESENT 1 /**< Presence of FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Core */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32PG1B200F256GM32_Part EFM32PG1B200F256GM32 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+/** Part family */\r
+#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */\r
+#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
+#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */\r
+#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */\r
+\r
+/* If part number is not defined as compiler option, define it */\r
+#if !defined(EFM32PG1B200F256GM32)\r
+#define EFM32PG1B200F256GM32 1 /**< PEARL Gecko Part */\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32PG1B200F256GM32" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */\r
+#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */\r
+#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */\r
+#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */\r
+#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */\r
+#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */\r
+#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */\r
+#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */\r
+#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */\r
+#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */\r
+#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */\r
+#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */\r
+#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */\r
+#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */\r
+#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */\r
+#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */\r
+#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */\r
+#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */\r
+#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */\r
+#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */\r
+#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+\r
+/** Bit banding area */\r
+#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
+#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
+\r
+/** Flash and SRAM limits for EFM32PG1B200F256GM32 */\r
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */\r
+#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */\r
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
+#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */\r
+#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */\r
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 72\r
+#define AFCHANLOC_MAX 32\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 61\r
+\r
+/* Part number capabilities */\r
+\r
+#define TIMER_PRESENT /**< TIMER is available in this part */\r
+#define TIMER_COUNT 2 /**< 2 TIMERs available */\r
+#define USART_PRESENT /**< USART is available in this part */\r
+#define USART_COUNT 2 /**< 2 USARTs available */\r
+#define LEUART_PRESENT /**< LEUART is available in this part */\r
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */\r
+#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
+#define PCNT_PRESENT /**< PCNT is available in this part */\r
+#define PCNT_COUNT 1 /**< 1 PCNTs available */\r
+#define I2C_PRESENT /**< I2C is available in this part */\r
+#define I2C_COUNT 1 /**< 1 I2Cs available */\r
+#define ADC_PRESENT /**< ADC is available in this part */\r
+#define ADC_COUNT 1 /**< 1 ADCs available */\r
+#define ACMP_PRESENT /**< ACMP is available in this part */\r
+#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
+#define IDAC_PRESENT /**< IDAC is available in this part */\r
+#define IDAC_COUNT 1 /**< 1 IDACs available */\r
+#define WDOG_PRESENT /**< WDOG is available in this part */\r
+#define WDOG_COUNT 1 /**< 1 WDOGs available */\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define CRYPTO_PRESENT\r
+#define CRYPTO_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define LDMA_PRESENT\r
+#define LDMA_COUNT 1\r
+#define FPUEH_PRESENT\r
+#define FPUEH_COUNT 1\r
+#define GPCRC_PRESENT\r
+#define GPCRC_COUNT 1\r
+#define CRYOTIMER_PRESENT\r
+#define CRYOTIMER_COUNT 1\r
+#define RTCC_PRESENT\r
+#define RTCC_COUNT 1\r
+#define BOOTLOADER_PRESENT\r
+#define BOOTLOADER_COUNT 1\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_efm32pg1b.h" /* System Header File */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Part */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_TypeDefs EFM32PG1B200F256GM32 Peripheral TypeDefs\r
+ * @{\r
+ * @brief Device Specific Peripheral Register Structures\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_msc.h"\r
+#include "efm32pg1b_emu.h"\r
+#include "efm32pg1b_rmu.h"\r
+#include "efm32pg1b_cmu.h"\r
+#include "efm32pg1b_crypto.h"\r
+#include "efm32pg1b_gpio_p.h"\r
+#include "efm32pg1b_gpio.h"\r
+#include "efm32pg1b_prs_ch.h"\r
+#include "efm32pg1b_prs.h"\r
+#include "efm32pg1b_ldma_ch.h"\r
+#include "efm32pg1b_ldma.h"\r
+#include "efm32pg1b_fpueh.h"\r
+#include "efm32pg1b_gpcrc.h"\r
+#include "efm32pg1b_timer_cc.h"\r
+#include "efm32pg1b_timer.h"\r
+#include "efm32pg1b_usart.h"\r
+#include "efm32pg1b_leuart.h"\r
+#include "efm32pg1b_letimer.h"\r
+#include "efm32pg1b_cryotimer.h"\r
+#include "efm32pg1b_pcnt.h"\r
+#include "efm32pg1b_i2c.h"\r
+#include "efm32pg1b_adc.h"\r
+#include "efm32pg1b_acmp.h"\r
+#include "efm32pg1b_idac.h"\r
+#include "efm32pg1b_rtcc_cc.h"\r
+#include "efm32pg1b_rtcc_ret.h"\r
+#include "efm32pg1b_rtcc.h"\r
+#include "efm32pg1b_wdog_pch.h"\r
+#include "efm32pg1b_wdog.h"\r
+#include "efm32pg1b_dma_descriptor.h"\r
+#include "efm32pg1b_devinfo.h"\r
+#include "efm32pg1b_romtable.h"\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_TypeDefs */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_Base EFM32PG1B200F256GM32 Peripheral Memory Map\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */\r
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */\r
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */\r
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */\r
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */\r
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */\r
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */\r
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */\r
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */\r
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */\r
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */\r
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */\r
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */\r
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */\r
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */\r
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */\r
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */\r
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */\r
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */\r
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */\r
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */\r
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_Base */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_Declaration EFM32PG1B200F256GM32 Peripheral Declarations\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */\r
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */\r
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */\r
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */\r
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_Declaration */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_Peripheral_Offsets EFM32PG1B200F256GM32 Peripheral Offsets\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */\r
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */\r
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */\r
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */\r
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */\r
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */\r
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */\r
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */\r
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */\r
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Peripheral_Offsets */\r
+\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_BitFields EFM32PG1B200F256GM32 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_prs_signals.h"\r
+#include "efm32pg1b_dmareq.h"\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_UNLOCK EFM32PG1B200F256GM32 Unlock Codes\r
+ * @{\r
+ *****************************************************************************/\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_UNLOCK */\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_BitFields */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM32_Alternate_Function EFM32PG1B200F256GM32 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_af_ports.h"\r
+#include "efm32pg1b_af_pins.h"\r
+\r
+/** @} End of group EFM32PG1B200F256GM32_Alternate_Function */\r
+\r
+/**************************************************************************//**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ *****************************************************************************/\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/** @} End of group EFM32PG1B200F256GM32 */\r
+\r
+/** @} End of group Parts */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SILICON_LABS_EFM32PG1B200F256GM32_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b200f256gm48.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
+ * for EFM32PG1B200F256GM48\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SILICON_LABS_EFM32PG1B200F256GM48_H\r
+#define SILICON_LABS_EFM32PG1B200F256GM48_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**************************************************************************//**\r
+ * @addtogroup Parts\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48 EFM32PG1B200F256GM48\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers *******************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+\r
+/****** EFM32PG1B Peripheral Interrupt Numbers *********************************************/\r
+\r
+ EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */\r
+ WDOG0_IRQn = 2, /*!< 16+2 EFM32 WDOG0 Interrupt */\r
+ LDMA_IRQn = 8, /*!< 16+8 EFM32 LDMA Interrupt */\r
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFM32 GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 10, /*!< 16+10 EFM32 TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 11, /*!< 16+11 EFM32 USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 12, /*!< 16+12 EFM32 USART0_TX Interrupt */\r
+ ACMP0_IRQn = 13, /*!< 16+13 EFM32 ACMP0 Interrupt */\r
+ ADC0_IRQn = 14, /*!< 16+14 EFM32 ADC0 Interrupt */\r
+ IDAC0_IRQn = 15, /*!< 16+15 EFM32 IDAC0 Interrupt */\r
+ I2C0_IRQn = 16, /*!< 16+16 EFM32 I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFM32 GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 18, /*!< 16+18 EFM32 TIMER1 Interrupt */\r
+ USART1_RX_IRQn = 19, /*!< 16+19 EFM32 USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 20, /*!< 16+20 EFM32 USART1_TX Interrupt */\r
+ LEUART0_IRQn = 21, /*!< 16+21 EFM32 LEUART0 Interrupt */\r
+ PCNT0_IRQn = 22, /*!< 16+22 EFM32 PCNT0 Interrupt */\r
+ CMU_IRQn = 23, /*!< 16+23 EFM32 CMU Interrupt */\r
+ MSC_IRQn = 24, /*!< 16+24 EFM32 MSC Interrupt */\r
+ CRYPTO_IRQn = 25, /*!< 16+25 EFM32 CRYPTO Interrupt */\r
+ LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
+ RTCC_IRQn = 29, /*!< 16+29 EFM32 RTCC Interrupt */\r
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFM32 CRYOTIMER Interrupt */\r
+ FPUEH_IRQn = 33, /*!< 16+33 EFM32 FPUEH Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_Core EFM32PG1B200F256GM48 Core\r
+ * @{\r
+ * @brief Processor and Core Peripheral Section\r
+ *****************************************************************************/\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __FPU_PRESENT 1 /**< Presence of FPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Core */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32PG1B200F256GM48_Part EFM32PG1B200F256GM48 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+/** Part family */\r
+#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */\r
+#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
+#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */\r
+#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */\r
+\r
+/* If part number is not defined as compiler option, define it */\r
+#if !defined(EFM32PG1B200F256GM48)\r
+#define EFM32PG1B200F256GM48 1 /**< PEARL Gecko Part */\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32PG1B200F256GM48" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */\r
+#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */\r
+#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */\r
+#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */\r
+#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */\r
+#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */\r
+#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */\r
+#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */\r
+#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */\r
+#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */\r
+#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */\r
+#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */\r
+#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */\r
+#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */\r
+#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */\r
+#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */\r
+#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */\r
+#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */\r
+#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */\r
+#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */\r
+#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+\r
+/** Bit banding area */\r
+#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
+#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
+\r
+/** Flash and SRAM limits for EFM32PG1B200F256GM48 */\r
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */\r
+#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */\r
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
+#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */\r
+#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */\r
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 72\r
+#define AFCHANLOC_MAX 32\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 61\r
+\r
+/* Part number capabilities */\r
+\r
+#define TIMER_PRESENT /**< TIMER is available in this part */\r
+#define TIMER_COUNT 2 /**< 2 TIMERs available */\r
+#define USART_PRESENT /**< USART is available in this part */\r
+#define USART_COUNT 2 /**< 2 USARTs available */\r
+#define LEUART_PRESENT /**< LEUART is available in this part */\r
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */\r
+#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
+#define PCNT_PRESENT /**< PCNT is available in this part */\r
+#define PCNT_COUNT 1 /**< 1 PCNTs available */\r
+#define I2C_PRESENT /**< I2C is available in this part */\r
+#define I2C_COUNT 1 /**< 1 I2Cs available */\r
+#define ADC_PRESENT /**< ADC is available in this part */\r
+#define ADC_COUNT 1 /**< 1 ADCs available */\r
+#define ACMP_PRESENT /**< ACMP is available in this part */\r
+#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
+#define IDAC_PRESENT /**< IDAC is available in this part */\r
+#define IDAC_COUNT 1 /**< 1 IDACs available */\r
+#define WDOG_PRESENT /**< WDOG is available in this part */\r
+#define WDOG_COUNT 1 /**< 1 WDOGs available */\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define CRYPTO_PRESENT\r
+#define CRYPTO_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define LDMA_PRESENT\r
+#define LDMA_COUNT 1\r
+#define FPUEH_PRESENT\r
+#define FPUEH_COUNT 1\r
+#define GPCRC_PRESENT\r
+#define GPCRC_COUNT 1\r
+#define CRYOTIMER_PRESENT\r
+#define CRYOTIMER_COUNT 1\r
+#define RTCC_PRESENT\r
+#define RTCC_COUNT 1\r
+#define BOOTLOADER_PRESENT\r
+#define BOOTLOADER_COUNT 1\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_efm32pg1b.h" /* System Header File */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Part */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_TypeDefs EFM32PG1B200F256GM48 Peripheral TypeDefs\r
+ * @{\r
+ * @brief Device Specific Peripheral Register Structures\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_msc.h"\r
+#include "efm32pg1b_emu.h"\r
+#include "efm32pg1b_rmu.h"\r
+#include "efm32pg1b_cmu.h"\r
+#include "efm32pg1b_crypto.h"\r
+#include "efm32pg1b_gpio_p.h"\r
+#include "efm32pg1b_gpio.h"\r
+#include "efm32pg1b_prs_ch.h"\r
+#include "efm32pg1b_prs.h"\r
+#include "efm32pg1b_ldma_ch.h"\r
+#include "efm32pg1b_ldma.h"\r
+#include "efm32pg1b_fpueh.h"\r
+#include "efm32pg1b_gpcrc.h"\r
+#include "efm32pg1b_timer_cc.h"\r
+#include "efm32pg1b_timer.h"\r
+#include "efm32pg1b_usart.h"\r
+#include "efm32pg1b_leuart.h"\r
+#include "efm32pg1b_letimer.h"\r
+#include "efm32pg1b_cryotimer.h"\r
+#include "efm32pg1b_pcnt.h"\r
+#include "efm32pg1b_i2c.h"\r
+#include "efm32pg1b_adc.h"\r
+#include "efm32pg1b_acmp.h"\r
+#include "efm32pg1b_idac.h"\r
+#include "efm32pg1b_rtcc_cc.h"\r
+#include "efm32pg1b_rtcc_ret.h"\r
+#include "efm32pg1b_rtcc.h"\r
+#include "efm32pg1b_wdog_pch.h"\r
+#include "efm32pg1b_wdog.h"\r
+#include "efm32pg1b_dma_descriptor.h"\r
+#include "efm32pg1b_devinfo.h"\r
+#include "efm32pg1b_romtable.h"\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_TypeDefs */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_Base EFM32PG1B200F256GM48 Peripheral Memory Map\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */\r
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */\r
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */\r
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */\r
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */\r
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */\r
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */\r
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */\r
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */\r
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */\r
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */\r
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */\r
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */\r
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */\r
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */\r
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */\r
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */\r
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */\r
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */\r
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */\r
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */\r
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_Base */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_Declaration EFM32PG1B200F256GM48 Peripheral Declarations\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */\r
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */\r
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */\r
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */\r
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_Declaration */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_Peripheral_Offsets EFM32PG1B200F256GM48 Peripheral Offsets\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */\r
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */\r
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */\r
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */\r
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */\r
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */\r
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */\r
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */\r
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */\r
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Peripheral_Offsets */\r
+\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_BitFields EFM32PG1B200F256GM48 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_prs_signals.h"\r
+#include "efm32pg1b_dmareq.h"\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_UNLOCK EFM32PG1B200F256GM48 Unlock Codes\r
+ * @{\r
+ *****************************************************************************/\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_UNLOCK */\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_BitFields */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B200F256GM48_Alternate_Function EFM32PG1B200F256GM48 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#include "efm32pg1b_af_ports.h"\r
+#include "efm32pg1b_af_pins.h"\r
+\r
+/** @} End of group EFM32PG1B200F256GM48_Alternate_Function */\r
+\r
+/**************************************************************************//**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ *****************************************************************************/\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/** @} End of group EFM32PG1B200F256GM48 */\r
+\r
+/** @} End of group Parts */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SILICON_LABS_EFM32PG1B200F256GM48_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_acmp.h\r
+ * @brief EFM32PG1B_ACMP register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_ACMP\r
+ * @{\r
+ * @brief EFM32PG1B_ACMP Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t INPUTSEL; /**< Input Selection Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __I uint32_t APORTREQ; /**< APORT Request Status Register */\r
+ __I uint32_t APORTCONFLICT; /**< APORT Request Status Register */\r
+ __IO uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */\r
+ __IO uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */\r
+\r
+ uint32_t RESERVED1[4]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+} ACMP_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_ACMP_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for ACMP CTRL */\r
+#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */\r
+#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */\r
+#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */\r
+#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */\r
+#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */\r
+#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */\r
+#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */\r
+#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */\r
+#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */\r
+#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */\r
+#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */\r
+#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */\r
+#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */\r
+#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */\r
+#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */\r
+#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */\r
+#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */\r
+#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */\r
+#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */\r
+#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */\r
+#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */\r
+#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */\r
+#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */\r
+#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */\r
+#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */\r
+#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */\r
+#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */\r
+#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */\r
+#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */\r
+#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */\r
+#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */\r
+#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */\r
+#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */\r
+#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */\r
+#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */\r
+#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */\r
+#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */\r
+#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */\r
+#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */\r
+#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */\r
+#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */\r
+#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */\r
+#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */\r
+#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */\r
+#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */\r
+#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */\r
+#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */\r
+#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */\r
+#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */\r
+#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */\r
+#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */\r
+#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */\r
+#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */\r
+#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */\r
+#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */\r
+#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */\r
+#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */\r
+#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */\r
+#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+\r
+/* Bit fields for ACMP INPUTSEL */\r
+#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */\r
+#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */\r
+#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */\r
+#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */\r
+#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */\r
+#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */\r
+#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */\r
+#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */\r
+#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */\r
+#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */\r
+#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */\r
+#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */\r
+\r
+/* Bit fields for ACMP STATUS */\r
+#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */\r
+#define _ACMP_STATUS_MASK 0x00000007UL /**< Mask for ACMP_STATUS */\r
+#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */\r
+#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */\r
+#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */\r
+#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */\r
+#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */\r
+#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */\r
+#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */\r
+#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */\r
+#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */\r
+#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */\r
+#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */\r
+#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */\r
+#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */\r
+#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */\r
+#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */\r
+\r
+/* Bit fields for ACMP IF */\r
+#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */\r
+#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */\r
+#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */\r
+#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */\r
+#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */\r
+#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */\r
+#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */\r
+#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */\r
+#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */\r
+#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */\r
+#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */\r
+#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */\r
+#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */\r
+\r
+/* Bit fields for ACMP IFS */\r
+#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */\r
+#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */\r
+#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */\r
+#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */\r
+#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */\r
+#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */\r
+#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */\r
+#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */\r
+#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */\r
+#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */\r
+#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */\r
+#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */\r
+#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */\r
+\r
+/* Bit fields for ACMP IFC */\r
+#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */\r
+#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */\r
+#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */\r
+#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */\r
+#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */\r
+#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */\r
+#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */\r
+#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */\r
+#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */\r
+#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */\r
+#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */\r
+#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */\r
+#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */\r
+\r
+/* Bit fields for ACMP IEN */\r
+#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */\r
+#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */\r
+#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */\r
+#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */\r
+#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */\r
+#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */\r
+#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */\r
+#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */\r
+#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */\r
+#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */\r
+#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */\r
+#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */\r
+#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */\r
+\r
+/* Bit fields for ACMP APORTREQ */\r
+#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */\r
+#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */\r
+#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */\r
+#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */\r
+#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */\r
+#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */\r
+#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */\r
+#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */\r
+#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */\r
+#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */\r
+#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */\r
+#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */\r
+#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */\r
+#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */\r
+#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */\r
+#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */\r
+#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */\r
+#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */\r
+#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */\r
+#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */\r
+#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */\r
+#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */\r
+#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */\r
+#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */\r
+#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */\r
+#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */\r
+#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */\r
+#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */\r
+#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */\r
+#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */\r
+#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */\r
+#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */\r
+#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */\r
+\r
+/* Bit fields for ACMP APORTCONFLICT */\r
+#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */\r
+#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */\r
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */\r
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */\r
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */\r
+\r
+/* Bit fields for ACMP HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */\r
+#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */\r
+#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */\r
+#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */\r
+#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */\r
+#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */\r
+#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */\r
+#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */\r
+#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */\r
+\r
+/* Bit fields for ACMP HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */\r
+#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */\r
+#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */\r
+#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */\r
+#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */\r
+#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */\r
+#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */\r
+#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */\r
+#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */\r
+\r
+/* Bit fields for ACMP ROUTEPEN */\r
+#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */\r
+#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */\r
+#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */\r
+#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */\r
+#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */\r
+#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */\r
+#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */\r
+\r
+/* Bit fields for ACMP ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */\r
+#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */\r
+#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */\r
+#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */\r
+\r
+/** @} End of group EFM32PG1B_ACMP */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_adc.h\r
+ * @brief EFM32PG1B_ADC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_ADC\r
+ * @{\r
+ * @brief EFM32PG1B_ADC Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t SINGLECTRL; /**< Single Channel Control Register */\r
+ __IO uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */\r
+ __IO uint32_t SCANCTRL; /**< Scan Control Register */\r
+ __IO uint32_t SCANCTRLX; /**< Scan Control Register continued */\r
+ __IO uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */\r
+ __IO uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */\r
+ __IO uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */\r
+ __IO uint32_t CMPTHR; /**< Compare Threshold Register */\r
+ __IO uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation */\r
+ __IO uint32_t CAL; /**< Calibration Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */\r
+ __I uint32_t SCANDATA; /**< Scan Conversion Result Data */\r
+ __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */\r
+ __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */\r
+ uint32_t RESERVED1[4]; /**< Reserved for future use **/\r
+ __I uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */\r
+ __I uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */\r
+\r
+ uint32_t RESERVED2[3]; /**< Reserved for future use **/\r
+ __I uint32_t APORTREQ; /**< APORT Request Status Register */\r
+ __I uint32_t APORTCONFLICT; /**< APORT BUS Request Status Register */\r
+ __I uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */\r
+ __I uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */\r
+ __IO uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */\r
+ __IO uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */\r
+ __IO uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */\r
+} ADC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_ADC_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for ADC CTRL */\r
+#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */\r
+#define _ADC_CTRL_MASK 0x2F7F7FDFUL /**< Mask for ADC_CTRL */\r
+#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */\r
+#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */\r
+#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */\r
+#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */\r
+#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */\r
+#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */\r
+#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */\r
+#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */\r
+#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */\r
+#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */\r
+#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */\r
+#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */\r
+#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */\r
+#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */\r
+#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */\r
+#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */\r
+#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */\r
+#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */\r
+#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */\r
+#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */\r
+#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */\r
+#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */\r
+#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */\r
+#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */\r
+#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */\r
+#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */\r
+#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */\r
+#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */\r
+#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */\r
+#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */\r
+#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */\r
+#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */\r
+#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */\r
+#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */\r
+#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */\r
+#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */\r
+#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */\r
+#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */\r
+#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */\r
+#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */\r
+#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */\r
+#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */\r
+#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */\r
+#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */\r
+#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */\r
+#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */\r
+#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */\r
+#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */\r
+#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */\r
+#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */\r
+#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */\r
+\r
+/* Bit fields for ADC CMD */\r
+#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */\r
+#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */\r
+#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */\r
+#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */\r
+#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */\r
+#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */\r
+#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */\r
+#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */\r
+#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */\r
+#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */\r
+#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */\r
+#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */\r
+#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */\r
+#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */\r
+#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */\r
+\r
+/* Bit fields for ADC STATUS */\r
+#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */\r
+#define _ADC_STATUS_MASK 0x00031F03UL /**< Mask for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */\r
+#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */\r
+#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */\r
+#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */\r
+#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */\r
+#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */\r
+#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */\r
+#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */\r
+#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */\r
+#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */\r
+#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */\r
+#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */\r
+#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */\r
+#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */\r
+#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */\r
+#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */\r
+#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */\r
+#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */\r
+#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */\r
+#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */\r
+#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */\r
+#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */\r
+#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */\r
+#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */\r
+#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */\r
+#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */\r
+#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */\r
+#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+\r
+/* Bit fields for ADC SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */\r
+#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */\r
+#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */\r
+#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */\r
+#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */\r
+#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */\r
+#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */\r
+#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */\r
+#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */\r
+#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */\r
+#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */\r
+#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */\r
+#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */\r
+#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 5) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */\r
+#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_SP0 0x000000F2UL /**< Mode SP0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_SP0 (_ADC_SINGLECTRL_POSSEL_SP0 << 8) /**< Shifted mode SP0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */\r
+#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */\r
+#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */\r
+#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */\r
+#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */\r
+#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */\r
+#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */\r
+#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */\r
+#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */\r
+#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+\r
+/* Bit fields for ADC SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_MASK 0x0F1F7FFFUL /**< Mask for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */\r
+#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */\r
+#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable 1/3 scaling on VREF */\r
+#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */\r
+#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */\r
+#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */\r
+#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */\r
+#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */\r
+#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */\r
+#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */\r
+#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */\r
+#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */\r
+#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */\r
+#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */\r
+#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */\r
+#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */\r
+#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */\r
+#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */\r
+#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */\r
+#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */\r
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 24 /**< Shift value for ADC_CONVSTARTDELAY */\r
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */\r
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */\r
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */\r
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */\r
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */\r
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */\r
+\r
+/* Bit fields for ADC SCANCTRL */\r
+#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */\r
+#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */\r
+#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */\r
+#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */\r
+#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */\r
+#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */\r
+#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */\r
+#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */\r
+#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */\r
+#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */\r
+#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */\r
+#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */\r
+#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */\r
+#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 5) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */\r
+#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */\r
+#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */\r
+#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */\r
+#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */\r
+#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */\r
+#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */\r
+#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */\r
+#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+\r
+/* Bit fields for ADC SCANCTRLX */\r
+#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_MASK 0x0F1F7FFFUL /**< Mask for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */\r
+#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */\r
+#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VENTROPY (_ADC_SCANCTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed 1/3 scaling on VREF */\r
+#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */\r
+#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */\r
+#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */\r
+#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */\r
+#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */\r
+#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */\r
+#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */\r
+#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */\r
+#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */\r
+#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */\r
+#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */\r
+#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */\r
+#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */\r
+#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */\r
+#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */\r
+#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */\r
+#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */\r
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 24 /**< Shift value for ADC_CONVSTARTDELAY */\r
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */\r
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */\r
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */\r
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */\r
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */\r
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */\r
+\r
+/* Bit fields for ADC SCANMASK */\r
+#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */\r
+#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */\r
+#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */\r
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */\r
+#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */\r
+\r
+/* Bit fields for ADC SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */\r
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */\r
+\r
+/* Bit fields for ADC SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */\r
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */\r
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */\r
+\r
+/* Bit fields for ADC CMPTHR */\r
+#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */\r
+#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */\r
+#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */\r
+#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */\r
+#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */\r
+#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */\r
+#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */\r
+#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */\r
+#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */\r
+#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */\r
+\r
+/* Bit fields for ADC BIASPROG */\r
+#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_MASK 0x0000100FUL /**< Mask for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */\r
+#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */\r
+#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Set Vfault_clr flag */\r
+#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */\r
+#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */\r
+#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */\r
+#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
+\r
+/* Bit fields for ADC CAL */\r
+#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */\r
+#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */\r
+#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */\r
+#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */\r
+#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */\r
+#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */\r
+#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */\r
+#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */\r
+#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */\r
+#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */\r
+#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */\r
+#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */\r
+#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */\r
+#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */\r
+#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */\r
+#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */\r
+#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */\r
+#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */\r
+#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */\r
+#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */\r
+#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */\r
+#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */\r
+\r
+/* Bit fields for ADC IF */\r
+#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */\r
+#define _ADC_IF_MASK 0x03030F03UL /**< Mask for ADC_IF */\r
+#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */\r
+#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */\r
+#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */\r
+#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */\r
+#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */\r
+#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */\r
+#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */\r
+#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */\r
+#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single Result Underflow Interrupt Flag */\r
+#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */\r
+#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */\r
+#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan Result Underflow Interrupt Flag */\r
+#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */\r
+#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */\r
+#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */\r
+#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */\r
+#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */\r
+#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */\r
+#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */\r
+#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */\r
+#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF OverVoltage Interrupt Flag */\r
+#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */\r
+#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */\r
+#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */\r
+#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */\r
+#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */\r
+#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */\r
+\r
+/* Bit fields for ADC IFS */\r
+#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */\r
+#define _ADC_IFS_MASK 0x03030F00UL /**< Mask for ADC_IFS */\r
+#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */\r
+#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */\r
+#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */\r
+#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */\r
+#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */\r
+#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */\r
+#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */\r
+#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */\r
+#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */\r
+#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */\r
+#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */\r
+#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */\r
+#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */\r
+#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */\r
+#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */\r
+#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */\r
+#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */\r
+#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */\r
+#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */\r
+#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */\r
+#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */\r
+\r
+/* Bit fields for ADC IFC */\r
+#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */\r
+#define _ADC_IFC_MASK 0x03030F00UL /**< Mask for ADC_IFC */\r
+#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */\r
+#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */\r
+#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */\r
+#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */\r
+#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */\r
+#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */\r
+#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */\r
+#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */\r
+#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */\r
+#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */\r
+#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */\r
+#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */\r
+#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */\r
+#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */\r
+#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */\r
+#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */\r
+#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */\r
+#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */\r
+#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */\r
+#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */\r
+#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */\r
+\r
+/* Bit fields for ADC IEN */\r
+#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */\r
+#define _ADC_IEN_MASK 0x03030F03UL /**< Mask for ADC_IEN */\r
+#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */\r
+#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */\r
+#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */\r
+#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */\r
+#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */\r
+#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */\r
+#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */\r
+#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */\r
+#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */\r
+#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */\r
+#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */\r
+#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */\r
+#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */\r
+#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */\r
+#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */\r
+#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */\r
+#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */\r
+#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */\r
+#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */\r
+#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */\r
+#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */\r
+#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */\r
+#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */\r
+#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */\r
+#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */\r
+#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */\r
+#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */\r
+\r
+/* Bit fields for ADC SINGLEDATA */\r
+#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */\r
+#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */\r
+#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */\r
+#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */\r
+\r
+/* Bit fields for ADC SCANDATA */\r
+#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */\r
+#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */\r
+#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */\r
+#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */\r
+#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */\r
+#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */\r
+\r
+/* Bit fields for ADC SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */\r
+#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */\r
+#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */\r
+#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */\r
+\r
+/* Bit fields for ADC SCANDATAP */\r
+#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */\r
+#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */\r
+#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */\r
+#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */\r
+#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */\r
+#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */\r
+\r
+/* Bit fields for ADC SCANDATAX */\r
+#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */\r
+#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */\r
+#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */\r
+#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */\r
+#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */\r
+#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */\r
+#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */\r
+#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */\r
+#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */\r
+#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */\r
+\r
+/* Bit fields for ADC SCANDATAXP */\r
+#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */\r
+#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */\r
+#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */\r
+#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */\r
+#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */\r
+#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */\r
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */\r
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */\r
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */\r
+#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */\r
+\r
+/* Bit fields for ADC APORTREQ */\r
+#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */\r
+#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */\r
+#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */\r
+#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */\r
+#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */\r
+#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */\r
+#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */\r
+#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */\r
+#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */\r
+#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */\r
+#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */\r
+#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */\r
+#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */\r
+#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */\r
+#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */\r
+#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */\r
+#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */\r
+#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */\r
+#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */\r
+#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */\r
+#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */\r
+#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */\r
+#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */\r
+#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */\r
+#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */\r
+#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */\r
+#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */\r
+#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */\r
+#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */\r
+#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */\r
+#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */\r
+#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */\r
+#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */\r
+\r
+/* Bit fields for ADC APORTCONFLICT */\r
+#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */\r
+#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */\r
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */\r
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */\r
+#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */\r
+\r
+/* Bit fields for ADC SINGLEFIFOCOUNT */\r
+#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */\r
+#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */\r
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */\r
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */\r
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */\r
+#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */\r
+\r
+/* Bit fields for ADC SCANFIFOCOUNT */\r
+#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */\r
+#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */\r
+#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */\r
+#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */\r
+#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */\r
+#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */\r
+\r
+/* Bit fields for ADC SINGLEFIFOCLEAR */\r
+#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */\r
+#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */\r
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */\r
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */\r
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */\r
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */\r
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */\r
+\r
+/* Bit fields for ADC SCANFIFOCLEAR */\r
+#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */\r
+#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */\r
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */\r
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */\r
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */\r
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */\r
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */\r
+\r
+/* Bit fields for ADC APORTMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */\r
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */\r
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */\r
+#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */\r
+\r
+/** @} End of group EFM32PG1B_ADC */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_af_pins.h\r
+ * @brief EFM32PG1B_AF_PINS register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_AF_Pins\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** AF pin number for location number i */\r
+#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1)\r
+#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1)\r
+#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1)\r
+#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1)\r
+#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1)\r
+#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1)\r
+#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1)\r
+#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1)\r
+#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1)\r
+#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1)\r
+#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1)\r
+#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1)\r
+#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1)\r
+#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1)\r
+#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)\r
+#define AF_TIMER0_CC3_PIN(i) (-1)\r
+#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)\r
+#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)\r
+#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)\r
+#define AF_TIMER0_CDTI3_PIN(i) (-1)\r
+#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)\r
+#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)\r
+#define AF_TIMER1_CDTI0_PIN(i) (-1)\r
+#define AF_TIMER1_CDTI1_PIN(i) (-1)\r
+#define AF_TIMER1_CDTI2_PIN(i) (-1)\r
+#define AF_TIMER1_CDTI3_PIN(i) (-1)\r
+#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)\r
+#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)\r
+#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)\r
+#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)\r
+#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)\r
+#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)\r
+#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)\r
+#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)\r
+#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)\r
+#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)\r
+#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1)\r
+#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1)\r
+#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1)\r
+#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1)\r
+#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1)\r
+\r
+/** @} End of group EFM32PG1B_AF_Pins */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_af_ports.h\r
+ * @brief EFM32PG1B_AF_PORTS register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_AF_Ports\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** AF port number for location number i */\r
+#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)\r
+#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)\r
+#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1)\r
+#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)\r
+#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)\r
+#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1)\r
+#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)\r
+#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)\r
+#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1)\r
+#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1)\r
+#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1)\r
+#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1)\r
+#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)\r
+#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)\r
+#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER0_CC3_PORT(i) (-1)\r
+#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER0_CDTI3_PORT(i) (-1)\r
+#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_TIMER1_CDTI0_PORT(i) (-1)\r
+#define AF_TIMER1_CDTI1_PORT(i) (-1)\r
+#define AF_TIMER1_CDTI2_PORT(i) (-1)\r
+#define AF_TIMER1_CDTI3_PORT(i) (-1)\r
+#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)\r
+#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)\r
+#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)\r
+#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1)\r
+#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1)\r
+#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1)\r
+#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1)\r
+#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1)\r
+\r
+/** @} End of group EFM32PG1B_AF_Ports */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_cmu.h\r
+ * @brief EFM32PG1B_CMU register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_CMU\r
+ * @{\r
+ * @brief EFM32PG1B_CMU Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< CMU Control Register */\r
+\r
+ uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
+ __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
+\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
+\r
+ uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
+ __IO uint32_t HFXOCTRL; /**< HFXO Control Register */\r
+ __IO uint32_t HFXOCTRL1; /**< HFXO Control 1 */\r
+ __IO uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */\r
+ __IO uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */\r
+ __IO uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */\r
+ __IO uint32_t LFXOCTRL; /**< LFXO Control Register */\r
+\r
+ uint32_t RESERVED3[5]; /**< Reserved for future use **/\r
+ __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
+ __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
+ uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
+ __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ uint32_t RESERVED5[2]; /**< Reserved for future use **/\r
+ __IO uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */\r
+ __IO uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */\r
+ uint32_t RESERVED6[2]; /**< Reserved for future use **/\r
+ __IO uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */\r
+ __IO uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */\r
+ __IO uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */\r
+\r
+ uint32_t RESERVED7[1]; /**< Reserved for future use **/\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t HFCLKSTATUS; /**< HFCLK Status Register */\r
+ uint32_t RESERVED8[1]; /**< Reserved for future use **/\r
+ __I uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */\r
+\r
+ uint32_t RESERVED9[3]; /**< Reserved for future use **/\r
+ __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
+\r
+ uint32_t RESERVED10[7]; /**< Reserved for future use **/\r
+ __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
+ uint32_t RESERVED11[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
+ uint32_t RESERVED12[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */\r
+\r
+ uint32_t RESERVED13[3]; /**< Reserved for future use **/\r
+ __IO uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */\r
+\r
+ uint32_t RESERVED14[1]; /**< Reserved for future use **/\r
+ __IO uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */\r
+ __IO uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */\r
+\r
+ uint32_t RESERVED15[1]; /**< Reserved for future use **/\r
+ __IO uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */\r
+\r
+ uint32_t RESERVED16[2]; /**< Reserved for future use **/\r
+ __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
+ uint32_t RESERVED17[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
+ uint32_t RESERVED18[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */\r
+ uint32_t RESERVED19[3]; /**< Reserved for future use **/\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ uint32_t RESERVED20[2]; /**< Reserved for future use **/\r
+ __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
+\r
+ uint32_t RESERVED21[2]; /**< Reserved for future use **/\r
+ __IO uint32_t ADCCTRL; /**< ADC Control Register */\r
+ uint32_t RESERVED22[4]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+\r
+ uint32_t RESERVED23[2]; /**< Reserved for future use **/\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+} CMU_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_CMU_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for CMU CTRL */\r
+#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */\r
+#define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */\r
+#define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */\r
+#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */\r
+#define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
+#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */\r
+#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */\r
+#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */\r
+#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */\r
+#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */\r
+#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */\r
+#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */\r
+#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+\r
+/* Bit fields for CMU HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F3CUL /**< Default value for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
+#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000003CUL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */\r
+#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */\r
+#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */\r
+#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */\r
+#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */\r
+#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */\r
+#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */\r
+#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */\r
+#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */\r
+#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */\r
+#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */\r
+#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */\r
+#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */\r
+#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */\r
+#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */\r
+#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */\r
+#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+\r
+/* Bit fields for CMU AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F3CUL /**< Default value for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
+#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000003CUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */\r
+#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */\r
+#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */\r
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */\r
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */\r
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */\r
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */\r
+#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */\r
+#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */\r
+#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */\r
+#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */\r
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */\r
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */\r
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */\r
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */\r
+#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */\r
+#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+\r
+/* Bit fields for CMU LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_MASK 0xF30701FFUL /**< Mask for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */\r
+#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */\r
+#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */\r
+#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */\r
+#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */\r
+#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */\r
+#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */\r
+#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */\r
+#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */\r
+#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */\r
+#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */\r
+#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */\r
+#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */\r
+#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */\r
+#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+\r
+/* Bit fields for CMU HFXOCTRL */\r
+#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_MASK 0x77000F31UL /**< Mask for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */\r
+#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */\r
+#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */\r
+#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */\r
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */\r
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */\r
+#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */\r
+#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */\r
+#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off and KEEPWARM=0. */\r
+#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */\r
+#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */\r
+#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off and KEEPWARM=0. */\r
+#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */\r
+#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */\r
+#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_KEEPWARM (0x1UL << 11) /**< Keep HFXO warm when turning off HFXO. */\r
+#define _CMU_HFXOCTRL_KEEPWARM_SHIFT 11 /**< Shift value for CMU_KEEPWARM */\r
+#define _CMU_HFXOCTRL_KEEPWARM_MASK 0x800UL /**< Bit mask for CMU_KEEPWARM */\r
+#define _CMU_HFXOCTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_KEEPWARM_DEFAULT (_CMU_HFXOCTRL_KEEPWARM_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */\r
+#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */\r
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */\r
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */\r
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */\r
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */\r
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */\r
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_AUTOSTARTRDYSELRAC (0x1UL << 30) /**< Automatically start HFXO on RAC wake-up and select it upon HFXO Ready */\r
+#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_SHIFT 30 /**< Shift value for CMU_AUTOSTARTRDYSELRAC */\r
+#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK 0x40000000UL /**< Bit mask for CMU_AUTOSTARTRDYSELRAC */\r
+#define _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */\r
+#define CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */\r
+\r
+/* Bit fields for CMU HFXOCTRL1 */\r
+#define _CMU_HFXOCTRL1_RESETVALUE 0x00000240UL /**< Default value for CMU_HFXOCTRL1 */\r
+#define _CMU_HFXOCTRL1_MASK 0x00000277UL /**< Mask for CMU_HFXOCTRL1 */\r
+#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 0 /**< Shift value for CMU_PEAKDETTHR */\r
+#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7UL /**< Bit mask for CMU_PEAKDETTHR */\r
+#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */\r
+#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */\r
+#define _CMU_HFXOCTRL1_REGLVL_SHIFT 4 /**< Shift value for CMU_REGLVL */\r
+#define _CMU_HFXOCTRL1_REGLVL_MASK 0x70UL /**< Bit mask for CMU_REGLVL */\r
+#define _CMU_HFXOCTRL1_REGLVL_DEFAULT 0x00000004UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */\r
+#define CMU_HFXOCTRL1_REGLVL_DEFAULT (_CMU_HFXOCTRL1_REGLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */\r
+#define CMU_HFXOCTRL1_XTIBIASEN (0x1UL << 9) /**< Reserved for internal use. Do not change. */\r
+#define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT 9 /**< Shift value for CMU_XTIBIASEN */\r
+#define _CMU_HFXOCTRL1_XTIBIASEN_MASK 0x200UL /**< Bit mask for CMU_XTIBIASEN */\r
+#define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */\r
+#define CMU_HFXOCTRL1_XTIBIASEN_DEFAULT (_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */\r
+\r
+/* Bit fields for CMU HFXOSTARTUPCTRL */\r
+#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0xA1250060UL /**< Default value for CMU_HFXOSTARTUPCTRL */\r
+#define _CMU_HFXOSTARTUPCTRL_MASK 0xFFEFF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */\r
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */\r
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */\r
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000060UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */\r
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */\r
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT 21 /**< Shift value for CMU_IBTRIMXOCOREWARM */\r
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK 0xFE00000UL /**< Bit mask for CMU_IBTRIMXOCOREWARM */\r
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT 28 /**< Shift value for CMU_REGISHWARM */\r
+#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHWARM */\r
+#define _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+#define CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT (_CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */\r
+\r
+/* Bit fields for CMU HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30AAD09UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */\r
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */\r
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */\r
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */\r
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000155UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */\r
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */\r
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */\r
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */\r
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */\r
+\r
+/* Bit fields for CMU HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x00026667UL /**< Default value for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT 8 /**< Shift value for CMU_WARMSTEADYTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK 0xF00UL /**< Bit mask for CMU_WARMSTEADYTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2CYCLES << 8) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4CYCLES << 8) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16CYCLES << 8) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32CYCLES << 8) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_256CYCLES << 8) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_1KCYCLES << 8) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_2KCYCLES << 8) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_4KCYCLES << 8) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_8KCYCLES << 8) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_16KCYCLES << 8) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_32KCYCLES << 8) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */\r
+\r
+/* Bit fields for CMU LFXOCTRL */\r
+#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
+#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */\r
+#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */\r
+#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */\r
+#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */\r
+#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */\r
+#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */\r
+#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */\r
+#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */\r
+#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */\r
+#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */\r
+#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */\r
+#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */\r
+#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */\r
+#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */\r
+#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */\r
+#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */\r
+#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */\r
+#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */\r
+#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */\r
+#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */\r
+\r
+/* Bit fields for CMU CALCTRL */\r
+#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
+#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
+#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */\r
+#define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */\r
+#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */\r
+#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */\r
+#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */\r
+#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */\r
+#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
+#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */\r
+#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */\r
+#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */\r
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */\r
+\r
+/* Bit fields for CMU CALCNT */\r
+#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
+#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
+#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
+#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
+#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
+#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
+\r
+/* Bit fields for CMU OSCENCMD */\r
+#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
+#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
+#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
+#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
+#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
+#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
+#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
+#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
+#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
+#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
+#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
+#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
+#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
+#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
+#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
+#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
+#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
+#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
+#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
+#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
+#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
+#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
+#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
+#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
+#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
+#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
+#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
+#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
+#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
+#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
+#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+\r
+/* Bit fields for CMU CMD */\r
+#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
+#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */\r
+#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */\r
+#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */\r
+#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */\r
+#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */\r
+#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */\r
+#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */\r
+#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */\r
+#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */\r
+#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */\r
+#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */\r
+#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */\r
+#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */\r
+#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
+\r
+/* Bit fields for CMU DBGCLKSEL */\r
+#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */\r
+#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */\r
+#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */\r
+#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */\r
+#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */\r
+#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */\r
+#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */\r
+#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */\r
+#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */\r
+#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */\r
+\r
+/* Bit fields for CMU HFCLKSEL */\r
+#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */\r
+#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */\r
+#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */\r
+#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */\r
+#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */\r
+#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */\r
+#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */\r
+#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */\r
+#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */\r
+#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */\r
+#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */\r
+#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */\r
+#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */\r
+#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */\r
+\r
+/* Bit fields for CMU LFACLKSEL */\r
+#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */\r
+#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */\r
+#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
+#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */\r
+#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */\r
+#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */\r
+#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */\r
+#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */\r
+#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */\r
+#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */\r
+#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */\r
+#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */\r
+#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */\r
+#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */\r
+\r
+/* Bit fields for CMU LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */\r
+#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */\r
+#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */\r
+#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */\r
+#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */\r
+#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */\r
+#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */\r
+#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */\r
+#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */\r
+#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */\r
+\r
+/* Bit fields for CMU LFECLKSEL */\r
+#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */\r
+#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */\r
+#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */\r
+#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */\r
+#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */\r
+#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */\r
+#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */\r
+#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */\r
+#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */\r
+#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */\r
+#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */\r
+#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */\r
+#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */\r
+#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */\r
+\r
+/* Bit fields for CMU STATUS */\r
+#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */\r
+#define _CMU_STATUS_MASK 0x07D103FFUL /**< Mask for CMU_STATUS */\r
+#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
+#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
+#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
+#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
+#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
+#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
+#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
+#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
+#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
+#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
+#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
+#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
+#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
+#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
+#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
+#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
+#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
+#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
+#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
+#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
+#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
+#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
+#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
+#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
+#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */\r
+#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */\r
+#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOWARMS (0x1UL << 20) /**< HFXO Warm Status */\r
+#define _CMU_STATUS_HFXOWARMS_SHIFT 20 /**< Shift value for CMU_HFXOWARMS */\r
+#define _CMU_STATUS_HFXOWARMS_MASK 0x100000UL /**< Bit mask for CMU_HFXOWARMS */\r
+#define _CMU_STATUS_HFXOWARMS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOWARMS_DEFAULT (_CMU_STATUS_HFXOWARMS_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */\r
+#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */\r
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */\r
+#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */\r
+#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */\r
+#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */\r
+#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */\r
+#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */\r
+#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */\r
+#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */\r
+#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */\r
+#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+\r
+/* Bit fields for CMU HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */\r
+#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */\r
+#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */\r
+#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */\r
+#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */\r
+#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */\r
+#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */\r
+#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */\r
+#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */\r
+\r
+/* Bit fields for CMU HFXOTRIMSTATUS */\r
+#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */\r
+#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */\r
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */\r
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */\r
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */\r
+#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */\r
+#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */\r
+#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */\r
+#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */\r
+#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */\r
+\r
+/* Bit fields for CMU IF */\r
+#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
+#define _CMU_IF_MASK 0x80007F7FUL /**< Mask for CMU_IF */\r
+#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
+#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
+#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
+#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
+#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
+#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
+#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
+#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
+#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
+#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */\r
+#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */\r
+#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */\r
+#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */\r
+#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */\r
+#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */\r
+#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */\r
+#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */\r
+#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */\r
+#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */\r
+#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */\r
+#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */\r
+#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */\r
+#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */\r
+#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */\r
+#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */\r
+#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */\r
+#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */\r
+#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */\r
+\r
+/* Bit fields for CMU IFS */\r
+#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
+#define _CMU_IFS_MASK 0x80007F7FUL /**< Mask for CMU_IFS */\r
+#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */\r
+#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */\r
+#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */\r
+#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */\r
+#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */\r
+#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */\r
+#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */\r
+#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
+#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
+#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */\r
+#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */\r
+#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */\r
+#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */\r
+#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */\r
+#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */\r
+#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */\r
+#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */\r
+#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */\r
+#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */\r
+#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */\r
+#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */\r
+#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */\r
+#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */\r
+#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */\r
+#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */\r
+#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */\r
+#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */\r
+#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */\r
+\r
+/* Bit fields for CMU IFC */\r
+#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
+#define _CMU_IFC_MASK 0x80007F7FUL /**< Mask for CMU_IFC */\r
+#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */\r
+#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */\r
+#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */\r
+#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */\r
+#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */\r
+#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */\r
+#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */\r
+#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
+#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
+#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */\r
+#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */\r
+#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */\r
+#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */\r
+#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */\r
+#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */\r
+#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */\r
+#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */\r
+#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */\r
+#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */\r
+#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */\r
+#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */\r
+#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */\r
+#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */\r
+#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */\r
+#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */\r
+#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */\r
+#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */\r
+#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */\r
+\r
+/* Bit fields for CMU IEN */\r
+#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
+#define _CMU_IEN_MASK 0x80007F7FUL /**< Mask for CMU_IEN */\r
+#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */\r
+#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */\r
+#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */\r
+#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */\r
+#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */\r
+#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */\r
+#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */\r
+#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
+#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
+#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */\r
+#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */\r
+#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */\r
+#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */\r
+#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */\r
+#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */\r
+#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */\r
+#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */\r
+#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */\r
+#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */\r
+#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */\r
+#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */\r
+#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */\r
+#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */\r
+#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */\r
+#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */\r
+#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */\r
+#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */\r
+#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */\r
+#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */\r
+#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */\r
+#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */\r
+\r
+/* Bit fields for CMU HFBUSCLKEN0 */\r
+#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */\r
+#define _CMU_HFBUSCLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */\r
+#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */\r
+#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */\r
+#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_CRYPTO (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
+#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT 1 /**< Shift value for CMU_CRYPTO */\r
+#define _CMU_HFBUSCLKEN0_CRYPTO_MASK 0x2UL /**< Bit mask for CMU_CRYPTO */\r
+#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 2) /**< General purpose Input/Output Clock Enable */\r
+#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 2 /**< Shift value for CMU_GPIO */\r
+#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x4UL /**< Bit mask for CMU_GPIO */\r
+#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_PRS (0x1UL << 3) /**< Peripheral Reflex System Clock Enable */\r
+#define _CMU_HFBUSCLKEN0_PRS_SHIFT 3 /**< Shift value for CMU_PRS */\r
+#define _CMU_HFBUSCLKEN0_PRS_MASK 0x8UL /**< Bit mask for CMU_PRS */\r
+#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 4) /**< Linked Direct Memory Access Controller Clock Enable */\r
+#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 4 /**< Shift value for CMU_LDMA */\r
+#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x10UL /**< Bit mask for CMU_LDMA */\r
+#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 5) /**< General Purpose CRC Clock Enable */\r
+#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 5 /**< Shift value for CMU_GPCRC */\r
+#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x20UL /**< Bit mask for CMU_GPCRC */\r
+#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */\r
+\r
+/* Bit fields for CMU HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */\r
+#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */\r
+#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */\r
+#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */\r
+#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART0 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_USART0_SHIFT 2 /**< Shift value for CMU_USART0 */\r
+#define _CMU_HFPERCLKEN0_USART0_MASK 0x4UL /**< Bit mask for CMU_USART0 */\r
+#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART1 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_USART1_SHIFT 3 /**< Shift value for CMU_USART1 */\r
+#define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL /**< Bit mask for CMU_USART1 */\r
+#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 4) /**< Analog Comparator 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 4 /**< Shift value for CMU_ACMP0 */\r
+#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x10UL /**< Bit mask for CMU_ACMP0 */\r
+#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 5) /**< Analog Comparator 1 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 5 /**< Shift value for CMU_ACMP1 */\r
+#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL /**< Bit mask for CMU_ACMP1 */\r
+#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CryoTimer Clock Enable */\r
+#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6 /**< Shift value for CMU_CRYOTIMER */\r
+#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL /**< Bit mask for CMU_CRYOTIMER */\r
+#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 7) /**< I2C 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_I2C0_SHIFT 7 /**< Shift value for CMU_I2C0 */\r
+#define _CMU_HFPERCLKEN0_I2C0_MASK 0x80UL /**< Bit mask for CMU_I2C0 */\r
+#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 8) /**< Analog to Digital Converter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_ADC0_SHIFT 8 /**< Shift value for CMU_ADC0 */\r
+#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100UL /**< Bit mask for CMU_ADC0 */\r
+#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 9) /**< Current Digital to Analog Converter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 9 /**< Shift value for CMU_IDAC0 */\r
+#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x200UL /**< Bit mask for CMU_IDAC0 */\r
+#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+\r
+/* Bit fields for CMU LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */\r
+#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */\r
+#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */\r
+#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */\r
+#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
+#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
+\r
+/* Bit fields for CMU LFBCLKEN0 */\r
+#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
+#define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */\r
+#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
+#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
+#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
+#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
+#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
+\r
+/* Bit fields for CMU LFECLKEN0 */\r
+#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */\r
+#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */\r
+#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */\r
+#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */\r
+#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */\r
+#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */\r
+#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */\r
+\r
+/* Bit fields for CMU HFPRESC */\r
+#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */\r
+#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */\r
+#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */\r
+#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */\r
+#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */\r
+#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */\r
+#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */\r
+#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */\r
+#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */\r
+#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */\r
+#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */\r
+#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */\r
+#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */\r
+#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */\r
+#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */\r
+#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */\r
+\r
+/* Bit fields for CMU HFCOREPRESC */\r
+#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */\r
+#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */\r
+#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */\r
+#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */\r
+#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */\r
+#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */\r
+#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */\r
+#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */\r
+\r
+/* Bit fields for CMU HFPERPRESC */\r
+#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */\r
+#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */\r
+#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */\r
+#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */\r
+#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */\r
+#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */\r
+#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */\r
+#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */\r
+\r
+/* Bit fields for CMU HFEXPPRESC */\r
+#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */\r
+#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */\r
+#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */\r
+#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */\r
+#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */\r
+#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */\r
+#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */\r
+#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */\r
+\r
+/* Bit fields for CMU LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
+\r
+/* Bit fields for CMU LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
+#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
+\r
+/* Bit fields for CMU LFEPRESC0 */\r
+#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */\r
+#define _CMU_LFEPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFEPRESC0 */\r
+#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */\r
+#define _CMU_LFEPRESC0_RTCC_MASK 0xFUL /**< Bit mask for CMU_RTCC */\r
+#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */\r
+#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */\r
+\r
+/* Bit fields for CMU SYNCBUSY */\r
+#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
+#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
+#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
+#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
+#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
+#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
+#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
+#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
+#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
+#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
+#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
+#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
+#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
+#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */\r
+#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */\r
+#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */\r
+#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */\r
+#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */\r
+#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */\r
+#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */\r
+#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */\r
+#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */\r
+#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */\r
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */\r
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */\r
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */\r
+#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */\r
+#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */\r
+#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */\r
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */\r
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */\r
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */\r
+#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */\r
+#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */\r
+#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */\r
+#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */\r
+#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */\r
+#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+\r
+/* Bit fields for CMU FREEZE */\r
+#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
+#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
+#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
+\r
+/* Bit fields for CMU PCNTCTRL */\r
+#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
+#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
+#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
+#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
+\r
+/* Bit fields for CMU ADCCTRL */\r
+#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */\r
+#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */\r
+#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */\r
+#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */\r
+#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */\r
+#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */\r
+#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */\r
+\r
+/* Bit fields for CMU ROUTEPEN */\r
+#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */\r
+#define _CMU_ROUTEPEN_MASK 0x00000003UL /**< Mask for CMU_ROUTEPEN */\r
+#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
+#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
+#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
+#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */\r
+#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */\r
+#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
+#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
+#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
+#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */\r
+#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */\r
+\r
+/* Bit fields for CMU ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */\r
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */\r
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */\r
+\r
+/* Bit fields for CMU LOCK */\r
+#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
+#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
+#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
+#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
+\r
+/** @} End of group EFM32PG1B_CMU */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_cryotimer.h\r
+ * @brief EFM32PG1B_CRYOTIMER register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_CRYOTIMER\r
+ * @{\r
+ * @brief EFM32PG1B_CRYOTIMER Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t PERIODSEL; /**< Interrupt Duration */\r
+ __I uint32_t CNT; /**< Counter Value */\r
+ __IO uint32_t EM4WUEN; /**< Wake Up Enable */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+} CRYOTIMER_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_CRYOTIMER_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for CRYOTIMER CTRL */\r
+#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */\r
+#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */\r
+#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */\r
+#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */\r
+#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */\r
+#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */\r
+#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */\r
+#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */\r
+#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000000UL /**< Mode LFRCO for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000001UL /**< Mode LFXO for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000002UL /**< Mode ULFRCO for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */\r
+#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */\r
+#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */\r
+#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */\r
+#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */\r
+\r
+/* Bit fields for CRYOTIMER PERIODSEL */\r
+#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */\r
+#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */\r
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */\r
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */\r
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */\r
+#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */\r
+\r
+/* Bit fields for CRYOTIMER CNT */\r
+#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */\r
+#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */\r
+#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */\r
+#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */\r
+#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */\r
+#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */\r
+\r
+/* Bit fields for CRYOTIMER EM4WUEN */\r
+#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */\r
+#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */\r
+#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */\r
+#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */\r
+#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */\r
+#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */\r
+#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */\r
+\r
+/* Bit fields for CRYOTIMER IF */\r
+#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */\r
+#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */\r
+#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */\r
+#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */\r
+#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */\r
+\r
+/* Bit fields for CRYOTIMER IFS */\r
+#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */\r
+#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */\r
+#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */\r
+#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */\r
+#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */\r
+\r
+/* Bit fields for CRYOTIMER IFC */\r
+#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */\r
+#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */\r
+#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */\r
+#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */\r
+#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */\r
+\r
+/* Bit fields for CRYOTIMER IEN */\r
+#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */\r
+#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */\r
+#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */\r
+#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */\r
+#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */\r
+#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */\r
+\r
+/** @} End of group EFM32PG1B_CRYOTIMER */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_crypto.h\r
+ * @brief EFM32PG1B_CRYPTO register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_CRYPTO\r
+ * @{\r
+ * @brief EFM32PG1B_CRYPTO Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t WAC; /**< Wide Arithmetic Configuration */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t DSTATUS; /**< Data Status Register */\r
+ __I uint32_t CSTATUS; /**< Control Status Register */\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t KEY; /**< KEY Register Access */\r
+ __IO uint32_t KEYBUF; /**< KEY Buffer Register Access */\r
+ uint32_t RESERVED2[2]; /**< Reserved for future use **/\r
+ __IO uint32_t SEQCTRL; /**< Sequence Control */\r
+ __IO uint32_t SEQCTRLB; /**< Sequence Control B */\r
+ uint32_t RESERVED3[2]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< AES Interrupt Flags */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t SEQ0; /**< Sequence register 0 */\r
+ __IO uint32_t SEQ1; /**< Sequence Register 1 */\r
+ __IO uint32_t SEQ2; /**< Sequence Register 2 */\r
+ __IO uint32_t SEQ3; /**< Sequence Register 3 */\r
+ __IO uint32_t SEQ4; /**< Sequence Register 4 */\r
+ uint32_t RESERVED4[7]; /**< Reserved for future use **/\r
+ __IO uint32_t DATA0; /**< DATA0 Register Access */\r
+ __IO uint32_t DATA1; /**< DATA1 Register Access */\r
+ __IO uint32_t DATA2; /**< DATA2 Register Access */\r
+ __IO uint32_t DATA3; /**< DATA3 Register Access */\r
+ uint32_t RESERVED5[4]; /**< Reserved for future use **/\r
+ __IO uint32_t DATA0XOR; /**< DATA0XOR Register Access */\r
+ uint32_t RESERVED6[3]; /**< Reserved for future use **/\r
+ __IO uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */\r
+ __IO uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */\r
+ uint32_t RESERVED7[1]; /**< Reserved for future use **/\r
+ __IO uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */\r
+ __IO uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */\r
+ __IO uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */\r
+ __IO uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */\r
+ __IO uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */\r
+ uint32_t RESERVED8[12]; /**< Reserved for future use **/\r
+ __IO uint32_t DDATA0; /**< DDATA0 Register Access */\r
+ __IO uint32_t DDATA1; /**< DDATA1 Register Access */\r
+ __IO uint32_t DDATA2; /**< DDATA2 Register Access */\r
+ __IO uint32_t DDATA3; /**< DDATA3 Register Access */\r
+ __IO uint32_t DDATA4; /**< DDATA4 Register Access */\r
+ uint32_t RESERVED9[7]; /**< Reserved for future use **/\r
+ __IO uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */\r
+ uint32_t RESERVED10[3]; /**< Reserved for future use **/\r
+ __IO uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */\r
+ __IO uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */\r
+ __IO uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */\r
+ uint32_t RESERVED11[13]; /**< Reserved for future use **/\r
+ __IO uint32_t QDATA0; /**< QDATA0 Register Access */\r
+ __IO uint32_t QDATA1; /**< QDATA1 Register Access */\r
+ uint32_t RESERVED12[7]; /**< Reserved for future use **/\r
+ __IO uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */\r
+ uint32_t RESERVED13[6]; /**< Reserved for future use **/\r
+ __IO uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */\r
+ __IO uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */\r
+} CRYPTO_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_CRYPTO_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for CRYPTO CTRL */\r
+#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */\r
+#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */\r
+#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */\r
+#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */\r
+#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */\r
+#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */\r
+#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */\r
+#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */\r
+#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */\r
+#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */\r
+#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */\r
+#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */\r
+#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */\r
+#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */\r
+#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */\r
+#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */\r
+#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */\r
+#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */\r
+#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */\r
+#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */\r
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */\r
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */\r
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */\r
+#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */\r
+\r
+/* Bit fields for CRYPTO WAC */\r
+#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */\r
+#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */\r
+#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */\r
+#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */\r
+#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */\r
+#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */\r
+#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */\r
+#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */\r
+#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */\r
+#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */\r
+#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */\r
+#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */\r
+#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */\r
+\r
+/* Bit fields for CRYPTO CMD */\r
+#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */\r
+#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */\r
+#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */\r
+#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */\r
+#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */\r
+#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */\r
+#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */\r
+#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */\r
+#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */\r
+#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */\r
+#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */\r
+#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */\r
+#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */\r
+#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */\r
+#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */\r
+#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */\r
+#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */\r
+#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */\r
+#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */\r
+#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */\r
+\r
+/* Bit fields for CRYPTO STATUS */\r
+#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */\r
+#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */\r
+#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */\r
+#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */\r
+#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */\r
+#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */\r
+#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */\r
+#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */\r
+#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */\r
+#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */\r
+#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */\r
+#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */\r
+#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */\r
+#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */\r
+#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */\r
+#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */\r
+#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */\r
+\r
+/* Bit fields for CRYPTO DSTATUS */\r
+#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */\r
+#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */\r
+#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */\r
+#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */\r
+#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */\r
+#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */\r
+#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */\r
+#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */\r
+#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */\r
+#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */\r
+#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */\r
+#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */\r
+#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */\r
+\r
+/* Bit fields for CRYPTO CSTATUS */\r
+#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */\r
+#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */\r
+#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */\r
+#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */\r
+#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */\r
+#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */\r
+#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */\r
+#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */\r
+#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */\r
+#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */\r
+#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */\r
+#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */\r
+#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */\r
+#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */\r
+#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */\r
+\r
+/* Bit fields for CRYPTO KEY */\r
+#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */\r
+#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */\r
+#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */\r
+#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */\r
+#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */\r
+#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */\r
+\r
+/* Bit fields for CRYPTO KEYBUF */\r
+#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */\r
+#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */\r
+#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */\r
+#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */\r
+#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */\r
+#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */\r
+\r
+/* Bit fields for CRYPTO SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */\r
+#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */\r
+#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */\r
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */\r
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */\r
+#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */\r
+#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */\r
+#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */\r
+#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */\r
+#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */\r
+#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */\r
+#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */\r
+#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */\r
+#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */\r
+#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */\r
+#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */\r
+#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */\r
+#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */\r
+#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */\r
+\r
+/* Bit fields for CRYPTO SEQCTRLB */\r
+#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */\r
+#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */\r
+#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */\r
+#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */\r
+#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */\r
+#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */\r
+#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */\r
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */\r
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */\r
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */\r
+#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */\r
+#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */\r
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */\r
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */\r
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */\r
+#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */\r
+\r
+/* Bit fields for CRYPTO IF */\r
+#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */\r
+#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */\r
+#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */\r
+#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */\r
+#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */\r
+#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */\r
+#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */\r
+#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */\r
+\r
+/* Bit fields for CRYPTO IFS */\r
+#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */\r
+#define _CRYPTO_IFS_MASK 0x0000000FUL /**< Mask for CRYPTO_IFS */\r
+#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */\r
+#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */\r
+#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_BUFOF (0x1UL << 2) /**< Set BUFOF Interrupt Flag */\r
+#define _CRYPTO_IFS_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */\r
+#define _CRYPTO_IFS_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */\r
+#define _CRYPTO_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_BUFOF_DEFAULT (_CRYPTO_IFS_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_BUFUF (0x1UL << 3) /**< Set BUFUF Interrupt Flag */\r
+#define _CRYPTO_IFS_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */\r
+#define _CRYPTO_IFS_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */\r
+#define _CRYPTO_IFS_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */\r
+#define CRYPTO_IFS_BUFUF_DEFAULT (_CRYPTO_IFS_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFS */\r
+\r
+/* Bit fields for CRYPTO IFC */\r
+#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */\r
+#define _CRYPTO_IFC_MASK 0x0000000FUL /**< Mask for CRYPTO_IFC */\r
+#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */\r
+#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */\r
+#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_BUFOF (0x1UL << 2) /**< Clear BUFOF Interrupt Flag */\r
+#define _CRYPTO_IFC_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */\r
+#define _CRYPTO_IFC_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */\r
+#define _CRYPTO_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_BUFOF_DEFAULT (_CRYPTO_IFC_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_BUFUF (0x1UL << 3) /**< Clear BUFUF Interrupt Flag */\r
+#define _CRYPTO_IFC_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */\r
+#define _CRYPTO_IFC_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */\r
+#define _CRYPTO_IFC_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */\r
+#define CRYPTO_IFC_BUFUF_DEFAULT (_CRYPTO_IFC_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFC */\r
+\r
+/* Bit fields for CRYPTO IEN */\r
+#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */\r
+#define _CRYPTO_IEN_MASK 0x0000000FUL /**< Mask for CRYPTO_IEN */\r
+#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */\r
+#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */\r
+#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */\r
+#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */\r
+#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_BUFOF (0x1UL << 2) /**< BUFOF Interrupt Enable */\r
+#define _CRYPTO_IEN_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */\r
+#define _CRYPTO_IEN_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */\r
+#define _CRYPTO_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_BUFOF_DEFAULT (_CRYPTO_IEN_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_BUFUF (0x1UL << 3) /**< BUFUF Interrupt Enable */\r
+#define _CRYPTO_IEN_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */\r
+#define _CRYPTO_IEN_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */\r
+#define _CRYPTO_IEN_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */\r
+#define CRYPTO_IEN_BUFUF_DEFAULT (_CRYPTO_IEN_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IEN */\r
+\r
+/* Bit fields for CRYPTO SEQ0 */\r
+#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */\r
+#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */\r
+#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */\r
+#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */\r
+#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */\r
+#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */\r
+#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */\r
+#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */\r
+#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */\r
+#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */\r
+#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */\r
+#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */\r
+#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */\r
+#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */\r
+#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */\r
+#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */\r
+#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */\r
+#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */\r
+\r
+/* Bit fields for CRYPTO SEQ1 */\r
+#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */\r
+#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */\r
+#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */\r
+#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */\r
+#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */\r
+#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */\r
+#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */\r
+#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */\r
+#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */\r
+#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */\r
+#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */\r
+#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */\r
+#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */\r
+#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */\r
+#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */\r
+#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */\r
+#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */\r
+#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */\r
+\r
+/* Bit fields for CRYPTO SEQ2 */\r
+#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */\r
+#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */\r
+#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */\r
+#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */\r
+#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */\r
+#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */\r
+#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */\r
+#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */\r
+#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */\r
+#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */\r
+#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */\r
+#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */\r
+#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */\r
+#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */\r
+#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */\r
+#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */\r
+#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */\r
+#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */\r
+\r
+/* Bit fields for CRYPTO SEQ3 */\r
+#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */\r
+#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */\r
+#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */\r
+#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */\r
+#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */\r
+#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */\r
+#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */\r
+#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */\r
+#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */\r
+#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */\r
+#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */\r
+#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */\r
+#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */\r
+#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */\r
+#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */\r
+#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */\r
+#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */\r
+#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */\r
+\r
+/* Bit fields for CRYPTO SEQ4 */\r
+#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */\r
+#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */\r
+#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */\r
+#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */\r
+#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */\r
+#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */\r
+#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */\r
+#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */\r
+#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */\r
+#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */\r
+#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */\r
+#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */\r
+#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */\r
+#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */\r
+#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */\r
+#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */\r
+#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */\r
+#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */\r
+\r
+/* Bit fields for CRYPTO DATA0 */\r
+#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */\r
+#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */\r
+#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */\r
+#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */\r
+#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */\r
+#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */\r
+\r
+/* Bit fields for CRYPTO DATA1 */\r
+#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */\r
+#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */\r
+#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */\r
+#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */\r
+#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */\r
+#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */\r
+\r
+/* Bit fields for CRYPTO DATA2 */\r
+#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */\r
+#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */\r
+#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */\r
+#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */\r
+#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */\r
+#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */\r
+\r
+/* Bit fields for CRYPTO DATA3 */\r
+#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */\r
+#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */\r
+#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */\r
+#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */\r
+#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */\r
+#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */\r
+\r
+/* Bit fields for CRYPTO DATA0XOR */\r
+#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */\r
+#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */\r
+#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */\r
+#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */\r
+#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */\r
+#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */\r
+\r
+/* Bit fields for CRYPTO DATA0BYTE */\r
+#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */\r
+#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */\r
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */\r
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */\r
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */\r
+#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */\r
+\r
+/* Bit fields for CRYPTO DATA1BYTE */\r
+#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */\r
+#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */\r
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */\r
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */\r
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */\r
+#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */\r
+\r
+/* Bit fields for CRYPTO DATA0XORBYTE */\r
+#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */\r
+#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */\r
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */\r
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */\r
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */\r
+#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */\r
+\r
+/* Bit fields for CRYPTO DATA0BYTE12 */\r
+#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */\r
+#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */\r
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */\r
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */\r
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */\r
+#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */\r
+\r
+/* Bit fields for CRYPTO DATA0BYTE13 */\r
+#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */\r
+#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */\r
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */\r
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */\r
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */\r
+#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */\r
+\r
+/* Bit fields for CRYPTO DATA0BYTE14 */\r
+#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */\r
+#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */\r
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */\r
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */\r
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */\r
+#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */\r
+\r
+/* Bit fields for CRYPTO DATA0BYTE15 */\r
+#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */\r
+#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */\r
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */\r
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */\r
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */\r
+#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */\r
+\r
+/* Bit fields for CRYPTO DDATA0 */\r
+#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */\r
+#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */\r
+#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */\r
+#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */\r
+#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */\r
+#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */\r
+\r
+/* Bit fields for CRYPTO DDATA1 */\r
+#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */\r
+#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */\r
+#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */\r
+#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */\r
+#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */\r
+#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */\r
+\r
+/* Bit fields for CRYPTO DDATA2 */\r
+#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */\r
+#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */\r
+#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */\r
+#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */\r
+#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */\r
+#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */\r
+\r
+/* Bit fields for CRYPTO DDATA3 */\r
+#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */\r
+#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */\r
+#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */\r
+#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */\r
+#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */\r
+#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */\r
+\r
+/* Bit fields for CRYPTO DDATA4 */\r
+#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */\r
+#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */\r
+#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */\r
+#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */\r
+#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */\r
+#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */\r
+\r
+/* Bit fields for CRYPTO DDATA0BIG */\r
+#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */\r
+#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */\r
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */\r
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */\r
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */\r
+#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */\r
+\r
+/* Bit fields for CRYPTO DDATA0BYTE */\r
+#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */\r
+#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */\r
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */\r
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */\r
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */\r
+#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */\r
+\r
+/* Bit fields for CRYPTO DDATA1BYTE */\r
+#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */\r
+#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */\r
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */\r
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */\r
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */\r
+#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */\r
+\r
+/* Bit fields for CRYPTO DDATA0BYTE32 */\r
+#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */\r
+#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */\r
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */\r
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */\r
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */\r
+#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */\r
+\r
+/* Bit fields for CRYPTO QDATA0 */\r
+#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */\r
+#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */\r
+#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */\r
+#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */\r
+#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */\r
+#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */\r
+\r
+/* Bit fields for CRYPTO QDATA1 */\r
+#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */\r
+#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */\r
+#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */\r
+#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */\r
+#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */\r
+#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */\r
+\r
+/* Bit fields for CRYPTO QDATA1BIG */\r
+#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */\r
+#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */\r
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */\r
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */\r
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */\r
+#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */\r
+\r
+/* Bit fields for CRYPTO QDATA0BYTE */\r
+#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */\r
+#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */\r
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */\r
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */\r
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */\r
+#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */\r
+\r
+/* Bit fields for CRYPTO QDATA1BYTE */\r
+#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */\r
+#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */\r
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */\r
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */\r
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */\r
+#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */\r
+\r
+/** @} End of group EFM32PG1B_CRYPTO */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_devinfo.h\r
+ * @brief EFM32PG1B_DEVINFO register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_DEVINFO\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+typedef struct\r
+{\r
+ __I uint32_t CAL; /**< CRC of DI-page and calibration temperature */\r
+ uint32_t RESERVED0[9]; /**< Reserved for future use **/\r
+ __I uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */\r
+ __I uint32_t EUI48H; /**< OUI */\r
+ __I uint32_t CUSTOMINFO; /**< Custom information */\r
+ __I uint32_t MEMINFO; /**< Flash page size and misc. chip information */\r
+ uint32_t RESERVED1[2]; /**< Reserved for future use **/\r
+ __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */\r
+ __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */\r
+ __I uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */\r
+ __I uint32_t PART; /**< Part description */\r
+ __I uint32_t DEVINFOREV; /**< Device information page revision */\r
+ __I uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */\r
+ uint32_t RESERVED2[2]; /**< Reserved for future use **/\r
+ __I uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */\r
+ __I uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */\r
+ __I uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */\r
+ __I uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */\r
+ uint32_t RESERVED3[4]; /**< Reserved for future use **/\r
+ __I uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */\r
+ uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
+ __I uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */\r
+ uint32_t RESERVED5[2]; /**< Reserved for future use **/\r
+ __I uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */\r
+ __I uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */\r
+ __I uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */\r
+ uint32_t RESERVED6[1]; /**< Reserved for future use **/\r
+ __I uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */\r
+ __I uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */\r
+ __I uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */\r
+ uint32_t RESERVED7[11]; /**< Reserved for future use **/\r
+ __I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */\r
+ uint32_t RESERVED8[2]; /**< Reserved for future use **/\r
+ __I uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */\r
+ uint32_t RESERVED9[2]; /**< Reserved for future use **/\r
+ __I uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */\r
+ __I uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */\r
+ __I uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */\r
+ uint32_t RESERVED10[1]; /**< Reserved for future use **/\r
+ __I uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */\r
+ __I uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */\r
+ __I uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */\r
+ uint32_t RESERVED11[11]; /**< Reserved for future use **/\r
+ __I uint32_t VMONCAL0; /**< VMON Calibration Register 0 */\r
+ __I uint32_t VMONCAL1; /**< VMON Calibration Register 1 */\r
+ __I uint32_t VMONCAL2; /**< VMON Calibration Register 2 */\r
+ uint32_t RESERVED12[3]; /**< Reserved for future use **/\r
+ __I uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */\r
+ __I uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */\r
+ uint32_t RESERVED13[2]; /**< Reserved for future use **/\r
+ __I uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */\r
+ __I uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */\r
+ __I uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */\r
+ __I uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */\r
+ __I uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */\r
+ __I uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */\r
+ __I uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */\r
+} DEVINFO_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_DEVINFO_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for DEVINFO CAL */\r
+#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */\r
+#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */\r
+#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */\r
+#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */\r
+#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */\r
+\r
+/* Bit fields for DEVINFO EUI48L */\r
+#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */\r
+#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */\r
+#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */\r
+#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */\r
+#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */\r
+\r
+/* Bit fields for DEVINFO EUI48H */\r
+#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */\r
+#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */\r
+#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */\r
+\r
+/* Bit fields for DEVINFO CUSTOMINFO */\r
+#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */\r
+#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */\r
+#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */\r
+\r
+/* Bit fields for DEVINFO MEMINFO */\r
+#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */\r
+#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */\r
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */\r
+#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */\r
+#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */\r
+#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */\r
+#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */\r
+#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */\r
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */\r
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */\r
+\r
+/* Bit fields for DEVINFO UNIQUEL */\r
+#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */\r
+#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */\r
+#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */\r
+\r
+/* Bit fields for DEVINFO UNIQUEH */\r
+#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */\r
+#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */\r
+#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */\r
+\r
+/* Bit fields for DEVINFO MSIZE */\r
+#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */\r
+#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */\r
+#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */\r
+#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */\r
+#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */\r
+\r
+/* Bit fields for DEVINFO PART */\r
+#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */\r
+#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P 0x00000016UL /**< Mode EFR32ZG1P for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B 0x00000017UL /**< Mode EFR32ZG1B for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V 0x00000018UL /**< Mode EFR32ZG1V for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */\r
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P << 16) /**< Shifted mode EFR32ZG1P for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B << 16) /**< Shifted mode EFR32ZG1B for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V << 16) /**< Shifted mode EFR32ZG1V for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */\r
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */\r
+#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */\r
+#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */\r
+\r
+/* Bit fields for DEVINFO DEVINFOREV */\r
+#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */\r
+#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */\r
+#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */\r
+\r
+/* Bit fields for DEVINFO EMUTEMP */\r
+#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */\r
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */\r
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */\r
+\r
+/* Bit fields for DEVINFO ADC0CAL0 */\r
+#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */\r
+#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */\r
+#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */\r
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */\r
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */\r
+#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */\r
+#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */\r
+#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */\r
+#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */\r
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */\r
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */\r
+#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */\r
+#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */\r
+\r
+/* Bit fields for DEVINFO ADC0CAL1 */\r
+#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */\r
+#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */\r
+#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */\r
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */\r
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */\r
+#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */\r
+#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */\r
+#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */\r
+#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */\r
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */\r
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */\r
+#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */\r
+#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */\r
+\r
+/* Bit fields for DEVINFO ADC0CAL2 */\r
+#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */\r
+#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */\r
+#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */\r
+#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */\r
+#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */\r
+\r
+/* Bit fields for DEVINFO ADC0CAL3 */\r
+#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */\r
+#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */\r
+#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL0 */\r
+#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */\r
+#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL3 */\r
+#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */\r
+#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL6 */\r
+#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */\r
+#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL7 */\r
+#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */\r
+#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL8 */\r
+#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */\r
+#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL10 */\r
+#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */\r
+#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL11 */\r
+#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */\r
+#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO HFRCOCAL12 */\r
+#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */\r
+#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL0 */\r
+#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */\r
+#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL3 */\r
+#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */\r
+#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL6 */\r
+#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */\r
+#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL7 */\r
+#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */\r
+#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL8 */\r
+#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */\r
+#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL10 */\r
+#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */\r
+#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL11 */\r
+#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */\r
+#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO AUXHFRCOCAL12 */\r
+#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */\r
+#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */\r
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */\r
+#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */\r
+#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */\r
+#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */\r
+#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */\r
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */\r
+#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */\r
+#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */\r
+\r
+/* Bit fields for DEVINFO VMONCAL0 */\r
+#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */\r
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */\r
+\r
+/* Bit fields for DEVINFO VMONCAL1 */\r
+#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */\r
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */\r
+#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */\r
+#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */\r
+#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */\r
+#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */\r
+\r
+/* Bit fields for DEVINFO VMONCAL2 */\r
+#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */\r
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */\r
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */\r
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */\r
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */\r
+\r
+/* Bit fields for DEVINFO IDAC0CAL0 */\r
+#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */\r
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */\r
+\r
+/* Bit fields for DEVINFO IDAC0CAL1 */\r
+#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */\r
+#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */\r
+\r
+/* Bit fields for DEVINFO DCDCLNVCTRL0 */\r
+#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */\r
+#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */\r
+#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */\r
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */\r
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */\r
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */\r
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */\r
+#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */\r
+#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */\r
+\r
+/* Bit fields for DEVINFO DCDCLPVCTRL0 */\r
+#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */\r
+\r
+/* Bit fields for DEVINFO DCDCLPVCTRL1 */\r
+#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */\r
+\r
+/* Bit fields for DEVINFO DCDCLPVCTRL2 */\r
+#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */\r
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */\r
+\r
+/* Bit fields for DEVINFO DCDCLPVCTRL3 */\r
+#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */\r
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */\r
+\r
+/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */\r
+\r
+/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */\r
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */\r
+\r
+/** @} End of group EFM32PG1B_DEVINFO */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_dma_descriptor.h\r
+ * @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_DMA_DESCRIPTOR\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ /* Note! Use of double __IO (volatile) qualifier to ensure that both */\r
+ /* pointer and referenced memory are declared volatile. */\r
+ __IO uint32_t CTRL; /**< DMA control register */\r
+ __IO void * __IO SRC; /**< DMA source address */\r
+ __IO void * __IO DST; /**< DMA destination address */\r
+ __IO void * __IO LINK; /**< DMA link address */\r
+} DMA_DESCRIPTOR_TypeDef; /**< @} */\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_dmareq.h\r
+ * @brief EFM32PG1B_DMAREQ register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_DMAREQ_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */\r
+#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */\r
+#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */\r
+#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */\r
+#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */\r
+#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */\r
+#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */\r
+#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */\r
+#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */\r
+#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */\r
+#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */\r
+#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */\r
+#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */\r
+#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */\r
+#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */\r
+#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */\r
+#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */\r
+#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */\r
+#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */\r
+#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */\r
+#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */\r
+#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */\r
+#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */\r
+#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */\r
+#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */\r
+#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */\r
+#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */\r
+#define DMAREQ_CRYPTO_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO_DATA0WR */\r
+#define DMAREQ_CRYPTO_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO_DATA0XWR */\r
+#define DMAREQ_CRYPTO_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO_DATA0RD */\r
+#define DMAREQ_CRYPTO_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO_DATA1WR */\r
+#define DMAREQ_CRYPTO_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO_DATA1RD */\r
+\r
+/** @} End of group EFM32PG1B_DMAREQ */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_emu.h\r
+ * @brief EFM32PG1B_EMU register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_EMU\r
+ * @{\r
+ * @brief EFM32PG1B_EMU Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+ __IO uint32_t RAM0CTRL; /**< Memory Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __IO uint32_t PERACTCONF; /**< Peripheral to Peripheral Activation Clock Configuration */\r
+ __IO uint32_t EM4CTRL; /**< EM4 Control Register */\r
+ __IO uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */\r
+ __I uint32_t TEMP; /**< Value of last temperature measurement */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */\r
+ __IO uint32_t PWRCFG; /**< Power Configuration Register. */\r
+ __IO uint32_t PWRCTRL; /**< Power Control Register. */\r
+ __IO uint32_t DCDCCTRL; /**< DCDC Control */\r
+\r
+ uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
+ __IO uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */\r
+ __IO uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */\r
+ __IO uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */\r
+\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */\r
+ __IO uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */\r
+ __IO uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */\r
+\r
+ uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
+ __IO uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */\r
+ __IO uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */\r
+\r
+ uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
+ __I uint32_t DCDCSYNC; /**< DCDC Read Status Register */\r
+\r
+ uint32_t RESERVED4[5]; /**< Reserved for future use **/\r
+ __IO uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */\r
+ __IO uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */\r
+ __IO uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */\r
+ __IO uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */\r
+} EMU_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_EMU_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for EMU CTRL */\r
+#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */\r
+#define _EMU_CTRL_MASK 0x00000002UL /**< Mask for EMU_CTRL */\r
+#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */\r
+#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */\r
+#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */\r
+#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */\r
+#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */\r
+\r
+/* Bit fields for EMU STATUS */\r
+#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */\r
+#define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */\r
+#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */\r
+#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */\r
+#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */\r
+#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */\r
+#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */\r
+#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */\r
+#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */\r
+#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */\r
+#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */\r
+#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */\r
+#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */\r
+#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */\r
+#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */\r
+#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */\r
+#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */\r
+#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */\r
+#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */\r
+#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */\r
+#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */\r
+#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */\r
+#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */\r
+#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */\r
+#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */\r
+#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */\r
+#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */\r
+#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */\r
+#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */\r
+\r
+/* Bit fields for EMU LOCK */\r
+#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */\r
+#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */\r
+#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */\r
+#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */\r
+\r
+/* Bit fields for EMU RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */\r
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */\r
+#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */\r
+#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */\r
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */\r
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */\r
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */\r
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */\r
+\r
+/* Bit fields for EMU CMD */\r
+#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */\r
+#define _EMU_CMD_MASK 0x00000001UL /**< Mask for EMU_CMD */\r
+#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */\r
+#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */\r
+#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */\r
+#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */\r
+#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */\r
+\r
+/* Bit fields for EMU PERACTCONF */\r
+#define _EMU_PERACTCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PERACTCONF */\r
+#define _EMU_PERACTCONF_MASK 0x00000001UL /**< Mask for EMU_PERACTCONF */\r
+#define EMU_PERACTCONF_RACPER (0x1UL << 0) /**< Enable PER clock when RAC is activated */\r
+#define _EMU_PERACTCONF_RACPER_SHIFT 0 /**< Shift value for EMU_RACPER */\r
+#define _EMU_PERACTCONF_RACPER_MASK 0x1UL /**< Bit mask for EMU_RACPER */\r
+#define _EMU_PERACTCONF_RACPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PERACTCONF */\r
+#define EMU_PERACTCONF_RACPER_DEFAULT (_EMU_PERACTCONF_RACPER_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PERACTCONF */\r
+\r
+/* Bit fields for EMU EM4CTRL */\r
+#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */\r
+#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */\r
+#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */\r
+#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */\r
+#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */\r
+#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */\r
+#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */\r
+#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */\r
+#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */\r
+#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */\r
+#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */\r
+#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */\r
+#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */\r
+#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */\r
+#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */\r
+#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */\r
+#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */\r
+#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */\r
+#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */\r
+\r
+/* Bit fields for EMU TEMPLIMITS */\r
+#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */\r
+#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */\r
+#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */\r
+#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */\r
+#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */\r
+#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */\r
+#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */\r
+#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */\r
+#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */\r
+#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */\r
+#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temerature */\r
+#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */\r
+#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */\r
+#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */\r
+#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */\r
+\r
+/* Bit fields for EMU TEMP */\r
+#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */\r
+#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */\r
+#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */\r
+#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */\r
+#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */\r
+#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */\r
+\r
+/* Bit fields for EMU IF */\r
+#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */\r
+#define _EMU_IF_MASK 0xE11FC0FFUL /**< Mask for EMU_IF */\r
+#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */\r
+#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */\r
+#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */\r
+#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */\r
+#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */\r
+#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */\r
+#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */\r
+#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */\r
+#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */\r
+#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */\r
+#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */\r
+#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */\r
+#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */\r
+#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */\r
+#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */\r
+#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */\r
+#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */\r
+#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */\r
+#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */\r
+#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */\r
+#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */\r
+#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */\r
+#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */\r
+#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */\r
+#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */\r
+#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */\r
+#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */\r
+#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */\r
+#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */\r
+#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */\r
+#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */\r
+#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */\r
+#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */\r
+#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */\r
+#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */\r
+#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */\r
+#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */\r
+#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */\r
+#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */\r
+#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */\r
+#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */\r
+#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */\r
+#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */\r
+#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */\r
+#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */\r
+#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */\r
+#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */\r
+#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */\r
+#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */\r
+#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */\r
+#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */\r
+#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */\r
+\r
+/* Bit fields for EMU IFS */\r
+#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */\r
+#define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */\r
+#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */\r
+#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */\r
+#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */\r
+#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */\r
+#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */\r
+#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */\r
+#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */\r
+#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */\r
+#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */\r
+#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */\r
+#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */\r
+#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */\r
+#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */\r
+#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */\r
+#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */\r
+#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */\r
+#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */\r
+#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */\r
+#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */\r
+#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */\r
+#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */\r
+#define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */\r
+#define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */\r
+#define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */\r
+#define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */\r
+#define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */\r
+#define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */\r
+#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */\r
+#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */\r
+#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */\r
+#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */\r
+#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */\r
+#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */\r
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */\r
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */\r
+#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */\r
+#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */\r
+#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */\r
+#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */\r
+#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */\r
+#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */\r
+#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */\r
+#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */\r
+#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */\r
+#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */\r
+#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */\r
+#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */\r
+#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */\r
+#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */\r
+#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */\r
+#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */\r
+#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */\r
+#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */\r
+#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */\r
+#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */\r
+#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */\r
+#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */\r
+\r
+/* Bit fields for EMU IFC */\r
+#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */\r
+#define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */\r
+#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */\r
+#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */\r
+#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */\r
+#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */\r
+#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */\r
+#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */\r
+#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */\r
+#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */\r
+#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */\r
+#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */\r
+#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */\r
+#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */\r
+#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */\r
+#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */\r
+#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */\r
+#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */\r
+#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */\r
+#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */\r
+#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */\r
+#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */\r
+#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */\r
+#define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */\r
+#define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */\r
+#define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */\r
+#define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */\r
+#define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */\r
+#define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */\r
+#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */\r
+#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */\r
+#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */\r
+#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */\r
+#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */\r
+#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */\r
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */\r
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */\r
+#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */\r
+#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */\r
+#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */\r
+#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */\r
+#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */\r
+#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */\r
+#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */\r
+#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */\r
+#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */\r
+#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */\r
+#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */\r
+#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */\r
+#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */\r
+#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */\r
+#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */\r
+#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */\r
+#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */\r
+#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */\r
+#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */\r
+#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */\r
+#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */\r
+#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */\r
+\r
+/* Bit fields for EMU IEN */\r
+#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */\r
+#define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */\r
+#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */\r
+#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */\r
+#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */\r
+#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */\r
+#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */\r
+#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */\r
+#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */\r
+#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */\r
+#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */\r
+#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */\r
+#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */\r
+#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */\r
+#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */\r
+#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */\r
+#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */\r
+#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */\r
+#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */\r
+#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */\r
+#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */\r
+#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */\r
+#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */\r
+#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */\r
+#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */\r
+#define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */\r
+#define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */\r
+#define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */\r
+#define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */\r
+#define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */\r
+#define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */\r
+#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */\r
+#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */\r
+#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */\r
+#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */\r
+#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */\r
+#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */\r
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */\r
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */\r
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */\r
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */\r
+#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */\r
+#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */\r
+#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */\r
+#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */\r
+#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */\r
+#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */\r
+#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */\r
+#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */\r
+#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */\r
+#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */\r
+#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */\r
+#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */\r
+#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */\r
+#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */\r
+#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */\r
+#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */\r
+#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */\r
+#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */\r
+#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */\r
+#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */\r
+#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */\r
+#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */\r
+\r
+/* Bit fields for EMU PWRLOCK */\r
+#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */\r
+#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */\r
+#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */\r
+#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */\r
+#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */\r
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */\r
+#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */\r
+#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */\r
+#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */\r
+#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */\r
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */\r
+#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */\r
+#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */\r
+#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */\r
+\r
+/* Bit fields for EMU PWRCFG */\r
+#define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL /**< Mode STARTUP for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_PWRCFG_NODCDC 0x00000001UL /**< Mode NODCDC for EMU_PWRCFG */\r
+#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */\r
+#define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */\r
+#define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0) /**< Shifted mode STARTUP for EMU_PWRCFG */\r
+#define EMU_PWRCFG_PWRCFG_NODCDC (_EMU_PWRCFG_PWRCFG_NODCDC << 0) /**< Shifted mode NODCDC for EMU_PWRCFG */\r
+#define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */\r
+\r
+/* Bit fields for EMU PWRCTRL */\r
+#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */\r
+#define _EMU_PWRCTRL_MASK 0x00000020UL /**< Mask for EMU_PWRCTRL */\r
+#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */\r
+#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */\r
+#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */\r
+#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */\r
+#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */\r
+#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */\r
+#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */\r
+#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */\r
+#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */\r
+\r
+/* Bit fields for EMU DCDCCTRL */\r
+#define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL /**< Default value for EMU_DCDCCTRL */\r
+#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */\r
+#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */\r
+#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */\r
+#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCTRL */\r
+#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */\r
+#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */\r
+#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */\r
+#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< Reserved for internal use. Do not change. */\r
+#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */\r
+#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */\r
+#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< Reserved for internal use. Do not change. */\r
+#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */\r
+#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */\r
+#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */\r
+#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */\r
+\r
+/* Bit fields for EMU DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */\r
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */\r
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */\r
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */\r
+#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */\r
+#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */\r
+#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */\r
+#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */\r
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */\r
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */\r
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */\r
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */\r
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */\r
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28 /**< Shift value for EMU_LPCMPBIAS */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIAS */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */\r
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */\r
+\r
+/* Bit fields for EMU DCDCZDETCTRL */\r
+#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL /**< Default value for EMU_DCDCZDETCTRL */\r
+#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */\r
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */\r
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */\r
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */\r
+#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */\r
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */\r
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */\r
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */\r
+#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */\r
+\r
+/* Bit fields for EMU DCDCCLIMCTRL */\r
+#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL /**< Default value for EMU_DCDCCLIMCTRL */\r
+#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */\r
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */\r
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */\r
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */\r
+#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */\r
+#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */\r
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */\r
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */\r
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */\r
+#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */\r
+\r
+/* Bit fields for EMU DCDCLNVCTRL */\r
+#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */\r
+#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */\r
+#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */\r
+#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */\r
+#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */\r
+#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */\r
+#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */\r
+#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */\r
+#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */\r
+#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */\r
+#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */\r
+#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */\r
+#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */\r
+#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */\r
+#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */\r
+\r
+/* Bit fields for EMU DCDCTIMING */\r
+#define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL /**< Default value for EMU_DCDCTIMING */\r
+#define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL /**< Mask for EMU_DCDCTIMING */\r
+#define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0 /**< Shift value for EMU_LPINITWAIT */\r
+#define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */\r
+#define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */\r
+#define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */\r
+#define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN mode precharge enable */\r
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */\r
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */\r
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */\r
+#define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */\r
+#define _EMU_DCDCTIMING_LNWAIT_SHIFT 12 /**< Shift value for EMU_LNWAIT */\r
+#define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL /**< Bit mask for EMU_LNWAIT */\r
+#define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL /**< Mode DEFAULT for EMU_DCDCTIMING */\r
+#define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */\r
+#define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20 /**< Shift value for EMU_BYPWAIT */\r
+#define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL /**< Bit mask for EMU_BYPWAIT */\r
+#define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */\r
+#define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */\r
+#define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29 /**< Shift value for EMU_DUTYSCALE */\r
+#define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL /**< Bit mask for EMU_DUTYSCALE */\r
+#define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCTIMING */\r
+#define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */\r
+\r
+/* Bit fields for EMU DCDCLPVCTRL */\r
+#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */\r
+#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */\r
+#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */\r
+#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */\r
+#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */\r
+#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */\r
+#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */\r
+#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */\r
+#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */\r
+#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */\r
+#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */\r
+#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */\r
+#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */\r
+#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */\r
+#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */\r
+\r
+/* Bit fields for EMU DCDCLPCTRL */\r
+#define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL /**< Default value for EMU_DCDCLPCTRL */\r
+#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */\r
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSEL */\r
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */\r
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */\r
+#define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */\r
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< Lp mode duty cycling enable */\r
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */\r
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */\r
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */\r
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */\r
+#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */\r
+#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */\r
+#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */\r
+#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */\r
+\r
+/* Bit fields for EMU DCDCLNFREQCTRL */\r
+#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */\r
+#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */\r
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */\r
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */\r
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */\r
+#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */\r
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */\r
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */\r
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */\r
+#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */\r
+\r
+/* Bit fields for EMU DCDCSYNC */\r
+#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */\r
+#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */\r
+#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */\r
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */\r
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */\r
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */\r
+#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */\r
+\r
+/* Bit fields for EMU VMONAVDDCTRL */\r
+#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */\r
+#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */\r
+#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */\r
+#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */\r
+#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */\r
+#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */\r
+#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */\r
+#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */\r
+#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */\r
+#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */\r
+#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */\r
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */\r
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */\r
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */\r
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */\r
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */\r
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */\r
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */\r
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */\r
+#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */\r
+\r
+/* Bit fields for EMU VMONALTAVDDCTRL */\r
+#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */\r
+#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */\r
+#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */\r
+#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */\r
+#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */\r
+#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */\r
+#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */\r
+#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */\r
+#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */\r
+#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */\r
+#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */\r
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */\r
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */\r
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */\r
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */\r
+\r
+/* Bit fields for EMU VMONDVDDCTRL */\r
+#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */\r
+#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */\r
+#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */\r
+#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */\r
+#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */\r
+#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */\r
+#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */\r
+#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */\r
+#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */\r
+#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */\r
+#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */\r
+#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */\r
+#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */\r
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */\r
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */\r
+#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */\r
+\r
+/* Bit fields for EMU VMONIO0CTRL */\r
+#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */\r
+#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */\r
+#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */\r
+#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */\r
+#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */\r
+#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */\r
+#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */\r
+#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */\r
+#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */\r
+#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */\r
+#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */\r
+#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */\r
+#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */\r
+#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */\r
+#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */\r
+#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */\r
+#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */\r
+#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */\r
+#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */\r
+\r
+/** @} End of group EFM32PG1B_EMU */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_fpueh.h\r
+ * @brief EFM32PG1B_FPUEH register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_FPUEH\r
+ * @{\r
+ * @brief EFM32PG1B_FPUEH Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+} FPUEH_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_FPUEH_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for FPUEH IF */\r
+#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */\r
+#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */\r
+#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */\r
+#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */\r
+#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */\r
+#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */\r
+#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */\r
+#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */\r
+#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */\r
+#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */\r
+#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */\r
+#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */\r
+#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */\r
+#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */\r
+#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */\r
+#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */\r
+#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */\r
+#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */\r
+#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */\r
+#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */\r
+#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */\r
+#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */\r
+\r
+/* Bit fields for FPUEH IFS */\r
+#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */\r
+#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */\r
+#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */\r
+#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */\r
+#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */\r
+#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */\r
+#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */\r
+#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */\r
+#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */\r
+#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */\r
+#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */\r
+#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */\r
+#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */\r
+#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */\r
+#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */\r
+#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */\r
+#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */\r
+#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */\r
+#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */\r
+#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */\r
+#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */\r
+#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */\r
+\r
+/* Bit fields for FPUEH IFC */\r
+#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */\r
+#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */\r
+#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */\r
+#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */\r
+#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */\r
+#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */\r
+#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */\r
+#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */\r
+#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */\r
+#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */\r
+#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */\r
+#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */\r
+#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */\r
+#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */\r
+#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */\r
+#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */\r
+#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */\r
+#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */\r
+#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */\r
+#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */\r
+#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */\r
+#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */\r
+\r
+/* Bit fields for FPUEH IEN */\r
+#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */\r
+#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */\r
+#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */\r
+#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */\r
+#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */\r
+#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */\r
+#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */\r
+#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */\r
+#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */\r
+#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */\r
+#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */\r
+#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */\r
+#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */\r
+#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */\r
+#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */\r
+#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */\r
+#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */\r
+#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */\r
+#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */\r
+#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */\r
+#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */\r
+#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
+\r
+/** @} End of group EFM32PG1B_FPUEH */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_gpcrc.h\r
+ * @brief EFM32PG1B_GPCRC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_GPCRC\r
+ * @{\r
+ * @brief EFM32PG1B_GPCRC Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __IO uint32_t INIT; /**< CRC Init Value */\r
+ __IO uint32_t POLY; /**< CRC Polynomial Value */\r
+ __IO uint32_t INPUTDATA; /**< Input 32-bit Data Register */\r
+ __IO uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */\r
+ __IO uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */\r
+ __I uint32_t DATA; /**< CRC Data Register */\r
+ __I uint32_t DATAREV; /**< CRC Data Reverse Register */\r
+ __I uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */\r
+} GPCRC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_GPCRC_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for GPCRC CTRL */\r
+#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */\r
+#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */\r
+#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */\r
+#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */\r
+#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */\r
+#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */\r
+#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */\r
+#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */\r
+#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */\r
+#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */\r
+#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */\r
+#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */\r
+#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */\r
+#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */\r
+#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */\r
+#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */\r
+#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */\r
+#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */\r
+#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */\r
+#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */\r
+#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */\r
+#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */\r
+#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */\r
+#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */\r
+#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */\r
+#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */\r
+#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */\r
+#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */\r
+#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */\r
+\r
+/* Bit fields for GPCRC CMD */\r
+#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */\r
+#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */\r
+#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */\r
+#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */\r
+#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */\r
+#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */\r
+#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */\r
+\r
+/* Bit fields for GPCRC INIT */\r
+#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */\r
+#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */\r
+#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */\r
+#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */\r
+#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */\r
+#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */\r
+\r
+/* Bit fields for GPCRC POLY */\r
+#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */\r
+#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */\r
+#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */\r
+#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */\r
+#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */\r
+#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */\r
+\r
+/* Bit fields for GPCRC INPUTDATA */\r
+#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */\r
+#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */\r
+#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */\r
+#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */\r
+#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */\r
+#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */\r
+\r
+/* Bit fields for GPCRC INPUTDATAHWORD */\r
+#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */\r
+#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */\r
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */\r
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */\r
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */\r
+#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */\r
+\r
+/* Bit fields for GPCRC INPUTDATABYTE */\r
+#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */\r
+#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */\r
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */\r
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */\r
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */\r
+#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */\r
+\r
+/* Bit fields for GPCRC DATA */\r
+#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */\r
+#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */\r
+#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */\r
+#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */\r
+#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */\r
+#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */\r
+\r
+/* Bit fields for GPCRC DATAREV */\r
+#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */\r
+#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */\r
+#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */\r
+#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */\r
+#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */\r
+#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */\r
+\r
+/* Bit fields for GPCRC DATABYTEREV */\r
+#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */\r
+#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */\r
+#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */\r
+#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */\r
+#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */\r
+#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */\r
+\r
+/** @} End of group EFM32PG1B_GPCRC */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_gpio.h\r
+ * @brief EFM32PG1B_GPIO register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_GPIO\r
+ * @{\r
+ * @brief EFM32PG1B_GPIO Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ GPIO_P_TypeDef P[12]; /**< Port configuration bits */\r
+\r
+ uint32_t RESERVED0[112]; /**< Reserved for future use **/\r
+ __IO uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */\r
+ __IO uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */\r
+ __IO uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */\r
+ __IO uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */\r
+ __IO uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */\r
+ __IO uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */\r
+ __IO uint32_t EXTILEVEL; /**< External Interrupt Level Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t EM4WUEN; /**< EM4 wake up Enable Register */\r
+\r
+ uint32_t RESERVED1[4]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+\r
+ uint32_t RESERVED2[2]; /**< Reserved for future use **/\r
+ __IO uint32_t INSENSE; /**< Input Sense Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+} GPIO_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_GPIO_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for GPIO P_CTRL */\r
+#define _GPIO_P_CTRL_RESETVALUE 0x00600060UL /**< Default value for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */\r
+#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */\r
+#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000006UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */\r
+#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */\r
+#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */\r
+#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */\r
+#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */\r
+#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000006UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */\r
+#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */\r
+#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */\r
+#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+\r
+/* Bit fields for GPIO P_MODEL */\r
+#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */\r
+#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */\r
+#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */\r
+#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */\r
+#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */\r
+#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */\r
+#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */\r
+#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */\r
+#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */\r
+#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */\r
+#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */\r
+#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */\r
+#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */\r
+#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */\r
+#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */\r
+#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */\r
+#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */\r
+\r
+/* Bit fields for GPIO P_MODEH */\r
+#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */\r
+#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */\r
+#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */\r
+#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */\r
+#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */\r
+#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */\r
+#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */\r
+#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */\r
+#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */\r
+#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */\r
+#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */\r
+#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */\r
+#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */\r
+#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */\r
+#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */\r
+#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */\r
+#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */\r
+\r
+/* Bit fields for GPIO P_DOUT */\r
+#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */\r
+#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */\r
+#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */\r
+#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */\r
+#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */\r
+#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */\r
+\r
+/* Bit fields for GPIO P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */\r
+#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */\r
+\r
+/* Bit fields for GPIO P_DIN */\r
+#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */\r
+#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */\r
+#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */\r
+#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */\r
+#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */\r
+#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */\r
+\r
+/* Bit fields for GPIO P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */\r
+#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */\r
+\r
+/* Bit fields for GPIO P_OVTDIS */\r
+#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */\r
+#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */\r
+#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */\r
+#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */\r
+#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */\r
+#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */\r
+\r
+/* Bit fields for GPIO EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+\r
+/* Bit fields for GPIO EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+\r
+/* Bit fields for GPIO EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */\r
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */\r
+\r
+/* Bit fields for GPIO EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */\r
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */\r
+\r
+/* Bit fields for GPIO EXTIRISE */\r
+#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */\r
+#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */\r
+\r
+/* Bit fields for GPIO EXTIFALL */\r
+#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */\r
+#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */\r
+\r
+/* Bit fields for GPIO EXTILEVEL */\r
+#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */\r
+#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */\r
+#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */\r
+#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */\r
+#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */\r
+#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */\r
+#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */\r
+#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */\r
+#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */\r
+#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */\r
+#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */\r
+#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */\r
+#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */\r
+#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */\r
+#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */\r
+#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */\r
+#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */\r
+#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */\r
+#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */\r
+#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */\r
+#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */\r
+\r
+/* Bit fields for GPIO IF */\r
+#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */\r
+#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */\r
+#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */\r
+#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */\r
+#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */\r
+#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */\r
+#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */\r
+#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */\r
+\r
+/* Bit fields for GPIO IFS */\r
+#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */\r
+#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */\r
+#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */\r
+#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */\r
+#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */\r
+#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */\r
+#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */\r
+#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */\r
+\r
+/* Bit fields for GPIO IFC */\r
+#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */\r
+#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */\r
+#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */\r
+#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */\r
+#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */\r
+#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */\r
+#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */\r
+#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */\r
+\r
+/* Bit fields for GPIO IEN */\r
+#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */\r
+#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */\r
+#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */\r
+#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */\r
+#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */\r
+#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */\r
+#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */\r
+#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */\r
+\r
+/* Bit fields for GPIO EM4WUEN */\r
+#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */\r
+#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */\r
+#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */\r
+#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */\r
+#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */\r
+#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */\r
+\r
+/* Bit fields for GPIO ROUTEPEN */\r
+#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */\r
+#define _GPIO_ROUTEPEN_MASK 0x0000001FUL /**< Mask for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */\r
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */\r
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */\r
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */\r
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */\r
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */\r
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */\r
+#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */\r
+#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */\r
+#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */\r
+#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */\r
+#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */\r
+#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */\r
+#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */\r
+#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */\r
+#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */\r
+#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */\r
+\r
+/* Bit fields for GPIO ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */\r
+#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */\r
+#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */\r
+#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */\r
+#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */\r
+#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */\r
+#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */\r
+#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */\r
+#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */\r
+\r
+/* Bit fields for GPIO INSENSE */\r
+#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */\r
+#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */\r
+#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */\r
+#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */\r
+#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */\r
+#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */\r
+#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */\r
+#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */\r
+#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */\r
+#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */\r
+#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */\r
+#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */\r
+\r
+/* Bit fields for GPIO LOCK */\r
+#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */\r
+#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */\r
+#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */\r
+#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */\r
+\r
+/** @} End of group EFM32PG1B_GPIO */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_gpio_p.h\r
+ * @brief EFM32PG1B_GPIO_P register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief GPIO_P EFM32PG1B GPIO P\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Port Control Register */\r
+ __IO uint32_t MODEL; /**< Port Pin Mode Low Register */\r
+ __IO uint32_t MODEH; /**< Port Pin Mode High Register */\r
+ __IO uint32_t DOUT; /**< Port Data Out Register */\r
+ uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
+ __IO uint32_t DOUTTGL; /**< Port Data Out Toggle Register */\r
+ __I uint32_t DIN; /**< Port Data In Register */\r
+ __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t OVTDIS; /**< Over Voltage Disable for all modes */\r
+ uint32_t RESERVED2[1]; /**< Reserved future */\r
+} GPIO_P_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_i2c.h\r
+ * @brief EFM32PG1B_I2C register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_I2C\r
+ * @{\r
+ * @brief EFM32PG1B_I2C Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATE; /**< State Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t CLKDIV; /**< Clock Division Register */\r
+ __IO uint32_t SADDR; /**< Slave Address Register */\r
+ __IO uint32_t SADDRMASK; /**< Slave Address Mask Register */\r
+ __I uint32_t RXDATA; /**< Receive Buffer Data Register */\r
+ __I uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */\r
+ __I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */\r
+ __I uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */\r
+ __IO uint32_t TXDATA; /**< Transmit Buffer Data Register */\r
+ __IO uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+} I2C_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_I2C_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for I2C CTRL */\r
+#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */\r
+#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */\r
+#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */\r
+#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */\r
+#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */\r
+#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */\r
+#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */\r
+#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */\r
+#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */\r
+#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */\r
+#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */\r
+#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */\r
+#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */\r
+#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */\r
+#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */\r
+#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */\r
+#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */\r
+#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */\r
+#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */\r
+#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */\r
+#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */\r
+#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */\r
+#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */\r
+#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */\r
+#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */\r
+#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */\r
+#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */\r
+#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */\r
+#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */\r
+#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */\r
+#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */\r
+#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */\r
+#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */\r
+#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */\r
+#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */\r
+#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */\r
+#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */\r
+#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */\r
+#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */\r
+#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */\r
+#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */\r
+#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */\r
+#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */\r
+#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */\r
+\r
+/* Bit fields for I2C CMD */\r
+#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */\r
+#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */\r
+#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */\r
+#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */\r
+#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */\r
+#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */\r
+#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */\r
+#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */\r
+#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */\r
+#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */\r
+#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */\r
+#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */\r
+#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */\r
+#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */\r
+#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */\r
+#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */\r
+#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */\r
+#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */\r
+#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */\r
+#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */\r
+#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */\r
+#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */\r
+#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */\r
+#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */\r
+#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */\r
+\r
+/* Bit fields for I2C STATE */\r
+#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */\r
+#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */\r
+#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */\r
+#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */\r
+#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */\r
+#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */\r
+#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */\r
+#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */\r
+#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */\r
+#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */\r
+#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */\r
+#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */\r
+#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */\r
+#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */\r
+#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */\r
+#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */\r
+#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */\r
+#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */\r
+#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */\r
+#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */\r
+#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */\r
+#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */\r
+#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */\r
+#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */\r
+#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */\r
+#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */\r
+#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */\r
+#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */\r
+#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */\r
+#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */\r
+#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */\r
+#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */\r
+\r
+/* Bit fields for I2C STATUS */\r
+#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */\r
+#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */\r
+#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */\r
+#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */\r
+#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */\r
+#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */\r
+#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */\r
+#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */\r
+#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */\r
+#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */\r
+#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */\r
+#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */\r
+#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */\r
+#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */\r
+#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */\r
+#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */\r
+#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */\r
+#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */\r
+#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */\r
+#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */\r
+#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */\r
+#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */\r
+#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */\r
+#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */\r
+#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */\r
+#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */\r
+#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */\r
+#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */\r
+#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */\r
+#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */\r
+#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */\r
+#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+\r
+/* Bit fields for I2C CLKDIV */\r
+#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */\r
+#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */\r
+#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */\r
+#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */\r
+#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */\r
+#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */\r
+\r
+/* Bit fields for I2C SADDR */\r
+#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */\r
+#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */\r
+#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */\r
+#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */\r
+#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */\r
+#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */\r
+\r
+/* Bit fields for I2C SADDRMASK */\r
+#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */\r
+#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */\r
+#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */\r
+#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */\r
+#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */\r
+#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */\r
+\r
+/* Bit fields for I2C RXDATA */\r
+#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */\r
+#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */\r
+#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */\r
+#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */\r
+#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */\r
+#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */\r
+\r
+/* Bit fields for I2C RXDOUBLE */\r
+#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */\r
+#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */\r
+#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */\r
+#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */\r
+#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */\r
+#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */\r
+#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */\r
+#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */\r
+#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */\r
+#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */\r
+\r
+/* Bit fields for I2C RXDATAP */\r
+#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */\r
+#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */\r
+\r
+/* Bit fields for I2C RXDOUBLEP */\r
+#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */\r
+#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */\r
+#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */\r
+#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */\r
+#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */\r
+#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */\r
+#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */\r
+#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */\r
+#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */\r
+#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */\r
+\r
+/* Bit fields for I2C TXDATA */\r
+#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */\r
+#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */\r
+#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */\r
+#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */\r
+#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */\r
+#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */\r
+\r
+/* Bit fields for I2C TXDOUBLE */\r
+#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */\r
+#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */\r
+#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */\r
+#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */\r
+#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */\r
+#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */\r
+#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */\r
+#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */\r
+#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */\r
+#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */\r
+\r
+/* Bit fields for I2C IF */\r
+#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */\r
+#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */\r
+#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */\r
+#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */\r
+#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */\r
+#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */\r
+#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */\r
+#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */\r
+#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */\r
+#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */\r
+#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */\r
+#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */\r
+#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */\r
+#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */\r
+#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */\r
+#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */\r
+#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */\r
+#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */\r
+#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */\r
+#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */\r
+#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */\r
+#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */\r
+#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */\r
+#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */\r
+#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */\r
+#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */\r
+#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */\r
+#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */\r
+#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */\r
+\r
+/* Bit fields for I2C IFS */\r
+#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */\r
+#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */\r
+#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */\r
+#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */\r
+#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */\r
+#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */\r
+#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */\r
+#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */\r
+#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */\r
+#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */\r
+#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */\r
+#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */\r
+#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */\r
+#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */\r
+#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */\r
+#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */\r
+#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */\r
+#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */\r
+#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */\r
+#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */\r
+#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */\r
+#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */\r
+#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */\r
+#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */\r
+\r
+/* Bit fields for I2C IFC */\r
+#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */\r
+#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */\r
+#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */\r
+#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */\r
+#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */\r
+#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */\r
+#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */\r
+#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */\r
+#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */\r
+#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */\r
+#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */\r
+#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */\r
+#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */\r
+#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */\r
+#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */\r
+#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */\r
+#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */\r
+#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */\r
+#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */\r
+#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */\r
+#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */\r
+#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */\r
+#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */\r
+#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */\r
+\r
+/* Bit fields for I2C IEN */\r
+#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */\r
+#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */\r
+#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */\r
+#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */\r
+#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */\r
+#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */\r
+#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */\r
+#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */\r
+#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */\r
+#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */\r
+#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */\r
+#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */\r
+#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */\r
+#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */\r
+#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */\r
+#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */\r
+#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */\r
+#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */\r
+#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */\r
+#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */\r
+#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */\r
+#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */\r
+#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */\r
+#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */\r
+#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */\r
+#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */\r
+#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */\r
+#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */\r
+#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */\r
+\r
+/* Bit fields for I2C ROUTEPEN */\r
+#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */\r
+#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */\r
+#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */\r
+#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */\r
+#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */\r
+#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */\r
+#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */\r
+#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */\r
+#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */\r
+#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */\r
+#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */\r
+#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */\r
+\r
+/* Bit fields for I2C ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */\r
+#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */\r
+#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */\r
+#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */\r
+#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */\r
+\r
+/** @} End of group EFM32PG1B_I2C */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_idac.h\r
+ * @brief EFM32PG1B_IDAC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_IDAC\r
+ * @{\r
+ * @brief EFM32PG1B_IDAC Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CURPROG; /**< Current Programming Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */\r
+\r
+ uint32_t RESERVED1[2]; /**< Reserved for future use **/\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
+ __I uint32_t APORTREQ; /**< APORT Request Status Register */\r
+ __I uint32_t APORTCONFLICT; /**< APORT Request Status Register */\r
+} IDAC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_IDAC_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for IDAC CTRL */\r
+#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */\r
+#define _IDAC_CTRL_MASK 0x00F17FFFUL /**< Mask for IDAC_CTRL */\r
+#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */\r
+#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */\r
+#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */\r
+#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */\r
+#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */\r
+#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */\r
+#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */\r
+#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */\r
+#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */\r
+#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_OUTEN (0x1UL << 3) /**< Output Enable */\r
+#define _IDAC_CTRL_OUTEN_SHIFT 3 /**< Shift value for IDAC_OUTEN */\r
+#define _IDAC_CTRL_OUTEN_MASK 0x8UL /**< Bit mask for IDAC_OUTEN */\r
+#define _IDAC_CTRL_OUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_OUTEN_DEFAULT (_IDAC_CTRL_OUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */\r
+#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */\r
+#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */\r
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */\r
+#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */\r
+#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */\r
+#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */\r
+#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */\r
+#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */\r
+#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */\r
+#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */\r
+#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */\r
+#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */\r
+#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */\r
+#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */\r
+#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */\r
+#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */\r
+#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_OUTENPRS (0x1UL << 16) /**< PRS Controlled Output Enable */\r
+#define _IDAC_CTRL_OUTENPRS_SHIFT 16 /**< Shift value for IDAC_OUTENPRS */\r
+#define _IDAC_CTRL_OUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_OUTENPRS */\r
+#define _IDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_OUTENPRS_DEFAULT (_IDAC_CTRL_OUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */\r
+#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */\r
+#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */\r
+#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */\r
+#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */\r
+\r
+/* Bit fields for IDAC CURPROG */\r
+#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */\r
+#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */\r
+#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */\r
+#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */\r
+#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */\r
+#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */\r
+#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */\r
+#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */\r
+#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */\r
+#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */\r
+#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */\r
+#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */\r
+#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */\r
+#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */\r
+#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */\r
+\r
+/* Bit fields for IDAC DUTYCONFIG */\r
+#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */\r
+#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */\r
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */\r
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */\r
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */\r
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */\r
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */\r
+\r
+/* Bit fields for IDAC STATUS */\r
+#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */\r
+#define _IDAC_STATUS_MASK 0x00000002UL /**< Mask for IDAC_STATUS */\r
+#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */\r
+#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */\r
+#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */\r
+#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */\r
+#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */\r
+\r
+/* Bit fields for IDAC IF */\r
+#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */\r
+#define _IDAC_IF_MASK 0x00000002UL /**< Mask for IDAC_IF */\r
+#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */\r
+#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */\r
+#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */\r
+#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */\r
+#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */\r
+\r
+/* Bit fields for IDAC IFS */\r
+#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */\r
+#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */\r
+#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */\r
+#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */\r
+#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */\r
+#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */\r
+#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */\r
+#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */\r
+#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */\r
+#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */\r
+#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */\r
+#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */\r
+\r
+/* Bit fields for IDAC IFC */\r
+#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */\r
+#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */\r
+#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */\r
+#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */\r
+#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */\r
+#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */\r
+#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */\r
+#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */\r
+#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */\r
+#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */\r
+#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */\r
+#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */\r
+\r
+/* Bit fields for IDAC IEN */\r
+#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */\r
+#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */\r
+#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */\r
+#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */\r
+#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */\r
+#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */\r
+#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */\r
+#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */\r
+#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */\r
+#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */\r
+#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */\r
+#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */\r
+\r
+/* Bit fields for IDAC APORTREQ */\r
+#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */\r
+#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */\r
+#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */\r
+#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */\r
+#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */\r
+#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */\r
+#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */\r
+#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */\r
+#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */\r
+#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */\r
+#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */\r
+#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */\r
+\r
+/* Bit fields for IDAC APORTCONFLICT */\r
+#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */\r
+#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */\r
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */\r
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */\r
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */\r
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */\r
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */\r
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */\r
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */\r
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */\r
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */\r
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */\r
+\r
+/** @} End of group EFM32PG1B_IDAC */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_ldma.h\r
+ * @brief EFM32PG1B_LDMA register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_LDMA\r
+ * @{\r
+ * @brief EFM32PG1B_LDMA Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< DMA Control Register */\r
+ __I uint32_t STATUS; /**< DMA Status Register */\r
+ __IO uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */\r
+ uint32_t RESERVED0[5]; /**< Reserved for future use **/\r
+ __IO uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */\r
+ __I uint32_t CHBUSY; /**< DMA Channel Busy Register */\r
+ __IO uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */\r
+ __IO uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */\r
+ __IO uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */\r
+ __IO uint32_t REQDIS; /**< DMA Channel Request Disable Register */\r
+ __I uint32_t REQPEND; /**< DMA Channel Requests Pending Register */\r
+ __IO uint32_t LINKLOAD; /**< DMA Channel Link Load Register */\r
+ __IO uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */\r
+ uint32_t RESERVED1[7]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable register */\r
+\r
+ uint32_t RESERVED2[4]; /**< Reserved registers */\r
+ LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */\r
+} LDMA_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_LDMA_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for LDMA CTRL */\r
+#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */\r
+#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */\r
+#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */\r
+#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */\r
+#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */\r
+#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */\r
+#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */\r
+#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */\r
+#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */\r
+#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */\r
+#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */\r
+#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */\r
+#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */\r
+#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */\r
+\r
+/* Bit fields for LDMA STATUS */\r
+#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */\r
+#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */\r
+#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */\r
+#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */\r
+#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */\r
+#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */\r
+#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */\r
+#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */\r
+#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */\r
+#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */\r
+#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */\r
+#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */\r
+#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */\r
+#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */\r
+#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */\r
+#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */\r
+#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */\r
+#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */\r
+#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */\r
+#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */\r
+#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */\r
+#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */\r
+\r
+/* Bit fields for LDMA SYNC */\r
+#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */\r
+#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */\r
+#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */\r
+#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */\r
+#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */\r
+#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */\r
+\r
+/* Bit fields for LDMA CHEN */\r
+#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */\r
+#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */\r
+#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */\r
+#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */\r
+#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */\r
+#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */\r
+\r
+/* Bit fields for LDMA CHBUSY */\r
+#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */\r
+#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */\r
+#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */\r
+#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */\r
+#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */\r
+#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */\r
+\r
+/* Bit fields for LDMA CHDONE */\r
+#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */\r
+#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */\r
+#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */\r
+#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */\r
+#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */\r
+#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */\r
+\r
+/* Bit fields for LDMA DBGHALT */\r
+#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */\r
+#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */\r
+#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */\r
+#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */\r
+#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */\r
+#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */\r
+\r
+/* Bit fields for LDMA SWREQ */\r
+#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */\r
+#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */\r
+#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */\r
+#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */\r
+#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */\r
+#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */\r
+\r
+/* Bit fields for LDMA REQDIS */\r
+#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */\r
+#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */\r
+#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */\r
+#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */\r
+#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */\r
+#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */\r
+\r
+/* Bit fields for LDMA REQPEND */\r
+#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */\r
+#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */\r
+#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */\r
+#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */\r
+#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */\r
+#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */\r
+\r
+/* Bit fields for LDMA LINKLOAD */\r
+#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */\r
+#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */\r
+#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */\r
+#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */\r
+#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */\r
+#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */\r
+\r
+/* Bit fields for LDMA REQCLEAR */\r
+#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */\r
+#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */\r
+#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */\r
+#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */\r
+#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */\r
+#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */\r
+\r
+/* Bit fields for LDMA IF */\r
+#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */\r
+#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */\r
+#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */\r
+#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */\r
+#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */\r
+#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */\r
+#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */\r
+#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */\r
+#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */\r
+#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */\r
+#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */\r
+\r
+/* Bit fields for LDMA IFS */\r
+#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */\r
+#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */\r
+#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */\r
+#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */\r
+#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */\r
+#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */\r
+#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */\r
+#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */\r
+#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */\r
+#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */\r
+#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */\r
+\r
+/* Bit fields for LDMA IFC */\r
+#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */\r
+#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */\r
+#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */\r
+#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */\r
+#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */\r
+#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */\r
+#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */\r
+#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */\r
+#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */\r
+#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */\r
+#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */\r
+\r
+/* Bit fields for LDMA IEN */\r
+#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */\r
+#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */\r
+#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */\r
+#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */\r
+#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */\r
+#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */\r
+#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */\r
+#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */\r
+#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */\r
+#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */\r
+#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */\r
+\r
+/* Bit fields for LDMA CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR 0x00000000UL /**< Mode CRYPTODATA0WR for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR 0x00000001UL /**< Mode CRYPTODATA0XWR for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD 0x00000002UL /**< Mode CRYPTODATA0RD for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR 0x00000003UL /**< Mode CRYPTODATA1WR for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD 0x00000004UL /**< Mode CRYPTODATA1RD for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR << 0) /**< Shifted mode CRYPTODATA0WR for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR << 0) /**< Shifted mode CRYPTODATA0XWR for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD << 0) /**< Shifted mode CRYPTODATA0RD for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR << 0) /**< Shifted mode CRYPTODATA1WR for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD << 0) /**< Shifted mode CRYPTODATA1RD for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */\r
+#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO 0x00000031UL /**< Mode CRYPTO for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */\r
+#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO << 16) /**< Shifted mode CRYPTO for LDMA_CH_REQSEL */\r
+\r
+/* Bit fields for LDMA CH_CFG */\r
+#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */\r
+#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */\r
+#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */\r
+#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */\r
+#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */\r
+#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */\r
+#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */\r
+#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */\r
+#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */\r
+#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */\r
+#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */\r
+\r
+/* Bit fields for LDMA CH_LOOP */\r
+#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */\r
+#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */\r
+#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */\r
+#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */\r
+#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */\r
+#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */\r
+\r
+/* Bit fields for LDMA CH_CTRL */\r
+#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */\r
+#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */\r
+#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */\r
+#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */\r
+#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */\r
+#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */\r
+#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */\r
+#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */\r
+#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */\r
+#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */\r
+#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */\r
+#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */\r
+#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */\r
+#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */\r
+#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */\r
+#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */\r
+#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */\r
+#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */\r
+#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */\r
+#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */\r
+#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */\r
+#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */\r
+#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */\r
+#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */\r
+#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */\r
+#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */\r
+#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */\r
+#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */\r
+#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */\r
+#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */\r
+#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */\r
+#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */\r
+#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */\r
+#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */\r
+#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */\r
+#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */\r
+#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */\r
+\r
+/* Bit fields for LDMA CH_SRC */\r
+#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */\r
+#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */\r
+#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */\r
+#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */\r
+#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */\r
+#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */\r
+\r
+/* Bit fields for LDMA CH_DST */\r
+#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */\r
+#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */\r
+#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */\r
+#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */\r
+#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */\r
+#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */\r
+\r
+/* Bit fields for LDMA CH_LINK */\r
+#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */\r
+#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */\r
+#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */\r
+#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */\r
+#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */\r
+#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */\r
+#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */\r
+#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */\r
+#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */\r
+#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */\r
+#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */\r
+#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */\r
+#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */\r
+#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */\r
+\r
+/** @} End of group EFM32PG1B_LDMA */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_ldma_ch.h\r
+ * @brief EFM32PG1B_LDMA_CH register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief LDMA_CH EFM32PG1B LDMA CH\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t REQSEL; /**< Channel Peripheral Request Select Register */\r
+ __IO uint32_t CFG; /**< Channel Configuration Register */\r
+ __IO uint32_t LOOP; /**< Channel Loop Counter Register */\r
+ __IO uint32_t CTRL; /**< Channel Descriptor Control Word Register */\r
+ __IO uint32_t SRC; /**< Channel Descriptor Source Data Address Register */\r
+ __IO uint32_t DST; /**< Channel Descriptor Destination Data Address Register */\r
+ __IO uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */\r
+ uint32_t RESERVED0[5]; /**< Reserved future */\r
+} LDMA_CH_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_letimer.h\r
+ * @brief EFM32PG1B_LETIMER register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_LETIMER\r
+ * @{\r
+ * @brief EFM32PG1B_LETIMER Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t CNT; /**< Counter Value Register */\r
+ __IO uint32_t COMP0; /**< Compare Value Register 0 */\r
+ __IO uint32_t COMP1; /**< Compare Value Register 1 */\r
+ __IO uint32_t REP0; /**< Repeat Counter Register 0 */\r
+ __IO uint32_t REP1; /**< Repeat Counter Register 1 */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+\r
+ uint32_t RESERVED1[2]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+\r
+ uint32_t RESERVED2[2]; /**< Reserved for future use **/\r
+ __IO uint32_t PRSSEL; /**< PRS Input Select Register */\r
+} LETIMER_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_LETIMER_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for LETIMER CTRL */\r
+#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */\r
+#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */\r
+#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */\r
+#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */\r
+#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */\r
+#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */\r
+#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */\r
+#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */\r
+#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */\r
+#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */\r
+#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */\r
+#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */\r
+#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */\r
+#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */\r
+#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */\r
+#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */\r
+#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */\r
+#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */\r
+#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */\r
+#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */\r
+#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */\r
+#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */\r
+#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+\r
+/* Bit fields for LETIMER CMD */\r
+#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */\r
+#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */\r
+#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */\r
+#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */\r
+#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */\r
+#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */\r
+#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */\r
+#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */\r
+#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */\r
+#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */\r
+#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */\r
+#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */\r
+#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */\r
+#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */\r
+#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */\r
+#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */\r
+#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */\r
+#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+\r
+/* Bit fields for LETIMER STATUS */\r
+#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */\r
+#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */\r
+#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */\r
+#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */\r
+#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */\r
+#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */\r
+#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */\r
+\r
+/* Bit fields for LETIMER CNT */\r
+#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */\r
+#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */\r
+#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */\r
+#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */\r
+#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */\r
+#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */\r
+\r
+/* Bit fields for LETIMER COMP0 */\r
+#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */\r
+#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */\r
+\r
+/* Bit fields for LETIMER COMP1 */\r
+#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */\r
+#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */\r
+\r
+/* Bit fields for LETIMER REP0 */\r
+#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */\r
+#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */\r
+#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */\r
+#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */\r
+#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */\r
+\r
+/* Bit fields for LETIMER REP1 */\r
+#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */\r
+#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */\r
+#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */\r
+#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */\r
+#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */\r
+\r
+/* Bit fields for LETIMER IF */\r
+#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */\r
+#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */\r
+#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */\r
+#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */\r
+#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */\r
+#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */\r
+#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */\r
+#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+\r
+/* Bit fields for LETIMER IFS */\r
+#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */\r
+#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */\r
+#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */\r
+#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */\r
+#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */\r
+#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */\r
+#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */\r
+#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+\r
+/* Bit fields for LETIMER IFC */\r
+#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */\r
+#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */\r
+#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */\r
+#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */\r
+#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */\r
+#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */\r
+#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */\r
+#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+\r
+/* Bit fields for LETIMER IEN */\r
+#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */\r
+#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */\r
+#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */\r
+#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */\r
+#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */\r
+#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */\r
+#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */\r
+#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+\r
+/* Bit fields for LETIMER SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */\r
+#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */\r
+#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */\r
+#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+\r
+/* Bit fields for LETIMER ROUTEPEN */\r
+#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */\r
+#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */\r
+#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */\r
+#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */\r
+#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */\r
+#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */\r
+#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */\r
+#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */\r
+#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */\r
+#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */\r
+#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */\r
+#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */\r
+\r
+/* Bit fields for LETIMER ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */\r
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */\r
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */\r
+\r
+/* Bit fields for LETIMER PRSSEL */\r
+#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */\r
+#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */\r
+#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */\r
+\r
+/** @} End of group EFM32PG1B_LETIMER */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_leuart.h\r
+ * @brief EFM32PG1B_LEUART register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_LEUART\r
+ * @{\r
+ * @brief EFM32PG1B_LEUART Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t CLKDIV; /**< Clock Control Register */\r
+ __IO uint32_t STARTFRAME; /**< Start Frame Register */\r
+ __IO uint32_t SIGFRAME; /**< Signal Frame Register */\r
+ __I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */\r
+ __I uint32_t RXDATA; /**< Receive Buffer Data Register */\r
+ __I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */\r
+ __IO uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */\r
+ __IO uint32_t TXDATA; /**< Transmit Buffer Data Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t PULSECTRL; /**< Pulse Control Register */\r
+\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+\r
+ uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+ uint32_t RESERVED1[2]; /**< Reserved for future use **/\r
+ __IO uint32_t INPUT; /**< LEUART Input Register */\r
+} LEUART_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_LEUART_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for LEUART CTRL */\r
+#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */\r
+#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */\r
+#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */\r
+#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */\r
+#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */\r
+#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */\r
+#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */\r
+#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */\r
+#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */\r
+#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */\r
+#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */\r
+#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */\r
+#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */\r
+#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */\r
+#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */\r
+#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */\r
+#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */\r
+#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */\r
+#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */\r
+#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */\r
+#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */\r
+#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */\r
+#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */\r
+#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */\r
+#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */\r
+#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */\r
+#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */\r
+#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */\r
+#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */\r
+#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */\r
+#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */\r
+#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */\r
+#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */\r
+#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */\r
+#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */\r
+#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */\r
+#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */\r
+#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */\r
+#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */\r
+#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */\r
+#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */\r
+#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */\r
+#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */\r
+#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */\r
+#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */\r
+#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */\r
+\r
+/* Bit fields for LEUART CMD */\r
+#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */\r
+#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */\r
+#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */\r
+#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */\r
+#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */\r
+#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */\r
+#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */\r
+#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */\r
+#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */\r
+#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */\r
+#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */\r
+#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */\r
+#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */\r
+#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */\r
+#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */\r
+#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */\r
+#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */\r
+#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */\r
+#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */\r
+#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */\r
+#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */\r
+#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */\r
+#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */\r
+#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */\r
+#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */\r
+#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */\r
+#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+\r
+/* Bit fields for LEUART STATUS */\r
+#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */\r
+#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */\r
+#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */\r
+#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */\r
+#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */\r
+#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */\r
+#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */\r
+#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */\r
+#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */\r
+#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */\r
+#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */\r
+#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */\r
+#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */\r
+#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */\r
+#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */\r
+#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */\r
+#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */\r
+#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */\r
+#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */\r
+#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */\r
+#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */\r
+#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */\r
+#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+\r
+/* Bit fields for LEUART CLKDIV */\r
+#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */\r
+#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */\r
+#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */\r
+#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */\r
+#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */\r
+#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */\r
+\r
+/* Bit fields for LEUART STARTFRAME */\r
+#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */\r
+#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */\r
+\r
+/* Bit fields for LEUART SIGFRAME */\r
+#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */\r
+#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */\r
+\r
+/* Bit fields for LEUART RXDATAX */\r
+#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */\r
+#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */\r
+#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */\r
+#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */\r
+#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */\r
+#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */\r
+#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */\r
+\r
+/* Bit fields for LEUART RXDATA */\r
+#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */\r
+#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */\r
+\r
+/* Bit fields for LEUART RXDATAXP */\r
+#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */\r
+#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */\r
+#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */\r
+#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */\r
+#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */\r
+#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */\r
+#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */\r
+#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */\r
+#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */\r
+\r
+/* Bit fields for LEUART TXDATAX */\r
+#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */\r
+#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */\r
+#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */\r
+#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */\r
+#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */\r
+#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */\r
+#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */\r
+#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */\r
+#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */\r
+#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */\r
+#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */\r
+#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+\r
+/* Bit fields for LEUART TXDATA */\r
+#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */\r
+#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */\r
+\r
+/* Bit fields for LEUART IF */\r
+#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */\r
+#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */\r
+#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */\r
+#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */\r
+#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */\r
+#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */\r
+#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */\r
+#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */\r
+#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */\r
+#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */\r
+#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */\r
+#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */\r
+#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */\r
+#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */\r
+#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */\r
+#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */\r
+#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */\r
+#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */\r
+\r
+/* Bit fields for LEUART IFS */\r
+#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */\r
+#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */\r
+#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */\r
+#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */\r
+#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */\r
+#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */\r
+#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */\r
+#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */\r
+#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */\r
+#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */\r
+#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */\r
+#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+\r
+/* Bit fields for LEUART IFC */\r
+#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */\r
+#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */\r
+#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */\r
+#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */\r
+#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */\r
+#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */\r
+#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */\r
+#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */\r
+#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */\r
+#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */\r
+#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */\r
+#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+\r
+/* Bit fields for LEUART IEN */\r
+#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */\r
+#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */\r
+#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */\r
+#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */\r
+#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */\r
+#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */\r
+#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */\r
+#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */\r
+#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */\r
+#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */\r
+#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */\r
+#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */\r
+#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */\r
+#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */\r
+#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */\r
+#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */\r
+#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */\r
+#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+\r
+/* Bit fields for LEUART PULSECTRL */\r
+#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */\r
+#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */\r
+#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */\r
+#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */\r
+#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */\r
+#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */\r
+#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */\r
+#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */\r
+#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */\r
+\r
+/* Bit fields for LEUART FREEZE */\r
+#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
+#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */\r
+\r
+/* Bit fields for LEUART SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */\r
+#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */\r
+#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */\r
+#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */\r
+#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */\r
+#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */\r
+#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */\r
+#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */\r
+#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */\r
+#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */\r
+#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */\r
+#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */\r
+#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */\r
+#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */\r
+#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */\r
+#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */\r
+#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */\r
+#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */\r
+#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */\r
+#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */\r
+#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */\r
+#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */\r
+#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */\r
+#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */\r
+#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+\r
+/* Bit fields for LEUART ROUTEPEN */\r
+#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */\r
+#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */\r
+#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */\r
+#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */\r
+#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */\r
+#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */\r
+#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */\r
+#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */\r
+#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */\r
+#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */\r
+#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */\r
+#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */\r
+\r
+/* Bit fields for LEUART ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */\r
+#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */\r
+#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */\r
+#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */\r
+#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */\r
+\r
+/* Bit fields for LEUART INPUT */\r
+#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */\r
+#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */\r
+#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */\r
+#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */\r
+#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */\r
+#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */\r
+#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */\r
+#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */\r
+#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */\r
+\r
+/** @} End of group EFM32PG1B_LEUART */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_msc.h\r
+ * @brief EFM32PG1B_MSC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_MSC\r
+ * @{\r
+ * @brief EFM32PG1B_MSC Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Memory System Control Register */\r
+ __IO uint32_t READCTRL; /**< Read Control Register */\r
+ __IO uint32_t WRITECTRL; /**< Write Control Register */\r
+ __IO uint32_t WRITECMD; /**< Write Command Register */\r
+ __IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t WDATA; /**< Write Data Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+\r
+ uint32_t RESERVED1[4]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+ __IO uint32_t CACHECMD; /**< Flash Cache Command Register */\r
+ __I uint32_t CACHEHITS; /**< Cache Hits Performance Counter */\r
+ __I uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */\r
+\r
+ uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
+ __IO uint32_t MASSLOCK; /**< Mass Erase Lock Register */\r
+ uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
+ __IO uint32_t STARTUP; /**< Startup Control */\r
+\r
+ uint32_t RESERVED4[5]; /**< Reserved for future use **/\r
+ __IO uint32_t CMD; /**< Command Register */\r
+} MSC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_MSC_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for MSC CTRL */\r
+#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */\r
+#define _MSC_CTRL_MASK 0x0000000FUL /**< Mask for MSC_CTRL */\r
+#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */\r
+#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */\r
+#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */\r
+#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */\r
+#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */\r
+#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */\r
+#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */\r
+#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */\r
+#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */\r
+#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */\r
+#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */\r
+#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */\r
+#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */\r
+\r
+/* Bit fields for MSC READCTRL */\r
+#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */\r
+#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */\r
+#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */\r
+#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */\r
+#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */\r
+#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */\r
+#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */\r
+#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */\r
+#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */\r
+#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */\r
+#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */\r
+#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */\r
+#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */\r
+#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */\r
+#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */\r
+#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */\r
+#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */\r
+#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */\r
+#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */\r
+#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */\r
+#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */\r
+#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */\r
+#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */\r
+#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+\r
+/* Bit fields for MSC WRITECTRL */\r
+#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */\r
+#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */\r
+#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */\r
+#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */\r
+#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */\r
+#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */\r
+#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */\r
+#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */\r
+#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */\r
+#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */\r
+#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */\r
+#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */\r
+\r
+/* Bit fields for MSC WRITECMD */\r
+#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */\r
+#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */\r
+#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */\r
+#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */\r
+#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */\r
+#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */\r
+#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */\r
+#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */\r
+#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */\r
+#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */\r
+#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */\r
+#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */\r
+#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */\r
+#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */\r
+#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */\r
+#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */\r
+#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */\r
+#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */\r
+#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */\r
+#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */\r
+#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */\r
+#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */\r
+#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */\r
+#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */\r
+#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */\r
+#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+\r
+/* Bit fields for MSC ADDRB */\r
+#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */\r
+#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */\r
+#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */\r
+#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */\r
+#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */\r
+#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */\r
+\r
+/* Bit fields for MSC WDATA */\r
+#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */\r
+#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */\r
+#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */\r
+#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */\r
+#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */\r
+#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */\r
+\r
+/* Bit fields for MSC STATUS */\r
+#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */\r
+#define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */\r
+#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */\r
+#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */\r
+#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */\r
+#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */\r
+#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */\r
+#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */\r
+#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */\r
+#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */\r
+#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */\r
+#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */\r
+#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */\r
+#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */\r
+#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */\r
+#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */\r
+#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */\r
+#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */\r
+#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */\r
+#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */\r
+#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */\r
+#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */\r
+#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */\r
+#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+\r
+/* Bit fields for MSC IF */\r
+#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */\r
+#define _MSC_IF_MASK 0x0000003FUL /**< Mask for MSC_IF */\r
+#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */\r
+#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */\r
+#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */\r
+#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */\r
+#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */\r
+#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */\r
+#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */\r
+#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */\r
+#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */\r
+#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */\r
+#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */\r
+#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */\r
+#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */\r
+#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */\r
+#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */\r
+\r
+/* Bit fields for MSC IFS */\r
+#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */\r
+#define _MSC_IFS_MASK 0x0000003FUL /**< Mask for MSC_IFS */\r
+#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */\r
+#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */\r
+#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */\r
+#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */\r
+#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */\r
+#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */\r
+#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */\r
+#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */\r
+#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */\r
+#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */\r
+#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */\r
+#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */\r
+#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */\r
+#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */\r
+#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */\r
+\r
+/* Bit fields for MSC IFC */\r
+#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */\r
+#define _MSC_IFC_MASK 0x0000003FUL /**< Mask for MSC_IFC */\r
+#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */\r
+#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */\r
+#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */\r
+#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */\r
+#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */\r
+#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */\r
+#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */\r
+#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */\r
+#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */\r
+#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */\r
+#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */\r
+#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */\r
+#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */\r
+#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */\r
+#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */\r
+\r
+/* Bit fields for MSC IEN */\r
+#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */\r
+#define _MSC_IEN_MASK 0x0000003FUL /**< Mask for MSC_IEN */\r
+#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */\r
+#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */\r
+#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */\r
+#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */\r
+#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */\r
+#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */\r
+#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */\r
+#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */\r
+#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */\r
+#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */\r
+#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */\r
+#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */\r
+#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */\r
+#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */\r
+#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */\r
+\r
+/* Bit fields for MSC LOCK */\r
+#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */\r
+#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */\r
+#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */\r
+#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */\r
+\r
+/* Bit fields for MSC CACHECMD */\r
+#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */\r
+#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */\r
+#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */\r
+#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */\r
+#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */\r
+#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */\r
+#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */\r
+#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */\r
+#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */\r
+#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */\r
+#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */\r
+#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */\r
+#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */\r
+#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */\r
+#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */\r
+#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */\r
+#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */\r
+\r
+/* Bit fields for MSC CACHEHITS */\r
+#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */\r
+#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */\r
+#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */\r
+#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */\r
+#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */\r
+#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */\r
+\r
+/* Bit fields for MSC CACHEMISSES */\r
+#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */\r
+#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */\r
+#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */\r
+#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */\r
+#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */\r
+#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */\r
+\r
+/* Bit fields for MSC MASSLOCK */\r
+#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */\r
+#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */\r
+#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */\r
+#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */\r
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */\r
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */\r
+#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */\r
+#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */\r
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */\r
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */\r
+#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */\r
+#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */\r
+#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */\r
+#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */\r
+\r
+/* Bit fields for MSC STARTUP */\r
+#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */\r
+#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */\r
+#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */\r
+#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */\r
+#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */\r
+#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */\r
+#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */\r
+#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */\r
+#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */\r
+#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */\r
+#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */\r
+#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */\r
+#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */\r
+#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */\r
+#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */\r
+#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */\r
+#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */\r
+#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */\r
+#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */\r
+#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */\r
+#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */\r
+\r
+/* Bit fields for MSC CMD */\r
+#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */\r
+#define _MSC_CMD_MASK 0x00000001UL /**< Mask for MSC_CMD */\r
+#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */\r
+#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */\r
+#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */\r
+#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */\r
+#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */\r
+\r
+/** @} End of group EFM32PG1B_MSC */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_pcnt.h\r
+ * @brief EFM32PG1B_PCNT register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_PCNT\r
+ * @{\r
+ * @brief EFM32PG1B_PCNT Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t CNT; /**< Counter Value Register */\r
+ __I uint32_t TOP; /**< Top Value Register */\r
+ __IO uint32_t TOPB; /**< Top Value Buffer Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+\r
+ uint32_t RESERVED1[4]; /**< Reserved for future use **/\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+\r
+ uint32_t RESERVED2[7]; /**< Reserved for future use **/\r
+ __I uint32_t AUXCNT; /**< Auxiliary Counter Value Register */\r
+ __IO uint32_t INPUT; /**< PCNT Input Register */\r
+ __IO uint32_t OVSCFG; /**< Oversampling Config Register */\r
+} PCNT_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_PCNT_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for PCNT CTRL */\r
+#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */\r
+#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */\r
+#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */\r
+#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */\r
+#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */\r
+#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */\r
+#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */\r
+#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */\r
+#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */\r
+#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */\r
+#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */\r
+#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */\r
+#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */\r
+#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */\r
+#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */\r
+#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */\r
+#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */\r
+#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */\r
+#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */\r
+#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */\r
+#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */\r
+#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */\r
+#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */\r
+#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */\r
+#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */\r
+#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */\r
+#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */\r
+#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */\r
+#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */\r
+#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */\r
+#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */\r
+#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */\r
+#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */\r
+#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */\r
+#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */\r
+#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */\r
+#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */\r
+#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */\r
+#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */\r
+#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */\r
+#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */\r
+#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */\r
+#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */\r
+#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */\r
+#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */\r
+#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */\r
+#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */\r
+#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */\r
+#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */\r
+#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */\r
+#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */\r
+#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */\r
+#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */\r
+#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */\r
+#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */\r
+#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */\r
+#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */\r
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */\r
+#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */\r
+#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */\r
+#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */\r
+#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */\r
+#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+\r
+/* Bit fields for PCNT CMD */\r
+#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */\r
+#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */\r
+#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */\r
+#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */\r
+#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */\r
+#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */\r
+#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */\r
+#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */\r
+#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */\r
+#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */\r
+#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */\r
+#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */\r
+\r
+/* Bit fields for PCNT STATUS */\r
+#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */\r
+#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */\r
+#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */\r
+#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */\r
+#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */\r
+#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */\r
+#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */\r
+\r
+/* Bit fields for PCNT CNT */\r
+#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */\r
+#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */\r
+#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */\r
+#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */\r
+#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */\r
+#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */\r
+\r
+/* Bit fields for PCNT TOP */\r
+#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */\r
+#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */\r
+#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */\r
+#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */\r
+#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */\r
+#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */\r
+\r
+/* Bit fields for PCNT TOPB */\r
+#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */\r
+#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */\r
+#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */\r
+#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */\r
+#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */\r
+#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */\r
+\r
+/* Bit fields for PCNT IF */\r
+#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */\r
+#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */\r
+#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */\r
+#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */\r
+#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */\r
+#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_AUXOF (0x1UL << 3) /**< Overflow Interrupt Read Flag */\r
+#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */\r
+#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */\r
+#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */\r
+#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */\r
+#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */\r
+#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */\r
+#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */\r
+#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */\r
+#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */\r
+\r
+/* Bit fields for PCNT IFS */\r
+#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */\r
+#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */\r
+#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */\r
+#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */\r
+#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */\r
+#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */\r
+#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */\r
+#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */\r
+#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */\r
+#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */\r
+#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */\r
+#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */\r
+#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */\r
+#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */\r
+#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+\r
+/* Bit fields for PCNT IFC */\r
+#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */\r
+#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */\r
+#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */\r
+#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */\r
+#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */\r
+#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */\r
+#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */\r
+#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */\r
+#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */\r
+#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */\r
+#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */\r
+#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */\r
+#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */\r
+#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */\r
+#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+\r
+/* Bit fields for PCNT IEN */\r
+#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */\r
+#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */\r
+#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */\r
+#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */\r
+#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */\r
+#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */\r
+#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */\r
+#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */\r
+#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */\r
+#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */\r
+#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */\r
+#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */\r
+#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */\r
+#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */\r
+#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+\r
+/* Bit fields for PCNT ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */\r
+#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */\r
+#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */\r
+#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */\r
+#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */\r
+\r
+/* Bit fields for PCNT FREEZE */\r
+#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
+#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */\r
+\r
+/* Bit fields for PCNT SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */\r
+#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */\r
+#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */\r
+#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */\r
+#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */\r
+#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */\r
+#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */\r
+#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */\r
+#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */\r
+#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */\r
+#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */\r
+#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */\r
+#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+\r
+/* Bit fields for PCNT AUXCNT */\r
+#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */\r
+#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */\r
+#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */\r
+#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */\r
+#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */\r
+#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */\r
+\r
+/* Bit fields for PCNT INPUT */\r
+#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */\r
+#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */\r
+#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */\r
+#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */\r
+#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */\r
+#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */\r
+#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */\r
+#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */\r
+#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */\r
+#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */\r
+#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */\r
+#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */\r
+#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */\r
+#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */\r
+#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */\r
+\r
+/* Bit fields for PCNT OVSCFG */\r
+#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */\r
+#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */\r
+#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */\r
+#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */\r
+#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */\r
+#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */\r
+#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */\r
+#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */\r
+#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */\r
+#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */\r
+#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */\r
+\r
+/** @} End of group EFM32PG1B_PCNT */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_prs.h\r
+ * @brief EFM32PG1B_PRS register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_PRS\r
+ * @{\r
+ * @brief EFM32PG1B_PRS Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
+ __IO uint32_t SWLEVEL; /**< Software Level Register */\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+ __IO uint32_t ROUTELOC1; /**< I/O Routing Location Register */\r
+ __IO uint32_t ROUTELOC2; /**< I/O Routing Location Register */\r
+\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t DMAREQ0; /**< DMA Request 0 Register */\r
+ __IO uint32_t DMAREQ1; /**< DMA Request 1 Register */\r
+ uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
+ __I uint32_t PEEK; /**< PRS Channel Values */\r
+\r
+ uint32_t RESERVED3[3]; /**< Reserved registers */\r
+ PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
+} PRS_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_PRS_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for PRS SWPULSE */\r
+#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
+#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
+#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
+#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
+#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
+#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
+#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
+#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
+#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
+#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
+#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
+#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
+#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
+#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
+#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
+#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
+#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
+#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
+#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
+#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
+#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
+#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
+#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
+#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
+#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
+#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
+#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
+#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
+#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
+#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
+#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
+#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
+#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
+#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
+#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
+#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
+#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
+#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+\r
+/* Bit fields for PRS SWLEVEL */\r
+#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
+#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
+#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
+#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
+#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
+#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
+#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
+#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
+#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
+#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
+#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
+#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
+#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
+#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
+#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
+#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
+#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
+#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
+#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
+#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
+#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
+#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
+#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
+#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
+#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
+#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
+#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
+#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
+#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
+#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
+#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
+#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
+#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
+#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
+#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
+#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
+#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
+#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+\r
+/* Bit fields for PRS ROUTEPEN */\r
+#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */\r
+#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
+#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
+#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
+#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
+#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
+#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
+#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
+#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
+#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */\r
+#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */\r
+#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */\r
+#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */\r
+#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */\r
+#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */\r
+#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */\r
+#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */\r
+#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */\r
+#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */\r
+#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */\r
+#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */\r
+#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */\r
+#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */\r
+#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */\r
+#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */\r
+#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */\r
+#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */\r
+#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */\r
+\r
+/* Bit fields for PRS ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */\r
+#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */\r
+#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */\r
+#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */\r
+#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */\r
+#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */\r
+#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */\r
+\r
+/* Bit fields for PRS ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */\r
+#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */\r
+#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */\r
+#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */\r
+#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */\r
+#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */\r
+#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */\r
+\r
+/* Bit fields for PRS ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */\r
+#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */\r
+#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */\r
+#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */\r
+#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */\r
+#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */\r
+#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */\r
+#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */\r
+#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */\r
+\r
+/* Bit fields for PRS CTRL */\r
+#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */\r
+#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */\r
+#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */\r
+#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */\r
+#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */\r
+#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */\r
+#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */\r
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */\r
+#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */\r
+\r
+/* Bit fields for PRS DMAREQ0 */\r
+#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */\r
+#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */\r
+#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */\r
+#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */\r
+#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */\r
+\r
+/* Bit fields for PRS DMAREQ1 */\r
+#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */\r
+#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */\r
+#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */\r
+#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */\r
+#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */\r
+\r
+/* Bit fields for PRS PEEK */\r
+#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */\r
+#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */\r
+#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */\r
+#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */\r
+#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */\r
+#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */\r
+#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */\r
+#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */\r
+#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */\r
+#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */\r
+#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */\r
+#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */\r
+#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */\r
+#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */\r
+#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */\r
+#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */\r
+#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */\r
+#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */\r
+#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */\r
+#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */\r
+#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */\r
+#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */\r
+#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */\r
+#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */\r
+#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */\r
+#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */\r
+#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */\r
+#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */\r
+#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */\r
+#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */\r
+#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */\r
+#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */\r
+#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */\r
+#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */\r
+#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */\r
+#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */\r
+#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */\r
+#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */\r
+#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */\r
+#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */\r
+\r
+/* Bit fields for PRS CH_CTRL */\r
+#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
+#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */\r
+#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */\r
+#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000006UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000007UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000029UL /**< Mode RTCC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000003CUL /**< Mode CRYOTIMER for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_CMU 0x0000003DUL /**< Mode CMU for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */\r
+#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */\r
+#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */\r
+#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */\r
+#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */\r
+#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */\r
+#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */\r
+#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */\r
+#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */\r
+#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */\r
+#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */\r
+#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */\r
+#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */\r
+#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */\r
+#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */\r
+#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */\r
+#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */\r
+#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+\r
+/** @} End of group EFM32PG1B_PRS */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_prs_ch.h\r
+ * @brief EFM32PG1B_PRS_CH register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief PRS_CH EFM32PG1B PRS CH\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Channel Control Register */\r
+} PRS_CH_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_prs_signals.h\r
+ * @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @addtogroup EFM32PG1B_PRS_Signals\r
+ * @{\r
+ * @brief PRS Signal names\r
+ *****************************************************************************/\r
+#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */\r
+#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */\r
+#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */\r
+#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */\r
+#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */\r
+#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */\r
+#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */\r
+#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */\r
+#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */\r
+#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */\r
+#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */\r
+#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */\r
+#define PRS_ACMP0_OUT ((6 << 8) + 0) /**< PRS Analog comparator output */\r
+#define PRS_ACMP1_OUT ((7 << 8) + 0) /**< PRS Analog comparator output */\r
+#define PRS_ADC0_SINGLE ((8 << 8) + 0) /**< PRS ADC single conversion done */\r
+#define PRS_ADC0_SCAN ((8 << 8) + 1) /**< PRS ADC scan conversion done */\r
+#define PRS_USART0_IRTX ((16 << 8) + 0) /**< PRS USART 0 IRDA out */\r
+#define PRS_USART0_TXC ((16 << 8) + 1) /**< PRS USART 0 TX complete */\r
+#define PRS_USART0_RXDATAV ((16 << 8) + 2) /**< PRS USART 0 RX Data Valid */\r
+#define PRS_USART0_RTS ((16 << 8) + 3) /**< PRS USART 0 RTS */\r
+#define PRS_USART0_TX ((16 << 8) + 5) /**< PRS USART 0 TX */\r
+#define PRS_USART0_CS ((16 << 8) + 6) /**< PRS USART 0 CS */\r
+#define PRS_USART1_TXC ((17 << 8) + 1) /**< PRS USART 1 TX complete */\r
+#define PRS_USART1_RXDATAV ((17 << 8) + 2) /**< PRS USART 1 RX Data Valid */\r
+#define PRS_USART1_RTS ((17 << 8) + 3) /**< PRS USART 0 RTS */\r
+#define PRS_USART1_TX ((17 << 8) + 5) /**< PRS USART 1 TX */\r
+#define PRS_USART1_CS ((17 << 8) + 6) /**< PRS USART 1 CS */\r
+#define PRS_TIMER0_UF ((28 << 8) + 0) /**< PRS Timer 0 Underflow */\r
+#define PRS_TIMER0_OF ((28 << 8) + 1) /**< PRS Timer 0 Overflow */\r
+#define PRS_TIMER0_CC0 ((28 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
+#define PRS_TIMER0_CC1 ((28 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
+#define PRS_TIMER0_CC2 ((28 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
+#define PRS_TIMER1_UF ((29 << 8) + 0) /**< PRS Timer 1 Underflow */\r
+#define PRS_TIMER1_OF ((29 << 8) + 1) /**< PRS Timer 1 Overflow */\r
+#define PRS_TIMER1_CC0 ((29 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
+#define PRS_TIMER1_CC1 ((29 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
+#define PRS_TIMER1_CC2 ((29 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
+#define PRS_TIMER1_CC3 ((29 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */\r
+#define PRS_RTCC_CCV0 ((41 << 8) + 1) /**< PRS RTCC Compare 0 */\r
+#define PRS_RTCC_CCV1 ((41 << 8) + 2) /**< PRS RTCC Compare 1 */\r
+#define PRS_RTCC_CCV2 ((41 << 8) + 3) /**< PRS RTCC Compare 2 */\r
+#define PRS_GPIO_PIN0 ((48 << 8) + 0) /**< PRS GPIO pin 0 */\r
+#define PRS_GPIO_PIN1 ((48 << 8) + 1) /**< PRS GPIO pin 1 */\r
+#define PRS_GPIO_PIN2 ((48 << 8) + 2) /**< PRS GPIO pin 2 */\r
+#define PRS_GPIO_PIN3 ((48 << 8) + 3) /**< PRS GPIO pin 3 */\r
+#define PRS_GPIO_PIN4 ((48 << 8) + 4) /**< PRS GPIO pin 4 */\r
+#define PRS_GPIO_PIN5 ((48 << 8) + 5) /**< PRS GPIO pin 5 */\r
+#define PRS_GPIO_PIN6 ((48 << 8) + 6) /**< PRS GPIO pin 6 */\r
+#define PRS_GPIO_PIN7 ((48 << 8) + 7) /**< PRS GPIO pin 7 */\r
+#define PRS_GPIO_PIN8 ((49 << 8) + 0) /**< PRS GPIO pin 8 */\r
+#define PRS_GPIO_PIN9 ((49 << 8) + 1) /**< PRS GPIO pin 9 */\r
+#define PRS_GPIO_PIN10 ((49 << 8) + 2) /**< PRS GPIO pin 10 */\r
+#define PRS_GPIO_PIN11 ((49 << 8) + 3) /**< PRS GPIO pin 11 */\r
+#define PRS_GPIO_PIN12 ((49 << 8) + 4) /**< PRS GPIO pin 12 */\r
+#define PRS_GPIO_PIN13 ((49 << 8) + 5) /**< PRS GPIO pin 13 */\r
+#define PRS_GPIO_PIN14 ((49 << 8) + 6) /**< PRS GPIO pin 14 */\r
+#define PRS_GPIO_PIN15 ((49 << 8) + 7) /**< PRS GPIO pin 15 */\r
+#define PRS_LETIMER0_CH0 ((52 << 8) + 0) /**< PRS LETIMER CH0 Out */\r
+#define PRS_LETIMER0_CH1 ((52 << 8) + 1) /**< PRS LETIMER CH1 Out */\r
+#define PRS_PCNT0_TCC ((54 << 8) + 0) /**< PRS Triggered compare match */\r
+#define PRS_PCNT0_UFOF ((54 << 8) + 1) /**< PRS Counter overflow or underflow */\r
+#define PRS_PCNT0_DIR ((54 << 8) + 2) /**< PRS Counter direction */\r
+#define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */\r
+#define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */\r
+#define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */\r
+\r
+/** @} End of group EFM32PG1B_PRS */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_rmu.h\r
+ * @brief EFM32PG1B_RMU register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_RMU\r
+ * @{\r
+ * @brief EFM32PG1B_RMU Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __I uint32_t RSTCAUSE; /**< Reset Cause Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __IO uint32_t RST; /**< Reset Control Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+} RMU_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_RMU_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for RMU CTRL */\r
+#define _RMU_CTRL_RESETVALUE 0x00004224UL /**< Default value for RMU_CTRL */\r
+#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */\r
+#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */\r
+#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */\r
+#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */\r
+#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */\r
+#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */\r
+#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */\r
+#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */\r
+#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */\r
+#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */\r
+#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */\r
+#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */\r
+#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */\r
+#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */\r
+#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */\r
+#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */\r
+#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */\r
+#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */\r
+#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */\r
+#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */\r
+#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */\r
+#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */\r
+#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */\r
+#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */\r
+#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */\r
+#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */\r
+#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */\r
+#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */\r
+#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */\r
+#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */\r
+#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */\r
+#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */\r
+#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */\r
+#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */\r
+#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */\r
+#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */\r
+#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */\r
+#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */\r
+#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */\r
+#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */\r
+#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */\r
+#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */\r
+#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */\r
+#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */\r
+#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */\r
+#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */\r
+#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */\r
+#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */\r
+#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */\r
+#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */\r
+#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */\r
+#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */\r
+#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */\r
+\r
+/* Bit fields for RMU RSTCAUSE */\r
+#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */\r
+#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */\r
+#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */\r
+#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */\r
+#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */\r
+#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */\r
+#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */\r
+#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */\r
+#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */\r
+#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */\r
+#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */\r
+#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */\r
+#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */\r
+#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */\r
+#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */\r
+#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */\r
+#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */\r
+#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */\r
+#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */\r
+#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */\r
+#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */\r
+#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */\r
+#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */\r
+#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */\r
+#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */\r
+#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */\r
+#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */\r
+#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+\r
+/* Bit fields for RMU CMD */\r
+#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */\r
+#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */\r
+#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */\r
+#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */\r
+#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */\r
+#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */\r
+#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */\r
+\r
+/* Bit fields for RMU RST */\r
+#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */\r
+#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */\r
+\r
+/* Bit fields for RMU LOCK */\r
+#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */\r
+#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */\r
+#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */\r
+#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */\r
+#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */\r
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */\r
+#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */\r
+#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */\r
+#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */\r
+#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */\r
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */\r
+#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */\r
+#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */\r
+#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */\r
+\r
+/** @} End of group EFM32PG1B_RMU */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_romtable.h\r
+ * @brief EFM32PG1B_ROMTABLE register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_ROMTABLE\r
+ * @{\r
+ * @brief Chip Information, Revision numbers\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __I uint32_t PID4; /**< JEP_106_BANK */\r
+ __I uint32_t PID5; /**< Unused */\r
+ __I uint32_t PID6; /**< Unused */\r
+ __I uint32_t PID7; /**< Unused */\r
+ __I uint32_t PID0; /**< Chip family LSB, chip major revision */\r
+ __I uint32_t PID1; /**< JEP_106_NO, Chip family MSB */\r
+ __I uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */\r
+ __I uint32_t PID3; /**< Chip minor rev LSB */\r
+ __I uint32_t CID0; /**< Unused */\r
+} ROMTABLE_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_ROMTABLE_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+/* Bit fields for EFM32PG1B_ROMTABLE */\r
+#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */\r
+#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */\r
+#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */\r
+#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */\r
+#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */\r
+#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */\r
+#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */\r
+#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */\r
+#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */\r
+#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */\r
+\r
+/** @} End of group EFM32PG1B_ROMTABLE */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_rtcc.h\r
+ * @brief EFM32PG1B_RTCC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_RTCC\r
+ * @{\r
+ * @brief EFM32PG1B_RTCC Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t PRECNT; /**< Pre-Counter Value Register */\r
+ __IO uint32_t CNT; /**< Counter Value Register */\r
+ __I uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */\r
+ __IO uint32_t TIME; /**< Time of day register */\r
+ __IO uint32_t DATE; /**< Date register */\r
+ __I uint32_t IF; /**< RTCC Interrupt Flags */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t STATUS; /**< Status register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+ __IO uint32_t POWERDOWN; /**< Retention RAM power-down register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+ __IO uint32_t EM4WUEN; /**< Wake Up Enable */\r
+\r
+ RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */\r
+\r
+ uint32_t RESERVED0[37]; /**< Reserved registers */\r
+ RTCC_RET_TypeDef RET[32]; /**< RetentionReg */\r
+} RTCC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_RTCC_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for RTCC CTRL */\r
+#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */\r
+#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */\r
+#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */\r
+#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */\r
+#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */\r
+#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */\r
+#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */\r
+#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */\r
+#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */\r
+#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */\r
+#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */\r
+#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */\r
+#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */\r
+#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */\r
+#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */\r
+#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */\r
+#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */\r
+#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */\r
+#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */\r
+#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */\r
+#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */\r
+#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */\r
+#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */\r
+#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */\r
+#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */\r
+#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */\r
+#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */\r
+#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */\r
+#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */\r
+#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */\r
+#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */\r
+#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */\r
+#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */\r
+#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */\r
+\r
+/* Bit fields for RTCC PRECNT */\r
+#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */\r
+#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */\r
+#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */\r
+#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */\r
+#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */\r
+#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */\r
+\r
+/* Bit fields for RTCC CNT */\r
+#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */\r
+#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */\r
+#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */\r
+#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */\r
+#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */\r
+#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */\r
+\r
+/* Bit fields for RTCC COMBCNT */\r
+#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */\r
+#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */\r
+#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */\r
+#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */\r
+#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */\r
+#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */\r
+#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */\r
+#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */\r
+#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */\r
+#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */\r
+\r
+/* Bit fields for RTCC TIME */\r
+#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */\r
+#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */\r
+#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */\r
+#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */\r
+#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */\r
+#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */\r
+#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */\r
+#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */\r
+#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */\r
+#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */\r
+#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */\r
+#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */\r
+#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */\r
+#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */\r
+#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */\r
+#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */\r
+#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */\r
+#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */\r
+#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */\r
+#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */\r
+#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */\r
+#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */\r
+#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */\r
+#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */\r
+#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */\r
+#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */\r
+\r
+/* Bit fields for RTCC DATE */\r
+#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */\r
+#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */\r
+#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */\r
+#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */\r
+#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */\r
+#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */\r
+#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */\r
+#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */\r
+#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */\r
+#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */\r
+#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */\r
+#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */\r
+#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */\r
+#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */\r
+#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */\r
+#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */\r
+#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */\r
+#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */\r
+#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */\r
+\r
+/* Bit fields for RTCC IF */\r
+#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */\r
+#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */\r
+#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */\r
+#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */\r
+#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */\r
+#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */\r
+#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */\r
+#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */\r
+#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */\r
+#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */\r
+#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */\r
+#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */\r
+#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */\r
+#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */\r
+#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */\r
+#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */\r
+#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */\r
+#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */\r
+#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */\r
+#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */\r
+#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */\r
+#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */\r
+#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */\r
+#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */\r
+#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */\r
+#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */\r
+#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */\r
+#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */\r
+#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */\r
+#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */\r
+#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */\r
+#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */\r
+#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */\r
+#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */\r
+#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */\r
+#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */\r
+#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */\r
+\r
+/* Bit fields for RTCC IFS */\r
+#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */\r
+#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */\r
+#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */\r
+#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */\r
+#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */\r
+#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */\r
+#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */\r
+#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */\r
+#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */\r
+#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */\r
+#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */\r
+#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */\r
+#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */\r
+#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */\r
+#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */\r
+#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */\r
+#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */\r
+#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */\r
+#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */\r
+#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */\r
+#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */\r
+#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */\r
+#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */\r
+#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */\r
+#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */\r
+#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */\r
+#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */\r
+#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */\r
+#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */\r
+#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */\r
+#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */\r
+#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */\r
+#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */\r
+#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */\r
+#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */\r
+#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */\r
+#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */\r
+\r
+/* Bit fields for RTCC IFC */\r
+#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */\r
+#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */\r
+#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */\r
+#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */\r
+#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */\r
+#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */\r
+#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */\r
+#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */\r
+#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */\r
+#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */\r
+#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */\r
+#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */\r
+#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */\r
+#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */\r
+#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */\r
+#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */\r
+#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */\r
+#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */\r
+#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */\r
+#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */\r
+#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */\r
+#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */\r
+#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */\r
+#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */\r
+#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */\r
+#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */\r
+#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */\r
+#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */\r
+#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */\r
+#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */\r
+#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */\r
+#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */\r
+#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */\r
+#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */\r
+#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */\r
+#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */\r
+#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */\r
+\r
+/* Bit fields for RTCC IEN */\r
+#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */\r
+#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */\r
+#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */\r
+#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */\r
+#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */\r
+#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */\r
+#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */\r
+#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */\r
+#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */\r
+#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */\r
+#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */\r
+#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */\r
+#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */\r
+#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */\r
+#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */\r
+#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */\r
+#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */\r
+#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */\r
+#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */\r
+#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */\r
+#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */\r
+#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */\r
+#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */\r
+#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */\r
+#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */\r
+#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */\r
+#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */\r
+#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */\r
+#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */\r
+#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */\r
+#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */\r
+#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */\r
+#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */\r
+#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */\r
+#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */\r
+#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */\r
+#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */\r
+\r
+/* Bit fields for RTCC STATUS */\r
+#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */\r
+#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */\r
+\r
+/* Bit fields for RTCC CMD */\r
+#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */\r
+#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */\r
+#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */\r
+#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */\r
+#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */\r
+#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */\r
+#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */\r
+\r
+/* Bit fields for RTCC SYNCBUSY */\r
+#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */\r
+#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */\r
+#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */\r
+#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */\r
+#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */\r
+#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */\r
+#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */\r
+\r
+/* Bit fields for RTCC POWERDOWN */\r
+#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */\r
+#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */\r
+#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */\r
+#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */\r
+#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */\r
+#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */\r
+#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */\r
+\r
+/* Bit fields for RTCC LOCK */\r
+#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */\r
+#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */\r
+#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */\r
+#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */\r
+#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */\r
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */\r
+#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */\r
+#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */\r
+#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */\r
+#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */\r
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */\r
+#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */\r
+#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */\r
+#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */\r
+\r
+/* Bit fields for RTCC EM4WUEN */\r
+#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */\r
+#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */\r
+#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */\r
+#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */\r
+#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */\r
+#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */\r
+#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */\r
+\r
+/* Bit fields for RTCC CC_CTRL */\r
+#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */\r
+#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */\r
+#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */\r
+#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */\r
+#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */\r
+#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */\r
+#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */\r
+#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */\r
+#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */\r
+#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */\r
+#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */\r
+#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */\r
+#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */\r
+#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */\r
+#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */\r
+#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */\r
+#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */\r
+#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */\r
+#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */\r
+\r
+/* Bit fields for RTCC CC_CCV */\r
+#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */\r
+#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */\r
+#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */\r
+#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */\r
+#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */\r
+#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */\r
+\r
+/* Bit fields for RTCC CC_TIME */\r
+#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */\r
+#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */\r
+#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */\r
+#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */\r
+#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */\r
+#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */\r
+#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */\r
+#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */\r
+#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */\r
+#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */\r
+#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */\r
+#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */\r
+#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */\r
+#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */\r
+#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */\r
+#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */\r
+#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */\r
+#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */\r
+#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */\r
+#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */\r
+\r
+/* Bit fields for RTCC CC_DATE */\r
+#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */\r
+#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */\r
+#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */\r
+#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */\r
+#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */\r
+#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */\r
+#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */\r
+#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */\r
+#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */\r
+#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */\r
+#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */\r
+#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */\r
+#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */\r
+#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */\r
+#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */\r
+#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */\r
+#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */\r
+#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */\r
+#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */\r
+\r
+/* Bit fields for RTCC RET_REG */\r
+#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */\r
+#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */\r
+#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */\r
+#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */\r
+#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */\r
+#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */\r
+\r
+/** @} End of group EFM32PG1B_RTCC */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_rtcc_cc.h\r
+ * @brief EFM32PG1B_RTCC_CC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief RTCC_CC EFM32PG1B RTCC CC\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< CC Channel Control Register */\r
+ __IO uint32_t CCV; /**< Capture/Compare Value Register */\r
+ __IO uint32_t TIME; /**< Capture/Compare Time Register */\r
+ __IO uint32_t DATE; /**< Capture/Compare Date Register */\r
+} RTCC_CC_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_rtcc_ret.h\r
+ * @brief EFM32PG1B_RTCC_RET register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief RTCC_RET EFM32PG1B RTCC RET\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t REG; /**< Retention register */\r
+} RTCC_RET_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_timer.h\r
+ * @brief EFM32PG1B_TIMER register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_TIMER\r
+ * @{\r
+ * @brief EFM32PG1B_TIMER Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t TOP; /**< Counter Top Value Register */\r
+ __IO uint32_t TOPB; /**< Counter Top Value Buffer Register */\r
+ __IO uint32_t CNT; /**< Counter Value Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LOCK; /**< TIMER Configuration Lock Register */\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTELOC2; /**< I/O Routing Location Register */\r
+\r
+ uint32_t RESERVED2[8]; /**< Reserved registers */\r
+ TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */\r
+\r
+ __IO uint32_t DTCTRL; /**< DTI Control Register */\r
+ __IO uint32_t DTTIME; /**< DTI Time Control Register */\r
+ __IO uint32_t DTFC; /**< DTI Fault Configuration Register */\r
+ __IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */\r
+ __I uint32_t DTFAULT; /**< DTI Fault Register */\r
+ __IO uint32_t DTFAULTC; /**< DTI Fault Clear Register */\r
+ __IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */\r
+} TIMER_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_TIMER_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for TIMER CTRL */\r
+#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */\r
+#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */\r
+#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */\r
+#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */\r
+#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */\r
+#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */\r
+#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */\r
+#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */\r
+#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */\r
+#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */\r
+#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */\r
+#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */\r
+#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */\r
+#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */\r
+#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */\r
+#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */\r
+#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */\r
+#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */\r
+#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */\r
+#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */\r
+#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */\r
+#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */\r
+#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */\r
+#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */\r
+#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */\r
+#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */\r
+#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */\r
+#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */\r
+#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */\r
+#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */\r
+#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */\r
+#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */\r
+#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */\r
+#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */\r
+#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */\r
+#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */\r
+#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */\r
+#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */\r
+#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */\r
+#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */\r
+#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */\r
+#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */\r
+#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+\r
+/* Bit fields for TIMER CMD */\r
+#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */\r
+#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */\r
+#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */\r
+#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */\r
+#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */\r
+#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */\r
+#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */\r
+#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */\r
+#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */\r
+#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */\r
+#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */\r
+#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */\r
+\r
+/* Bit fields for TIMER STATUS */\r
+#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */\r
+#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */\r
+#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */\r
+#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */\r
+#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */\r
+#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */\r
+#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */\r
+#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */\r
+#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */\r
+#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */\r
+#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */\r
+#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */\r
+#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */\r
+#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */\r
+#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */\r
+#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */\r
+#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */\r
+#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */\r
+#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */\r
+#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */\r
+#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */\r
+#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */\r
+#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */\r
+#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */\r
+#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */\r
+#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */\r
+#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */\r
+#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */\r
+#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */\r
+#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */\r
+#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */\r
+#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */\r
+#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */\r
+#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */\r
+#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */\r
+#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */\r
+#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */\r
+#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */\r
+#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */\r
+#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */\r
+#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */\r
+#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+\r
+/* Bit fields for TIMER IF */\r
+#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */\r
+#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */\r
+#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */\r
+#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */\r
+#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */\r
+#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */\r
+#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */\r
+#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */\r
+#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */\r
+#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */\r
+#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */\r
+#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */\r
+#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */\r
+#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */\r
+#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */\r
+#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */\r
+\r
+/* Bit fields for TIMER IFS */\r
+#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */\r
+#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */\r
+#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */\r
+#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */\r
+#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */\r
+#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */\r
+#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */\r
+#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */\r
+#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */\r
+#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */\r
+#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */\r
+#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */\r
+#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */\r
+#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */\r
+#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */\r
+#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */\r
+#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */\r
+#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */\r
+#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */\r
+#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+\r
+/* Bit fields for TIMER IFC */\r
+#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */\r
+#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */\r
+#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */\r
+#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */\r
+#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */\r
+#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */\r
+#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */\r
+#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */\r
+#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */\r
+#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */\r
+#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */\r
+#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */\r
+#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */\r
+#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */\r
+#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */\r
+#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */\r
+#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */\r
+#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */\r
+#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */\r
+#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+\r
+/* Bit fields for TIMER IEN */\r
+#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */\r
+#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */\r
+#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */\r
+#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */\r
+#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */\r
+#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */\r
+#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */\r
+#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */\r
+#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */\r
+#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */\r
+#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */\r
+#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */\r
+#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */\r
+#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */\r
+#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */\r
+#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+\r
+/* Bit fields for TIMER TOP */\r
+#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */\r
+#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */\r
+#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */\r
+#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */\r
+#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */\r
+#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */\r
+\r
+/* Bit fields for TIMER TOPB */\r
+#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */\r
+#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */\r
+#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */\r
+#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */\r
+#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */\r
+#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */\r
+\r
+/* Bit fields for TIMER CNT */\r
+#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */\r
+#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */\r
+#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */\r
+#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */\r
+#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */\r
+#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */\r
+\r
+/* Bit fields for TIMER LOCK */\r
+#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */\r
+#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */\r
+#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */\r
+#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */\r
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */\r
+#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */\r
+#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */\r
+#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */\r
+\r
+/* Bit fields for TIMER ROUTEPEN */\r
+#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */\r
+#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */\r
+#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */\r
+#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */\r
+#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */\r
+#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */\r
+#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */\r
+#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */\r
+#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */\r
+#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */\r
+#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */\r
+#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */\r
+#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */\r
+#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */\r
+#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */\r
+#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */\r
+#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */\r
+#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */\r
+#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */\r
+#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */\r
+#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */\r
+#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */\r
+#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */\r
+#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */\r
+\r
+/* Bit fields for TIMER ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */\r
+#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */\r
+#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */\r
+#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */\r
+#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */\r
+#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */\r
+#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */\r
+\r
+/* Bit fields for TIMER ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */\r
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */\r
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */\r
+\r
+/* Bit fields for TIMER CC_CTRL */\r
+#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */\r
+#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */\r
+#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */\r
+#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */\r
+#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */\r
+#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */\r
+#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */\r
+#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */\r
+#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */\r
+#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */\r
+#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */\r
+#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */\r
+#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */\r
+#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */\r
+#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */\r
+#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */\r
+#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */\r
+#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */\r
+#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */\r
+#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */\r
+#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */\r
+#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */\r
+#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */\r
+#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */\r
+#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */\r
+#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */\r
+#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */\r
+#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */\r
+\r
+/* Bit fields for TIMER CC_CCV */\r
+#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */\r
+#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */\r
+#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */\r
+#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */\r
+#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */\r
+#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */\r
+\r
+/* Bit fields for TIMER CC_CCVP */\r
+#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */\r
+#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */\r
+#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */\r
+#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */\r
+#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */\r
+#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */\r
+\r
+/* Bit fields for TIMER CC_CCVB */\r
+#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */\r
+#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */\r
+#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */\r
+#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */\r
+#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */\r
+#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */\r
+\r
+/* Bit fields for TIMER DTCTRL */\r
+#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */\r
+#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */\r
+#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */\r
+#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */\r
+#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */\r
+#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */\r
+#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */\r
+#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */\r
+#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */\r
+#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */\r
+#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */\r
+#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */\r
+#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */\r
+#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */\r
+#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */\r
+#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */\r
+#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */\r
+#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */\r
+#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */\r
+#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */\r
+#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */\r
+#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+\r
+/* Bit fields for TIMER DTTIME */\r
+#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */\r
+#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */\r
+#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */\r
+#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */\r
+#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */\r
+#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */\r
+#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */\r
+\r
+/* Bit fields for TIMER DTFC */\r
+#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */\r
+#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */\r
+#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */\r
+#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */\r
+#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */\r
+#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */\r
+#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */\r
+#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */\r
+#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */\r
+#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */\r
+#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */\r
+#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */\r
+#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */\r
+#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */\r
+#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */\r
+#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */\r
+#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */\r
+#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */\r
+#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */\r
+#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+\r
+/* Bit fields for TIMER DTOGEN */\r
+#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */\r
+#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */\r
+#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */\r
+#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */\r
+#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */\r
+#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */\r
+#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */\r
+#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */\r
+#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */\r
+#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */\r
+#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */\r
+#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */\r
+#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */\r
+#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */\r
+#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */\r
+#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */\r
+#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */\r
+#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */\r
+#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+\r
+/* Bit fields for TIMER DTFAULT */\r
+#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */\r
+#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */\r
+#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */\r
+#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */\r
+#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */\r
+#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */\r
+#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */\r
+#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */\r
+#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */\r
+#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */\r
+#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */\r
+#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */\r
+#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */\r
+\r
+/* Bit fields for TIMER DTFAULTC */\r
+#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */\r
+#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */\r
+#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */\r
+#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */\r
+#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */\r
+#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */\r
+#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */\r
+#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */\r
+#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */\r
+#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */\r
+#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */\r
+#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */\r
+#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */\r
+\r
+/* Bit fields for TIMER DTLOCK */\r
+#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */\r
+#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */\r
+#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */\r
+\r
+/** @} End of group EFM32PG1B_TIMER */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_timer_cc.h\r
+ * @brief EFM32PG1B_TIMER_CC register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief TIMER_CC EFM32PG1B TIMER CC\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< CC Channel Control Register */\r
+ __IO uint32_t CCV; /**< CC Channel Value Register */\r
+ __I uint32_t CCVP; /**< CC Channel Value Peek Register */\r
+ __IO uint32_t CCVB; /**< CC Channel Buffer Register */\r
+} TIMER_CC_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_usart.h\r
+ * @brief EFM32PG1B_USART register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_USART\r
+ * @{\r
+ * @brief EFM32PG1B_USART Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t FRAME; /**< USART Frame Format Register */\r
+ __IO uint32_t TRIGCTRL; /**< USART Trigger Control register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< USART Status Register */\r
+ __IO uint32_t CLKDIV; /**< Clock Control Register */\r
+ __I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */\r
+ __I uint32_t RXDATA; /**< RX Buffer Data Register */\r
+ __I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */\r
+ __I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */\r
+ __I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */\r
+ __I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */\r
+ __IO uint32_t TXDATAX; /**< TX Buffer Data Extended Register */\r
+ __IO uint32_t TXDATA; /**< TX Buffer Data Register */\r
+ __IO uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */\r
+ __IO uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t IRCTRL; /**< IrDA Control Register */\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t INPUT; /**< USART Input Register */\r
+ __IO uint32_t I2SCTRL; /**< I2S Control Register */\r
+ __IO uint32_t TIMING; /**< Timing Register */\r
+ __IO uint32_t CTRLX; /**< Control Register Extended */\r
+ __IO uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */\r
+ __IO uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */\r
+ __IO uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */\r
+ __IO uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */\r
+ __IO uint32_t ROUTELOC0; /**< I/O Routing Location Register */\r
+ __IO uint32_t ROUTELOC1; /**< I/O Routing Location Register */\r
+} USART_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_USART_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for USART CTRL */\r
+#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */\r
+#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */\r
+#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */\r
+#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */\r
+#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */\r
+#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */\r
+#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */\r
+#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */\r
+#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */\r
+#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */\r
+#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */\r
+#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */\r
+#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */\r
+#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */\r
+#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */\r
+#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */\r
+#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */\r
+#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */\r
+#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */\r
+#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */\r
+#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */\r
+#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */\r
+#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */\r
+#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */\r
+#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */\r
+#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */\r
+#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */\r
+#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */\r
+#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */\r
+#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */\r
+#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */\r
+#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */\r
+#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */\r
+#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */\r
+#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */\r
+#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */\r
+#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */\r
+#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */\r
+#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */\r
+#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */\r
+#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */\r
+#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */\r
+#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */\r
+#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */\r
+#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */\r
+#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */\r
+#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */\r
+#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */\r
+#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */\r
+#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */\r
+#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */\r
+#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */\r
+#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */\r
+#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */\r
+#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */\r
+#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */\r
+#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */\r
+#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */\r
+#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */\r
+#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */\r
+#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */\r
+#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */\r
+#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */\r
+#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */\r
+#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */\r
+#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */\r
+#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */\r
+#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */\r
+#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */\r
+#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */\r
+#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */\r
+#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */\r
+#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */\r
+#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */\r
+#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */\r
+#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */\r
+#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */\r
+#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */\r
+#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */\r
+#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */\r
+#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */\r
+#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */\r
+#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */\r
+#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */\r
+#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */\r
+#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */\r
+#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */\r
+#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */\r
+#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */\r
+#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */\r
+#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */\r
+#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */\r
+#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */\r
+#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */\r
+#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */\r
+#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */\r
+#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */\r
+#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */\r
+#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */\r
+#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */\r
+#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */\r
+#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */\r
+#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */\r
+#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */\r
+#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */\r
+#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */\r
+#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */\r
+#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */\r
+#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */\r
+#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */\r
+\r
+/* Bit fields for USART FRAME */\r
+#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */\r
+#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */\r
+#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */\r
+#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */\r
+#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */\r
+#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */\r
+#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */\r
+#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */\r
+#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */\r
+#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */\r
+#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */\r
+#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */\r
+#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */\r
+#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */\r
+#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */\r
+#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */\r
+#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */\r
+#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */\r
+#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */\r
+#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */\r
+#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */\r
+#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */\r
+\r
+/* Bit fields for USART TRIGCTRL */\r
+#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */\r
+#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */\r
+#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */\r
+#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */\r
+#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */\r
+#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */\r
+#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */\r
+#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */\r
+#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */\r
+#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */\r
+#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */\r
+#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */\r
+#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */\r
+#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */\r
+#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */\r
+#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */\r
+#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */\r
+#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */\r
+#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */\r
+#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */\r
+#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */\r
+#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */\r
+#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */\r
+#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */\r
+#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */\r
+#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */\r
+#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */\r
+#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */\r
+#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */\r
+#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */\r
+\r
+/* Bit fields for USART CMD */\r
+#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */\r
+#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */\r
+#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */\r
+#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */\r
+#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */\r
+#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */\r
+#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */\r
+#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */\r
+#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */\r
+#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */\r
+#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */\r
+#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */\r
+#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */\r
+#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */\r
+#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */\r
+#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */\r
+#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */\r
+#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */\r
+#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */\r
+#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */\r
+#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */\r
+#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */\r
+#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */\r
+#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */\r
+#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */\r
+#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */\r
+#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */\r
+#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */\r
+#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */\r
+#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */\r
+#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */\r
+#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */\r
+#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */\r
+#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */\r
+#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */\r
+#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */\r
+#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */\r
+#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */\r
+#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */\r
+\r
+/* Bit fields for USART STATUS */\r
+#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */\r
+#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */\r
+#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */\r
+#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */\r
+#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */\r
+#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */\r
+#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */\r
+#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */\r
+#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */\r
+#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */\r
+#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */\r
+#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */\r
+#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */\r
+#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */\r
+#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */\r
+#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */\r
+#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */\r
+#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */\r
+#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */\r
+#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */\r
+#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */\r
+#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */\r
+#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */\r
+#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */\r
+#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */\r
+#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */\r
+#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */\r
+#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */\r
+#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */\r
+#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */\r
+#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */\r
+#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */\r
+#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */\r
+#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */\r
+#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */\r
+#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */\r
+#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */\r
+#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */\r
+#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */\r
+#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */\r
+#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */\r
+#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */\r
+#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */\r
+#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */\r
+#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */\r
+#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */\r
+#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */\r
+#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */\r
+#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */\r
+#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */\r
+\r
+/* Bit fields for USART CLKDIV */\r
+#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */\r
+#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */\r
+#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */\r
+#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */\r
+#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */\r
+#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */\r
+#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */\r
+#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */\r
+#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */\r
+#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */\r
+#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */\r
+\r
+/* Bit fields for USART RXDATAX */\r
+#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */\r
+#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */\r
+#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */\r
+#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */\r
+#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */\r
+#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */\r
+#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */\r
+#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */\r
+#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */\r
+#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */\r
+#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */\r
+\r
+/* Bit fields for USART RXDATA */\r
+#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */\r
+#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */\r
+#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */\r
+#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */\r
+#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */\r
+#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */\r
+\r
+/* Bit fields for USART RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */\r
+#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */\r
+#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */\r
+#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */\r
+#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */\r
+#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */\r
+#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */\r
+#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */\r
+#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */\r
+#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */\r
+#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */\r
+#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */\r
+#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */\r
+#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */\r
+#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */\r
+#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */\r
+#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+\r
+/* Bit fields for USART RXDOUBLE */\r
+#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */\r
+#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */\r
+#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */\r
+#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */\r
+#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */\r
+#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */\r
+#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */\r
+\r
+/* Bit fields for USART RXDATAXP */\r
+#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */\r
+#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */\r
+#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */\r
+#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */\r
+#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */\r
+#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */\r
+#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */\r
+#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */\r
+#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */\r
+\r
+/* Bit fields for USART RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */\r
+#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */\r
+#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */\r
+#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */\r
+#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */\r
+#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */\r
+#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */\r
+#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */\r
+#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */\r
+#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */\r
+#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */\r
+#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */\r
+#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */\r
+#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */\r
+#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */\r
+#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */\r
+#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+\r
+/* Bit fields for USART TXDATAX */\r
+#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */\r
+#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */\r
+#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */\r
+#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */\r
+#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */\r
+#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */\r
+#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */\r
+#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */\r
+#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */\r
+#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */\r
+#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */\r
+#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */\r
+#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */\r
+#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */\r
+#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */\r
+#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */\r
+#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+\r
+/* Bit fields for USART TXDATA */\r
+#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */\r
+#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */\r
+#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */\r
+#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */\r
+#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */\r
+#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */\r
+\r
+/* Bit fields for USART TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */\r
+#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */\r
+#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */\r
+#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */\r
+#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */\r
+#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */\r
+#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */\r
+#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */\r
+#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */\r
+#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */\r
+#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */\r
+#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */\r
+#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */\r
+#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */\r
+#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */\r
+#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */\r
+#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */\r
+#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */\r
+#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */\r
+#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */\r
+#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */\r
+#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */\r
+#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */\r
+#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */\r
+#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */\r
+#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */\r
+#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */\r
+#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */\r
+#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */\r
+#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */\r
+#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */\r
+#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */\r
+#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */\r
+#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */\r
+#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+\r
+/* Bit fields for USART TXDOUBLE */\r
+#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */\r
+#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */\r
+#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */\r
+#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */\r
+#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */\r
+#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */\r
+#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */\r
+\r
+/* Bit fields for USART IF */\r
+#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */\r
+#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */\r
+#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */\r
+#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */\r
+#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */\r
+#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */\r
+#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */\r
+#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */\r
+#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */\r
+#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */\r
+#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */\r
+#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */\r
+#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */\r
+#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */\r
+#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */\r
+#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */\r
+#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */\r
+#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */\r
+#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */\r
+#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */\r
+#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */\r
+#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */\r
+#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */\r
+#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */\r
+#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */\r
+#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */\r
+#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */\r
+#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */\r
+#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */\r
+#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */\r
+#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */\r
+#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */\r
+#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */\r
+\r
+/* Bit fields for USART IFS */\r
+#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */\r
+#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */\r
+#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */\r
+#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */\r
+#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */\r
+#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */\r
+#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */\r
+#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */\r
+#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */\r
+#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */\r
+#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */\r
+#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */\r
+#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */\r
+#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */\r
+#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */\r
+#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */\r
+#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */\r
+#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */\r
+#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */\r
+#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */\r
+#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */\r
+#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */\r
+#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */\r
+#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */\r
+#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */\r
+#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */\r
+\r
+/* Bit fields for USART IFC */\r
+#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */\r
+#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */\r
+#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */\r
+#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */\r
+#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */\r
+#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */\r
+#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */\r
+#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */\r
+#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */\r
+#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */\r
+#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */\r
+#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */\r
+#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */\r
+#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */\r
+#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */\r
+#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */\r
+#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */\r
+#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */\r
+#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */\r
+#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */\r
+#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */\r
+#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */\r
+#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */\r
+#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */\r
+#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */\r
+#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */\r
+\r
+/* Bit fields for USART IEN */\r
+#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */\r
+#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */\r
+#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */\r
+#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */\r
+#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */\r
+#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */\r
+#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */\r
+#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */\r
+#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */\r
+#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */\r
+#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */\r
+#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */\r
+#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */\r
+#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */\r
+#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */\r
+#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */\r
+#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */\r
+#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */\r
+#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */\r
+#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */\r
+#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */\r
+#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */\r
+#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */\r
+#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */\r
+#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */\r
+#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */\r
+#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */\r
+#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */\r
+#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */\r
+#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */\r
+#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */\r
+#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */\r
+\r
+/* Bit fields for USART IRCTRL */\r
+#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */\r
+#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */\r
+#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */\r
+#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */\r
+#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */\r
+#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */\r
+#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */\r
+#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */\r
+#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */\r
+#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */\r
+#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */\r
+#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */\r
+#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */\r
+#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */\r
+#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */\r
+#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */\r
+#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */\r
+\r
+/* Bit fields for USART INPUT */\r
+#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */\r
+#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */\r
+#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */\r
+#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */\r
+#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */\r
+#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */\r
+#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */\r
+#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */\r
+#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */\r
+#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */\r
+#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */\r
+#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */\r
+#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */\r
+#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */\r
+#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */\r
+#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */\r
+#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */\r
+#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */\r
+#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */\r
+#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */\r
+\r
+/* Bit fields for USART I2SCTRL */\r
+#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */\r
+#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */\r
+#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */\r
+#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */\r
+#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */\r
+#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */\r
+#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */\r
+#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */\r
+#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */\r
+#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */\r
+#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */\r
+#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */\r
+#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */\r
+#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */\r
+#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */\r
+#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */\r
+#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */\r
+#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */\r
+#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */\r
+#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */\r
+#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */\r
+\r
+/* Bit fields for USART TIMING */\r
+#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */\r
+#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */\r
+#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */\r
+#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */\r
+#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */\r
+#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */\r
+#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */\r
+#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */\r
+#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */\r
+#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */\r
+#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */\r
+#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */\r
+#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */\r
+#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */\r
+#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */\r
+#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */\r
+#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */\r
+#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */\r
+#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */\r
+#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */\r
+#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */\r
+#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */\r
+#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */\r
+#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */\r
+#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */\r
+#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */\r
+#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */\r
+#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */\r
+#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */\r
+#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */\r
+#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */\r
+#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */\r
+#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */\r
+#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */\r
+\r
+/* Bit fields for USART CTRLX */\r
+#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */\r
+#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */\r
+#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */\r
+#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */\r
+#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */\r
+#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */\r
+#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */\r
+#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */\r
+#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */\r
+#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */\r
+#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */\r
+#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */\r
+#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */\r
+#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */\r
+#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */\r
+#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */\r
+\r
+/* Bit fields for USART TIMECMP0 */\r
+#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */\r
+#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */\r
+#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */\r
+#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */\r
+#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */\r
+#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */\r
+#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */\r
+#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */\r
+#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */\r
+#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */\r
+#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */\r
+#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */\r
+\r
+/* Bit fields for USART TIMECMP1 */\r
+#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */\r
+#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */\r
+#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */\r
+#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */\r
+#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */\r
+#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */\r
+#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */\r
+#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */\r
+#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */\r
+#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */\r
+#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */\r
+#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */\r
+\r
+/* Bit fields for USART TIMECMP2 */\r
+#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */\r
+#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */\r
+#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */\r
+#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */\r
+#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */\r
+#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */\r
+#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */\r
+#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */\r
+#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */\r
+#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */\r
+#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */\r
+#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */\r
+\r
+/* Bit fields for USART ROUTEPEN */\r
+#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */\r
+#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */\r
+#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */\r
+#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */\r
+#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */\r
+#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */\r
+#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */\r
+#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */\r
+#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */\r
+#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */\r
+#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */\r
+#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */\r
+#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */\r
+#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */\r
+#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */\r
+#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */\r
+#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */\r
+#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */\r
+#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */\r
+#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */\r
+#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */\r
+\r
+/* Bit fields for USART ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */\r
+#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */\r
+#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */\r
+#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */\r
+#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */\r
+#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */\r
+#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */\r
+#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */\r
+#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */\r
+#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */\r
+\r
+/* Bit fields for USART ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */\r
+#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */\r
+#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */\r
+#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */\r
+#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */\r
+\r
+/** @} End of group EFM32PG1B_USART */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_wdog.h\r
+ * @brief EFM32PG1B_WDOG register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_WDOG\r
+ * @{\r
+ * @brief EFM32PG1B_WDOG Register Declaration\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t CMD; /**< Command Register */\r
+\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+\r
+ WDOG_PCH_TypeDef PCH[2]; /**< PCH */\r
+\r
+ uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< Watchdog Interrupt Flags */\r
+ __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+} WDOG_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32PG1B_WDOG_BitFields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/* Bit fields for WDOG CTRL */\r
+#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */\r
+#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */\r
+#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */\r
+#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */\r
+#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */\r
+#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */\r
+#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */\r
+#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */\r
+#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */\r
+#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */\r
+#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */\r
+#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */\r
+#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */\r
+#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */\r
+#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */\r
+#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */\r
+#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */\r
+#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */\r
+#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */\r
+#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */\r
+#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */\r
+#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */\r
+#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */\r
+#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */\r
+#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */\r
+#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */\r
+#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */\r
+#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */\r
+#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */\r
+#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */\r
+#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */\r
+#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */\r
+#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */\r
+#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */\r
+#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */\r
+#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */\r
+#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */\r
+#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */\r
+#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */\r
+#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */\r
+#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */\r
+#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */\r
+#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */\r
+#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */\r
+#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */\r
+\r
+/* Bit fields for WDOG CMD */\r
+#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */\r
+#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */\r
+#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */\r
+#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */\r
+#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */\r
+#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */\r
+#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */\r
+\r
+/* Bit fields for WDOG SYNCBUSY */\r
+#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */\r
+#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */\r
+#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */\r
+#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */\r
+#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */\r
+#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */\r
+#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */\r
+#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */\r
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */\r
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */\r
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */\r
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */\r
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */\r
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
+\r
+/* Bit fields for WDOG PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */\r
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */\r
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */\r
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */\r
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */\r
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */\r
+\r
+/* Bit fields for WDOG IF */\r
+#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */\r
+#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */\r
+#define WDOG_IF_TOUT (0x1UL << 0) /**< Wdog Timeout Interrupt Flag */\r
+#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */\r
+#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */\r
+#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_WARN (0x1UL << 1) /**< Wdog Warning Timeout Interrupt Flag */\r
+#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */\r
+#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */\r
+#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_WIN (0x1UL << 2) /**< Wdog Window Interrupt Flag */\r
+#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */\r
+#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */\r
+#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */\r
+#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */\r
+#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */\r
+#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */\r
+#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */\r
+#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */\r
+#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */\r
+#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */\r
+\r
+/* Bit fields for WDOG IFS */\r
+#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */\r
+#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */\r
+#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */\r
+#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */\r
+#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */\r
+#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */\r
+#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */\r
+#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */\r
+#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */\r
+#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */\r
+#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */\r
+#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */\r
+#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */\r
+#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */\r
+#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */\r
+#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */\r
+#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */\r
+#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */\r
+#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */\r
+\r
+/* Bit fields for WDOG IFC */\r
+#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */\r
+#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */\r
+#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */\r
+#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */\r
+#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */\r
+#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */\r
+#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */\r
+#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */\r
+#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */\r
+#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */\r
+#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */\r
+#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */\r
+#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */\r
+#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */\r
+#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */\r
+#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */\r
+#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */\r
+#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */\r
+#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */\r
+\r
+/* Bit fields for WDOG IEN */\r
+#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */\r
+#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */\r
+#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */\r
+#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */\r
+#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */\r
+#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */\r
+#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */\r
+#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */\r
+#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */\r
+#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */\r
+#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */\r
+#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */\r
+#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */\r
+#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */\r
+#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */\r
+#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */\r
+#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */\r
+#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */\r
+#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */\r
+\r
+/** @} End of group EFM32PG1B_WDOG */\r
+/** @} End of group Parts */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file efm32pg1b_wdog_pch.h\r
+ * @brief EFM32PG1B_WDOG_PCH register and bit field definitions\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
+/**************************************************************************//**\r
+ * @brief WDOG_PCH EFM32PG1B WDOG PCH\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t PRSCTRL; /**< PRS Control Register */\r
+} WDOG_PCH_TypeDef;\r
+\r
+/** @} End of group Parts */\r
+\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file em_device.h\r
+ * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories\r
+ * microcontroller devices\r
+ *\r
+ * This is a convenience header file for defining the part number on the\r
+ * build command line, instead of specifying the part specific header file.\r
+ *\r
+ * @verbatim\r
+ * Example: Add "-DEFM32G890F128" to your build options, to define part\r
+ * Add "#include "em_device.h" to your source files\r
+ *\r
+ *\r
+ * @endverbatim\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef EM_DEVICE_H\r
+#define EM_DEVICE_H\r
+\r
+#if defined(EFM32PG1B100F128GM32)\r
+#include "efm32pg1b100f128gm32.h"\r
+\r
+#elif defined(EFM32PG1B100F256GM32)\r
+#include "efm32pg1b100f256gm32.h"\r
+\r
+#elif defined(EFM32PG1B200F128GM32)\r
+#include "efm32pg1b200f128gm32.h"\r
+\r
+#elif defined(EFM32PG1B200F128GM48)\r
+#include "efm32pg1b200f128gm48.h"\r
+\r
+#elif defined(EFM32PG1B200F256GM32)\r
+#include "efm32pg1b200f256gm32.h"\r
+\r
+#elif defined(EFM32PG1B200F256GM48)\r
+#include "efm32pg1b200f256gm48.h"\r
+\r
+#else\r
+#error "em_device.h: PART NUMBER undefined"\r
+#endif\r
+#endif /* EM_DEVICE_H */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file system_efm32pg1b.h\r
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef SYSTEM_EFM32_H\r
+#define SYSTEM_EFM32_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/*******************************************************************************\r
+ ************************** GLOBAL VARIABLES *******************************\r
+ ******************************************************************************/\r
+\r
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */\r
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+void Reset_Handler(void);\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+void EMU_IRQHandler(void);\r
+void WDOG_IRQHandler(void);\r
+void LDMA_IRQHandler(void);\r
+void GPIO_EVEN_IRQHandler(void);\r
+void TIMER0_IRQHandler(void);\r
+void USART0_RX_IRQHandler(void);\r
+void USART0_TX_IRQHandler(void);\r
+void ACMP0_IRQHandler(void);\r
+void ADC0_IRQHandler(void);\r
+void IDAC0_IRQHandler(void);\r
+void I2C0_IRQHandler(void);\r
+void GPIO_ODD_IRQHandler(void);\r
+void TIMER1_IRQHandler(void);\r
+void USART1_RX_IRQHandler(void);\r
+void USART1_TX_IRQHandler(void);\r
+void LEUART0_IRQHandler(void);\r
+void PCNT0_IRQHandler(void);\r
+void CMU_IRQHandler(void);\r
+void MSC_IRQHandler(void);\r
+void LETIMER0_IRQHandler(void);\r
+void RTCC_IRQHandler(void);\r
+void CRYOTIMER_IRQHandler(void);\r
+\r
+#if (__FPU_PRESENT == 1)\r
+void FPUEH_IRQHandler(void);\r
+#endif\r
+\r
+uint32_t SystemCoreClockGet(void);\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Update CMSIS SystemCoreClock variable.\r
+ *\r
+ * @details\r
+ * CMSIS defines a global variable SystemCoreClock that shall hold the\r
+ * core frequency in Hz. If the core frequency is dynamically changed, the\r
+ * variable must be kept updated in order to be CMSIS compliant.\r
+ *\r
+ * Notice that only if changing the core clock frequency through the EFM CMU\r
+ * API, this variable will be kept updated. This function is only provided\r
+ * for CMSIS compliance and if a user modifies the the core clock outside\r
+ * the CMU API.\r
+ *****************************************************************************/\r
+static __INLINE void SystemCoreClockUpdate(void)\r
+{\r
+ SystemCoreClockGet();\r
+}\r
+\r
+uint32_t SystemMaxCoreClockGet(void);\r
+\r
+void SystemInit(void);\r
+uint32_t SystemHFClockGet(void);\r
+\r
+uint32_t SystemHFXOClockGet(void);\r
+void SystemHFXOClockSet(uint32_t freq);\r
+\r
+uint32_t SystemLFRCOClockGet(void);\r
+uint32_t SystemULFRCOClockGet(void);\r
+\r
+uint32_t SystemLFXOClockGet(void);\r
+void SystemLFXOClockSet(uint32_t freq);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* SYSTEM_EFM32_H */\r
--- /dev/null
+/* Linker script for Silicon Labs EFM32PG1B devices */\r
+/* */\r
+/* This file is subject to the license terms as defined in ARM's */\r
+/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */\r
+/* Example Code. */\r
+/* */\r
+/* Silicon Laboratories, Inc. 2015 */\r
+/* */\r
+/* Version 4.2.0 */\r
+/* */\r
+\r
+MEMORY\r
+{\r
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144\r
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32768\r
+}\r
+\r
+/* Linker script to place sections and symbol values. Should be used together\r
+ * with other linker script that defines memory regions FLASH and RAM.\r
+ * It references following symbols, which must be defined in code:\r
+ * Reset_Handler : Entry of reset handler\r
+ *\r
+ * It defines following symbols, which code can use without definition:\r
+ * __exidx_start\r
+ * __exidx_end\r
+ * __copy_table_start__\r
+ * __copy_table_end__\r
+ * __zero_table_start__\r
+ * __zero_table_end__\r
+ * __etext\r
+ * __data_start__\r
+ * __preinit_array_start\r
+ * __preinit_array_end\r
+ * __init_array_start\r
+ * __init_array_end\r
+ * __fini_array_start\r
+ * __fini_array_end\r
+ * __data_end__\r
+ * __bss_start__\r
+ * __bss_end__\r
+ * __end__\r
+ * end\r
+ * __HeapLimit\r
+ * __StackLimit\r
+ * __StackTop\r
+ * __stack\r
+ * __Vectors_End\r
+ * __Vectors_Size\r
+ */\r
+ENTRY(Reset_Handler)\r
+\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ KEEP(*(.vectors))\r
+ __Vectors_End = .;\r
+ __Vectors_Size = __Vectors_End - __Vectors;\r
+ __end__ = .;\r
+\r
+ *(.text*)\r
+\r
+ KEEP(*(.init))\r
+ KEEP(*(.fini))\r
+\r
+ /* .ctors */\r
+ *crtbegin.o(.ctors)\r
+ *crtbegin?.o(.ctors)\r
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r
+ *(SORT(.ctors.*))\r
+ *(.ctors)\r
+\r
+ /* .dtors */\r
+ *crtbegin.o(.dtors)\r
+ *crtbegin?.o(.dtors)\r
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r
+ *(SORT(.dtors.*))\r
+ *(.dtors)\r
+\r
+ *(.rodata*)\r
+\r
+ KEEP(*(.eh_frame*))\r
+ } > FLASH\r
+\r
+ .ARM.extab :\r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > FLASH\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > FLASH\r
+ __exidx_end = .;\r
+\r
+ /* To copy multiple ROM to RAM sections,\r
+ * uncomment .copy.table section and,\r
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */\r
+ /*\r
+ .copy.table :\r
+ {\r
+ . = ALIGN(4);\r
+ __copy_table_start__ = .;\r
+ LONG (__etext)\r
+ LONG (__data_start__)\r
+ LONG (__data_end__ - __data_start__)\r
+ LONG (__etext2)\r
+ LONG (__data2_start__)\r
+ LONG (__data2_end__ - __data2_start__)\r
+ __copy_table_end__ = .;\r
+ } > FLASH\r
+ */\r
+\r
+ /* To clear multiple BSS sections,\r
+ * uncomment .zero.table section and,\r
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */\r
+ /*\r
+ .zero.table :\r
+ {\r
+ . = ALIGN(4);\r
+ __zero_table_start__ = .;\r
+ LONG (__bss_start__)\r
+ LONG (__bss_end__ - __bss_start__)\r
+ LONG (__bss2_start__)\r
+ LONG (__bss2_end__ - __bss2_start__)\r
+ __zero_table_end__ = .;\r
+ } > FLASH\r
+ */\r
+\r
+ __etext = .;\r
+\r
+ .data : AT (__etext)\r
+ {\r
+ __data_start__ = .;\r
+ *(vtable)\r
+ *(.data*)\r
+ . = ALIGN (4);\r
+ *(.ram)\r
+\r
+ . = ALIGN(4);\r
+ /* preinit data */\r
+ PROVIDE_HIDDEN (__preinit_array_start = .);\r
+ KEEP(*(.preinit_array))\r
+ PROVIDE_HIDDEN (__preinit_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+ /* init data */\r
+ PROVIDE_HIDDEN (__init_array_start = .);\r
+ KEEP(*(SORT(.init_array.*)))\r
+ KEEP(*(.init_array))\r
+ PROVIDE_HIDDEN (__init_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+ /* finit data */\r
+ PROVIDE_HIDDEN (__fini_array_start = .);\r
+ KEEP(*(SORT(.fini_array.*)))\r
+ KEEP(*(.fini_array))\r
+ PROVIDE_HIDDEN (__fini_array_end = .);\r
+\r
+ KEEP(*(.jcr*))\r
+ . = ALIGN(4);\r
+ /* All data end */\r
+ __data_end__ = .;\r
+\r
+ } > RAM\r
+\r
+ .bss :\r
+ {\r
+ . = ALIGN(4);\r
+ __bss_start__ = .;\r
+ *(.bss*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ __bss_end__ = .;\r
+ } > RAM\r
+\r
+ .heap (COPY):\r
+ {\r
+ __HeapBase = .;\r
+ __end__ = .;\r
+ end = __end__;\r
+ _end = __end__;\r
+ KEEP(*(.heap*))\r
+ __HeapLimit = .;\r
+ } > RAM\r
+\r
+ /* .stack_dummy section doesn't contains any symbols. It is only\r
+ * used for linker to calculate size of stack sections, and assign\r
+ * values to stack symbols later */\r
+ .stack_dummy (COPY):\r
+ {\r
+ KEEP(*(.stack*))\r
+ } > RAM\r
+\r
+ /* Set stack top to end of RAM, and stack limit move down by\r
+ * size of stack_dummy section */\r
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r
+ PROVIDE(__stack = __StackTop);\r
+\r
+ /* Check if data + heap + stack exceeds RAM limit */\r
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")\r
+\r
+ /* Check if FLASH usage exceeds FLASH size */\r
+ ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")\r
+}\r
--- /dev/null
+/* @file startup_efm32pg1b.S\r
+ * @brief startup file for Silicon Labs EFM32PG1B devices.\r
+ * For use with GCC for ARM Embedded Processors\r
+ * @version 4.2.1\r
+ * Date: 12 June 2014\r
+ *\r
+ */\r
+/* Copyright (c) 2011 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+ .syntax unified\r
+ .arch armv7-m\r
+ .section .stack\r
+ .align 3\r
+#ifdef __STACK_SIZE\r
+ .equ Stack_Size, __STACK_SIZE\r
+#else\r
+ .equ Stack_Size, 0x00000400\r
+#endif\r
+ .globl __StackTop\r
+ .globl __StackLimit\r
+__StackLimit:\r
+ .space Stack_Size\r
+ .size __StackLimit, . - __StackLimit\r
+__StackTop:\r
+ .size __StackTop, . - __StackTop\r
+\r
+ .section .heap\r
+ .align 3\r
+#ifdef __HEAP_SIZE\r
+ .equ Heap_Size, __HEAP_SIZE\r
+#else\r
+ .equ Heap_Size, 0x00000C00\r
+#endif\r
+ .globl __HeapBase\r
+ .globl __HeapLimit\r
+__HeapBase:\r
+ .if Heap_Size\r
+ .space Heap_Size\r
+ .endif\r
+ .size __HeapBase, . - __HeapBase\r
+__HeapLimit:\r
+ .size __HeapLimit, . - __HeapLimit\r
+\r
+ .section .vectors\r
+ .align 2\r
+ .globl __Vectors\r
+__Vectors:\r
+ .long __StackTop /* Top of Stack */\r
+ .long Reset_Handler /* Reset Handler */\r
+ .long NMI_Handler /* NMI Handler */\r
+ .long HardFault_Handler /* Hard Fault Handler */\r
+ .long MemManage_Handler /* MPU Fault Handler */\r
+ .long BusFault_Handler /* Bus Fault Handler */\r
+ .long UsageFault_Handler /* Usage Fault Handler */\r
+ .long Default_Handler /* Reserved */\r
+ .long Default_Handler /* Reserved */\r
+ .long Default_Handler /* Reserved */\r
+ .long Default_Handler /* Reserved */\r
+ .long SVC_Handler /* SVCall Handler */\r
+ .long DebugMon_Handler /* Debug Monitor Handler */\r
+ .long Default_Handler /* Reserved */\r
+ .long PendSV_Handler /* PendSV Handler */\r
+ .long SysTick_Handler /* SysTick Handler */\r
+\r
+ /* External interrupts */\r
+ .long EMU_IRQHandler /* 0 - EMU */\r
+ .long Default_Handler /* 1 - Reserved */\r
+ .long WDOG0_IRQHandler /* 2 - WDOG0 */\r
+ .long Default_Handler /* 3 - Reserved */\r
+ .long Default_Handler /* 4 - Reserved */\r
+ .long Default_Handler /* 5 - Reserved */\r
+ .long Default_Handler /* 6 - Reserved */\r
+ .long Default_Handler /* 7 - Reserved */\r
+ .long LDMA_IRQHandler /* 8 - LDMA */\r
+ .long GPIO_EVEN_IRQHandler /* 9 - GPIO_EVEN */\r
+ .long TIMER0_IRQHandler /* 10 - TIMER0 */\r
+ .long USART0_RX_IRQHandler /* 11 - USART0_RX */\r
+ .long USART0_TX_IRQHandler /* 12 - USART0_TX */\r
+ .long ACMP0_IRQHandler /* 13 - ACMP0 */\r
+ .long ADC0_IRQHandler /* 14 - ADC0 */\r
+ .long IDAC0_IRQHandler /* 15 - IDAC0 */\r
+ .long I2C0_IRQHandler /* 16 - I2C0 */\r
+ .long GPIO_ODD_IRQHandler /* 17 - GPIO_ODD */\r
+ .long TIMER1_IRQHandler /* 18 - TIMER1 */\r
+ .long USART1_RX_IRQHandler /* 19 - USART1_RX */\r
+ .long USART1_TX_IRQHandler /* 20 - USART1_TX */\r
+ .long LEUART0_IRQHandler /* 21 - LEUART0 */\r
+ .long PCNT0_IRQHandler /* 22 - PCNT0 */\r
+ .long CMU_IRQHandler /* 23 - CMU */\r
+ .long MSC_IRQHandler /* 24 - MSC */\r
+ .long CRYPTO_IRQHandler /* 25 - CRYPTO */\r
+ .long LETIMER0_IRQHandler /* 26 - LETIMER0 */\r
+ .long Default_Handler /* 27 - Reserved */\r
+ .long Default_Handler /* 28 - Reserved */\r
+ .long RTCC_IRQHandler /* 29 - RTCC */\r
+ .long Default_Handler /* 30 - Reserved */\r
+ .long CRYOTIMER_IRQHandler /* 31 - CRYOTIMER */\r
+ .long Default_Handler /* 32 - Reserved */\r
+ .long FPUEH_IRQHandler /* 33 - FPUEH */\r
+\r
+\r
+ .size __Vectors, . - __Vectors\r
+\r
+ .text\r
+ .thumb\r
+ .thumb_func\r
+ .align 2\r
+ .globl Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+#ifndef __NO_SYSTEM_INIT\r
+ ldr r0, =SystemInit\r
+ blx r0\r
+#endif\r
+\r
+/* Firstly it copies data from read only memory to RAM. There are two schemes\r
+ * to copy. One can copy more than one sections. Another can only copy\r
+ * one section. The former scheme needs more instructions and read-only\r
+ * data to implement than the latter.\r
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */\r
+\r
+#ifdef __STARTUP_COPY_MULTIPLE\r
+/* Multiple sections scheme.\r
+ *\r
+ * Between symbol address __copy_table_start__ and __copy_table_end__,\r
+ * there are array of triplets, each of which specify:\r
+ * offset 0: LMA of start of a section to copy from\r
+ * offset 4: VMA of start of a section to copy to\r
+ * offset 8: size of the section to copy. Must be multiply of 4\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r4, =__copy_table_start__\r
+ ldr r5, =__copy_table_end__\r
+\r
+.L_loop0:\r
+ cmp r4, r5\r
+ bge .L_loop0_done\r
+ ldr r1, [r4]\r
+ ldr r2, [r4, #4]\r
+ ldr r3, [r4, #8]\r
+\r
+.L_loop0_0:\r
+ subs r3, #4\r
+ ittt ge\r
+ ldrge r0, [r1, r3]\r
+ strge r0, [r2, r3]\r
+ bge .L_loop0_0\r
+\r
+ adds r4, #12\r
+ b .L_loop0\r
+\r
+.L_loop0_done:\r
+#else\r
+/* Single section scheme.\r
+ *\r
+ * The ranges of copy from/to are specified by following symbols\r
+ * __etext: LMA of start of the section to copy from. Usually end of text\r
+ * __data_start__: VMA of start of the section to copy to\r
+ * __data_end__: VMA of end of the section to copy to\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r1, =__etext\r
+ ldr r2, =__data_start__\r
+ ldr r3, =__data_end__\r
+\r
+.L_loop1:\r
+ cmp r2, r3\r
+ ittt lt\r
+ ldrlt r0, [r1], #4\r
+ strlt r0, [r2], #4\r
+ blt .L_loop1\r
+#endif /*__STARTUP_COPY_MULTIPLE */\r
+\r
+/* This part of work usually is done in C library startup code. Otherwise,\r
+ * define this macro to enable it in this startup.\r
+ *\r
+ * There are two schemes too. One can clear multiple BSS sections. Another\r
+ * can only clear one section. The former is more size expensive than the\r
+ * latter.\r
+ *\r
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.\r
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.\r
+ */\r
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE\r
+/* Multiple sections scheme.\r
+ *\r
+ * Between symbol address __copy_table_start__ and __copy_table_end__,\r
+ * there are array of tuples specifying:\r
+ * offset 0: Start of a BSS section\r
+ * offset 4: Size of this BSS section. Must be multiply of 4\r
+ */\r
+ ldr r3, =__zero_table_start__\r
+ ldr r4, =__zero_table_end__\r
+\r
+.L_loop2:\r
+ cmp r3, r4\r
+ bge .L_loop2_done\r
+ ldr r1, [r3]\r
+ ldr r2, [r3, #4]\r
+ movs r0, 0\r
+\r
+.L_loop2_0:\r
+ subs r2, #4\r
+ itt ge\r
+ strge r0, [r1, r2]\r
+ bge .L_loop2_0\r
+ adds r3, #8\r
+ b .L_loop2\r
+.L_loop2_done:\r
+#elif defined (__STARTUP_CLEAR_BSS)\r
+/* Single BSS section scheme.\r
+ *\r
+ * The BSS section is specified by following symbols\r
+ * __bss_start__: start of the BSS section.\r
+ * __bss_end__: end of the BSS section.\r
+ *\r
+ * Both addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r1, =__bss_start__\r
+ ldr r2, =__bss_end__\r
+\r
+ movs r0, 0\r
+.L_loop3:\r
+ cmp r1, r2\r
+ itt lt\r
+ strlt r0, [r1], #4\r
+ blt .L_loop3\r
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */\r
+\r
+#ifndef __START\r
+#define __START _start\r
+#endif\r
+ bl __START\r
+\r
+ .pool\r
+ .size Reset_Handler, . - Reset_Handler\r
+\r
+ .align 1\r
+ .thumb_func\r
+ .weak Default_Handler\r
+ .type Default_Handler, %function\r
+Default_Handler:\r
+ b .\r
+ .size Default_Handler, . - Default_Handler\r
+\r
+/* Macro to define default handlers. Default handler\r
+ * will be weak symbol and just dead loops. They can be\r
+ * overwritten by other handlers */\r
+ .macro def_irq_handler handler_name\r
+ .weak \handler_name\r
+ .set \handler_name, Default_Handler\r
+ .endm\r
+\r
+ def_irq_handler NMI_Handler\r
+ def_irq_handler HardFault_Handler\r
+ def_irq_handler MemManage_Handler\r
+ def_irq_handler BusFault_Handler\r
+ def_irq_handler UsageFault_Handler\r
+ def_irq_handler SVC_Handler\r
+ def_irq_handler DebugMon_Handler\r
+ def_irq_handler PendSV_Handler\r
+ def_irq_handler SysTick_Handler\r
+\r
+\r
+ def_irq_handler EMU_IRQHandler\r
+ def_irq_handler WDOG0_IRQHandler\r
+ def_irq_handler LDMA_IRQHandler\r
+ def_irq_handler GPIO_EVEN_IRQHandler\r
+ def_irq_handler TIMER0_IRQHandler\r
+ def_irq_handler USART0_RX_IRQHandler\r
+ def_irq_handler USART0_TX_IRQHandler\r
+ def_irq_handler ACMP0_IRQHandler\r
+ def_irq_handler ADC0_IRQHandler\r
+ def_irq_handler IDAC0_IRQHandler\r
+ def_irq_handler I2C0_IRQHandler\r
+ def_irq_handler GPIO_ODD_IRQHandler\r
+ def_irq_handler TIMER1_IRQHandler\r
+ def_irq_handler USART1_RX_IRQHandler\r
+ def_irq_handler USART1_TX_IRQHandler\r
+ def_irq_handler LEUART0_IRQHandler\r
+ def_irq_handler PCNT0_IRQHandler\r
+ def_irq_handler CMU_IRQHandler\r
+ def_irq_handler MSC_IRQHandler\r
+ def_irq_handler CRYPTO_IRQHandler\r
+ def_irq_handler LETIMER0_IRQHandler\r
+ def_irq_handler RTCC_IRQHandler\r
+ def_irq_handler CRYOTIMER_IRQHandler\r
+ def_irq_handler FPUEH_IRQHandler\r
+\r
+ .end\r
--- /dev/null
+/*\r
+ * @file startup_efm32pg1b.c\r
+ * @brief CMSIS Compatible EFM32PG1B startup file in C.\r
+ * Should be used with GCC 'GNU Tools ARM Embedded'\r
+ * @version 4.2.1\r
+ * Date: 12 June 2014\r
+ *\r
+ */\r
+/* Copyright (c) 2011 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Linker generated Symbols\r
+ *----------------------------------------------------------------------------*/\r
+extern uint32_t __etext;\r
+extern uint32_t __data_start__;\r
+extern uint32_t __data_end__;\r
+extern uint32_t __copy_table_start__;\r
+extern uint32_t __copy_table_end__;\r
+extern uint32_t __zero_table_start__;\r
+extern uint32_t __zero_table_end__;\r
+extern uint32_t __bss_start__;\r
+extern uint32_t __bss_end__;\r
+extern uint32_t __StackTop;\r
+\r
+/*----------------------------------------------------------------------------\r
+ Exception / Interrupt Handler Function Prototype\r
+ *----------------------------------------------------------------------------*/\r
+typedef void( *pFunc )( void );\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ External References\r
+ *----------------------------------------------------------------------------*/\r
+#ifndef __START\r
+extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */\r
+#else\r
+extern int __START(void) __attribute__((noreturn)); /* main entry point */\r
+#endif\r
+\r
+#ifndef __NO_SYSTEM_INIT\r
+extern void SystemInit (void); /* CMSIS System Initialization */\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Internal References\r
+ *----------------------------------------------------------------------------*/\r
+void Default_Handler(void); /* Default empty handler */\r
+void Reset_Handler(void); /* Reset Handler */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ User Initial Stack & Heap\r
+ *----------------------------------------------------------------------------*/\r
+#ifndef __STACK_SIZE\r
+#define __STACK_SIZE 0x00000400\r
+#endif\r
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));\r
+\r
+#ifndef __HEAP_SIZE\r
+#define __HEAP_SIZE 0x00000C00\r
+#endif\r
+#if __HEAP_SIZE > 0\r
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Exception / Interrupt Handler\r
+ *----------------------------------------------------------------------------*/\r
+/* Cortex-M Processor Exceptions */\r
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));\r
+\r
+/* Part Specific Interrupts */\r
+\r
+void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void IDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void CRYPTO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void CRYOTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Exception / Interrupt Vector table\r
+ *----------------------------------------------------------------------------*/\r
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {\r
+ /* Cortex-M Exception Handlers */\r
+ (pFunc)&__StackTop, /* Initial Stack Pointer */\r
+ Reset_Handler, /* Reset Handler */\r
+ NMI_Handler, /* NMI Handler */\r
+ HardFault_Handler, /* Hard Fault Handler */\r
+ MemManage_Handler, /* MPU Fault Handler */\r
+ BusFault_Handler, /* Bus Fault Handler */\r
+ UsageFault_Handler, /* Usage Fault Handler */\r
+ Default_Handler, /* Reserved */\r
+ Default_Handler, /* Reserved */\r
+ Default_Handler, /* Reserved */\r
+ Default_Handler, /* Reserved */\r
+ SVC_Handler, /* SVCall Handler */\r
+ DebugMon_Handler, /* Debug Monitor Handler */\r
+ Default_Handler, /* Reserved */\r
+ PendSV_Handler, /* PendSV Handler */\r
+ SysTick_Handler, /* SysTick Handler */\r
+\r
+ /* External interrupts */\r
+\r
+ EMU_IRQHandler, /* 0 - EMU */\r
+ Default_Handler, /* 1 - Reserved */\r
+ WDOG0_IRQHandler, /* 2 - WDOG0 */\r
+ Default_Handler, /* 3 - Reserved */\r
+ Default_Handler, /* 4 - Reserved */\r
+ Default_Handler, /* 5 - Reserved */\r
+ Default_Handler, /* 6 - Reserved */\r
+ Default_Handler, /* 7 - Reserved */\r
+ LDMA_IRQHandler, /* 8 - LDMA */\r
+ GPIO_EVEN_IRQHandler, /* 9 - GPIO_EVEN */\r
+ TIMER0_IRQHandler, /* 10 - TIMER0 */\r
+ USART0_RX_IRQHandler, /* 11 - USART0_RX */\r
+ USART0_TX_IRQHandler, /* 12 - USART0_TX */\r
+ ACMP0_IRQHandler, /* 13 - ACMP0 */\r
+ ADC0_IRQHandler, /* 14 - ADC0 */\r
+ IDAC0_IRQHandler, /* 15 - IDAC0 */\r
+ I2C0_IRQHandler, /* 16 - I2C0 */\r
+ GPIO_ODD_IRQHandler, /* 17 - GPIO_ODD */\r
+ TIMER1_IRQHandler, /* 18 - TIMER1 */\r
+ USART1_RX_IRQHandler, /* 19 - USART1_RX */\r
+ USART1_TX_IRQHandler, /* 20 - USART1_TX */\r
+ LEUART0_IRQHandler, /* 21 - LEUART0 */\r
+ PCNT0_IRQHandler, /* 22 - PCNT0 */\r
+ CMU_IRQHandler, /* 23 - CMU */\r
+ MSC_IRQHandler, /* 24 - MSC */\r
+ CRYPTO_IRQHandler, /* 25 - CRYPTO */\r
+ LETIMER0_IRQHandler, /* 26 - LETIMER0 */\r
+ Default_Handler, /* 27 - Reserved */\r
+ Default_Handler, /* 28 - Reserved */\r
+ RTCC_IRQHandler, /* 29 - RTCC */\r
+ Default_Handler, /* 30 - Reserved */\r
+ CRYOTIMER_IRQHandler, /* 31 - CRYOTIMER */\r
+ Default_Handler, /* 32 - Reserved */\r
+ FPUEH_IRQHandler, /* 33 - FPUEH */\r
+\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ Reset Handler called on controller reset\r
+ *----------------------------------------------------------------------------*/\r
+void Reset_Handler(void) {\r
+ uint32_t *pSrc, *pDest;\r
+ uint32_t *pTable __attribute__((unused));\r
+\r
+#ifndef __NO_SYSTEM_INIT\r
+ SystemInit();\r
+#endif\r
+\r
+/* Firstly it copies data from read only memory to RAM. There are two schemes\r
+ * to copy. One can copy more than one sections. Another can only copy\r
+ * one section. The former scheme needs more instructions and read-only\r
+ * data to implement than the latter.\r
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */\r
+\r
+#ifdef __STARTUP_COPY_MULTIPLE\r
+/* Multiple sections scheme.\r
+ *\r
+ * Between symbol address __copy_table_start__ and __copy_table_end__,\r
+ * there are array of triplets, each of which specify:\r
+ * offset 0: LMA of start of a section to copy from\r
+ * offset 4: VMA of start of a section to copy to\r
+ * offset 8: size of the section to copy. Must be multiply of 4\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ pTable = &__copy_table_start__;\r
+\r
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3)\r
+ {\r
+ pSrc = (uint32_t*)*(pTable + 0);\r
+ pDest = (uint32_t*)*(pTable + 1);\r
+ for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; )\r
+ {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+ }\r
+#else\r
+/* Single section scheme.\r
+ *\r
+ * The ranges of copy from/to are specified by following symbols\r
+ * __etext: LMA of start of the section to copy from. Usually end of text\r
+ * __data_start__: VMA of start of the section to copy to\r
+ * __data_end__: VMA of end of the section to copy to\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ pSrc = &__etext;\r
+ pDest = &__data_start__;\r
+\r
+ for ( ; pDest < &__data_end__ ; )\r
+ {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+#endif /*__STARTUP_COPY_MULTIPLE */\r
+\r
+/* This part of work usually is done in C library startup code. Otherwise,\r
+ * define this macro to enable it in this startup.\r
+ *\r
+ * There are two schemes too. One can clear multiple BSS sections. Another\r
+ * can only clear one section. The former is more size expensive than the\r
+ * latter.\r
+ *\r
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.\r
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.\r
+ */\r
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE\r
+/* Multiple sections scheme.\r
+ *\r
+ * Between symbol address __copy_table_start__ and __copy_table_end__,\r
+ * there are array of tuples specifying:\r
+ * offset 0: Start of a BSS section\r
+ * offset 4: Size of this BSS section. Must be multiply of 4\r
+ */\r
+ pTable = &__zero_table_start__;\r
+\r
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2)\r
+ {\r
+ pDest = (uint32_t*)*(pTable + 0);\r
+ for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; )\r
+ {\r
+ *pDest++ = 0;\r
+ }\r
+ }\r
+#elif defined (__STARTUP_CLEAR_BSS)\r
+/* Single BSS section scheme.\r
+ *\r
+ * The BSS section is specified by following symbols\r
+ * __bss_start__: start of the BSS section.\r
+ * __bss_end__: end of the BSS section.\r
+ *\r
+ * Both addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ pDest = &__bss_start__;\r
+\r
+ for ( ; pDest < &__bss_end__ ; )\r
+ {\r
+ *pDest++ = 0ul;\r
+ }\r
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */\r
+\r
+#ifndef __START\r
+#define __START _start\r
+#endif\r
+ __START();\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Default Handler for Exceptions / Interrupts\r
+ *----------------------------------------------------------------------------*/\r
+void Default_Handler(void)\r
+{\r
+ while(1);\r
+}\r
+\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file system_efm32pg1b.c\r
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
+ * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
+ * providing the Software "AS IS", with no express or implied warranties of any\r
+ * kind, including, but not limited to, any implied warranties of\r
+ * merchantability or fitness for any particular purpose or warranties against\r
+ * infringement of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Laboratories, Inc. will not be liable for any consequential,\r
+ * incidental, or special damages, or any other relief, or for any claim by\r
+ * any third party, arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#include <stdint.h>\r
+#include "em_device.h"\r
+\r
+/*******************************************************************************\r
+ ****************************** DEFINES ************************************\r
+ ******************************************************************************/\r
+\r
+/** LFRCO frequency, tuned to below frequency during manufacturing. */\r
+#define EFM32_LFRCO_FREQ (32768UL)\r
+#define EFM32_ULFRCO_FREQ (1000UL)\r
+\r
+/*******************************************************************************\r
+ ************************** LOCAL VARIABLES ********************************\r
+ ******************************************************************************/\r
+\r
+/* System oscillator frequencies. These frequencies are normally constant */\r
+/* for a target, but they are made configurable in order to allow run-time */\r
+/* handling of different boards. The crystal oscillator clocks can be set */\r
+/* compile time to a non-default value by defining respective EFM_nFXO_FREQ */\r
+/* values according to board design. By defining the EFM_nFXO_FREQ to 0, */\r
+/* one indicates that the oscillator is not present, in order to save some */\r
+/* SW footprint. */\r
+\r
+#ifndef EFM32_HFRCO_MAX_FREQ\r
+#define EFM32_HFRCO_MAX_FREQ (38000000UL)\r
+#endif\r
+\r
+#ifndef EFM32_HFXO_FREQ\r
+#define EFM32_HFXO_FREQ (40000000UL)\r
+#endif\r
+\r
+#ifndef EFM32_HFRCO_STARTUP_FREQ\r
+#define EFM32_HFRCO_STARTUP_FREQ (19000000UL)\r
+#endif\r
+\r
+\r
+/* Do not define variable if HF crystal oscillator not present */\r
+#if (EFM32_HFXO_FREQ > 0UL)\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/** System HFXO clock. */\r
+static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;\r
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
+#endif\r
+\r
+#ifndef EFM32_LFXO_FREQ\r
+#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)\r
+#endif\r
+/* Do not define variable if LF crystal oscillator not present */\r
+#if (EFM32_LFXO_FREQ > 0UL)\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/** System LFXO clock. */\r
+static uint32_t SystemLFXOClock = 32768UL;\r
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+ ************************** GLOBAL VARIABLES *******************************\r
+ ******************************************************************************/\r
+\r
+/**\r
+ * @brief\r
+ * System System Clock Frequency (Core Clock).\r
+ *\r
+ * @details\r
+ * Required CMSIS global variable that must be kept up-to-date.\r
+ */\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief\r
+ * System HFRCO frequency\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary variable, not part of the CMSIS definition.\r
+ *\r
+ * @details\r
+ * Frequency of the system HFRCO oscillator\r
+ */\r
+uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;\r
+\r
+\r
+/*******************************************************************************\r
+ ************************** GLOBAL FUNCTIONS *******************************\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the current core clock frequency.\r
+ *\r
+ * @details\r
+ * Calculate and get the current core clock frequency based on the current\r
+ * configuration. Assuming that the SystemCoreClock global variable is\r
+ * maintained, the core clock frequency is stored in that variable as well.\r
+ * This function will however calculate the core clock based on actual HW\r
+ * configuration. It will also update the SystemCoreClock global variable.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The current core clock frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemCoreClockGet(void)\r
+{\r
+ uint32_t ret;\r
+ uint32_t presc;\r
+\r
+ ret = SystemHFClockGet();\r
+ presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >>\r
+ _CMU_HFCOREPRESC_PRESC_SHIFT;\r
+ ret /= (presc + 1);\r
+\r
+ /* Keep CMSIS system clock variable up-to-date */\r
+ SystemCoreClock = ret;\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the maximum core clock frequency.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The maximum core clock frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemMaxCoreClockGet(void)\r
+{\r
+ return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \\r
+ EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the current HFCLK frequency.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The current HFCLK frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemHFClockGet(void)\r
+{\r
+ uint32_t ret;\r
+\r
+ switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)\r
+ {\r
+ case CMU_HFCLKSTATUS_SELECTED_LFXO:\r
+#if (EFM32_LFXO_FREQ > 0)\r
+ ret = SystemLFXOClock;\r
+#else\r
+ /* We should not get here, since core should not be clocked. May */\r
+ /* be caused by a misconfiguration though. */\r
+ ret = 0;\r
+#endif\r
+ break;\r
+\r
+ case CMU_HFCLKSTATUS_SELECTED_LFRCO:\r
+ ret = EFM32_LFRCO_FREQ;\r
+ break;\r
+\r
+ case CMU_HFCLKSTATUS_SELECTED_HFXO:\r
+#if (EFM32_HFXO_FREQ > 0)\r
+ ret = SystemHFXOClock;\r
+#else\r
+ /* We should not get here, since core should not be clocked. May */\r
+ /* be caused by a misconfiguration though. */\r
+ ret = 0;\r
+#endif\r
+ break;\r
+\r
+ default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */\r
+ ret = SystemHfrcoFreq;\r
+ break;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get high frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * HFXO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemHFXOClockGet(void)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_HFXO_FREQ > 0)\r
+ return SystemHFXOClock;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Set high frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This function is mainly provided for being able to handle target systems\r
+ * with different HF crystal oscillator frequencies run-time. If used, it\r
+ * should probably only be used once during system startup.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @param[in] freq\r
+ * HFXO frequency in Hz used for target.\r
+ *****************************************************************************/\r
+void SystemHFXOClockSet(uint32_t freq)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_HFXO_FREQ > 0)\r
+ SystemHFXOClock = freq;\r
+\r
+ /* Update core clock frequency if HFXO is used to clock core */\r
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO)\r
+ {\r
+ /* The function will update the global variable */\r
+ SystemCoreClockGet();\r
+ }\r
+#else\r
+ (void)freq; /* Unused parameter */\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Initialize the system.\r
+ *\r
+ * @details\r
+ * Do required generic HW system init.\r
+ *\r
+ * @note\r
+ * This function is invoked during system init, before the main() routine\r
+ * and any data has been initialized. For this reason, it cannot do any\r
+ * initialization of variables etc.\r
+ *****************************************************************************/\r
+void SystemInit(void)\r
+{\r
+#if (__FPU_PRESENT == 1)\r
+ /* Set floating point coprosessor access mode. */\r
+ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */\r
+ (3UL << 11 * 2)); /* set CP11 Full Access */\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get low frequency RC oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * LFRCO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemLFRCOClockGet(void)\r
+{\r
+ /* Currently we assume that this frequency is properly tuned during */\r
+ /* manufacturing and is not changed after reset. If future requirements */\r
+ /* for re-tuning by user, we can add support for that. */\r
+ return EFM32_LFRCO_FREQ;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get ultra low frequency RC oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * ULFRCO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemULFRCOClockGet(void)\r
+{\r
+ /* The ULFRCO frequency is not tuned, and can be very inaccurate */\r
+ return EFM32_ULFRCO_FREQ;\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get low frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * LFXO frequency in Hz.\r
+ *****************************************************************************/\r
+uint32_t SystemLFXOClockGet(void)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_LFXO_FREQ > 0)\r
+ return SystemLFXOClock;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Set low frequency crystal oscillator clock frequency for target system.\r
+ *\r
+ * @note\r
+ * This function is mainly provided for being able to handle target systems\r
+ * with different HF crystal oscillator frequencies run-time. If used, it\r
+ * should probably only be used once during system startup.\r
+ *\r
+ * @note\r
+ * This is an EFM32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @param[in] freq\r
+ * LFXO frequency in Hz used for target.\r
+ *****************************************************************************/\r
+void SystemLFXOClockSet(uint32_t freq)\r
+{\r
+ /* External crystal oscillator present? */\r
+#if (EFM32_LFXO_FREQ > 0)\r
+ SystemLFXOClock = freq;\r
+\r
+ /* Update core clock frequency if LFXO is used to clock core */\r
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO)\r
+ {\r
+ /* The function will update the global variable */\r
+ SystemCoreClockGet();\r
+ }\r
+#else\r
+ (void)freq; /* Unused parameter */\r
+#endif\r
+}\r
* @file efm32wg990f256.h\r
* @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
* for EFM32WG990F256\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
*****************************************************************************/\r
\r
-#ifndef __SILICON_LABS_EFM32WG990F256_H__\r
-#define __SILICON_LABS_EFM32WG990F256_H__\r
+#ifndef EFM32WG990F256_H\r
+#define EFM32WG990F256_H\r
\r
#ifdef __cplusplus\r
extern "C" {\r
#ifdef __cplusplus\r
}\r
#endif\r
-#endif /* __SILICON_LABS_EFM32WG990F256_H__ */\r
+#endif /* EFM32WG990F256_H */\r
/**************************************************************************//**\r
* @file efm32wg_acmp.h\r
* @brief EFM32WG_ACMP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_ACMP\r
* @{\r
#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */\r
\r
/** @} End of group EFM32WG_ACMP */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_adc.h\r
* @brief EFM32WG_ADC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_ADC\r
* @{\r
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
\r
/** @} End of group EFM32WG_ADC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_aes.h\r
* @brief EFM32WG_AES register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_AES\r
* @{\r
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */\r
\r
/** @} End of group EFM32WG_AES */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_af_pins.h\r
* @brief EFM32WG_AF_PINS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_AF_Pins\r
* @{\r
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : -1)\r
\r
/** @} End of group EFM32WG_AF_Pins */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_af_ports.h\r
* @brief EFM32WG_AF_PORTS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_AF_Ports\r
* @{\r
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : -1)\r
\r
/** @} End of group EFM32WG_AF_Ports */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_burtc.h\r
* @brief EFM32WG_BURTC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_BURTC\r
* @{\r
#define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */\r
\r
/** @} End of group EFM32WG_BURTC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_burtc_ret.h\r
* @brief EFM32WG_BURTC_RET register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief BURTC_RET EFM32WG BURTC RET\r
*****************************************************************************/\r
__IO uint32_t REG; /**< Retention Register */\r
} BURTC_RET_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_calibrate.h\r
* @brief EFM32WG_CALIBRATE register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_CALIBRATE\r
* @{\r
__I uint32_t VALUE; /**< Default value for calibration register */\r
} CALIBRATE_TypeDef; /** @} */\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_cmu.h\r
* @brief EFM32WG_CMU register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_CMU\r
* @{\r
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
\r
/** @} End of group EFM32WG_CMU */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_dac.h\r
* @brief EFM32WG_DAC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_DAC\r
* @{\r
#define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */\r
\r
/** @} End of group EFM32WG_DAC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_devinfo.h\r
* @brief EFM32WG_DEVINFO register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_DEVINFO\r
* @{\r
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */\r
\r
/** @} End of group EFM32WG_DEVINFO */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_dma.h\r
* @brief EFM32WG_DMA register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_DMA\r
* @{\r
#define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for DMA_CH_CTRL */\r
\r
/** @} End of group EFM32WG_DMA */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_dma_ch.h\r
* @brief EFM32WG_DMA_CH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief DMA_CH EFM32WG DMA CH\r
*****************************************************************************/\r
__IO uint32_t CTRL; /**< Channel Control Register */\r
} DMA_CH_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_dma_descriptor.h\r
* @brief EFM32WG_DMA_DESCRIPTOR register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_DMA_DESCRIPTOR\r
* @{\r
__IO uint32_t USER; /**< DMA padding register, available for user */\r
} DMA_DESCRIPTOR_TypeDef; /** @} */\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_dmactrl.h\r
* @brief EFM32WG_DMACTRL register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
\r
/**************************************************************************//**\r
* @defgroup EFM32WG_DMACTRL_BitFields\r
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */\r
\r
/** @} End of group EFM32WG_DMA */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_dmareq.h\r
* @brief EFM32WG_DMAREQ register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
\r
/**************************************************************************//**\r
* @defgroup EFM32WG_DMAREQ_BitFields\r
#define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */\r
\r
/** @} End of group EFM32WG_DMAREQ */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_ebi.h\r
* @brief EFM32WG_EBI register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_EBI\r
* @{\r
#define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */\r
\r
/** @} End of group EFM32WG_EBI */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_emu.h\r
* @brief EFM32WG_EMU register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_EMU\r
* @{\r
#define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */\r
\r
/** @} End of group EFM32WG_EMU */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_etm.h\r
* @brief EFM32WG_ETM register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_ETM\r
* @{\r
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */\r
\r
/** @} End of group EFM32WG_ETM */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_fpueh.h\r
* @brief EFM32WG_FPUEH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_FPUEH\r
* @{\r
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */\r
\r
/** @} End of group EFM32WG_FPUEH */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_gpio.h\r
* @brief EFM32WG_GPIO register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_GPIO\r
* @{\r
#define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUCAUSE */\r
\r
/** @} End of group EFM32WG_GPIO */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_gpio_p.h\r
* @brief EFM32WG_GPIO_P register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief GPIO_P EFM32WG GPIO P\r
*****************************************************************************/\r
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */\r
} GPIO_P_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_i2c.h\r
* @brief EFM32WG_I2C register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_I2C\r
* @{\r
#define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */\r
\r
/** @} End of group EFM32WG_I2C */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_lcd.h\r
* @brief EFM32WG_LCD register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_LCD\r
* @{\r
#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */\r
\r
/** @} End of group EFM32WG_LCD */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_lesense.h\r
* @brief EFM32WG_LESENSE register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_LESENSE\r
* @{\r
#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */\r
\r
/** @} End of group EFM32WG_LESENSE */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_lesense_buf.h\r
* @brief EFM32WG_LESENSE_BUF register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief LESENSE_BUF EFM32WG LESENSE BUF\r
*****************************************************************************/\r
__IO uint32_t DATA; /**< Scan results */\r
} LESENSE_BUF_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_lesense_ch.h\r
* @brief EFM32WG_LESENSE_CH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief LESENSE_CH EFM32WG LESENSE CH\r
*****************************************************************************/\r
uint32_t RESERVED0[1]; /**< Reserved future */\r
} LESENSE_CH_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_lesense_st.h\r
* @brief EFM32WG_LESENSE_ST register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief LESENSE_ST EFM32WG LESENSE ST\r
*****************************************************************************/\r
__IO uint32_t TCONFB; /**< State transition configuration B */\r
} LESENSE_ST_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_letimer.h\r
* @brief EFM32WG_LETIMER register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_LETIMER\r
* @{\r
#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */\r
\r
/** @} End of group EFM32WG_LETIMER */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_leuart.h\r
* @brief EFM32WG_LEUART register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_LEUART\r
* @{\r
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */\r
\r
/** @} End of group EFM32WG_LEUART */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_msc.h\r
* @brief EFM32WG_MSC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_MSC\r
* @{\r
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */\r
\r
/** @} End of group EFM32WG_MSC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_pcnt.h\r
* @brief EFM32WG_PCNT register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_PCNT\r
* @{\r
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */\r
\r
/** @} End of group EFM32WG_PCNT */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_prs.h\r
* @brief EFM32WG_PRS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_PRS\r
* @{\r
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
\r
/** @} End of group EFM32WG_PRS */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_prs_ch.h\r
* @brief EFM32WG_PRS_CH register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief PRS_CH EFM32WG PRS CH\r
*****************************************************************************/\r
__IO uint32_t CTRL; /**< Channel Control Register */\r
} PRS_CH_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_prs_signals.h\r
* @brief EFM32WG_PRS_SIGNALS register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @addtogroup EFM32WG_PRS_Signals\r
* @{\r
#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
\r
/** @} End of group EFM32WG_PRS */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_rmu.h\r
* @brief EFM32WG_RMU register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_RMU\r
* @{\r
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */\r
\r
/** @} End of group EFM32WG_RMU */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_romtable.h\r
* @brief EFM32WG_ROMTABLE register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_ROMTABLE\r
* @{\r
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */\r
\r
/** @} End of group EFM32WG_ROMTABLE */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_rtc.h\r
* @brief EFM32WG_RTC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_RTC\r
* @{\r
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */\r
\r
/** @} End of group EFM32WG_RTC */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_timer.h\r
* @brief EFM32WG_TIMER register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_TIMER\r
* @{\r
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */\r
\r
/** @} End of group EFM32WG_TIMER */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_timer_cc.h\r
* @brief EFM32WG_TIMER_CC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief TIMER_CC EFM32WG TIMER CC\r
*****************************************************************************/\r
__IO uint32_t CCVB; /**< CC Channel Buffer Register */\r
} TIMER_CC_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_uart.h\r
* @brief EFM32WG_UART register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
\r
/**************************************************************************//**\r
* @defgroup EFM32WG_UART_BitFields\r
#define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */\r
\r
/** @} End of group EFM32WG_UART */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_usart.h\r
* @brief EFM32WG_USART register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_USART\r
* @{\r
#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */\r
\r
/** @} End of group EFM32WG_USART */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_usb.h\r
* @brief EFM32WG_USB register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_USB\r
* @{\r
#define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */\r
\r
/** @} End of group EFM32WG_USB */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_usb_diep.h\r
* @brief EFM32WG_USB_DIEP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief USB_DIEP EFM32WG USB DIEP\r
*****************************************************************************/\r
uint32_t RESERVED2[1]; /**< Reserved future */\r
} USB_DIEP_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_usb_doep.h\r
* @brief EFM32WG_USB_DOEP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief USB_DOEP EFM32WG USB DOEP\r
*****************************************************************************/\r
uint32_t RESERVED2[2]; /**< Reserved future */\r
} USB_DOEP_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_usb_hc.h\r
* @brief EFM32WG_USB_HC register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @brief USB_HC EFM32WG USB HC\r
*****************************************************************************/\r
uint32_t RESERVED1[2]; /**< Reserved future */\r
} USB_HC_TypeDef;\r
\r
+/** @} End of group Parts */\r
+\r
+\r
/**************************************************************************//**\r
* @file efm32wg_vcmp.h\r
* @brief EFM32WG_VCMP register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_VCMP\r
* @{\r
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */\r
\r
/** @} End of group EFM32WG_VCMP */\r
-\r
+/** @} End of group Parts */\r
\r
/**************************************************************************//**\r
* @file efm32wg_wdog.h\r
* @brief EFM32WG_WDOG register and bit field definitions\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* any third party, arising from your use of this Software.\r
*\r
*****************************************************************************/\r
+/**************************************************************************//**\r
+* @addtogroup Parts\r
+* @{\r
+******************************************************************************/\r
/**************************************************************************//**\r
* @defgroup EFM32WG_WDOG\r
* @{\r
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
\r
/** @} End of group EFM32WG_WDOG */\r
-\r
+/** @} End of group Parts */\r
\r
*\r
*\r
* @endverbatim\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
*****************************************************************************/\r
\r
-#ifndef __SILICON_LABS_EM_DEVICE_H__\r
-#define __SILICON_LABS_EM_DEVICE_H__\r
+#ifndef EM_DEVICE_H\r
+#define EM_DEVICE_H\r
\r
#if defined(EFM32WG230F128)\r
#include "efm32wg230f128.h"\r
#else\r
#error "em_device.h: PART NUMBER undefined"\r
#endif\r
-#endif /* __SILICON_LABS_EM_DEVICE_H__ */\r
+#endif /* EM_DEVICE_H */\r
/***************************************************************************//**\r
* @file system_efm32wg.h\r
* @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
*****************************************************************************/\r
\r
-#ifndef __SYSTEM_EFM32WG_H\r
-#define __SYSTEM_EFM32WG_H\r
+#ifndef SYSTEM_EFM32WG_H\r
+#define SYSTEM_EFM32WG_H\r
\r
#ifdef __cplusplus\r
extern "C" {\r
******************************************************************************/\r
\r
/* Interrupt routines - prototypes */\r
-#if defined(_EFM32_WONDER_FAMILY)\r
void Reset_Handler(void);\r
void NMI_Handler(void);\r
void HardFault_Handler(void);\r
void DebugMon_Handler(void);\r
void PendSV_Handler(void);\r
void SysTick_Handler(void);\r
+\r
void DMA_IRQHandler(void);\r
void GPIO_EVEN_IRQHandler(void);\r
void TIMER0_IRQHandler(void);\r
void EBI_IRQHandler(void);\r
void EMU_IRQHandler(void);\r
void FPUEH_IRQHandler(void);\r
-#endif\r
\r
uint32_t SystemCoreClockGet(void);\r
+uint32_t SystemMaxCoreClockGet(void);\r
\r
/**************************************************************************//**\r
* @brief\r
#ifdef __cplusplus\r
}\r
#endif\r
-#endif /* __SYSTEM_EFM32WG_H */\r
+#endif /* SYSTEM_EFM32WG_H */\r
/* */\r
/* Silicon Laboratories, Inc. 2015 */\r
/* */\r
-/* Version 4.0.0 */\r
+/* Version 4.2.0 */\r
/* */\r
\r
MEMORY\r
/* @file startup_efm32wg.S\r
* @brief startup file for Silicon Labs EFM32WG devices.\r
* For use with GCC for ARM Embedded Processors\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
* Date: 12 June 2014\r
*\r
*/\r
.long SysTick_Handler /* SysTick Handler */\r
\r
/* External interrupts */\r
+\r
.long DMA_IRQHandler /* 0 - DMA */\r
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */\r
.long TIMER0_IRQHandler /* 2 - TIMER0 */\r
* @file startup_efm32wg.c\r
* @brief CMSIS Compatible EFM32WG startup file in C.\r
* Should be used with GCC 'GNU Tools ARM Embedded'\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
* Date: 12 June 2014\r
*\r
*/\r
SysTick_Handler, /* SysTick Handler */\r
\r
/* External interrupts */\r
+\r
DMA_IRQHandler, /* 0 - DMA */\r
GPIO_EVEN_IRQHandler, /* 1 - GPIO_EVEN */\r
TIMER0_IRQHandler, /* 2 - TIMER0 */\r
/***************************************************************************//**\r
* @file system_efm32wg.c\r
* @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
/* SW footprint. */\r
\r
#ifndef EFM32_HFXO_FREQ\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
-#define EFM32_HFXO_FREQ (48000000UL) \r
-#else\r
-#define EFM32_HFXO_FREQ (32000000UL)\r
-#endif\r
+#define EFM32_HFXO_FREQ (48000000UL)\r
#endif\r
+\r
+#define EFM32_HFRCO_MAX_FREQ (28000000UL)\r
+\r
/* Do not define variable if HF crystal oscillator not present */\r
#if (EFM32_HFXO_FREQ > 0)\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
-/** System HFXO clock. */ \r
+/** System HFXO clock. */\r
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;\r
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
#endif\r
\r
-#ifndef EFM32_LFXO_FREQ \r
+#ifndef EFM32_LFXO_FREQ\r
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)\r
#endif\r
+\r
/* Do not define variable if LF crystal oscillator not present */\r
#if (EFM32_LFXO_FREQ > 0)\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
-/** System LFXO clock. */ \r
+/** System LFXO clock. */\r
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;\r
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */\r
#endif\r
uint32_t SystemCoreClockGet(void)\r
{\r
uint32_t ret;\r
- \r
+\r
ret = SystemHFClockGet();\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
/* Leopard/Giant/Wonder Gecko has an additional divider */\r
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));\r
-#endif\r
- ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> \r
+ ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>\r
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;\r
\r
/* Keep CMSIS variable up-to-date just in case */\r
}\r
\r
\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the maximum core clock frequency.\r
+ *\r
+ * @note\r
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.\r
+ *\r
+ * @return\r
+ * The maximum core clock frequency in Hz.\r
+ ******************************************************************************/\r
+uint32_t SystemMaxCoreClockGet(void)\r
+{\r
+ return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \\r
+ EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);\r
+}\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Get the current HFCLK frequency.\r
uint32_t SystemHFClockGet(void)\r
{\r
uint32_t ret;\r
- \r
+\r
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |\r
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))\r
{\r
ret = 0;\r
#endif\r
break;\r
- \r
+\r
case CMU_STATUS_LFRCOSEL:\r
ret = EFM32_LFRCO_FREQ;\r
break;\r
- \r
+\r
case CMU_STATUS_HFXOSEL:\r
#if (EFM32_HFXO_FREQ > 0)\r
ret = SystemHFXOClock;\r
ret = 0;\r
#endif\r
break;\r
- \r
+\r
default: /* CMU_STATUS_HFRCOSEL */\r
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)\r
{\r
/***************************************************************************//**\r
* @file em_assert.c\r
* @brief Assert API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
/***************************************************************************//**\r
* @file em_burtc.c\r
* @brief Backup Real Time Counter (BURTC) Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
******************************************************************************/\r
\r
\r
-#include "em_device.h"\r
-#if defined(BURTC_PRESENT)\r
#include "em_burtc.h"\r
-\r
-#include "em_assert.h"\r
-#include "em_bitband.h"\r
+#if defined(BURTC_PRESENT)\r
\r
/***************************************************************************//**\r
* @addtogroup EM_Library\r
************************** LOCAL FUNCTIONS ********************************\r
******************************************************************************/\r
\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
/***************************************************************************//**\r
* @brief Convert dividend to prescaler logarithmic value. Only works for even\r
* numbers equal to 2^n\r
* @param[in] div Unscaled dividend,\r
* @return Base 2 logarithm of input, as used by fixed prescalers\r
******************************************************************************/\r
-__STATIC_INLINE uint32_t BURTC_DivToLog2(uint32_t div)\r
+__STATIC_INLINE uint32_t divToLog2(uint32_t div)\r
{\r
uint32_t log2;\r
\r
* Bitmask corresponding to SYNCBUSY register defined bits, indicating\r
* registers that must complete any ongoing synchronization.\r
******************************************************************************/\r
-__STATIC_INLINE void BURTC_Sync(uint32_t mask)\r
+__STATIC_INLINE void regSync(uint32_t mask)\r
{\r
/* Avoid deadlock if modifying the same register twice when freeze mode is\r
activated, or when no clock is selected for the BURTC. If no clock is\r
while (BURTC->SYNCBUSY & mask)\r
;\r
}\r
+/** @endcond */\r
\r
\r
/*******************************************************************************\r
* Before initialization, BURTC module must first be enabled by clearing the\r
* reset bit in the RMU, i.e.\r
* @verbatim\r
- * RMU_ResetControl(rmuResetBU, false);\r
+ * RMU_ResetControl(rmuResetBU, rmuResetModeClear);\r
* @endverbatim\r
* Compare channel 0 must be configured outside this function, before\r
* initialization if enable is set to true. The counter will always be reset.\r
EFM_ASSERT(burtcInit->lowPowerComp <= 6);\r
/* You cannot enable the BURTC if mode is set to disabled */\r
EFM_ASSERT((burtcInit->enable == false) ||\r
- ((burtcInit->enable == true) && (burtcInit->mode != burtcModeDisable)));\r
+ ((burtcInit->enable == true)\r
+ && (burtcInit->mode != burtcModeDisable)));\r
/* Low power mode is only available with LFRCO or LFXO as clock source */\r
- EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) ||\r
- ((burtcInit->clkSel == burtcClkSelULFRCO) && (burtcInit->lowPowerMode == burtcLPDisable)));\r
+ EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO)\r
+ || ((burtcInit->clkSel == burtcClkSelULFRCO)\r
+ && (burtcInit->lowPowerMode == burtcLPDisable)));\r
\r
/* Calculate prescaler value from clock divider input */\r
/* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of\r
value 1 will select a 2kHz ULFRCO clock, while any other value will\r
select a 1kHz ULFRCO clock source. */\r
- presc = BURTC_DivToLog2(burtcInit->clkDiv);\r
+ presc = divToLog2(burtcInit->clkDiv);\r
\r
/* Make sure all registers are updated simultaneously */\r
if (burtcInit->enable)\r
\r
/* Modification of LPMODE register requires sync with potential ongoing\r
* register updates in LF domain. */\r
- BURTC_Sync(BURTC_SYNCBUSY_LPMODE);\r
+ regSync(BURTC_SYNCBUSY_LPMODE);\r
\r
/* Configure low power mode */\r
BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode);\r
\r
/* New configuration */\r
- ctrl = ((BURTC_CTRL_RSTEN) |\r
- (burtcInit->mode) |\r
- (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) |\r
- (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) |\r
- (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) |\r
- (presc << _BURTC_CTRL_PRESC_SHIFT) |\r
- (burtcInit->clkSel) |\r
- (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));\r
+ ctrl = (BURTC_CTRL_RSTEN\r
+ | (burtcInit->mode)\r
+ | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT)\r
+ | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT)\r
+ | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT)\r
+ | (presc << _BURTC_CTRL_PRESC_SHIFT)\r
+ | (burtcInit->clkSel)\r
+ | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT));\r
\r
/* Clear interrupts */\r
BURTC_IntClear(0xFFFFFFFF);\r
\r
/* Modification of COMP0 register requires sync with potential ongoing\r
* register updates in LF domain. */\r
- BURTC_Sync(BURTC_SYNCBUSY_COMP0);\r
+ regSync(BURTC_SYNCBUSY_COMP0);\r
\r
/* Configure compare channel 0 */\r
BURTC->COMP0 = value;\r
void BURTC_CounterReset(void)\r
{\r
/* Set and clear reset bit */\r
- BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);\r
- BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);\r
+ BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);\r
+ BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);\r
}\r
\r
\r
bool buResetState;\r
\r
/* Read reset state, set reset and restore state */\r
- buResetState = BITBAND_PeripheralRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);\r
- BITBAND_Peripheral(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);\r
- BITBAND_Peripheral(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);\r
+ buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);\r
+ BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);\r
+ BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);\r
}\r
\r
\r
\r
switch (clkSel)\r
{\r
- /** Ultra low frequency (1 kHz) clock */\r
- case BURTC_CTRL_CLKSEL_ULFRCO:\r
- if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)\r
- {\r
- frequency = 2000; /* 2KHz when clock divisor is 1. */\r
- }\r
- else\r
- {\r
- frequency = SystemULFRCOClockGet(); /* 1KHz when divisor is different\r
- from 1. */\r
- }\r
- break;\r
-\r
- /** Low frequency RC oscillator */\r
- case BURTC_CTRL_CLKSEL_LFRCO:\r
- frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */\r
- break;\r
-\r
- /** Low frequency crystal osciallator */\r
- case BURTC_CTRL_CLKSEL_LFXO:\r
- frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */\r
- break;\r
-\r
- default:\r
- /* No clock selected for BURTC. */\r
- frequency = 0;\r
+ /** Ultra low frequency (1 kHz) clock */\r
+ case BURTC_CTRL_CLKSEL_ULFRCO:\r
+ if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)\r
+ {\r
+ frequency = 2000; /* 2KHz when clock divisor is 1. */\r
+ }\r
+ else\r
+ {\r
+ frequency = SystemULFRCOClockGet(); /* 1KHz when divisor is different\r
+ from 1. */\r
+ }\r
+ break;\r
+\r
+ /** Low frequency RC oscillator */\r
+ case BURTC_CTRL_CLKSEL_LFRCO:\r
+ frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */\r
+ break;\r
+\r
+ /** Low frequency crystal osciallator */\r
+ case BURTC_CTRL_CLKSEL_LFXO:\r
+ frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */\r
+ break;\r
+\r
+ default:\r
+ /* No clock selected for BURTC. */\r
+ frequency = 0;\r
}\r
return frequency;\r
}\r
/***************************************************************************//**\r
* @file em_cmu.c\r
* @brief Clock management unit (CMU) Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* arising from your use of this Software.\r
*\r
******************************************************************************/\r
-\r
-\r
#include "em_cmu.h"\r
#if defined( CMU_PRESENT )\r
\r
+#include <stddef.h>\r
+#include <limits.h>\r
#include "em_assert.h"\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
#include "em_emu.h"\r
+#include "em_system.h"\r
\r
/***************************************************************************//**\r
* @addtogroup EM_Library\r
\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
\r
-/** Maximum allowed core frequency when using 0 wait states on flash access. */\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+/** Maximum allowed core frequency when using 0 wait-states on flash access. */\r
+#define CMU_MAX_FREQ_0WS 26000000\r
+/** Maximum allowed core frequency when using 1 wait-states on flash access */\r
+#define CMU_MAX_FREQ_1WS 40000000\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+/** Maximum allowed core frequency when using 0 wait-states on flash access. */\r
#define CMU_MAX_FREQ_0WS 16000000\r
-/** Maximum allowed core frequency when using 1 wait states on flash access */\r
+/** Maximum allowed core frequency when using 1 wait-states on flash access */\r
#define CMU_MAX_FREQ_1WS 32000000\r
+#else\r
+#error "Unkown MCU platform."\r
+#endif\r
\r
#if defined( CMU_CTRL_HFLE )\r
/** Maximum frequency for HFLE needs to be enabled on Giant, Leopard and\r
Wonder. */\r
-#if defined ( _EFM32_WONDER_FAMILY ) || \\r
- defined ( _EZR32_LEOPARD_FAMILY ) || \\r
- defined ( _EZR32_WONDER_FAMILY )\r
-#define CMU_MAX_FREQ_HFLE 24000000\r
+#if defined( _EFM32_WONDER_FAMILY ) \\r
+ || defined( _EZR32_LEOPARD_FAMILY ) \\r
+ || defined( _EZR32_WONDER_FAMILY )\r
+#define CMU_MAX_FREQ_HFLE() 24000000\r
#elif defined ( _EFM32_GIANT_FAMILY )\r
-#define CMU_MAX_FREQ_HFLE (CMU_MaxFreqHfle())\r
+#define CMU_MAX_FREQ_HFLE() (maxFreqHfle())\r
#else\r
#error Invalid part/device.\r
#endif\r
#endif\r
\r
-/** Low frequency A group identifier */\r
-#define CMU_LFA 0\r
+/*******************************************************************************\r
+ ************************** LOCAL VARIABLES ********************************\r
+ ******************************************************************************/\r
\r
-/** Low frequency B group identifier */\r
-#define CMU_LFB 1\r
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
+static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;\r
+#endif\r
\r
/** @endcond */\r
\r
\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
\r
-#if defined( CMU_CTRL_HFLE ) && \\r
- !defined ( _EFM32_WONDER_FAMILY ) && \\r
- !defined ( _EZR32_LEOPARD_FAMILY ) && \\r
- !defined ( _EZR32_WONDER_FAMILY )\r
-\r
/***************************************************************************//**\r
* @brief\r
- * Return max allowed frequency for low energy peripherals.\r
+ * Get the AUX clock frequency. Used by MSC flash programming and LESENSE,\r
+ * by default also as debug clock.\r
+ *\r
+ * @return\r
+ * AUX Frequency in Hz\r
******************************************************************************/\r
-static uint32_t CMU_MaxFreqHfle(void)\r
+static uint32_t auxClkGet(void)\r
{\r
- /* SYSTEM_GetFamily and SYSTEM_ChipRevisionGet could have been used here\r
- but we want to minimize dependencies in em_cmu.c. */\r
- uint16_t majorMinorRev;\r
- uint8_t deviceFamily = ((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK)\r
- >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);\r
- switch (deviceFamily)\r
+ uint32_t ret;\r
+\r
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
+ ret = auxHfrcoFreq;\r
+\r
+#elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
+ /* All Geckos from TG and newer */\r
+ switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)\r
{\r
- case _DEVINFO_PART_DEVICE_FAMILY_LG:\r
- /* CHIP MAJOR bit [3:0] */\r
- majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)\r
- >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);\r
- /* CHIP MINOR bit [7:4] */\r
- majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)\r
- >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);\r
- /* CHIP MINOR bit [3:0] */\r
- majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)\r
- >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);\r
-\r
- if (majorMinorRev >= 0x0204)\r
- return 24000000;\r
- else\r
- return 32000000;\r
- case _DEVINFO_PART_DEVICE_FAMILY_GG:\r
- return 32000000;\r
- case _DEVINFO_PART_DEVICE_FAMILY_WG:\r
- return 24000000;\r
- default:\r
- /* Invalid device family. */\r
- EFM_ASSERT(false);\r
- return 0;\r
+ case CMU_AUXHFRCOCTRL_BAND_1MHZ:\r
+ ret = 1000000;\r
+ break;\r
+\r
+ case CMU_AUXHFRCOCTRL_BAND_7MHZ:\r
+ ret = 7000000;\r
+ break;\r
+\r
+ case CMU_AUXHFRCOCTRL_BAND_11MHZ:\r
+ ret = 11000000;\r
+ break;\r
+\r
+ case CMU_AUXHFRCOCTRL_BAND_14MHZ:\r
+ ret = 14000000;\r
+ break;\r
+\r
+ case CMU_AUXHFRCOCTRL_BAND_21MHZ:\r
+ ret = 21000000;\r
+ break;\r
+\r
+#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )\r
+ case CMU_AUXHFRCOCTRL_BAND_28MHZ:\r
+ ret = 28000000;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0;\r
+ break;\r
}\r
+\r
+#else\r
+ /* Gecko has a fixed 14Mhz AUXHFRCO clock */\r
+ ret = 14000000;\r
+\r
+#endif\r
+\r
+ return ret;\r
}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the Debug Trace clock frequency\r
+ *\r
+ * @return\r
+ * Debug Trace frequency in Hz\r
+ ******************************************************************************/\r
+static uint32_t dbgClkGet(void)\r
+{\r
+ uint32_t ret;\r
+ CMU_Select_TypeDef clk;\r
+\r
+ /* Get selected clock source */\r
+ clk = CMU_ClockSelectGet(cmuClock_DBG);\r
+\r
+ switch(clk)\r
+ {\r
+ case cmuSelect_HFCLK:\r
+ ret = SystemHFClockGet();\r
+#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
+ /* Family with an additional divider. */\r
+ ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)\r
+ >> _CMU_CTRL_HFCLKDIV_SHIFT));\r
#endif\r
+ break;\r
+\r
+ case cmuSelect_AUXHFRCO:\r
+ ret = auxClkGet();\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0;\r
+ break;\r
+ }\r
+ return ret;\r
+}\r
\r
\r
/***************************************************************************//**\r
* Configure flash access wait states in order to support given core clock\r
* frequency.\r
*\r
- * @param[in] hfcoreclk\r
+ * @param[in] coreFreq\r
* Core clock frequency to configure flash wait-states for\r
******************************************************************************/\r
-static void CMU_FlashWaitStateControl(uint32_t hfcoreclk)\r
+static void flashWaitStateControl(uint32_t coreFreq)\r
{\r
uint32_t mode;\r
bool mscLocked;\r
#if defined( MSC_READCTRL_MODE_WS0SCBTP )\r
- bool scbtpEn;\r
+ bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */\r
#endif\r
\r
/* Make sure the MSC is unlocked */\r
{\r
}\r
#if defined( MSC_READCTRL_MODE_WS2 )\r
- else if (hfcoreclk > CMU_MAX_FREQ_1WS)\r
+ else if (coreFreq > CMU_MAX_FREQ_1WS)\r
{\r
mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);\r
}\r
#endif\r
- else if ((hfcoreclk <= CMU_MAX_FREQ_1WS) && (hfcoreclk > CMU_MAX_FREQ_0WS))\r
+ else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))\r
{\r
mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1);\r
}\r
{\r
}\r
#if defined( MSC_READCTRL_MODE_WS2 )\r
- else if (hfcoreclk > CMU_MAX_FREQ_1WS)\r
+ else if (coreFreq > CMU_MAX_FREQ_1WS)\r
{\r
mode = MSC_READCTRL_MODE_WS2;\r
}\r
#endif\r
- else if ((hfcoreclk <= CMU_MAX_FREQ_1WS) && (hfcoreclk > CMU_MAX_FREQ_0WS))\r
+ else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))\r
{\r
mode = MSC_READCTRL_MODE_WS1;\r
}\r
/***************************************************************************//**\r
* @brief\r
* Configure flash access wait states to most conservative setting for\r
- * this target. Retain SCBTP setting.\r
+ * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch)\r
+ * setting.\r
+ ******************************************************************************/\r
+static void flashWaitStateMax(void)\r
+{\r
+ flashWaitStateControl(SystemMaxCoreClockGet());\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the LFnCLK frequency based on current configuration.\r
+ *\r
+ * @param[in] lfClkBranch\r
+ * Selected LF branch\r
+ *\r
+ * @return\r
+ * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is\r
+ * returned.\r
******************************************************************************/\r
-static void CMU_FlashWaitStateMax(void)\r
+static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch)\r
{\r
- uint32_t maxCoreClock;\r
-#if defined (_EFM32_GECKO_FAMILY)\r
- maxCoreClock = 32000000;\r
-#elif defined (_EFM32_GIANT_FAMILY)\r
- maxCoreClock = 48000000;\r
-#elif defined (_EFM32_TINY_FAMILY)\r
- maxCoreClock = 32000000;\r
-#elif defined (_EFM32_LEOPARD_FAMILY)\r
- maxCoreClock = 48000000;\r
-#elif defined (_EFM32_WONDER_FAMILY)\r
- maxCoreClock = 48000000;\r
-#elif defined (_EFM32_ZERO_FAMILY)\r
- maxCoreClock = 24000000;\r
-#elif defined (_EFM32_HAPPY_FAMILY)\r
- maxCoreClock = 25000000;\r
+ uint32_t sel;\r
+ uint32_t ret = 0;\r
+\r
+ switch (lfClkBranch)\r
+ {\r
+ case cmuClock_LFA:\r
+ case cmuClock_LFB:\r
+#if defined( _CMU_LFCCLKEN0_MASK )\r
+ case cmuClock_LFC:\r
+#endif\r
+#if defined( _CMU_LFECLKSEL_MASK )\r
+ case cmuClock_LFE:\r
+#endif\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+\r
+ sel = CMU_ClockSelectGet(lfClkBranch);\r
+\r
+ /* Get clock select field */\r
+ switch (lfClkBranch)\r
+ {\r
+ case cmuClock_LFA:\r
+#if defined( _CMU_LFCLKSEL_MASK )\r
+ sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;\r
+#elif defined( _CMU_LFACLKSEL_MASK )\r
+ sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;\r
+#else\r
+ EFM_ASSERT(0);\r
+#endif\r
+ break;\r
+\r
+ case cmuClock_LFB:\r
+#if defined( _CMU_LFCLKSEL_MASK )\r
+ sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;\r
+#elif defined( _CMU_LFBCLKSEL_MASK )\r
+ sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;\r
+#else\r
+ EFM_ASSERT(0);\r
+#endif\r
+ break;\r
+\r
+#if defined( _CMU_LFCCLKEN0_MASK )\r
+ case cmuClock_LFC:\r
+ sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFECLKSEL_MASK )\r
+ case cmuClock_LFE:\r
+ sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+\r
+ /* Get clock frequency */\r
+#if defined( _CMU_LFCLKSEL_MASK )\r
+ switch (sel)\r
+ {\r
+ case _CMU_LFCLKSEL_LFA_LFRCO:\r
+ ret = SystemLFRCOClockGet();\r
+ break;\r
+\r
+ case _CMU_LFCLKSEL_LFA_LFXO:\r
+ ret = SystemLFXOClockGet();\r
+ break;\r
+\r
+#if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )\r
+ case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:\r
+#if defined( CMU_CTRL_HFLE )\r
+ /* Family which can use an extra div 4 divider */\r
+ /* (and must if >32MHz) or HFLE is set. */\r
+ if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK)\r
+ == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)\r
+ || (CMU->CTRL & CMU_CTRL_HFLE))\r
+ {\r
+ ret = SystemCoreClockGet() / 4U;\r
+ }\r
+ else\r
+ {\r
+ ret = SystemCoreClockGet() / 2U;\r
+ }\r
#else\r
-#error "Max core clock frequency is not defined for this family"\r
+ ret = SystemCoreClockGet() / 2U;\r
+#endif\r
+ break;\r
+#endif\r
+\r
+ case _CMU_LFCLKSEL_LFA_DISABLED:\r
+ ret = 0;\r
+#if defined( CMU_LFCLKSEL_LFAE )\r
+ /* Check LF Extended bit setting for LFA or LFB ULFRCO clock */\r
+ if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB))\r
+ {\r
+ if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA\r
+ ? _CMU_LFCLKSEL_LFAE_SHIFT\r
+ : _CMU_LFCLKSEL_LFBE_SHIFT))\r
+ {\r
+ ret = SystemULFRCOClockGet();\r
+ }\r
+ }\r
+#endif\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0U;\r
+ break;\r
+ }\r
+#endif /* _CMU_LFCLKSEL_MASK */\r
+\r
+#if defined( _CMU_LFACLKSEL_MASK )\r
+ switch (sel)\r
+ {\r
+ case _CMU_LFACLKSEL_LFA_LFRCO:\r
+ ret = SystemLFRCOClockGet();\r
+ break;\r
+\r
+ case _CMU_LFACLKSEL_LFA_LFXO:\r
+ ret = SystemLFXOClockGet();\r
+ break;\r
+\r
+ case _CMU_LFACLKSEL_LFA_ULFRCO:\r
+ ret = SystemULFRCOClockGet();\r
+ break;\r
+\r
+#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )\r
+ case _CMU_LFACLKSEL_LFA_HFCLKLE:\r
+ ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)\r
+ == CMU_HFPRESC_HFCLKLEPRESC_DIV4)\r
+ ? SystemCoreClockGet() / 4U\r
+ : SystemCoreClockGet() / 2U;\r
+ break;\r
+#elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )\r
+ case _CMU_LFBCLKSEL_LFB_HFCLKLE:\r
+ ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)\r
+ == CMU_HFPRESC_HFCLKLEPRESC_DIV4)\r
+ ? SystemCoreClockGet() / 4U\r
+ : SystemCoreClockGet() / 2U;\r
+ break;\r
+#endif\r
+\r
+ case _CMU_LFACLKSEL_LFA_DISABLED:\r
+ ret = 0;\r
+ break;\r
+ }\r
#endif\r
\r
- /* Use SystemMaxCoreClockGet() when available in CMSIS */\r
- CMU_FlashWaitStateControl(maxCoreClock);\r
+ return ret;\r
}\r
\r
\r
+#if defined( CMU_CTRL_HFLE ) \\r
+ && !defined( _EFM32_WONDER_FAMILY ) \\r
+ && !defined( _EZR32_LEOPARD_FAMILY ) \\r
+ && !defined( _EZR32_WONDER_FAMILY )\r
/***************************************************************************//**\r
- * @brief Convert dividend to prescaler logarithmic value. Only works for even\r
- * numbers equal to 2^n\r
- * @param[in] div Unscaled dividend,\r
- * @return Base 2 logarithm of input, as used by fixed prescalers\r
+ * @brief\r
+ * Return max allowed frequency for low energy peripherals.\r
******************************************************************************/\r
-__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)\r
+static uint32_t maxFreqHfle(void)\r
{\r
- uint32_t log2;\r
-\r
- /* Prescalers take argument of 32768 or less */\r
- EFM_ASSERT((div>0) && (div <= 32768));\r
+ uint16_t majorMinorRev;\r
\r
- /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic */\r
- log2 = (31 - __CLZ(div));\r
+ switch (SYSTEM_GetFamily())\r
+ {\r
+ case systemPartFamilyEfm32Leopard:\r
+ /* CHIP MAJOR bit [5:0] */\r
+ majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)\r
+ >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);\r
+ /* CHIP MINOR bit [7:4] */\r
+ majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)\r
+ >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);\r
+ /* CHIP MINOR bit [3:0] */\r
+ majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)\r
+ >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);\r
+\r
+ if (majorMinorRev >= 0x0204)\r
+ return 24000000;\r
+ else\r
+ return 32000000;\r
+\r
+ case systemPartFamilyEfm32Giant:\r
+ return 32000000;\r
\r
- return log2;\r
+ default:\r
+ /* Invalid device family. */\r
+ EFM_ASSERT(false);\r
+ return 0;\r
+ }\r
}\r
+#endif\r
\r
\r
/***************************************************************************//**\r
- * @brief Convert logarithm of 2 prescaler to division factor\r
- * @param[in] log2\r
- * @return Dividend\r
+ * @brief\r
+ * Wait for ongoing sync of register(s) to low frequency domain to complete.\r
+ *\r
+ * @param[in] mask\r
+ * Bitmask corresponding to SYNCBUSY register defined bits, indicating\r
+ * registers that must complete any ongoing synchronization.\r
******************************************************************************/\r
-__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)\r
+__STATIC_INLINE void syncReg(uint32_t mask)\r
{\r
- return 1<<log2;\r
+ /* Avoid deadlock if modifying the same register twice when freeze mode is */\r
+ /* activated. */\r
+ if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)\r
+ return;\r
+\r
+ /* Wait for any pending previous write operation to have been completed */\r
+ /* in low frequency domain */\r
+ while (CMU->SYNCBUSY & mask)\r
+ {\r
+ }\r
}\r
\r
\r
* @return\r
* USBC frequency in Hz\r
******************************************************************************/\r
-static uint32_t CMU_USBCClkGet(void)\r
+static uint32_t usbCClkGet(void)\r
{\r
uint32_t ret;\r
CMU_Select_TypeDef clk;\r
\r
switch(clk)\r
{\r
- case cmuSelect_LFXO:\r
- ret = SystemLFXOClockGet();\r
- break;\r
- case cmuSelect_LFRCO:\r
- ret = SystemLFRCOClockGet();\r
- break;\r
- case cmuSelect_HFCLK:\r
- ret = SystemHFClockGet();\r
- break;\r
- default:\r
- /* Clock is not enabled */\r
- ret = 0;\r
- break;\r
+ case cmuSelect_LFXO:\r
+ ret = SystemLFXOClockGet();\r
+ break;\r
+ case cmuSelect_LFRCO:\r
+ ret = SystemLFRCOClockGet();\r
+ break;\r
+ case cmuSelect_HFCLK:\r
+ ret = SystemHFClockGet();\r
+ break;\r
+ default:\r
+ /* Clock is not enabled */\r
+ ret = 0;\r
+ break;\r
}\r
return ret;\r
}\r
#endif\r
\r
\r
+/** @endcond */\r
+\r
+/*******************************************************************************\r
+ ************************** GLOBAL FUNCTIONS *******************************\r
+ ******************************************************************************/\r
+\r
+#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
/***************************************************************************//**\r
* @brief\r
- * Get the AUX clock frequency. Used by MSC flash programming and LESENSE,\r
- * by default also as debug clock.\r
+ * Get AUXHFRCO band in use.\r
*\r
* @return\r
- * AUX Frequency in Hz\r
+ * AUXHFRCO band in use.\r
******************************************************************************/\r
-static uint32_t CMU_AUXClkGet(void)\r
+CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)\r
{\r
- uint32_t ret;\r
-\r
-#if defined(_EFM32_GECKO_FAMILY)\r
- /* Gecko has a fixed 14Mhz AUXHFRCO clock */\r
- ret = 14000000;\r
-#else\r
- switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)\r
- {\r
- case CMU_AUXHFRCOCTRL_BAND_1MHZ:\r
- ret = 1000000;\r
- break;\r
- case CMU_AUXHFRCOCTRL_BAND_7MHZ:\r
- ret = 7000000;\r
- break;\r
- case CMU_AUXHFRCOCTRL_BAND_11MHZ:\r
- ret = 11000000;\r
- break;\r
- case CMU_AUXHFRCOCTRL_BAND_14MHZ:\r
- ret = 14000000;\r
- break;\r
- case CMU_AUXHFRCOCTRL_BAND_21MHZ:\r
- ret = 21000000;\r
- break;\r
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )\r
- case CMU_AUXHFRCOCTRL_BAND_28MHZ:\r
- ret = 28000000;\r
- break;\r
-#endif\r
- default:\r
- ret = 0;\r
- break;\r
- }\r
-#endif\r
- return ret;\r
+ return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL\r
+ & _CMU_AUXHFRCOCTRL_BAND_MASK)\r
+ >> _CMU_AUXHFRCOCTRL_BAND_SHIFT);\r
}\r
+#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */\r
\r
\r
+#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
/***************************************************************************//**\r
* @brief\r
- * Get the Debug Trace clock frequency\r
+ * Set AUXHFRCO band and the tuning value based on the value in the\r
+ * calibration table made during production.\r
*\r
- * @return\r
- * Debug Trace frequency in Hz\r
+ * @param[in] band\r
+ * AUXHFRCO band to activate.\r
******************************************************************************/\r
-static uint32_t CMU_DBGClkGet(void)\r
+void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)\r
{\r
- uint32_t ret;\r
- CMU_Select_TypeDef clk;\r
+ uint32_t tuning;\r
\r
- /* Get selected clock source */\r
- clk = CMU_ClockSelectGet(cmuClock_DBG);\r
-\r
- switch(clk)\r
+ /* Read tuning value from calibration table */\r
+ switch (band)\r
{\r
- case cmuSelect_HFCLK:\r
- ret = SystemHFClockGet();\r
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
- /* Giant Gecko has an additional divider, not used by USBC */\r
- ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>\r
- _CMU_CTRL_HFCLKDIV_SHIFT));\r
-#endif\r
- break;\r
+ case cmuAUXHFRCOBand_1MHz:\r
+ tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)\r
+ >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;\r
+ break;\r
\r
- case cmuSelect_AUXHFRCO:\r
- ret = CMU_AUXClkGet();\r
- break;\r
+ case cmuAUXHFRCOBand_7MHz:\r
+ tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)\r
+ >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;\r
+ break;\r
\r
- default:\r
- EFM_ASSERT(0);\r
- ret = 0;\r
- break;\r
+ case cmuAUXHFRCOBand_11MHz:\r
+ tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)\r
+ >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;\r
+ break;\r
+\r
+ case cmuAUXHFRCOBand_14MHz:\r
+ tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)\r
+ >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;\r
+ break;\r
+\r
+ case cmuAUXHFRCOBand_21MHz:\r
+ tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)\r
+ >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;\r
+ break;\r
+\r
+#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )\r
+ case cmuAUXHFRCOBand_28MHz:\r
+ tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)\r
+ >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ return;\r
}\r
- return ret;\r
+\r
+ /* Set band/tuning */\r
+ CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &\r
+ ~(_CMU_AUXHFRCOCTRL_BAND_MASK\r
+ | _CMU_AUXHFRCOCTRL_TUNING_MASK))\r
+ | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)\r
+ | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);\r
+\r
}\r
+#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */\r
\r
\r
-/***************************************************************************//**\r
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
+/**************************************************************************//**\r
* @brief\r
- * Get the LFnCLK frequency based on current configuration.\r
+ * Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO\r
*\r
- * @param[in] lfClkBranch\r
- * LF branch, 0 = LFA, 1 = LFB, ...\r
+ * @param[in] freq\r
+ * Frequency in Hz\r
*\r
* @return\r
- * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is\r
- * returned.\r
- ******************************************************************************/\r
-static uint32_t CMU_LFClkGet(unsigned int lfClkBranch)\r
+ * AUXHFRCO calibration word for a given frequency\r
+ *****************************************************************************/\r
+static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)\r
{\r
- uint32_t ret;\r
+ switch (freq)\r
+ {\r
+ /* 1, 2 and 4MHz share the same calibration word */\r
+ case cmuAUXHFRCOFreq_1M0Hz:\r
+ case cmuAUXHFRCOFreq_2M0Hz:\r
+ case cmuAUXHFRCOFreq_4M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL0;\r
\r
- EFM_ASSERT(lfClkBranch == CMU_LFA || lfClkBranch == CMU_LFB);\r
+ case cmuAUXHFRCOFreq_7M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL3;\r
\r
- switch ((CMU->LFCLKSEL >> (lfClkBranch * 2)) & 0x3)\r
- {\r
- case _CMU_LFCLKSEL_LFA_LFRCO:\r
- ret = SystemLFRCOClockGet();\r
- break;\r
+ case cmuAUXHFRCOFreq_13M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL6;\r
\r
- case _CMU_LFCLKSEL_LFA_LFXO:\r
- ret = SystemLFXOClockGet();\r
- break;\r
+ case cmuAUXHFRCOFreq_16M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL7;\r
\r
- case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:\r
-#if defined( CMU_CTRL_HFLE )\r
- /* Giant Gecko can use a /4 divider (and must if >32MHz) or HFLE is set */\r
- if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)||\r
- (CMU->CTRL & CMU_CTRL_HFLE))\r
- {\r
- ret = SystemCoreClockGet() / 4;\r
- }\r
- else\r
- {\r
- ret = SystemCoreClockGet() / 2;\r
- }\r
-#else\r
- ret = SystemCoreClockGet() / 2;\r
-#endif\r
- break;\r
+ case cmuAUXHFRCOFreq_19M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL8;\r
\r
- case _CMU_LFCLKSEL_LFA_DISABLED:\r
-#if defined( CMU_LFCLKSEL_LFAE )\r
- /* Check LF Extended bit setting for ULFRCO clock */\r
- if(CMU->LFCLKSEL >> (_CMU_LFCLKSEL_LFAE_SHIFT + lfClkBranch * 4))\r
- {\r
- ret = SystemULFRCOClockGet();\r
- }\r
- else\r
- {\r
- ret = 0;\r
- }\r
-#else\r
- ret = 0;\r
-#endif\r
- break;\r
+ case cmuAUXHFRCOFreq_26M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL10;\r
\r
- default:\r
- ret = 0;\r
- break;\r
+ case cmuAUXHFRCOFreq_32M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL11;\r
+\r
+ case cmuAUXHFRCOFreq_38M0Hz:\r
+ return DEVINFO->AUXHFRCOCAL12;\r
+\r
+ default: /* cmuAUXHFRCOFreq_UserDefined */\r
+ return 0;\r
}\r
+}\r
+#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */\r
\r
- return ret;\r
+\r
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get AUXHFRCO frequency enumeration in use\r
+ *\r
+ * @return\r
+ * AUXHFRCO frequency enumeration in use\r
+ ******************************************************************************/\r
+CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)\r
+{\r
+ return auxHfrcoFreq;\r
}\r
+#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */\r
\r
\r
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
/***************************************************************************//**\r
* @brief\r
- * Wait for ongoing sync of register(s) to low frequency domain to complete.\r
+ * Set AUXHFRCO calibration for the selected target frequency\r
*\r
- * @param[in] mask\r
- * Bitmask corresponding to SYNCBUSY register defined bits, indicating\r
- * registers that must complete any ongoing synchronization.\r
+ * @param[in] frequency\r
+ * AUXHFRCO frequency to set\r
******************************************************************************/\r
-__STATIC_INLINE void CMU_Sync(uint32_t mask)\r
+void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freq)\r
{\r
- /* Avoid deadlock if modifying the same register twice when freeze mode is */\r
- /* activated. */\r
- if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)\r
- return;\r
+ uint32_t freqCal;\r
\r
- /* Wait for any pending previous write operation to have been completed */\r
- /* in low frequency domain */\r
- while (CMU->SYNCBUSY & mask)\r
- ;\r
-}\r
+ /* Get DEVINFO index, set global auxHfrcoFreq */\r
+ freqCal = CMU_AUXHFRCODevinfoGet(freq);\r
+ EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));\r
+ auxHfrcoFreq = freq;\r
\r
+ /* Wait for any previous sync to complete, and then set calibration data\r
+ for the selected frequency. */\r
+ while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));\r
\r
-/** @endcond */\r
+ /* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */\r
+ switch(freq)\r
+ {\r
+ case cmuAUXHFRCOFreq_1M0Hz:\r
+ freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)\r
+ | CMU_AUXHFRCOCTRL_CLKDIV_DIV4;\r
+ break;\r
+\r
+ case cmuAUXHFRCOFreq_2M0Hz:\r
+ freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)\r
+ | CMU_AUXHFRCOCTRL_CLKDIV_DIV2;\r
+ break;\r
+\r
+ case cmuAUXHFRCOFreq_4M0Hz:\r
+ freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)\r
+ | CMU_AUXHFRCOCTRL_CLKDIV_DIV1;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ CMU->AUXHFRCOCTRL = freqCal;\r
+}\r
+#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */\r
\r
-/*******************************************************************************\r
- ************************** GLOBAL FUNCTIONS *******************************\r
- ******************************************************************************/\r
\r
/***************************************************************************//**\r
* @brief\r
*\r
* @details\r
* Run a calibration for HFCLK against a selectable reference clock. Please\r
- * refer to the EFM32 reference manual, CMU chapter, for further details.\r
+ * refer to the reference manual, CMU chapter, for further details.\r
*\r
* @note\r
* This function will not return until calibration measurement is completed.\r
/* Set reference clock source */\r
switch (ref)\r
{\r
- case cmuOsc_LFXO:\r
- CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;\r
- break;\r
+ case cmuOsc_LFXO:\r
+ CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;\r
+ break;\r
\r
- case cmuOsc_LFRCO:\r
- CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;\r
- break;\r
+ case cmuOsc_LFRCO:\r
+ CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;\r
+ break;\r
\r
- case cmuOsc_HFXO:\r
- CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;\r
- break;\r
+ case cmuOsc_HFXO:\r
+ CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;\r
+ break;\r
\r
- case cmuOsc_HFRCO:\r
- CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;\r
- break;\r
+ case cmuOsc_HFRCO:\r
+ CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;\r
+ break;\r
\r
- case cmuOsc_AUXHFRCO:\r
- CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;\r
- break;\r
+ case cmuOsc_AUXHFRCO:\r
+ CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;\r
+ break;\r
\r
- default:\r
- EFM_ASSERT(0);\r
- return 0;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ return 0;\r
}\r
\r
/* Set top value */\r
/* Start calibration */\r
CMU->CMD = CMU_CMD_CALSTART;\r
\r
+#if defined( CMU_STATUS_CALRDY )\r
/* Wait until calibration completes */\r
- while (CMU->STATUS & CMU_STATUS_CALBSY)\r
- ;\r
+ while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))\r
+ {\r
+ }\r
+#else\r
+ /* Wait until calibration completes */\r
+ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))\r
+ {\r
+ }\r
+#endif\r
\r
return CMU->CALCNT;\r
}\r
* @details\r
* Configure a calibration for a selectable clock source against another\r
* selectable reference clock.\r
- * Refer to the EFM32 reference manual, CMU chapter, for further details.\r
+ * Refer to the reference manual, CMU chapter, for further details.\r
*\r
* @note\r
* After configuration, a call to CMU_CalibrateStart() is required, and\r
CMU_Osc_TypeDef upSel)\r
{\r
/* Keep untouched configuration settings */\r
- uint32_t calCtrl = CMU->CALCTRL & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);\r
+ uint32_t calCtrl = CMU->CALCTRL\r
+ & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);\r
\r
/* 20 bits of precision to calibration count register */\r
EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));\r
/* Set down counting clock source - down counter */\r
switch (downSel)\r
{\r
- case cmuOsc_LFXO:\r
- calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;\r
- break;\r
+ case cmuOsc_LFXO:\r
+ calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;\r
+ break;\r
\r
- case cmuOsc_LFRCO:\r
- calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;\r
- break;\r
+ case cmuOsc_LFRCO:\r
+ calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;\r
+ break;\r
\r
- case cmuOsc_HFXO:\r
- calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;\r
- break;\r
+ case cmuOsc_HFXO:\r
+ calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;\r
+ break;\r
\r
- case cmuOsc_HFRCO:\r
- calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;\r
- break;\r
+ case cmuOsc_HFRCO:\r
+ calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;\r
+ break;\r
\r
- case cmuOsc_AUXHFRCO:\r
- calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;\r
- break;\r
+ case cmuOsc_AUXHFRCO:\r
+ calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;\r
+ break;\r
\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
\r
/* Set top value to be counted down by the downSel clock */\r
/* Set reference clock source - up counter */\r
switch (upSel)\r
{\r
- case cmuOsc_LFXO:\r
- calCtrl |= CMU_CALCTRL_UPSEL_LFXO;\r
- break;\r
+ case cmuOsc_LFXO:\r
+ calCtrl |= CMU_CALCTRL_UPSEL_LFXO;\r
+ break;\r
\r
- case cmuOsc_LFRCO:\r
- calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;\r
- break;\r
+ case cmuOsc_LFRCO:\r
+ calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;\r
+ break;\r
\r
- case cmuOsc_HFXO:\r
- calCtrl |= CMU_CALCTRL_UPSEL_HFXO;\r
- break;\r
+ case cmuOsc_HFXO:\r
+ calCtrl |= CMU_CALCTRL_UPSEL_HFXO;\r
+ break;\r
\r
- case cmuOsc_HFRCO:\r
- calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;\r
- break;\r
+ case cmuOsc_HFRCO:\r
+ calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;\r
+ break;\r
\r
- case cmuOsc_AUXHFRCO:\r
- calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;\r
- break;\r
+ case cmuOsc_AUXHFRCO:\r
+ calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;\r
+ break;\r
\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
\r
CMU->CALCTRL = calCtrl;\r
#endif\r
\r
\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get calibration count register\r
+ * @note\r
+ * If continuous calibrartion mode is active, calibration busy will almost\r
+ * always be off, and we just need to read the value, where the normal case\r
+ * would be that this function call has been triggered by the CALRDY\r
+ * interrupt flag.\r
+ * @return\r
+ * Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)\r
+ * in the period of DOWNSEL oscillator clock cycles configured by a previous\r
+ * write operation to CMU->CALCNT\r
+ ******************************************************************************/\r
+uint32_t CMU_CalibrateCountGet(void)\r
+{\r
+ /* Wait until calibration completes, UNLESS continuous calibration mode is */\r
+ /* active */\r
+#if defined( CMU_CALCTRL_CONT )\r
+ if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))\r
+ {\r
+#if defined( CMU_STATUS_CALRDY )\r
+ /* Wait until calibration completes */\r
+ while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))\r
+ {\r
+ }\r
+#else\r
+ /* Wait until calibration completes */\r
+ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))\r
+ {\r
+ }\r
+#endif\r
+ }\r
+#else\r
+ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))\r
+ {\r
+ }\r
+#endif\r
+ return CMU->CALCNT;\r
+}\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Get clock divisor/prescaler.\r
******************************************************************************/\r
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)\r
{\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ return 1 + (uint32_t)CMU_ClockPrescGet(clock);\r
+\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
uint32_t divReg;\r
CMU_ClkDiv_TypeDef ret;\r
\r
switch (divReg)\r
{\r
#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
- case CMU_HFCLKDIV_REG:\r
- ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>\r
- _CMU_CTRL_HFCLKDIV_SHIFT);\r
- break;\r
+ case CMU_HFCLKDIV_REG:\r
+ ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)\r
+ >> _CMU_CTRL_HFCLKDIV_SHIFT);\r
+ break;\r
#endif\r
\r
- case CMU_HFPERCLKDIV_REG:\r
- ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV &\r
- _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>\r
- _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);\r
- ret = CMU_Log2ToDiv(ret);\r
- break;\r
-\r
- case CMU_HFCORECLKDIV_REG:\r
- ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV &\r
- _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>\r
- _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);\r
- ret = CMU_Log2ToDiv(ret);\r
- break;\r
-\r
- case CMU_LFAPRESC0_REG:\r
- switch (clock)\r
- {\r
- case cmuClock_RTC:\r
- ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >>\r
- _CMU_LFAPRESC0_RTC_SHIFT));\r
+ case CMU_HFPERCLKDIV_REG:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV\r
+ & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)\r
+ >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);\r
ret = CMU_Log2ToDiv(ret);\r
break;\r
\r
-#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)\r
- case cmuClock_LETIMER0:\r
- ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >>\r
- _CMU_LFAPRESC0_LETIMER0_SHIFT));\r
+ case CMU_HFCORECLKDIV_REG:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV\r
+ & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)\r
+ >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);\r
ret = CMU_Log2ToDiv(ret);\r
break;\r
+\r
+ case CMU_LFAPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+ case cmuClock_RTC:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)\r
+ >> _CMU_LFAPRESC0_RTC_SHIFT);\r
+ ret = CMU_Log2ToDiv(ret);\r
+ break;\r
+\r
+#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)\r
+ case cmuClock_LETIMER0:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)\r
+ >> _CMU_LFAPRESC0_LETIMER0_SHIFT);\r
+ ret = CMU_Log2ToDiv(ret);\r
+ break;\r
#endif\r
\r
#if defined(_CMU_LFAPRESC0_LCD_MASK)\r
- case cmuClock_LCDpre:\r
- ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>\r
- _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16));\r
- ret = CMU_Log2ToDiv(ret);\r
- break;\r
+ case cmuClock_LCDpre:\r
+ ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)\r
+ >> _CMU_LFAPRESC0_LCD_SHIFT)\r
+ + CMU_DivToLog2(cmuClkDiv_16));\r
+ ret = CMU_Log2ToDiv(ret);\r
+ break;\r
#endif\r
\r
#if defined(_CMU_LFAPRESC0_LESENSE_MASK)\r
- case cmuClock_LESENSE:\r
- ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >>\r
- _CMU_LFAPRESC0_LESENSE_SHIFT));\r
- ret = CMU_Log2ToDiv(ret);\r
- break;\r
+ case cmuClock_LESENSE:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)\r
+ >> _CMU_LFAPRESC0_LESENSE_SHIFT);\r
+ ret = CMU_Log2ToDiv(ret);\r
+ break;\r
#endif\r
\r
- default:\r
- EFM_ASSERT(0);\r
- ret = cmuClkDiv_1;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = cmuClkDiv_1;\r
+ break;\r
+ }\r
break;\r
- }\r
- break;\r
\r
- case CMU_LFBPRESC0_REG:\r
- switch (clock)\r
- {\r
+ case CMU_LFBPRESC0_REG:\r
+ switch (clock)\r
+ {\r
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)\r
- case cmuClock_LEUART0:\r
- ret = (CMU_ClkDiv_TypeDef)(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >>\r
- _CMU_LFBPRESC0_LEUART0_SHIFT));\r
- ret = CMU_Log2ToDiv(ret);\r
- break;\r
+ case cmuClock_LEUART0:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART0_SHIFT);\r
+ ret = CMU_Log2ToDiv(ret);\r
+ break;\r
#endif\r
\r
#if defined(_CMU_LFBPRESC0_LEUART1_MASK)\r
- case cmuClock_LEUART1:\r
- ret = (CMU_ClkDiv_TypeDef)(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >>\r
- _CMU_LFBPRESC0_LEUART1_SHIFT));\r
- ret = CMU_Log2ToDiv(ret);\r
- break;\r
+ case cmuClock_LEUART1:\r
+ ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART1_SHIFT);\r
+ ret = CMU_Log2ToDiv(ret);\r
+ break;\r
#endif\r
\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = cmuClkDiv_1;\r
+ break;\r
+ }\r
+ break;\r
+\r
default:\r
EFM_ASSERT(0);\r
ret = cmuClkDiv_1;\r
break;\r
- }\r
- break;\r
-\r
- default:\r
- EFM_ASSERT(0);\r
- ret = cmuClkDiv_1;\r
- break;\r
}\r
\r
- return(ret);\r
+ return ret;\r
+#endif\r
}\r
\r
\r
******************************************************************************/\r
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)\r
{\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));\r
+\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
uint32_t freq;\r
uint32_t divReg;\r
\r
switch (divReg)\r
{\r
#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
- case CMU_HFCLKDIV_REG:\r
- EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));\r
+ case CMU_HFCLKDIV_REG:\r
+ EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));\r
\r
- /* Configure worst case wait states for flash access before setting divisor */\r
- CMU_FlashWaitStateMax();\r
+ /* Configure worst case wait states for flash access before setting divisor */\r
+ flashWaitStateMax();\r
\r
- /* Set divider */\r
- CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) |\r
- ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);\r
+ /* Set divider */\r
+ CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)\r
+ | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);\r
\r
- /* Update CMSIS core clock variable */\r
- /* (The function will update the global variable) */\r
- freq = SystemCoreClockGet();\r
+ /* Update CMSIS core clock variable */\r
+ /* (The function will update the global variable) */\r
+ freq = SystemCoreClockGet();\r
\r
- /* Optimize flash access wait state setting for current core clk */\r
- CMU_FlashWaitStateControl(freq);\r
- break;\r
+ /* Optimize flash access wait state setting for current core clk */\r
+ flashWaitStateControl(freq);\r
+ break;\r
#endif\r
\r
- case CMU_HFPERCLKDIV_REG:\r
- EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
- CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) |\r
- (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);\r
- break;\r
+ case CMU_HFPERCLKDIV_REG:\r
+ EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
+ CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)\r
+ | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);\r
+ break;\r
\r
- case CMU_HFCORECLKDIV_REG:\r
- EFM_ASSERT(div <= cmuClkDiv_512);\r
+ case CMU_HFCORECLKDIV_REG:\r
+ EFM_ASSERT(div <= cmuClkDiv_512);\r
\r
- /* Configure worst case wait states for flash access before setting divisor */\r
- CMU_FlashWaitStateMax();\r
+ /* Configure worst case wait states for flash access before setting divisor */\r
+ flashWaitStateMax();\r
\r
#if defined( CMU_CTRL_HFLE )\r
- /* Clear HFLE and set DIV2 factor for peripheral clock\r
- when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */\r
- if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE)\r
- {\r
- /* Clear CMU HFLE */\r
- BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 0);\r
+ /* Clear HFLE and set DIV2 factor for peripheral clock\r
+ when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */\r
+ if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE())\r
+ {\r
+ /* Clear CMU HFLE */\r
+ BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 0);\r
\r
- /* Set DIV2 factor for peripheral clock */\r
- BITBAND_Peripheral(&(CMU->HFCORECLKDIV),\r
- _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);\r
- }\r
- else\r
- {\r
- /* Set CMU HFLE */\r
- BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);\r
+ /* Set DIV2 factor for peripheral clock */\r
+ BUS_RegBitWrite(&CMU->HFCORECLKDIV,\r
+ _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);\r
+ }\r
+ else\r
+ {\r
+ /* Set CMU HFLE */\r
+ BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);\r
\r
- /* Set DIV4 factor for peripheral clock */\r
- BITBAND_Peripheral(&(CMU->HFCORECLKDIV),\r
- _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
- }\r
+ /* Set DIV4 factor for peripheral clock */\r
+ BUS_RegBitWrite(&CMU->HFCORECLKDIV,\r
+ _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
+ }\r
#endif\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) |\r
- (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);\r
+ CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV\r
+ & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)\r
+ | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);\r
\r
- /* Update CMSIS core clock variable */\r
- /* (The function will update the global variable) */\r
- freq = SystemCoreClockGet();\r
+ /* Update CMSIS core clock variable */\r
+ /* (The function will update the global variable) */\r
+ freq = SystemCoreClockGet();\r
\r
- /* Optimize flash access wait state setting for current core clk */\r
- CMU_FlashWaitStateControl(freq);\r
- break;\r
+ /* Optimize flash access wait state setting for current core clk */\r
+ flashWaitStateControl(freq);\r
+ break;\r
\r
- case CMU_LFAPRESC0_REG:\r
- switch (clock)\r
- {\r
- case cmuClock_RTC:\r
- EFM_ASSERT(div <= cmuClkDiv_32768);\r
+ case CMU_LFAPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+ case cmuClock_RTC:\r
+ EFM_ASSERT(div <= cmuClkDiv_32768);\r
\r
- /* LF register about to be modified require sync. busy check */\r
- CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);\r
+ /* LF register about to be modified require sync. busy check */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) |\r
- (div << _CMU_LFAPRESC0_RTC_SHIFT);\r
- break;\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)\r
+ | (div << _CMU_LFAPRESC0_RTC_SHIFT);\r
+ break;\r
\r
#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)\r
- case cmuClock_LETIMER0:\r
- EFM_ASSERT(div <= cmuClkDiv_32768);\r
+ case cmuClock_LETIMER0:\r
+ EFM_ASSERT(div <= cmuClkDiv_32768);\r
\r
- /* LF register about to be modified require sync. busy check */\r
- CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);\r
+ /* LF register about to be modified require sync. busy check */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) |\r
- (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);\r
- break;\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)\r
+ | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);\r
+ break;\r
#endif\r
\r
#if defined(LCD_PRESENT)\r
- case cmuClock_LCDpre:\r
- EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));\r
+ case cmuClock_LCDpre:\r
+ EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));\r
\r
- /* LF register about to be modified require sync. busy check */\r
- CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);\r
+ /* LF register about to be modified require sync. busy check */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) |\r
- ((div - CMU_DivToLog2(cmuClkDiv_16)) << _CMU_LFAPRESC0_LCD_SHIFT);\r
- break;\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)\r
+ | ((div - CMU_DivToLog2(cmuClkDiv_16))\r
+ << _CMU_LFAPRESC0_LCD_SHIFT);\r
+ break;\r
#endif /* defined(LCD_PRESENT) */\r
\r
#if defined(LESENSE_PRESENT)\r
- case cmuClock_LESENSE:\r
- EFM_ASSERT(div <= cmuClkDiv_8);\r
+ case cmuClock_LESENSE:\r
+ EFM_ASSERT(div <= cmuClkDiv_8);\r
\r
- /* LF register about to be modified require sync. busy check */\r
- CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);\r
+ /* LF register about to be modified require sync. busy check */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) |\r
- (div << _CMU_LFAPRESC0_LESENSE_SHIFT);\r
- break;\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)\r
+ | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);\r
+ break;\r
#endif /* defined(LESENSE_PRESENT) */\r
\r
- default:\r
- EFM_ASSERT(0);\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
break;\r
- }\r
- break;\r
\r
- case CMU_LFBPRESC0_REG:\r
- switch (clock)\r
- {\r
+ case CMU_LFBPRESC0_REG:\r
+ switch (clock)\r
+ {\r
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)\r
- case cmuClock_LEUART0:\r
- EFM_ASSERT(div <= cmuClkDiv_8);\r
+ case cmuClock_LEUART0:\r
+ EFM_ASSERT(div <= cmuClkDiv_8);\r
\r
- /* LF register about to be modified require sync. busy check */\r
- CMU_Sync(CMU_SYNCBUSY_LFBPRESC0);\r
+ /* LF register about to be modified require sync. busy check */\r
+ syncReg(CMU_SYNCBUSY_LFBPRESC0);\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) |\r
- (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);\r
- break;\r
+ CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)\r
+ | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);\r
+ break;\r
#endif\r
\r
#if defined(_CMU_LFBPRESC0_LEUART1_MASK)\r
- case cmuClock_LEUART1:\r
- EFM_ASSERT(div <= cmuClkDiv_8);\r
+ case cmuClock_LEUART1:\r
+ EFM_ASSERT(div <= cmuClkDiv_8);\r
\r
- /* LF register about to be modified require sync. busy check */\r
- CMU_Sync(CMU_SYNCBUSY_LFBPRESC0);\r
+ /* LF register about to be modified require sync. busy check */\r
+ syncReg(CMU_SYNCBUSY_LFBPRESC0);\r
\r
- /* Convert to correct scale */\r
- div = CMU_DivToLog2(div);\r
+ /* Convert to correct scale */\r
+ div = CMU_DivToLog2(div);\r
\r
- CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) |\r
- (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);\r
- break;\r
+ CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)\r
+ | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);\r
+ break;\r
#endif\r
\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+ break;\r
+\r
default:\r
EFM_ASSERT(0);\r
break;\r
- }\r
- break;\r
-\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
}\r
+#endif\r
}\r
\r
\r
/* Identify enable register */\r
switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)\r
{\r
- case CMU_HFPERCLKDIV_EN_REG:\r
- reg = &(CMU->HFPERCLKDIV);\r
- break;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ case CMU_CTRL_EN_REG:\r
+ reg = &CMU->CTRL;\r
+ break;\r
+#endif\r
\r
- case CMU_HFPERCLKEN0_EN_REG:\r
- reg = &(CMU->HFPERCLKEN0);\r
- break;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ case CMU_HFCORECLKEN0_EN_REG:\r
+ reg = &CMU->HFCORECLKEN0;\r
+#if defined( CMU_CTRL_HFLE )\r
+ /* Set HFLE and DIV4 factor for peripheral clock when\r
+ running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */\r
+ if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE())\r
+ {\r
+ /* Enable CMU HFLE */\r
+ BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);\r
\r
- case CMU_HFCORECLKEN0_EN_REG:\r
- reg = &(CMU->HFCORECLKEN0);\r
+ /* Set DIV4 factor for peripheral clock */\r
+ BUS_RegBitWrite(&CMU->HFCORECLKDIV,\r
+ _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
\r
-#if defined( CMU_CTRL_HFLE )\r
- /* Set HFLE and DIV4 factor for peripheral clock when\r
- running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */\r
- if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE )\r
- {\r
- /* Enable CMU HFLE */\r
- BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);\r
+#if defined( _CMU_HFBUSCLKEN0_MASK )\r
+ case CMU_HFBUSCLKEN0_EN_REG:\r
+ reg = &CMU->HFBUSCLKEN0;\r
+ break;\r
+#endif\r
\r
- /* Set DIV4 factor for peripheral clock */\r
- BITBAND_Peripheral(&(CMU->HFCORECLKDIV),\r
- _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
- }\r
+#if defined( _CMU_HFRADIOCLKEN0_MASK )\r
+ case CMU_HFRADIOCLKEN0_EN_REG:\r
+ reg = &CMU->HFRADIOCLKEN0;\r
+ break;\r
#endif\r
- break;\r
\r
- case CMU_LFACLKEN0_EN_REG:\r
- reg = &(CMU->LFACLKEN0);\r
- sync = CMU_SYNCBUSY_LFACLKEN0;\r
- break;\r
+#if defined( _CMU_HFPERCLKDIV_MASK )\r
+ case CMU_HFPERCLKDIV_EN_REG:\r
+ reg = &CMU->HFPERCLKDIV;\r
+ break;\r
+#endif\r
\r
- case CMU_LFBCLKEN0_EN_REG:\r
- reg = &(CMU->LFBCLKEN0);\r
- sync = CMU_SYNCBUSY_LFBCLKEN0;\r
- break;\r
+ case CMU_HFPERCLKEN0_EN_REG:\r
+ reg = &CMU->HFPERCLKEN0;\r
+ break;\r
\r
- case CMU_PCNT_EN_REG:\r
- reg = &(CMU->PCNTCTRL);\r
- break;\r
+ case CMU_LFACLKEN0_EN_REG:\r
+ reg = &CMU->LFACLKEN0;\r
+ sync = CMU_SYNCBUSY_LFACLKEN0;\r
+ break;\r
+\r
+ case CMU_LFBCLKEN0_EN_REG:\r
+ reg = &CMU->LFBCLKEN0;\r
+ sync = CMU_SYNCBUSY_LFBCLKEN0;\r
+ break;\r
\r
#if defined( _CMU_LFCCLKEN0_MASK )\r
- case CMU_LFCCLKEN0_EN_REG:\r
- reg = &(CMU->LFCCLKEN0);\r
- sync = CMU_SYNCBUSY_LFCCLKEN0;\r
- break;\r
+ case CMU_LFCCLKEN0_EN_REG:\r
+ reg = &CMU->LFCCLKEN0;\r
+ sync = CMU_SYNCBUSY_LFCCLKEN0;\r
+ break;\r
#endif\r
\r
- default: /* Cannot enable/disable clock point */\r
- EFM_ASSERT(0);\r
- return;\r
+#if defined( _CMU_LFECLKEN0_MASK )\r
+ case CMU_LFECLKEN0_EN_REG:\r
+ reg = &CMU->LFECLKEN0;\r
+ sync = CMU_SYNCBUSY_LFECLKEN0;\r
+ break;\r
+#endif\r
+\r
+ case CMU_PCNT_EN_REG:\r
+ reg = &CMU->PCNTCTRL;\r
+ break;\r
+\r
+ default: /* Cannot enable/disable clock point */\r
+ EFM_ASSERT(0);\r
+ return;\r
}\r
\r
/* Get bit position used to enable/disable */\r
/* LF synchronization required? */\r
if (sync)\r
{\r
- CMU_Sync(sync);\r
+ syncReg(sync);\r
}\r
\r
/* Set/clear bit as requested */\r
- BITBAND_Peripheral(reg, bit, (unsigned int)enable);\r
+ BUS_RegBitWrite(reg, bit, enable);\r
}\r
\r
\r
switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))\r
{\r
case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
ret = SystemHFClockGet();\r
#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
- /* Giant Gecko has an additional divider, not used by USBC */\r
- ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>\r
- _CMU_CTRL_HFCLKDIV_SHIFT));\r
+ /* Family with an additional divider. */\r
+ ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)\r
+ >> _CMU_CTRL_HFCLKDIV_SHIFT));\r
#endif\r
- } break;\r
+#if defined( _CMU_HFPRESC_MASK )\r
+ ret = ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)\r
+ >> _CMU_HFPRESC_PRESC_SHIFT));\r
+#endif\r
+ break;\r
\r
-#if defined(_CMU_HFPERCLKEN0_USART0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_USART1_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_USART2_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_UART0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_UART1_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_TIMER0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_TIMER1_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_TIMER2_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_TIMER3_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_ACMP0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_ACMP1_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_DAC0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_IDAC0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_ADC0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_I2C0_MASK) || \\r
- defined(_CMU_HFPERCLKEN0_I2C1_MASK) || \\r
- defined(PRS_PRESENT) || \\r
- defined(VCMP_PRESENT)|| \\r
- defined(GPIO_PRESENT)\r
case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = SystemHFClockGet();\r
+ ret = SystemHFClockGet();\r
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )\r
#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
- /* Leopard/Giant Gecko has an additional divider */\r
- ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>\r
- _CMU_CTRL_HFCLKDIV_SHIFT));\r
+ /* Family with an additional divider. */\r
+ ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)\r
+ >> _CMU_CTRL_HFCLKDIV_SHIFT));\r
#endif\r
- ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>\r
- _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;\r
- } break;\r
+ ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)\r
+ >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)\r
+ >> _CMU_HFPERPRESC_PRESC_SHIFT);\r
+#endif\r
+ break;\r
+\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )\r
+ case (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = SystemHFClockGet();\r
+ ret /= 1U + ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)\r
+ >> _CMU_HFRADIOPRESC_PRESC_SHIFT);\r
+ break;\r
+#endif\r
+\r
+#if defined( CRYPTO_PRESENT ) \\r
+ || defined( LDMA_PRESENT ) \\r
+ || defined( GPCRC_PRESENT ) \\r
+ || defined( PRS_PRESENT ) \\r
+ || defined( GPIO_PRESENT )\r
+ case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = SystemHFClockGet();\r
+ break;\r
+#endif\r
+\r
+ case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = SystemHFClockGet();\r
+ ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)\r
+ >> _CMU_HFCOREPRESC_PRESC_SHIFT);\r
+ break;\r
+\r
+ case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = SystemHFClockGet();\r
+ ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)\r
+ >> _CMU_HFEXPPRESC_PRESC_SHIFT);\r
+ break;\r
#endif\r
\r
-#if defined(AES_PRESENT) || \\r
- defined(DMA_PRESENT) || \\r
- defined(EBI_PRESENT) || \\r
- defined(USB_PRESENT)\r
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+#if defined(AES_PRESENT) \\r
+ || defined(DMA_PRESENT) \\r
+ || defined(EBI_PRESENT) \\r
+ || defined(USB_PRESENT)\r
case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
{\r
ret = SystemCoreClockGet();\r
} break;\r
+#endif\r
#endif\r
\r
case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFA);\r
- } break;\r
-#if defined(_CMU_LFACLKEN0_RTC_MASK)\r
+ ret = lfClkGet(cmuClock_LFA);\r
+ break;\r
+\r
+#if defined( _CMU_LFACLKEN0_RTC_MASK )\r
case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFA);\r
- ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >>\r
- _CMU_LFAPRESC0_RTC_SHIFT;\r
- } break;\r
+ ret = lfClkGet(cmuClock_LFA);\r
+ ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)\r
+ >> _CMU_LFAPRESC0_RTC_SHIFT;\r
+ break;\r
#endif\r
-#if defined(_CMU_LFACLKEN0_LETIMER0_MASK)\r
- case (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFA);\r
- ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >>\r
- _CMU_LFAPRESC0_LETIMER0_SHIFT;\r
- } break;\r
+\r
+#if defined( _CMU_LFECLKEN0_RTCC_MASK )\r
+ case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = lfClkGet(cmuClock_LFE);\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFACLKEN0_LETIMER0_MASK )\r
+ case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = lfClkGet(cmuClock_LFA);\r
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)\r
+ >> _CMU_LFAPRESC0_LETIMER0_SHIFT;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)\r
+ >> _CMU_LFAPRESC0_LETIMER0_SHIFT);\r
#endif\r
+ break;\r
+#endif\r
+\r
#if defined(_CMU_LFACLKEN0_LCD_MASK)\r
case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFA);\r
- ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>\r
- _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16);\r
- } break;\r
+ ret = lfClkGet(cmuClock_LFA);\r
+ ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)\r
+ >> _CMU_LFAPRESC0_LCD_SHIFT)\r
+ + CMU_DivToLog2(cmuClkDiv_16);\r
+ break;\r
\r
case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFA);\r
- ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>\r
- _CMU_LFAPRESC0_LCD_SHIFT;\r
- ret /= (1 + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >>\r
- _CMU_LCDCTRL_FDIV_SHIFT));\r
- } break;\r
+ ret = lfClkGet(cmuClock_LFA);\r
+ ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)\r
+ >> _CMU_LFAPRESC0_LCD_SHIFT;\r
+ ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)\r
+ >> _CMU_LCDCTRL_FDIV_SHIFT);\r
+ break;\r
#endif\r
+\r
#if defined(_CMU_LFACLKEN0_LESENSE_MASK)\r
case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFA);\r
- ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >>\r
- _CMU_LFAPRESC0_LESENSE_SHIFT;\r
- } break;\r
+ ret = lfClkGet(cmuClock_LFA);\r
+ ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)\r
+ >> _CMU_LFAPRESC0_LESENSE_SHIFT;\r
+ break;\r
#endif\r
+\r
case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFB);\r
- } break;\r
-#if defined(_CMU_LFBCLKEN0_LEUART0_MASK)\r
+ ret = lfClkGet(cmuClock_LFB);\r
+ break;\r
+\r
+#if defined( _CMU_LFBCLKEN0_LEUART0_MASK )\r
case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFB);\r
- ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >>\r
- _CMU_LFBPRESC0_LEUART0_SHIFT;\r
- } break;\r
+ ret = lfClkGet(cmuClock_LFB);\r
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART0_SHIFT;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART0_SHIFT);\r
#endif\r
-#if defined(_CMU_LFBCLKEN0_LEUART1_MASK)\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFBCLKEN0_LEUART1_MASK )\r
case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_LFClkGet(CMU_LFB);\r
- ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >>\r
- _CMU_LFBPRESC0_LEUART1_SHIFT;\r
- } break;\r
+ ret = lfClkGet(cmuClock_LFB);\r
+#if defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART1_SHIFT;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART1_SHIFT);\r
+#endif\r
+ break;\r
+#endif\r
+\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
+ ret = lfClkGet(cmuClock_LFE);\r
+ break;\r
#endif\r
\r
case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_DBGClkGet();\r
- } break;\r
+ ret = dbgClkGet();\r
+ break;\r
\r
case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_AUXClkGet();\r
- } break;\r
+ ret = auxClkGet();\r
+ break;\r
\r
#if defined(USB_PRESENT)\r
case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):\r
- {\r
- ret = CMU_USBCClkGet();\r
- } break;\r
+ ret = usbCClkGet();\r
+ break;\r
#endif\r
+\r
default:\r
- {\r
EFM_ASSERT(0);\r
ret = 0;\r
- } break;\r
+ break;\r
}\r
+\r
return ret;\r
}\r
\r
\r
-/**************************************************************************//**\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+/***************************************************************************//**\r
* @brief\r
- * Get currently selected reference clock used for a clock branch.\r
+ * Get clock prescaler.\r
*\r
* @param[in] clock\r
- * Clock branch to fetch selected ref. clock for. One of:\r
- * @li #cmuClock_HF\r
- * @li #cmuClock_LFA\r
- * @li #cmuClock_LFB\r
- * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT\r
- * @li #cmuClock_USBC\r
- * @endif\r
+ * Clock point to get the prescaler for. Notice that not all clock points\r
+ * have a prescaler. Please refer to CMU overview in reference manual.\r
*\r
* @return\r
- * Reference clock used for clocking selected branch, #cmuSelect_Error if\r
- * invalid @p clock provided.\r
- *****************************************************************************/\r
-CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)\r
+ * The prescaler value of the current clock point. 0 is returned\r
+ * if @p clock specifies a clock point without a prescaler.\r
+ ******************************************************************************/\r
+uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)\r
{\r
- CMU_Select_TypeDef ret = cmuSelect_Disabled;\r
- uint32_t selReg;\r
- uint32_t statusClkSelMask;\r
-\r
- statusClkSelMask =\r
- (CMU_STATUS_HFRCOSEL |\r
- CMU_STATUS_HFXOSEL |\r
- CMU_STATUS_LFRCOSEL |\r
-#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
- CMU_STATUS_USHFRCODIV2SEL |\r
-#endif\r
- CMU_STATUS_LFXOSEL);\r
+ uint32_t prescReg;\r
+ uint32_t ret;\r
\r
- selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;\r
+ /* Get prescaler register id. */\r
+ prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;\r
\r
- switch (selReg)\r
+ switch (prescReg)\r
{\r
- case CMU_HFCLKSEL_REG:\r
- switch (CMU->STATUS & statusClkSelMask)\r
- {\r
- case CMU_STATUS_LFXOSEL:\r
- ret = cmuSelect_LFXO;\r
+ case CMU_HFPRESC_REG:\r
+ ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)\r
+ >> _CMU_HFPRESC_PRESC_SHIFT);\r
break;\r
\r
- case CMU_STATUS_LFRCOSEL:\r
- ret = cmuSelect_LFRCO;\r
+ case CMU_HFEXPPRESC_REG:\r
+ ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)\r
+ >> _CMU_HFEXPPRESC_PRESC_SHIFT);\r
break;\r
\r
- case CMU_STATUS_HFXOSEL:\r
- ret = cmuSelect_HFXO;\r
+ case CMU_HFCLKLEPRESC_REG:\r
+ ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)\r
+ >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);\r
break;\r
\r
-#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
- case CMU_STATUS_USHFRCODIV2SEL:\r
- ret = cmuSelect_USHFRCODIV2;\r
+ case CMU_HFPERPRESC_REG:\r
+ ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)\r
+ >> _CMU_HFPERPRESC_PRESC_SHIFT);\r
break;\r
-#endif\r
\r
- default:\r
- ret = cmuSelect_HFRCO;\r
+#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )\r
+ case CMU_HFRADIOPRESC_REG:\r
+ ret = ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)\r
+ >> _CMU_HFRADIOPRESC_PRESC_SHIFT);\r
break;\r
- }\r
- break;\r
+#endif\r
\r
- case CMU_LFACLKSEL_REG:\r
- switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)\r
- {\r
- case CMU_LFCLKSEL_LFA_LFRCO:\r
- ret = cmuSelect_LFRCO;\r
+ case CMU_HFCOREPRESC_REG:\r
+ ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)\r
+ >> _CMU_HFCOREPRESC_PRESC_SHIFT);\r
break;\r
\r
- case CMU_LFCLKSEL_LFA_LFXO:\r
- ret = cmuSelect_LFXO;\r
+ case CMU_LFAPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )\r
+ case cmuClock_LETIMER0:\r
+ ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)\r
+ >> _CMU_LFAPRESC0_LETIMER0_SHIFT));\r
+ /* Convert the exponent to prescaler value. */\r
+ ret = CMU_Log2ToDiv(ret) - 1U;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0U;\r
+ break;\r
+ }\r
break;\r
\r
- case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:\r
- ret = cmuSelect_CORELEDIV2;\r
+ case CMU_LFBPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+#if defined( _CMU_LFBPRESC0_LEUART0_MASK )\r
+ case cmuClock_LEUART0:\r
+ ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART0_SHIFT));\r
+ /* Convert the exponent to prescaler value. */\r
+ ret = CMU_Log2ToDiv(ret) - 1U;\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFBPRESC0_LEUART1_MASK )\r
+ case cmuClock_LEUART1:\r
+ ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)\r
+ >> _CMU_LFBPRESC0_LEUART1_SHIFT));\r
+ /* Convert the exponent to prescaler value. */\r
+ ret = CMU_Log2ToDiv(ret) - 1U;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0U;\r
+ break;\r
+ }\r
break;\r
\r
- default:\r
-#if defined( CMU_LFCLKSEL_LFAE )\r
- if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)\r
+ case CMU_LFEPRESC0_REG:\r
+ switch (clock)\r
{\r
- ret = cmuSelect_ULFRCO;\r
- break;\r
- }\r
-#else\r
- ret = cmuSelect_Disabled;\r
+#if defined( RTCC_PRESENT )\r
+ case cmuClock_RTCC:\r
+ /* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */\r
+ /* allowed value. Convert the exponent to prescaler value. */\r
+ ret = _CMU_LFEPRESC0_RTCC_DIV1;\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0U;\r
+ break;\r
#endif\r
+ }\r
break;\r
- }\r
- break;\r
\r
- case CMU_LFBCLKSEL_REG:\r
- switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)\r
- {\r
- case CMU_LFCLKSEL_LFB_LFRCO:\r
- ret = cmuSelect_LFRCO;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0U;\r
break;\r
+ }\r
\r
- case CMU_LFCLKSEL_LFB_LFXO:\r
- ret = cmuSelect_LFXO;\r
- break;\r
+ return ret;\r
+}\r
+#endif\r
\r
- case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:\r
- ret = cmuSelect_CORELEDIV2;\r
- break;\r
\r
- default:\r
-#if defined( CMU_LFCLKSEL_LFBE )\r
- if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)\r
- {\r
- ret = cmuSelect_ULFRCO;\r
- break;\r
- }\r
-#else\r
- ret = cmuSelect_Disabled;\r
-#endif\r
- break;\r
- }\r
- break;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set clock prescaler.\r
+ *\r
+ * @note\r
+ * If setting a LF clock prescaler, synchronization into the low frequency\r
+ * domain is required. If the same register is modified before a previous\r
+ * update has completed, this function will stall until the previous\r
+ * synchronization has completed. Please refer to CMU_FreezeEnable() for\r
+ * a suggestion on how to reduce stalling time in some use cases.\r
+ *\r
+ * @param[in] clock\r
+ * Clock point to set prescaler for. Notice that not all clock points\r
+ * have a prescaler, please refer to CMU overview in the reference manual.\r
+ *\r
+ * @param[in] presc\r
+ * The clock prescaler to use.\r
+ ******************************************************************************/\r
+void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)\r
+{\r
+ uint32_t freq;\r
+ uint32_t prescReg;\r
\r
-#if defined( _CMU_LFCLKSEL_LFC_MASK )\r
- case CMU_LFCCLKSEL_REG:\r
- switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)\r
- {\r
- case CMU_LFCLKSEL_LFC_LFRCO:\r
- ret = cmuSelect_LFRCO;\r
- break;\r
+ /* Get divisor reg id */\r
+ prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;\r
\r
- case CMU_LFCLKSEL_LFC_LFXO:\r
- ret = cmuSelect_LFXO;\r
- break;\r
+ switch (prescReg)\r
+ {\r
+ case CMU_HFPRESC_REG:\r
+ EFM_ASSERT(presc < 32U);\r
\r
- default:\r
- ret = cmuSelect_Disabled;\r
+ CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)\r
+ | (presc << _CMU_HFPRESC_PRESC_SHIFT);\r
break;\r
- }\r
- break;\r
-#endif\r
\r
- case CMU_DBGCLKSEL_REG:\r
+ case CMU_HFEXPPRESC_REG:\r
+ EFM_ASSERT(presc < 32U);\r
\r
-#if defined( _CMU_DBGCLKSEL_DBG_MASK )\r
- switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)\r
- {\r
- case CMU_DBGCLKSEL_DBG_HFCLK:\r
- ret = cmuSelect_HFCLK;\r
+ CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)\r
+ | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);\r
break;\r
\r
- case CMU_DBGCLKSEL_DBG_AUXHFRCO:\r
- ret = cmuSelect_AUXHFRCO;\r
+ case CMU_HFCLKLEPRESC_REG:\r
+ EFM_ASSERT(presc < 2U);\r
+\r
+ /* Specifies the clock divider for HFCLKLE. When running at frequencies\r
+ * higher than 32 MHz, this must be set to DIV4. */\r
+ CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)\r
+ | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);\r
break;\r
- }\r
-#else\r
- ret = cmuSelect_AUXHFRCO;\r
-#endif /* CMU_DBGCLKSEL_DBG */\r
\r
-#if defined( _CMU_CTRL_DBGCLK_MASK )\r
- switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)\r
- {\r
- case CMU_CTRL_DBGCLK_AUXHFRCO:\r
- ret = cmuSelect_AUXHFRCO;\r
+ case CMU_HFPERPRESC_REG:\r
+ EFM_ASSERT(presc < 512U);\r
+\r
+ CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)\r
+ | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);\r
break;\r
\r
- case CMU_CTRL_DBGCLK_HFCLK:\r
- ret = cmuSelect_HFCLK;\r
+#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )\r
+ case CMU_HFRADIOPRESC_REG:\r
+ EFM_ASSERT(presc < 512U);\r
+\r
+ CMU->HFRADIOPRESC = (CMU->HFRADIOPRESC & ~_CMU_HFRADIOPRESC_PRESC_MASK)\r
+ | (presc << _CMU_HFRADIOPRESC_PRESC_SHIFT);\r
break;\r
- }\r
-#else\r
- ret = cmuSelect_AUXHFRCO;\r
#endif\r
- break;\r
\r
+ case CMU_HFCOREPRESC_REG:\r
+ EFM_ASSERT(presc < 512U);\r
\r
-#if defined(USB_PRESENT)\r
+ /* Configure worst case wait states for flash access before setting\r
+ * the prescaler. */\r
+ flashWaitStateControl(CMU_MAX_FREQ_0WS + 1);\r
\r
- case CMU_USBCCLKSEL_REG:\r
- switch(CMU->STATUS &\r
- (CMU_STATUS_USBCLFXOSEL |\r
-#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)\r
- CMU_STATUS_USBCHFCLKSEL |\r
-#endif\r
-#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)\r
- CMU_STATUS_USBCUSHFRCOSEL |\r
-#endif\r
- CMU_STATUS_USBCLFRCOSEL))\r
- {\r
+ CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)\r
+ | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);\r
\r
- case CMU_STATUS_USBCLFXOSEL:\r
- ret = cmuSelect_LFXO;\r
- break;\r
+ /* Update CMSIS core clock variable */\r
+ /* (The function will update the global variable) */\r
+ freq = SystemCoreClockGet();\r
\r
- case CMU_STATUS_USBCLFRCOSEL:\r
- ret = cmuSelect_LFRCO;\r
+ /* Optimize flash access wait state setting for current core clk */\r
+ flashWaitStateControl(freq);\r
break;\r
\r
-#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)\r
- case CMU_STATUS_USBCHFCLKSEL:\r
- ret = cmuSelect_HFCLK;\r
- break;\r
-#endif\r
+ case CMU_LFAPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+#if defined( RTC_PRESENT )\r
+ case cmuClock_RTC:\r
+ EFM_ASSERT(presc <= 32768U);\r
\r
-#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)\r
- case CMU_STATUS_USBCUSHFRCOSEL:\r
- ret = cmuSelect_USHFRCO;\r
- break;\r
-#endif\r
+ /* Convert prescaler value to DIV exponent scale. */\r
+ presc = CMU_PrescToLog2(presc);\r
\r
- default:\r
- ret = cmuSelect_Disabled;\r
- break;\r
- }\r
- break;\r
+ /* LF register about to be modified require sync. Busy check. */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
+\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)\r
+ | (presc << _CMU_LFAPRESC0_RTC_SHIFT);\r
+ break;\r
#endif\r
\r
- default:\r
- EFM_ASSERT(0);\r
- ret = cmuSelect_Error;\r
- break;\r
- }\r
+#if defined( RTCC_PRESENT )\r
+ case cmuClock_RTCC:\r
+#if defined( _CMU_LFEPRESC0_RTCC_MASK )\r
+ /* DIV1 is the only accepted value. */\r
+ EFM_ASSERT(presc <= 0U);\r
\r
- return ret;\r
-}\r
+ /* LF register about to be modified require sync. Busy check.. */\r
+ syncReg(CMU_SYNCBUSY_LFEPRESC0);\r
\r
+ CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)\r
+ | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);\r
+#else\r
+ EFM_ASSERT(presc <= 32768U);\r
\r
-/**************************************************************************//**\r
- * @brief\r
+ /* Convert prescaler value to DIV exponent scale. */\r
+ presc = CMU_PrescToLog2(presc);\r
+\r
+ /* LF register about to be modified require sync. Busy check. */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
+\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)\r
+ | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);\r
+#endif\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )\r
+ case cmuClock_LETIMER0:\r
+ EFM_ASSERT(presc <= 32768U);\r
+\r
+ /* Convert prescaler value to DIV exponent scale. */\r
+ presc = CMU_PrescToLog2(presc);\r
+\r
+ /* LF register about to be modified require sync. Busy check. */\r
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);\r
+\r
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)\r
+ | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+ break;\r
+\r
+ case CMU_LFBPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+#if defined( _CMU_LFBPRESC0_LEUART0_MASK )\r
+ case cmuClock_LEUART0:\r
+ EFM_ASSERT(presc <= 8U);\r
+\r
+ /* Convert prescaler value to DIV exponent scale. */\r
+ presc = CMU_PrescToLog2(presc);\r
+\r
+ /* LF register about to be modified require sync. Busy check. */\r
+ syncReg(CMU_SYNCBUSY_LFBPRESC0);\r
+\r
+ CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)\r
+ | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFBPRESC0_LEUART1_MASK )\r
+ case cmuClock_LEUART1:\r
+ EFM_ASSERT(presc <= 8U);\r
+\r
+ /* Convert prescaler value to DIV exponent scale. */\r
+ presc = CMU_PrescToLog2(presc);\r
+\r
+ /* LF register about to be modified require sync. Busy check. */\r
+ syncReg(CMU_SYNCBUSY_LFBPRESC0);\r
+\r
+ CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)\r
+ | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+ break;\r
+\r
+ case CMU_LFEPRESC0_REG:\r
+ switch (clock)\r
+ {\r
+#if defined( _CMU_LFEPRESC0_RTCC_MASK )\r
+ case cmuClock_RTCC:\r
+ EFM_ASSERT(presc <= 0U);\r
+\r
+ /* LF register about to be modified require sync. Busy check. */\r
+ syncReg(CMU_SYNCBUSY_LFEPRESC0);\r
+\r
+ CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)\r
+ | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get currently selected reference clock used for a clock branch.\r
+ *\r
+ * @param[in] clock\r
+ * Clock branch to fetch selected ref. clock for. One of:\r
+ * @li #cmuClock_HF\r
+ * @li #cmuClock_LFA\r
+ * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO\r
+ * @li #cmuClock_LFC\r
+ * @endif @if _SILICON_LABS_32B_PLATFORM_2\r
+ * @li #cmuClock_LFE\r
+ * @endif\r
+ * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT\r
+ * @li #cmuClock_USBC\r
+ * @endif\r
+ *\r
+ * @return\r
+ * Reference clock used for clocking selected branch, #cmuSelect_Error if\r
+ * invalid @p clock provided.\r
+ ******************************************************************************/\r
+CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)\r
+{\r
+ CMU_Select_TypeDef ret = cmuSelect_Disabled;\r
+ uint32_t selReg;\r
+\r
+ selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;\r
+\r
+ switch (selReg)\r
+ {\r
+ case CMU_HFCLKSEL_REG:\r
+#if defined( _CMU_HFCLKSEL_HF_MASK )\r
+ switch (CMU->HFCLKSEL & _CMU_HFCLKSEL_HF_MASK)\r
+ {\r
+ case CMU_HFCLKSEL_HF_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ case CMU_HFCLKSEL_HF_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_HFCLKSEL_HF_HFXO:\r
+ ret = cmuSelect_HFXO;\r
+ break;\r
+\r
+ default:\r
+ ret = cmuSelect_HFRCO;\r
+ break;\r
+ }\r
+#else\r
+ switch (CMU->STATUS\r
+ & (CMU_STATUS_HFRCOSEL\r
+ | CMU_STATUS_HFXOSEL\r
+ | CMU_STATUS_LFRCOSEL\r
+#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
+ | CMU_STATUS_USHFRCODIV2SEL\r
+#endif\r
+ | CMU_STATUS_LFXOSEL))\r
+ {\r
+ case CMU_STATUS_LFXOSEL:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ case CMU_STATUS_LFRCOSEL:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_STATUS_HFXOSEL:\r
+ ret = cmuSelect_HFXO;\r
+ break;\r
+\r
+#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
+ case CMU_STATUS_USHFRCODIV2SEL:\r
+ ret = cmuSelect_USHFRCODIV2;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ ret = cmuSelect_HFRCO;\r
+ break;\r
+ }\r
+#endif\r
+ break;\r
+\r
+ case CMU_LFACLKSEL_REG:\r
+#if defined( _CMU_LFCLKSEL_MASK )\r
+ switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)\r
+ {\r
+ case CMU_LFCLKSEL_LFA_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_LFCLKSEL_LFA_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+#if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )\r
+ case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:\r
+ ret = cmuSelect_CORELEDIV2;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+#if defined( CMU_LFCLKSEL_LFAE )\r
+ if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)\r
+ {\r
+ ret = cmuSelect_ULFRCO;\r
+ break;\r
+ }\r
+#else\r
+ ret = cmuSelect_Disabled;\r
+#endif\r
+ break;\r
+ }\r
+#endif /* _CMU_LFCLKSEL_MASK */\r
+\r
+#if defined( _CMU_LFACLKSEL_MASK )\r
+ switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)\r
+ {\r
+ case CMU_LFACLKSEL_LFA_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_LFACLKSEL_LFA_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ case CMU_LFACLKSEL_LFA_ULFRCO:\r
+ ret = cmuSelect_ULFRCO;\r
+ break;\r
+\r
+#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )\r
+ case CMU_LFACLKSEL_LFA_HFCLKLE:\r
+ ret = cmuSelect_HFCLKLE;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ ret = cmuSelect_Disabled;\r
+ break;\r
+ }\r
+#endif\r
+ break;\r
+\r
+ case CMU_LFBCLKSEL_REG:\r
+#if defined( _CMU_LFCLKSEL_MASK )\r
+ switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)\r
+ {\r
+ case CMU_LFCLKSEL_LFB_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_LFCLKSEL_LFB_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+#if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )\r
+ case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:\r
+ ret = cmuSelect_CORELEDIV2;\r
+ break;\r
+#endif\r
+\r
+#if defined( CMU_LFCLKSEL_LFB_HFCLKLE )\r
+ case CMU_LFCLKSEL_LFB_HFCLKLE:\r
+ ret = cmuSelect_HFCLKLE;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+#if defined( CMU_LFCLKSEL_LFBE )\r
+ if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)\r
+ {\r
+ ret = cmuSelect_ULFRCO;\r
+ break;\r
+ }\r
+#else\r
+ ret = cmuSelect_Disabled;\r
+#endif\r
+ break;\r
+ }\r
+#endif /* _CMU_LFCLKSEL_MASK */\r
+\r
+#if defined( _CMU_LFBCLKSEL_MASK )\r
+ switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)\r
+ {\r
+ case CMU_LFBCLKSEL_LFB_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_LFBCLKSEL_LFB_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ case CMU_LFBCLKSEL_LFB_ULFRCO:\r
+ ret = cmuSelect_ULFRCO;\r
+ break;\r
+\r
+ case CMU_LFBCLKSEL_LFB_HFCLKLE:\r
+ ret = cmuSelect_HFCLKLE;\r
+ break;\r
+\r
+ default:\r
+ ret = cmuSelect_Disabled;\r
+ break;\r
+ }\r
+#endif\r
+ break;\r
+\r
+#if defined( _CMU_LFCLKSEL_LFC_MASK )\r
+ case CMU_LFCCLKSEL_REG:\r
+ switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)\r
+ {\r
+ case CMU_LFCLKSEL_LFC_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_LFCLKSEL_LFC_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ default:\r
+ ret = cmuSelect_Disabled;\r
+ break;\r
+ }\r
+ break;\r
+#endif\r
+\r
+#if defined( _CMU_LFECLKSEL_LFE_MASK )\r
+ case CMU_LFECLKSEL_REG:\r
+ switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)\r
+ {\r
+ case CMU_LFECLKSEL_LFE_LFRCO:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ case CMU_LFECLKSEL_LFE_LFXO:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ case CMU_LFECLKSEL_LFE_ULFRCO:\r
+ ret = cmuSelect_ULFRCO;\r
+ break;\r
+\r
+#if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )\r
+ case CMU_LFECLKSEL_LFE_HFCLKLE:\r
+ ret = cmuSelect_HFCLKLE;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ ret = cmuSelect_Disabled;\r
+ break;\r
+ }\r
+ break;\r
+#endif /* CMU_LFECLKSEL_REG */\r
+\r
+ case CMU_DBGCLKSEL_REG:\r
+#if defined( _CMU_DBGCLKSEL_DBG_MASK )\r
+ switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)\r
+ {\r
+ case CMU_DBGCLKSEL_DBG_HFCLK:\r
+ ret = cmuSelect_HFCLK;\r
+ break;\r
+\r
+ case CMU_DBGCLKSEL_DBG_AUXHFRCO:\r
+ ret = cmuSelect_AUXHFRCO;\r
+ break;\r
+ }\r
+#else\r
+ ret = cmuSelect_AUXHFRCO;\r
+#endif /* CMU_DBGCLKSEL_DBG */\r
+\r
+#if defined( _CMU_CTRL_DBGCLK_MASK )\r
+ switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)\r
+ {\r
+ case CMU_CTRL_DBGCLK_AUXHFRCO:\r
+ ret = cmuSelect_AUXHFRCO;\r
+ break;\r
+\r
+ case CMU_CTRL_DBGCLK_HFCLK:\r
+ ret = cmuSelect_HFCLK;\r
+ break;\r
+ }\r
+#else\r
+ ret = cmuSelect_AUXHFRCO;\r
+#endif\r
+ break;\r
+\r
+\r
+#if defined( USB_PRESENT )\r
+ case CMU_USBCCLKSEL_REG:\r
+ switch (CMU->STATUS\r
+ & (CMU_STATUS_USBCLFXOSEL\r
+#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)\r
+ | CMU_STATUS_USBCHFCLKSEL\r
+#endif\r
+#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)\r
+ | CMU_STATUS_USBCUSHFRCOSEL\r
+#endif\r
+ | CMU_STATUS_USBCLFRCOSEL))\r
+ {\r
+#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)\r
+ case CMU_STATUS_USBCHFCLKSEL:\r
+ ret = cmuSelect_HFCLK;\r
+ break;\r
+#endif\r
+\r
+#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)\r
+ case CMU_STATUS_USBCUSHFRCOSEL:\r
+ ret = cmuSelect_USHFRCO;\r
+ break;\r
+#endif\r
+\r
+ case CMU_STATUS_USBCLFXOSEL:\r
+ ret = cmuSelect_LFXO;\r
+ break;\r
+\r
+ case CMU_STATUS_USBCLFRCOSEL:\r
+ ret = cmuSelect_LFRCO;\r
+ break;\r
+\r
+ default:\r
+ ret = cmuSelect_Disabled;\r
+ break;\r
+ }\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = cmuSelect_Error;\r
+ break;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
* Select reference clock/oscillator used for a clock branch.\r
*\r
* @details\r
* Clock branch to select reference clock for. One of:\r
* @li #cmuClock_HF\r
* @li #cmuClock_LFA\r
- * @li #cmuClock_LFB\r
+ * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO\r
+ * @li #cmuClock_LFC\r
+ * @endif @if _SILICON_LABS_32B_PLATFORM_2\r
+ * @li #cmuClock_LFE\r
+ * @endif\r
* @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT\r
* @li #cmuClock_USBC\r
* @endif\r
* @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY\r
* @li #cmuSelect_ULFRCO\r
* @endif\r
- *****************************************************************************/\r
+ ******************************************************************************/\r
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)\r
{\r
uint32_t select = cmuOsc_HFRCO;\r
CMU_Osc_TypeDef osc = cmuOsc_HFRCO;\r
uint32_t freq;\r
- uint32_t selReg;\r
-#if !defined(_EFM32_GECKO_FAMILY)\r
+ uint32_t tmp;\r
+ uint32_t selRegId;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ volatile uint32_t *selReg = NULL;\r
+#endif\r
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )\r
uint32_t lfExtended = 0;\r
#endif\r
- uint32_t tmp;\r
\r
- selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;\r
+ selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;\r
\r
- switch (selReg)\r
+ switch (selRegId)\r
{\r
- case CMU_HFCLKSEL_REG:\r
- switch (ref)\r
- {\r
- case cmuSelect_LFXO:\r
- select = CMU_CMD_HFCLKSEL_LFXO;\r
- osc = cmuOsc_LFXO;\r
- break;\r
-\r
- case cmuSelect_LFRCO:\r
- select = CMU_CMD_HFCLKSEL_LFRCO;\r
- osc = cmuOsc_LFRCO;\r
- break;\r
-\r
- case cmuSelect_HFXO:\r
- select = CMU_CMD_HFCLKSEL_HFXO;\r
- osc = cmuOsc_HFXO;\r
-#if defined( CMU_CTRL_HFLE )\r
- /* Adjust HFXO buffer current for high frequencies, enable HFLE for */\r
- /* frequencies above CMU_MAX_FREQ_HFLE. */\r
- if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE)\r
+ case CMU_HFCLKSEL_REG:\r
+ switch (ref)\r
{\r
- CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |\r
- CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |\r
- /* Must have HFLE enabled to access some LE peripherals >=32MHz */\r
- CMU_CTRL_HFLE;\r
-\r
- /* Set HFLE and DIV4 factor for peripheral clock if HFCORE clock for\r
- LE is enabled. */\r
- if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)\r
- {\r
- BITBAND_Peripheral(&(CMU->HFCORECLKDIV),\r
- _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
- }\r
- } else {\r
- /* This can happen if the user configures the EFM32_HFXO_FREQ to */\r
- /* use another oscillator frequency */\r
- CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |\r
- CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;\r
- }\r
-#endif\r
- break;\r
-\r
- case cmuSelect_HFRCO:\r
- select = CMU_CMD_HFCLKSEL_HFRCO;\r
- osc = cmuOsc_HFRCO;\r
- break;\r
+ case cmuSelect_LFXO:\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ select = CMU_HFCLKSEL_HF_LFXO;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ select = CMU_CMD_HFCLKSEL_LFXO;\r
+#endif\r
+ osc = cmuOsc_LFXO;\r
+ break;\r
+\r
+ case cmuSelect_LFRCO:\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ select = CMU_HFCLKSEL_HF_LFRCO;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ select = CMU_CMD_HFCLKSEL_LFRCO;\r
+#endif\r
+ osc = cmuOsc_LFRCO;\r
+ break;\r
+\r
+ case cmuSelect_HFXO:\r
+ osc = cmuOsc_HFXO;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ select = CMU_HFCLKSEL_HF_HFXO;\r
+ /* Adjust HFXO buffer current for high frequencies, */\r
+ /* enable WSHFLE for frequencies above 32MHz. */\r
+ if (SystemHFXOClockGet() > 32000000)\r
+ {\r
+ CMU->CTRL |= CMU_CTRL_WSHFLE;\r
+ }\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ select = CMU_CMD_HFCLKSEL_HFXO;\r
+#if defined( CMU_CTRL_HFLE )\r
+ /* Adjust HFXO buffer current for high frequencies, */\r
+ /* enable HFLE for frequencies above CMU_MAX_FREQ_HFLE. */\r
+ if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE())\r
+ {\r
+ CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)\r
+ | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ\r
+ /* Must have HFLE enabled to access some LE peripherals >=32MHz */\r
+ | CMU_CTRL_HFLE;\r
+\r
+ /* Set HFLE and DIV4 factor for peripheral clock if HFCORE */\r
+ /* clock for LE is enabled. */\r
+ if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)\r
+ {\r
+ BUS_RegBitWrite(&CMU->HFCORECLKDIV,\r
+ _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* This can happen if the user configures the EFM32_HFXO_FREQ to */\r
+ /* use another oscillator frequency */\r
+ CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)\r
+ | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;\r
+ }\r
+#endif\r
+#endif\r
+ break;\r
+\r
+ case cmuSelect_HFRCO:\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ select = CMU_HFCLKSEL_HF_HFRCO;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ select = CMU_CMD_HFCLKSEL_HFRCO;\r
+#endif\r
+ osc = cmuOsc_HFRCO;\r
+ break;\r
\r
#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )\r
- case cmuSelect_USHFRCODIV2:\r
- select = CMU_CMD_HFCLKSEL_USHFRCODIV2;\r
- osc = cmuOsc_USHFRCO;\r
- break;\r
+ case cmuSelect_USHFRCODIV2:\r
+ select = CMU_CMD_HFCLKSEL_USHFRCODIV2;\r
+ osc = cmuOsc_USHFRCO;\r
+ break;\r
#endif\r
\r
-#if !defined( _EFM32_GECKO_FAMILY )\r
- case cmuSelect_ULFRCO:\r
- /* ULFRCO cannot be used as HFCLK */\r
- EFM_ASSERT(0);\r
- break;\r
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )\r
+ case cmuSelect_ULFRCO:\r
+ /* ULFRCO cannot be used as HFCLK */\r
+ EFM_ASSERT(0);\r
+ return;\r
#endif\r
\r
- default:\r
- EFM_ASSERT(0);\r
- return;\r
- }\r
-\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(osc, true, true);\r
-\r
- /* Configure worst case wait states for flash access before selecting */\r
- CMU_FlashWaitStateMax();\r
-\r
- /* Switch to selected oscillator */\r
- CMU->CMD = select;\r
-\r
- /* Keep EMU module informed */\r
- EMU_UpdateOscConfig();\r
+ default:\r
+ EFM_ASSERT(0);\r
+ return;\r
+ }\r
\r
- /* Update CMSIS core clock variable */\r
- /* (The function will update the global variable) */\r
- freq = SystemCoreClockGet();\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(osc, true, true);\r
\r
- /* Optimize flash access wait state setting for currently selected core clk */\r
- CMU_FlashWaitStateControl(freq);\r
- break;\r
+ /* Configure worst case wait states for flash access before selecting */\r
+ flashWaitStateMax();\r
\r
- case CMU_LFACLKSEL_REG:\r
- case CMU_LFBCLKSEL_REG:\r
+ /* Switch to selected oscillator */\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ CMU->HFCLKSEL = select;\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ CMU->CMD = select;\r
+#endif\r
\r
- switch (ref)\r
- {\r
- case cmuSelect_Disabled:\r
- tmp = _CMU_LFCLKSEL_LFA_DISABLED;\r
- break;\r
+ /* Keep EMU module informed */\r
+ EMU_UpdateOscConfig();\r
\r
- case cmuSelect_LFXO:\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
- tmp = _CMU_LFCLKSEL_LFA_LFXO;\r
- break;\r
+ /* Update CMSIS core clock variable */\r
+ /* (The function will update the global variable) */\r
+ freq = SystemCoreClockGet();\r
\r
- case cmuSelect_LFRCO:\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
- tmp = _CMU_LFCLKSEL_LFA_LFRCO;\r
+ /* Optimize flash access wait state setting for currently selected core clk */\r
+ flashWaitStateControl(freq);\r
break;\r
\r
- case cmuSelect_CORELEDIV2:\r
- /* Ensure HFCORE to LE clocking is enabled */\r
- BITBAND_Peripheral(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);\r
- tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;\r
-#if defined( CMU_CTRL_HFLE )\r
- /* If core frequency is higher than CMU_MAX_FREQ_HFLE on\r
- Giant/Leopard/Wonder, enable HFLE and DIV4. */\r
- freq = SystemCoreClockGet();\r
- if(freq > CMU_MAX_FREQ_HFLE)\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ case CMU_LFACLKSEL_REG:\r
+ selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;\r
+#if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )\r
+ /* HFCLKCLE can not be used as LFACLK */\r
+ EFM_ASSERT(ref != cmuSelect_HFCLKLE);\r
+#endif\r
+ case CMU_LFECLKSEL_REG:\r
+ selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;\r
+#if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )\r
+ /* HFCLKCLE can not be used as LFECLK */\r
+ EFM_ASSERT(ref != cmuSelect_HFCLKLE);\r
+#endif\r
+ case CMU_LFBCLKSEL_REG:\r
+ selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;\r
+ switch (ref)\r
{\r
- /* Enable CMU HFLE */\r
- BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);\r
-\r
- /* Enable DIV4 factor for peripheral clock */\r
- BITBAND_Peripheral(&(CMU->HFCORECLKDIV),\r
- _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
+ case cmuSelect_Disabled:\r
+ tmp = _CMU_LFACLKSEL_LFA_DISABLED;\r
+ break;\r
+\r
+ case cmuSelect_LFXO:\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
+ tmp = _CMU_LFACLKSEL_LFA_LFXO;\r
+ break;\r
+\r
+ case cmuSelect_LFRCO:\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
+ tmp = _CMU_LFACLKSEL_LFA_LFRCO;\r
+ break;\r
+\r
+ case cmuSelect_HFCLKLE:\r
+ /* Ensure HFCORE to LE clocking is enabled */\r
+ BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);\r
+ tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;\r
+\r
+ /* If core frequency is > 32MHz enable WSHFLE */\r
+ freq = SystemCoreClockGet();\r
+ if (freq > 32000000U)\r
+ {\r
+ /* Enable CMU HFLE */\r
+ BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_WSHFLE_SHIFT, 1);\r
+\r
+ /* Enable DIV4 factor for peripheral clock */\r
+ BUS_RegBitWrite(&CMU->HFPRESC, _CMU_HFPRESC_HFCLKLEPRESC_SHIFT, 1);\r
+ }\r
+ break;\r
+\r
+ case cmuSelect_ULFRCO:\r
+ /* ULFRCO is always on, there is no need to enable it. */\r
+ tmp = _CMU_LFACLKSEL_LFA_ULFRCO;\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ return;\r
}\r
-#endif\r
+ *selReg = tmp;\r
break;\r
\r
-#if !defined(_EFM32_GECKO_FAMILY)\r
- case cmuSelect_ULFRCO:\r
- /* ULFRCO is always enabled */\r
- tmp = _CMU_LFCLKSEL_LFA_DISABLED;\r
- lfExtended = 1;\r
- break;\r
-#endif\r
-\r
- default:\r
- /* Illegal clock source for LFA/LFB selected */\r
- EFM_ASSERT(0);\r
- return;\r
- }\r
+#elif defined( _SILICON_LABS_32B_PLATFORM_1 )\r
+ case CMU_LFACLKSEL_REG:\r
+ case CMU_LFBCLKSEL_REG:\r
+ switch (ref)\r
+ {\r
+ case cmuSelect_Disabled:\r
+ tmp = _CMU_LFCLKSEL_LFA_DISABLED;\r
+ break;\r
+\r
+ case cmuSelect_LFXO:\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
+ tmp = _CMU_LFCLKSEL_LFA_LFXO;\r
+ break;\r
+\r
+ case cmuSelect_LFRCO:\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
+ tmp = _CMU_LFCLKSEL_LFA_LFRCO;\r
+ break;\r
+\r
+ case cmuSelect_CORELEDIV2:\r
+ /* Ensure HFCORE to LE clocking is enabled */\r
+ BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);\r
+ tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;\r
+#if defined( CMU_CTRL_HFLE )\r
+ /* If core frequency is higher than CMU_MAX_FREQ_HFLE on\r
+ Giant/Leopard/Wonder, enable HFLE and DIV4. */\r
+ freq = SystemCoreClockGet();\r
+ if(freq > CMU_MAX_FREQ_HFLE())\r
+ {\r
+ /* Enable CMU HFLE */\r
+ BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);\r
+\r
+ /* Enable DIV4 factor for peripheral clock */\r
+ BUS_RegBitWrite(&CMU->HFCORECLKDIV,\r
+ _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);\r
+ }\r
+#endif\r
+ break;\r
+\r
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )\r
+ case cmuSelect_ULFRCO:\r
+ /* ULFRCO is always enabled */\r
+ tmp = _CMU_LFCLKSEL_LFA_DISABLED;\r
+ lfExtended = 1;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ /* Illegal clock source for LFA/LFB selected */\r
+ EFM_ASSERT(0);\r
+ return;\r
+ }\r
\r
- /* Apply select */\r
- if (selReg == CMU_LFACLKSEL_REG)\r
- {\r
-#if !defined( _EFM32_GECKO_FAMILY )\r
- CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK) ) |\r
- (tmp << _CMU_LFCLKSEL_LFA_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);\r
+ /* Apply select */\r
+ if (selRegId == CMU_LFACLKSEL_REG)\r
+ {\r
+#if defined( _CMU_LFCLKSEL_LFAE_MASK )\r
+ CMU->LFCLKSEL = (CMU->LFCLKSEL\r
+ & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))\r
+ | (tmp << _CMU_LFCLKSEL_LFA_SHIFT)\r
+ | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);\r
#else\r
- CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) |\r
- (tmp << _CMU_LFCLKSEL_LFA_SHIFT);\r
+ CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)\r
+ | (tmp << _CMU_LFCLKSEL_LFA_SHIFT);\r
#endif\r
- }\r
- else\r
- {\r
-#if !defined( _EFM32_GECKO_FAMILY )\r
- CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK) ) |\r
- (tmp << _CMU_LFCLKSEL_LFB_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);\r
+ }\r
+ else\r
+ {\r
+#if defined( _CMU_LFCLKSEL_LFBE_MASK )\r
+ CMU->LFCLKSEL = (CMU->LFCLKSEL\r
+ & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))\r
+ | (tmp << _CMU_LFCLKSEL_LFB_SHIFT)\r
+ | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);\r
#else\r
- CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) |\r
- (tmp << _CMU_LFCLKSEL_LFB_SHIFT);\r
+ CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)\r
+ | (tmp << _CMU_LFCLKSEL_LFB_SHIFT);\r
#endif\r
- }\r
- break;\r
-\r
-#if defined( _CMU_LFCLKSEL_LFC_MASK )\r
- case CMU_LFCCLKSEL_REG:\r
- switch(ref)\r
- {\r
- case cmuSelect_Disabled:\r
- tmp = _CMU_LFCLKSEL_LFA_DISABLED;\r
+ }\r
break;\r
\r
- case cmuSelect_LFXO:\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
- tmp = _CMU_LFCLKSEL_LFC_LFXO;\r
- break;\r
+#if defined( _CMU_LFCLKSEL_LFC_MASK )\r
+ case CMU_LFCCLKSEL_REG:\r
+ switch(ref)\r
+ {\r
+ case cmuSelect_Disabled:\r
+ tmp = _CMU_LFCLKSEL_LFA_DISABLED;\r
+ break;\r
+\r
+ case cmuSelect_LFXO:\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
+ tmp = _CMU_LFCLKSEL_LFC_LFXO;\r
+ break;\r
+\r
+ case cmuSelect_LFRCO:\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
+ tmp = _CMU_LFCLKSEL_LFC_LFRCO;\r
+ break;\r
+\r
+ default:\r
+ /* Illegal clock source for LFC selected */\r
+ EFM_ASSERT(0);\r
+ return;\r
+ }\r
\r
- case cmuSelect_LFRCO:\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
- tmp = _CMU_LFCLKSEL_LFC_LFRCO;\r
+ /* Apply select */\r
+ CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)\r
+ | (tmp << _CMU_LFCLKSEL_LFC_SHIFT);\r
break;\r
+#endif\r
+#endif\r
\r
- default:\r
- /* Illegal clock source for LFC selected */\r
- EFM_ASSERT(0);\r
- return;\r
- }\r
+#if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )\r
+ case CMU_DBGCLKSEL_REG:\r
+ switch(ref)\r
+ {\r
+#if defined( CMU_DBGCLKSEL_DBG )\r
+ case cmuSelect_AUXHFRCO:\r
+ /* Select AUXHFRCO as debug clock */\r
+ CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;\r
+ break;\r
\r
- /* Apply select */\r
- CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) |\r
- (tmp << _CMU_LFCLKSEL_LFC_SHIFT);\r
- break;\r
+ case cmuSelect_HFCLK:\r
+ /* Select divided HFCLK as debug clock */\r
+ CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;\r
+ break;\r
#endif\r
\r
#if defined( CMU_CTRL_DBGCLK )\r
- case CMU_DBGCLKSEL_REG:\r
- switch(ref)\r
- {\r
- case cmuSelect_AUXHFRCO:\r
- /* Select AUXHFRCO as debug clock */\r
- CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))| CMU_CTRL_DBGCLK_AUXHFRCO;\r
- break;\r
-\r
- case cmuSelect_HFCLK:\r
- /* Select divided HFCLK as debug clock */\r
- CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))| CMU_CTRL_DBGCLK_HFCLK;\r
+ case cmuSelect_AUXHFRCO:\r
+ /* Select AUXHFRCO as debug clock */\r
+ CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))\r
+ | CMU_CTRL_DBGCLK_AUXHFRCO;\r
+ break;\r
+\r
+ case cmuSelect_HFCLK:\r
+ /* Select divided HFCLK as debug clock */\r
+ CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))\r
+ | CMU_CTRL_DBGCLK_HFCLK;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ /* Illegal clock source for debug selected */\r
+ EFM_ASSERT(0);\r
+ return;\r
+ }\r
break;\r
-\r
- default:\r
- /* Illegal clock source for debug selected */\r
- EFM_ASSERT(0);\r
- return;\r
- }\r
- break;\r
#endif\r
\r
#if defined(USB_PRESENT)\r
- case CMU_USBCCLKSEL_REG:\r
- switch(ref)\r
- {\r
- case cmuSelect_LFXO:\r
- /* Select LFXO as clock source for USB, can only be used in sleep mode */\r
-\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
-\r
- /* Switch oscillator */\r
- CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;\r
-\r
- /* Wait until clock is activated */\r
- while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0);\r
- break;\r
-\r
- case cmuSelect_LFRCO:\r
- /* Select LFRCO as clock source for USB, can only be used in sleep mode */\r
-\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
-\r
- /* Switch oscillator */\r
- CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;\r
-\r
- /* Wait until clock is activated */\r
- while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0);\r
- break;\r
+ case CMU_USBCCLKSEL_REG:\r
+ switch(ref)\r
+ {\r
+ case cmuSelect_LFXO:\r
+ /* Select LFXO as clock source for USB, can only be used in sleep mode */\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFXO, true, true);\r
+\r
+ /* Switch oscillator */\r
+ CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;\r
+\r
+ /* Wait until clock is activated */\r
+ while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)\r
+ {\r
+ }\r
+ break;\r
+\r
+ case cmuSelect_LFRCO:\r
+ /* Select LFRCO as clock source for USB, can only be used in sleep mode */\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);\r
+\r
+ /* Switch oscillator */\r
+ CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;\r
+\r
+ /* Wait until clock is activated */\r
+ while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)\r
+ {\r
+ }\r
+ break;\r
\r
#if defined( CMU_STATUS_USBCHFCLKSEL )\r
- case cmuSelect_HFCLK:\r
- /* Select undivided HFCLK as clock source for USB */\r
-\r
- /* Oscillator must already be enabled to avoid a core lockup */\r
- CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;\r
- /* Wait until clock is activated */\r
- while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0);\r
- break;\r
+ case cmuSelect_HFCLK:\r
+ /* Select undivided HFCLK as clock source for USB */\r
+ /* Oscillator must already be enabled to avoid a core lockup */\r
+ CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;\r
+ /* Wait until clock is activated */\r
+ while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)\r
+ {\r
+ }\r
+ break;\r
#endif\r
\r
#if defined( CMU_CMD_USBCCLKSEL_USHFRCO )\r
- case cmuSelect_USHFRCO:\r
- /* Select USHFRCO as clock source for USB */\r
+ case cmuSelect_USHFRCO:\r
+ /* Select USHFRCO as clock source for USB */\r
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
+ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);\r
\r
- /* Ensure selected oscillator is enabled, waiting for it to stabilize */\r
- CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);\r
+ /* Switch oscillator */\r
+ CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;\r
\r
- /* Switch oscillator */\r
- CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;\r
+ /* Wait until clock is activated */\r
+ while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)\r
+ {\r
+ }\r
+ break;\r
+#endif\r
\r
- /* Wait until clock is activated */\r
- while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0);\r
+ default:\r
+ /* Illegal clock source for USB */\r
+ EFM_ASSERT(0);\r
+ return;\r
+ }\r
break;\r
#endif\r
\r
default:\r
- /* Illegal clock source for USB */\r
EFM_ASSERT(0);\r
- return;\r
- }\r
- /* Wait until clock has been activated */\r
- break;\r
-#endif\r
-\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
+ break;\r
}\r
}\r
\r
/* - then modifies the same register again */\r
/* since modifying a register while it is in sync progress should be */\r
/* avoided. */\r
- while (CMU->SYNCBUSY)\r
- ;\r
-\r
- CMU->FREEZE = CMU_FREEZE_REGFREEZE;\r
- }\r
- else\r
- {\r
- CMU->FREEZE = 0;\r
- }\r
-}\r
-\r
-\r
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
-/***************************************************************************//**\r
- * @brief\r
- * Get AUXHFRCO band in use.\r
- *\r
- * @return\r
- * AUXHFRCO band in use.\r
- ******************************************************************************/\r
-CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)\r
-{\r
- return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) >>\r
- _CMU_AUXHFRCOCTRL_BAND_SHIFT);\r
-}\r
-\r
-/***************************************************************************//**\r
- * @brief\r
- * Set AUIXHFRCO band and the tuning value based on the value in the\r
- * calibration table made during production.\r
- *\r
- * @param[in] band\r
- * AUXHFRCO band to activate.\r
- ******************************************************************************/\r
-void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)\r
-{\r
- uint32_t tuning;\r
-\r
- /* Read tuning value from calibration table */\r
- switch (band)\r
- {\r
- case cmuAUXHFRCOBand_1MHz:\r
- tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) >>\r
- _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;\r
- break;\r
-\r
- case cmuAUXHFRCOBand_7MHz:\r
- tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) >>\r
- _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;\r
- break;\r
-\r
- case cmuAUXHFRCOBand_11MHz:\r
- tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) >>\r
- _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;\r
- break;\r
-\r
- case cmuAUXHFRCOBand_14MHz:\r
- tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) >>\r
- _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;\r
- break;\r
-\r
- case cmuAUXHFRCOBand_21MHz:\r
- tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) >>\r
- _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;\r
- break;\r
-\r
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )\r
- case cmuAUXHFRCOBand_28MHz:\r
- tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) >>\r
- _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;\r
- break;\r
-#endif\r
-\r
- default:\r
- EFM_ASSERT(0);\r
- return;\r
- }\r
-\r
- /* Set band/tuning */\r
- CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &\r
- ~(_CMU_AUXHFRCOCTRL_BAND_MASK | _CMU_AUXHFRCOCTRL_TUNING_MASK)) |\r
- (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) |\r
- (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);\r
-\r
-}\r
-#endif\r
-\r
-\r
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )\r
-/***************************************************************************//**\r
- * @brief\r
- * Get USHFRCO band in use.\r
- *\r
- * @return\r
- * USHFRCO band in use.\r
- ******************************************************************************/\r
-CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)\r
-{\r
- return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF & _CMU_USHFRCOCONF_BAND_MASK) >>\r
- _CMU_USHFRCOCONF_BAND_SHIFT);\r
-}\r
-\r
-void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)\r
-{\r
- uint32_t tuning;\r
- uint32_t fineTuning;\r
- CMU_Select_TypeDef osc;\r
-\r
- /* Cannot switch band if USHFRCO is already selected as HF clock. */\r
- osc = CMU_ClockSelectGet(cmuClock_HF);\r
- EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));\r
-\r
- /* Read tuning value from calibration table */\r
- switch (band)\r
- {\r
- case cmuUSHFRCOBand_24MHz:\r
- tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) >>\r
- _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;\r
- fineTuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) >>\r
- _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;\r
- break;\r
-\r
- case cmuUSHFRCOBand_48MHz:\r
- tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) >>\r
- _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;\r
- fineTuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) >>\r
- _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;\r
- /* Enable the clock divider before switching the band from 24 to 48MHz */\r
- BITBAND_Peripheral(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);\r
- break;\r
+ while (CMU->SYNCBUSY)\r
+ {\r
+ }\r
\r
- default:\r
- EFM_ASSERT(0);\r
- return;\r
+ CMU->FREEZE = CMU_FREEZE_REGFREEZE;\r
}\r
-\r
- /* Set band and tuning */\r
- CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) |\r
- (band << _CMU_USHFRCOCONF_BAND_SHIFT);\r
- CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) |\r
- (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);\r
- CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) |\r
- (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);\r
-\r
- /* Disable the clock divider after switching the band from 48 to 24MHz */\r
- if (band == cmuUSHFRCOBand_24MHz)\r
+ else\r
{\r
- BITBAND_Peripheral(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);\r
+ CMU->FREEZE = 0;\r
}\r
}\r
-#endif\r
\r
\r
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Get HFRCO band in use.\r
******************************************************************************/\r
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)\r
{\r
- return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >>\r
- _CMU_HFRCOCTRL_BAND_SHIFT);\r
+ return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)\r
+ >> _CMU_HFRCOCTRL_BAND_SHIFT);\r
}\r
+#endif /* _CMU_HFRCOCTRL_BAND_MASK */\r
\r
\r
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Set HFRCO band and the tuning value based on the value in the calibration\r
/* Read tuning value from calibration table */\r
switch (band)\r
{\r
- case cmuHFRCOBand_1MHz:\r
- tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) >>\r
- _DEVINFO_HFRCOCAL0_BAND1_SHIFT;\r
- break;\r
+ case cmuHFRCOBand_1MHz:\r
+ tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)\r
+ >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;\r
+ break;\r
\r
- case cmuHFRCOBand_7MHz:\r
- tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) >>\r
- _DEVINFO_HFRCOCAL0_BAND7_SHIFT;\r
- break;\r
+ case cmuHFRCOBand_7MHz:\r
+ tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)\r
+ >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT;\r
+ break;\r
\r
- case cmuHFRCOBand_11MHz:\r
- tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) >>\r
- _DEVINFO_HFRCOCAL0_BAND11_SHIFT;\r
- break;\r
+ case cmuHFRCOBand_11MHz:\r
+ tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)\r
+ >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT;\r
+ break;\r
\r
- case cmuHFRCOBand_14MHz:\r
- tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) >>\r
- _DEVINFO_HFRCOCAL0_BAND14_SHIFT;\r
- break;\r
+ case cmuHFRCOBand_14MHz:\r
+ tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)\r
+ >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT;\r
+ break;\r
\r
- case cmuHFRCOBand_21MHz:\r
- tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) >>\r
- _DEVINFO_HFRCOCAL1_BAND21_SHIFT;\r
- break;\r
+ case cmuHFRCOBand_21MHz:\r
+ tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)\r
+ >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;\r
+ break;\r
\r
#if defined( _CMU_HFRCOCTRL_BAND_28MHZ )\r
- case cmuHFRCOBand_28MHz:\r
- tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) >>\r
- _DEVINFO_HFRCOCAL1_BAND28_SHIFT;\r
- break;\r
+ case cmuHFRCOBand_28MHz:\r
+ tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)\r
+ >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;\r
+ break;\r
#endif\r
\r
- default:\r
- EFM_ASSERT(0);\r
- return;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ return;\r
}\r
\r
/* If HFRCO is used for core clock, we have to consider flash access WS. */\r
if (osc == cmuSelect_HFRCO)\r
{\r
/* Configure worst case wait states for flash access before setting divider */\r
- CMU_FlashWaitStateMax();\r
+ flashWaitStateMax();\r
}\r
\r
/* Set band/tuning */\r
CMU->HFRCOCTRL = (CMU->HFRCOCTRL &\r
- ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) |\r
- (band << _CMU_HFRCOCTRL_BAND_SHIFT) |\r
- (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);\r
+ ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK))\r
+ | (band << _CMU_HFRCOCTRL_BAND_SHIFT)\r
+ | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);\r
\r
/* If HFRCO is used for core clock, optimize flash WS */\r
if (osc == cmuSelect_HFRCO)\r
freq = SystemCoreClockGet();\r
\r
/* Optimize flash access wait state setting for current core clk */\r
- CMU_FlashWaitStateControl(freq);\r
+ flashWaitStateControl(freq);\r
+ }\r
+}\r
+#endif /* _CMU_HFRCOCTRL_BAND_MASK */\r
+\r
+\r
+#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Get a pointer to the HFRCO frequency calibration word in DEVINFO\r
+ *\r
+ * @param[in] freq\r
+ * Frequency in Hz\r
+ *\r
+ * @return\r
+ * HFRCO calibration word for a given frequency\r
+ *****************************************************************************/\r
+static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)\r
+{\r
+ switch (freq)\r
+ {\r
+ /* 1, 2 and 4MHz share the same calibration word */\r
+ case cmuHFRCOFreq_1M0Hz:\r
+ case cmuHFRCOFreq_2M0Hz:\r
+ case cmuHFRCOFreq_4M0Hz:\r
+ return DEVINFO->HFRCOCAL0;\r
+\r
+ case cmuHFRCOFreq_7M0Hz:\r
+ return DEVINFO->HFRCOCAL3;\r
+\r
+ case cmuHFRCOFreq_13M0Hz:\r
+ return DEVINFO->HFRCOCAL6;\r
+\r
+ case cmuHFRCOFreq_16M0Hz:\r
+ return DEVINFO->HFRCOCAL7;\r
+\r
+ case cmuHFRCOFreq_19M0Hz:\r
+ return DEVINFO->HFRCOCAL8;\r
+\r
+ case cmuHFRCOFreq_26M0Hz:\r
+ return DEVINFO->HFRCOCAL10;\r
+\r
+ case cmuHFRCOFreq_32M0Hz:\r
+ return DEVINFO->HFRCOCAL11;\r
+\r
+ case cmuHFRCOFreq_38M0Hz:\r
+ return DEVINFO->HFRCOCAL12;\r
+\r
+ default: /* cmuHFRCOFreq_UserDefined */\r
+ return 0;\r
}\r
}\r
\r
\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get HFRCO frequency enumeration in use\r
+ *\r
+ * @return\r
+ * HFRCO frequency enumeration in use\r
+ ******************************************************************************/\r
+CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)\r
+{\r
+ return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set HFRCO calibration for the selected target frequency\r
+ *\r
+ * @param[in] freq\r
+ * HFRCO frequency band to set\r
+ ******************************************************************************/\r
+void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freq)\r
+{\r
+ uint32_t freqCal;\r
+\r
+ /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */\r
+ freqCal = CMU_HFRCODevinfoGet(freq);\r
+ EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));\r
+ SystemHfrcoFreq = (uint32_t)freq;\r
+\r
+ /* Set max wait-states while changing core clock */\r
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)\r
+ {\r
+ flashWaitStateMax();\r
+ }\r
+\r
+ /* Wait for any previous sync to complete, and then set calibration data\r
+ for the selected frequency. */\r
+ while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));\r
+\r
+ /* Check for valid calibration data */\r
+ EFM_ASSERT(freqCal != UINT_MAX);\r
+\r
+ /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */\r
+ switch(freq)\r
+ {\r
+ case cmuHFRCOFreq_1M0Hz:\r
+ freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)\r
+ | CMU_HFRCOCTRL_CLKDIV_DIV4;\r
+ break;\r
+\r
+ case cmuHFRCOFreq_2M0Hz:\r
+ freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)\r
+ | CMU_HFRCOCTRL_CLKDIV_DIV2;\r
+ break;\r
+\r
+ case cmuHFRCOFreq_4M0Hz:\r
+ freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)\r
+ | CMU_HFRCOCTRL_CLKDIV_DIV1;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ CMU->HFRCOCTRL = freqCal;\r
+\r
+ /* Optimize flash access wait-state configuration for this frequency, */\r
+ /* if HFRCO is reference for core clock. */\r
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)\r
+ {\r
+ flashWaitStateControl((uint32_t)freq);\r
+ }\r
+}\r
+#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */\r
+\r
+#if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Get the HFRCO startup delay.\r
******************************************************************************/\r
uint32_t CMU_HFRCOStartupDelayGet(void)\r
{\r
- return((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) >>\r
- _CMU_HFRCOCTRL_SUDELAY_SHIFT);\r
+ return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)\r
+ >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;\r
}\r
\r
\r
{\r
EFM_ASSERT(delay <= 31);\r
\r
- delay &= (_CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT);\r
- CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) |\r
- (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);\r
+ delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;\r
+ CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))\r
+ | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);\r
+}\r
+#endif\r
+\r
+\r
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable or disable HFXO autostart\r
+ *\r
+ * @param[in] enRACStartSel\r
+ * If true, HFXO is automatically started and selected upon RAC wakeup.\r
+ * If false, HFXO is not started or selected automatically upon RAC wakeup.\r
+ *\r
+ * @param[in] enEM0EM1Start\r
+ * If true, HFXO is automatically started upon entering EM0/EM1 entry from\r
+ * EM2/EM3. HFXO selection has to be handled by the user.\r
+ * If false, HFXO is not started automatically when entering EM0/EM1.\r
+ *\r
+ * @param[in] enEM0EM1StartSel\r
+ * If true, HFXO is automatically started and immediately selected upon\r
+ * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of\r
+ * HFSRCCLK until HFXO becomes ready.\r
+ * If false, HFXO is not started or selected automatically when entering\r
+ * EM0/EM1.\r
+ ******************************************************************************/\r
+void CMU_HFXOAutostartEnable(bool enRACStartSel,\r
+ bool enEM0EM1Start,\r
+ bool enEM0EM1StartSel)\r
+{\r
+ uint32_t hfxoCtrl;\r
+ hfxoCtrl = CMU->HFXOCTRL & ~(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK\r
+ | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK\r
+ | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);\r
+\r
+ hfxoCtrl |= (enRACStartSel ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)\r
+ | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)\r
+ | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);\r
+\r
+ CMU->HFXOCTRL = hfxoCtrl;\r
+}\r
+#endif /* _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK */\r
+\r
+\r
+#if defined( _CMU_HFXOCTRL_MASK )\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Set HFXO control registers\r
+ *\r
+ * @note\r
+ * HFXO configuration should be obtained from a configuration tool,\r
+ * app note or xtal datasheet. This function disables the HFXO to ensure\r
+ * a valid state before update.\r
+ *\r
+ * @param[in] hfxoInit\r
+ * HFXO setup parameters\r
+ *****************************************************************************/\r
+void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit)\r
+{\r
+ uint32_t ishReg;\r
+ uint32_t ishMax;\r
+\r
+ /* Do not disable HFXO if it is currently selected as HF/Core clock */\r
+ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO);\r
+\r
+ /* HFXO must be disabled before reconfiguration */\r
+ CMU_OscillatorEnable(cmuOsc_HFXO, false, false);\r
+\r
+ /* Apply control settings */\r
+ BUS_RegMaskedWrite(&CMU->HFXOCTRL,\r
+ _CMU_HFXOCTRL_LOWPOWER_MASK\r
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )\r
+ | _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK\r
+#endif\r
+ | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK\r
+ | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK,\r
+ (hfxoInit->lowPowerMode\r
+ ? CMU_HFXOCTRL_LOWPOWER : 0)\r
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )\r
+ | (hfxoInit->autoStartSelOnRacWakeup\r
+ ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)\r
+#endif\r
+ | (hfxoInit->autoStartEm01\r
+ ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)\r
+ | (hfxoInit->autoSelEm01\r
+ ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0));\r
+\r
+ /* Set XTAL tuning parameters */\r
+\r
+ /* Set peak detection threshold in CMU_HFXOCTRL1_PEAKDETTHR[2:0] (hidden). */\r
+ BUS_RegMaskedWrite((volatile uint32_t *)0x400E4028, 0x7, hfxoInit->thresholdPeakDetect);\r
+\r
+ /* Set tuning for startup and steady state */\r
+ BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,\r
+ _CMU_HFXOSTARTUPCTRL_CTUNE_MASK\r
+ | _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK\r
+ | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK\r
+ | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK,\r
+ (hfxoInit->ctuneStartup\r
+ << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)\r
+ | (hfxoInit->regIshStartup\r
+ << _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT)\r
+ | (hfxoInit->xoCoreBiasTrimStartup\r
+ << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT)\r
+ | 0x4 /* Recommended tuning */\r
+ << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT);\r
+\r
+ /* Adjust CMU_HFXOSTEADYSTATECTRL_REGISHUPPER according to regIshSteadyState.\r
+ Saturate at max value. Please see the reference manual page 433 and Section\r
+ 12.5.10 CMU_HFXOSTEADYSTATECTRL for more details. */\r
+ ishReg = hfxoInit->regIshSteadyState + 3;\r
+ ishMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK\r
+ >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;\r
+ ishReg = ishReg > ishMax ? ishMax : ishReg;\r
+ ishReg <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;\r
+\r
+ BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,\r
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK\r
+ | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK\r
+ | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK\r
+ | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,\r
+ (hfxoInit->ctuneSteadyState\r
+ << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)\r
+ | (hfxoInit->regIshSteadyState\r
+ << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)\r
+ | (hfxoInit->xoCoreBiasTrimSteadyState\r
+ << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)\r
+ | ishReg);\r
+\r
+ /* Set timeouts */\r
+ BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,\r
+ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK\r
+ | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK\r
+ | _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK\r
+ | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK\r
+ | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,\r
+ (hfxoInit->timeoutShuntOptimization\r
+ << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)\r
+ | (hfxoInit->timeoutPeakDetect\r
+ << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)\r
+ | (hfxoInit->timeoutWarmSteady\r
+ << _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT)\r
+ | (hfxoInit->timeoutSteady\r
+ << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)\r
+ | (hfxoInit->timeoutStartup\r
+ << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));\r
}\r
+#endif\r
\r
\r
/***************************************************************************//**\r
******************************************************************************/\r
uint32_t CMU_LCDClkFDIVGet(void)\r
{\r
-#if defined(LCD_PRESENT)\r
- return((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT);\r
+#if defined( LCD_PRESENT )\r
+ return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;\r
#else\r
return 0;\r
#endif /* defined(LCD_PRESENT) */\r
******************************************************************************/\r
void CMU_LCDClkFDIVSet(uint32_t div)\r
{\r
-#if defined(LCD_PRESENT)\r
+#if defined( LCD_PRESENT )\r
EFM_ASSERT(div <= cmuClkDiv_128);\r
\r
/* Do not allow modification if LCD clock enabled */\r
}\r
\r
\r
+#if defined( _CMU_LFXOCTRL_MASK )\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Set LFXO control registers\r
+ *\r
+ * @note\r
+ * LFXO configuration should be obtained from a configuration tool,\r
+ * app note or xtal datasheet. This function disables the LFXO to ensure\r
+ * a valid state before update.\r
+ *\r
+ * @param[in] lfxoInit\r
+ * LFXO setup parameters\r
+ *****************************************************************************/\r
+void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit)\r
+{\r
+ /* Do not disable LFXO if it is currently selected as HF/Core clock */\r
+ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO);\r
+\r
+ /* LFXO must be disabled before reconfiguration */\r
+ CMU_OscillatorEnable(cmuOsc_LFXO, false, false);\r
+\r
+ BUS_RegMaskedWrite(&CMU->LFXOCTRL,\r
+ _CMU_LFXOCTRL_TUNING_MASK\r
+ | _CMU_LFXOCTRL_GAIN_MASK\r
+ | _CMU_LFXOCTRL_TIMEOUT_MASK,\r
+ (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)\r
+ | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)\r
+ | (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT));\r
+}\r
+#endif\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Enable/disable oscillator.\r
******************************************************************************/\r
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)\r
{\r
- uint32_t status;\r
+ uint32_t rdyBitPos;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ uint32_t ensBitPos;\r
+#endif\r
uint32_t enBit;\r
uint32_t disBit;\r
\r
switch (osc)\r
{\r
- case cmuOsc_HFRCO:\r
- enBit = CMU_OSCENCMD_HFRCOEN;\r
- disBit = CMU_OSCENCMD_HFRCODIS;\r
- status = CMU_STATUS_HFRCORDY;\r
- break;\r
+ case cmuOsc_HFRCO:\r
+ enBit = CMU_OSCENCMD_HFRCOEN;\r
+ disBit = CMU_OSCENCMD_HFRCODIS;\r
+ rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;\r
+#endif\r
+ break;\r
\r
- case cmuOsc_HFXO:\r
- enBit = CMU_OSCENCMD_HFXOEN;\r
- disBit = CMU_OSCENCMD_HFXODIS;\r
- status = CMU_STATUS_HFXORDY;\r
- break;\r
+ case cmuOsc_HFXO:\r
+ enBit = CMU_OSCENCMD_HFXOEN;\r
+ disBit = CMU_OSCENCMD_HFXODIS;\r
+ rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;\r
+#endif\r
+ break;\r
\r
- case cmuOsc_AUXHFRCO:\r
- enBit = CMU_OSCENCMD_AUXHFRCOEN;\r
- disBit = CMU_OSCENCMD_AUXHFRCODIS;\r
- status = CMU_STATUS_AUXHFRCORDY;\r
- break;\r
+ case cmuOsc_AUXHFRCO:\r
+ enBit = CMU_OSCENCMD_AUXHFRCOEN;\r
+ disBit = CMU_OSCENCMD_AUXHFRCODIS;\r
+ rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;\r
+#endif\r
+ break;\r
\r
- case cmuOsc_LFRCO:\r
- enBit = CMU_OSCENCMD_LFRCOEN;\r
- disBit = CMU_OSCENCMD_LFRCODIS;\r
- status = CMU_STATUS_LFRCORDY;\r
- break;\r
+ case cmuOsc_LFRCO:\r
+ enBit = CMU_OSCENCMD_LFRCOEN;\r
+ disBit = CMU_OSCENCMD_LFRCODIS;\r
+ rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;\r
+#endif\r
+ break;\r
\r
- case cmuOsc_LFXO:\r
- enBit = CMU_OSCENCMD_LFXOEN;\r
- disBit = CMU_OSCENCMD_LFXODIS;\r
- status = CMU_STATUS_LFXORDY;\r
- break;\r
+ case cmuOsc_LFXO:\r
+ enBit = CMU_OSCENCMD_LFXOEN;\r
+ disBit = CMU_OSCENCMD_LFXODIS;\r
+ rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;\r
+#endif\r
+ break;\r
\r
#if defined( _CMU_STATUS_USHFRCOENS_MASK )\r
- case cmuOsc_USHFRCO:\r
- enBit = CMU_OSCENCMD_USHFRCOEN;\r
- disBit = CMU_OSCENCMD_USHFRCODIS;\r
- status = CMU_STATUS_USHFRCORDY;\r
- break;\r
+ case cmuOsc_USHFRCO:\r
+ enBit = CMU_OSCENCMD_USHFRCOEN;\r
+ disBit = CMU_OSCENCMD_USHFRCODIS;\r
+ rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;\r
+#endif\r
+ break;\r
#endif\r
\r
-#if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )\r
- case cmuOsc_ULFRCO:\r
- /* ULFRCO is always enabled, and cannot be turned off */\r
- return;\r
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )\r
+ case cmuOsc_ULFRCO:\r
+ /* ULFRCO is always enabled, and cannot be turned off */\r
+ return;\r
#endif\r
\r
- default:\r
- /* Undefined clock source */\r
- EFM_ASSERT(0);\r
- return;\r
+ default:\r
+ /* Undefined clock source */\r
+ EFM_ASSERT(0);\r
+ return;\r
}\r
\r
if (enable)\r
{\r
CMU->OSCENCMD = enBit;\r
\r
- /* Wait for clock to stabilize if requested */\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ /* Always wait for ENS to go high */\r
+ while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))\r
+ {\r
+ }\r
+#endif\r
+\r
+ /* Wait for clock to become ready after enable */\r
if (wait)\r
{\r
- while (!(CMU->STATUS & status))\r
- ;\r
+ while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));\r
+#if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )\r
+ /* Wait for shunt current optimization to complete */\r
+ if ((osc == cmuOsc_HFXO)\r
+ && (BUS_RegMaskedRead(&CMU->HFXOCTRL,\r
+ _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)\r
+ == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))\r
+ {\r
+ while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT))\r
+ {\r
+ }\r
+ /* Assert on failed peak detection. Incorrect HFXO initialization parameters\r
+ caused startup to fail. Please review parameters. */\r
+ EFM_ASSERT(BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOPEAKDETRDY_SHIFT));\r
+ }\r
+#endif\r
}\r
}\r
else\r
{\r
CMU->OSCENCMD = disBit;\r
+\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ /* Always wait for ENS to go low */\r
+ while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))\r
+ {\r
+ }\r
+#endif\r
}\r
\r
/* Keep EMU module informed */\r
\r
switch (osc)\r
{\r
- case cmuOsc_LFRCO:\r
- ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) >>\r
- _CMU_LFRCOCTRL_TUNING_SHIFT;\r
- break;\r
+ case cmuOsc_LFRCO:\r
+ ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)\r
+ >> _CMU_LFRCOCTRL_TUNING_SHIFT;\r
+ break;\r
\r
- case cmuOsc_HFRCO:\r
- ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) >>\r
- _CMU_HFRCOCTRL_TUNING_SHIFT;\r
- break;\r
+ case cmuOsc_HFRCO:\r
+ ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK)\r
+ >> _CMU_HFRCOCTRL_TUNING_SHIFT;\r
+ break;\r
\r
- case cmuOsc_AUXHFRCO:\r
- ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) >>\r
- _CMU_AUXHFRCOCTRL_TUNING_SHIFT;\r
- break;\r
+ case cmuOsc_AUXHFRCO:\r
+ ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)\r
+ >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT;\r
+ break;\r
\r
- default:\r
- EFM_ASSERT(0);\r
- ret = 0;\r
- break;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ ret = 0;\r
+ break;\r
}\r
\r
- return(ret);\r
+ return ret;\r
}\r
\r
\r
{\r
switch (osc)\r
{\r
- case cmuOsc_LFRCO:\r
- EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT));\r
-\r
- val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);\r
- CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) |\r
- (val << _CMU_LFRCOCTRL_TUNING_SHIFT);\r
- break;\r
-\r
- case cmuOsc_HFRCO:\r
- EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT));\r
-\r
- val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);\r
- CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) |\r
- (val << _CMU_HFRCOCTRL_TUNING_SHIFT);\r
- break;\r
+ case cmuOsc_LFRCO:\r
+ EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK\r
+ >> _CMU_LFRCOCTRL_TUNING_SHIFT));\r
+ val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));\r
+#endif\r
+ CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))\r
+ | (val << _CMU_LFRCOCTRL_TUNING_SHIFT);\r
+ break;\r
\r
- case cmuOsc_AUXHFRCO:\r
- EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));\r
+ case cmuOsc_HFRCO:\r
+ EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK\r
+ >> _CMU_HFRCOCTRL_TUNING_SHIFT));\r
+ val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))\r
+ {\r
+ }\r
+#endif\r
+ CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))\r
+ | (val << _CMU_HFRCOCTRL_TUNING_SHIFT);\r
+ break;\r
\r
- val <<= _CMU_AUXHFRCOCTRL_TUNING_SHIFT;\r
- val &= _CMU_AUXHFRCOCTRL_TUNING_MASK;\r
- CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) | val;\r
- break;\r
+ case cmuOsc_AUXHFRCO:\r
+ EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK\r
+ >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));\r
+ val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT);\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+ while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))\r
+ {\r
+ }\r
+#endif\r
+ CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))\r
+ | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);\r
+ break;\r
\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
}\r
\r
* @brief\r
* Determine if currently selected PCNTn clock used is external or LFBCLK.\r
*\r
- * @param[in] inst\r
+ * @param[in] instance\r
* PCNT instance number to get currently selected clock source for.\r
*\r
* @return\r
* @li true - selected clock is external clock.\r
* @li false - selected clock is LFBCLK.\r
*****************************************************************************/\r
-bool CMU_PCNTClockExternalGet(unsigned int inst)\r
+bool CMU_PCNTClockExternalGet(unsigned int instance)\r
{\r
- bool ret;\r
uint32_t setting;\r
\r
- switch (inst)\r
+ switch (instance)\r
{\r
-#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)\r
- case 0:\r
- setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;\r
- break;\r
+#if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )\r
+ case 0:\r
+ setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;\r
+ break;\r
\r
-#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)\r
- case 1:\r
- setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;\r
- break;\r
+#if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )\r
+ case 1:\r
+ setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;\r
+ break;\r
\r
-#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)\r
- case 2:\r
- setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;\r
- break;\r
+#if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )\r
+ case 2:\r
+ setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;\r
+ break;\r
#endif\r
#endif\r
#endif\r
\r
- default:\r
- setting = 0;\r
- break;\r
- }\r
-\r
- if (setting)\r
- {\r
- ret = true;\r
- }\r
- else\r
- {\r
- ret = false;\r
+ default:\r
+ setting = 0;\r
+ break;\r
}\r
- return ret;\r
+ return (setting ? true : false);\r
}\r
\r
\r
* @brief\r
* Select PCNTn clock.\r
*\r
- * @param[in] inst\r
+ * @param[in] instance\r
* PCNT instance number to set selected clock source for.\r
*\r
* @param[in] external\r
* Set to true to select external clock, false to select LFBCLK.\r
*****************************************************************************/\r
-void CMU_PCNTClockExternalSet(unsigned int inst, bool external)\r
+void CMU_PCNTClockExternalSet(unsigned int instance, bool external)\r
{\r
-#if defined(PCNT_PRESENT)\r
+#if defined( PCNT_PRESENT )\r
uint32_t setting = 0;\r
\r
- EFM_ASSERT(inst < PCNT_COUNT);\r
+ EFM_ASSERT(instance < PCNT_COUNT);\r
\r
if (external)\r
{\r
setting = 1;\r
}\r
\r
- BITBAND_Peripheral(&(CMU->PCNTCTRL), (inst * 2) + 1, setting);\r
+ BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting);\r
\r
#else\r
- (void)inst; /* Unused parameter */\r
+ (void)instance; /* Unused parameter */\r
(void)external; /* Unused parameter */\r
#endif\r
}\r
\r
\r
+#if defined( _CMU_USHFRCOCONF_BAND_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get USHFRCO band in use.\r
+ *\r
+ * @return\r
+ * USHFRCO band in use.\r
+ ******************************************************************************/\r
+CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)\r
+{\r
+ return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF\r
+ & _CMU_USHFRCOCONF_BAND_MASK)\r
+ >> _CMU_USHFRCOCONF_BAND_SHIFT);\r
+}\r
+#endif\r
+\r
+#if defined( _CMU_USHFRCOCONF_BAND_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set USHFRCO band to use.\r
+ *\r
+ * @param[in] band\r
+ * USHFRCO band to activate.\r
+ ******************************************************************************/\r
+void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)\r
+{\r
+ uint32_t tuning;\r
+ uint32_t fineTuning;\r
+ CMU_Select_TypeDef osc;\r
+\r
+ /* Cannot switch band if USHFRCO is already selected as HF clock. */\r
+ osc = CMU_ClockSelectGet(cmuClock_HF);\r
+ EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));\r
+\r
+ /* Read tuning value from calibration table */\r
+ switch (band)\r
+ {\r
+ case cmuUSHFRCOBand_24MHz:\r
+ tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)\r
+ >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;\r
+ fineTuning = (DEVINFO->USHFRCOCAL0\r
+ & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)\r
+ >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;\r
+ break;\r
+\r
+ case cmuUSHFRCOBand_48MHz:\r
+ tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)\r
+ >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;\r
+ fineTuning = (DEVINFO->USHFRCOCAL0\r
+ & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)\r
+ >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;\r
+ /* Enable the clock divider before switching the band from 24 to 48MHz */\r
+ BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ return;\r
+ }\r
+\r
+ /* Set band and tuning */\r
+ CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)\r
+ | (band << _CMU_USHFRCOCONF_BAND_SHIFT);\r
+ CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)\r
+ | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);\r
+ CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)\r
+ | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);\r
+\r
+ /* Disable the clock divider after switching the band from 48 to 24MHz */\r
+ if (band == cmuUSHFRCOBand_24MHz)\r
+ {\r
+ BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+\r
/** @} (end addtogroup CMU) */\r
/** @} (end addtogroup EM_Library) */\r
#endif /* __EM_CMU_H */\r
/***************************************************************************//**\r
* @file em_emu.c\r
* @brief Energy Management Unit (EMU) Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
+#include <limits.h>\r
\r
#include "em_emu.h"\r
#if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )\r
\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
/* Fix for errata EMU_E107 - non-WIC interrupt masks. */\r
-#if defined(_EFM32_GECKO_FAMILY)\r
- #define ERRATA_FIX_EMU_E107_EN\r
- #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))\r
- #define NON_WIC_INT_MASK_1 (~(0x0U))\r
-#elif defined(_EFM32_TINY_FAMILY)\r
- #define ERRATA_FIX_EMU_E107_EN\r
- #define NON_WIC_INT_MASK_0 (~(0x001be323U))\r
- #define NON_WIC_INT_MASK_1 (~(0x0U))\r
-#elif defined(_EFM32_GIANT_FAMILY)\r
- #define ERRATA_FIX_EMU_E107_EN\r
- #define NON_WIC_INT_MASK_0 (~(0xff020e63U))\r
- #define NON_WIC_INT_MASK_1 (~(0x00000046U))\r
-#elif defined(_EFM32_WONDER_FAMILY)\r
- #define ERRATA_FIX_EMU_E107_EN\r
- #define NON_WIC_INT_MASK_0 (~(0xff020e63U))\r
- #define NON_WIC_INT_MASK_1 (~(0x00000046U))\r
+#if defined( _EFM32_GECKO_FAMILY )\r
+#define ERRATA_FIX_EMU_E107_EN\r
+#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))\r
+#define NON_WIC_INT_MASK_1 (~(0x0U))\r
+\r
+#elif defined( _EFM32_TINY_FAMILY )\r
+#define ERRATA_FIX_EMU_E107_EN\r
+#define NON_WIC_INT_MASK_0 (~(0x001be323U))\r
+#define NON_WIC_INT_MASK_1 (~(0x0U))\r
+\r
+#elif defined( _EFM32_GIANT_FAMILY )\r
+#define ERRATA_FIX_EMU_E107_EN\r
+#define NON_WIC_INT_MASK_0 (~(0xff020e63U))\r
+#define NON_WIC_INT_MASK_1 (~(0x00000046U))\r
+\r
+#elif defined( _EFM32_WONDER_FAMILY )\r
+#define ERRATA_FIX_EMU_E107_EN\r
+#define NON_WIC_INT_MASK_0 (~(0xff020e63U))\r
+#define NON_WIC_INT_MASK_1 (~(0x00000046U))\r
+\r
#else\r
/* Zero Gecko and future families are not affected by errata EMU_E107 */\r
#endif\r
\r
/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */\r
-#if defined(_EFM32_HAPPY_FAMILY)\r
+#if defined( _EFM32_HAPPY_FAMILY )\r
#define ERRATA_FIX_EMU_E108_EN\r
#endif\r
/** @endcond */\r
\r
+\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+/* DCDCTODVDD output range min/max */\r
+#define PWRCFG_DCDCTODVDD_VMIN 1200\r
+#define PWRCFG_DCDCTODVDD_VMAX 3000\r
+typedef enum\r
+{\r
+ errataFixDcdcHsInit,\r
+ errataFixDcdcHsTrimSet,\r
+ errataFixDcdcHsLnWaitDone\r
+} errataFixDcdcHs_TypeDef;\r
+errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit;\r
+#endif\r
+\r
/*******************************************************************************\r
************************** LOCAL VARIABLES ********************************\r
******************************************************************************/\r
* for oscillator control).\r
*/\r
static uint32_t cmuStatus;\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
+static uint16_t cmuHfclkStatus;\r
+#endif\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+static uint16_t dcdcMaxCurrent_mA;\r
+static uint16_t dcdcOutput_mVout;\r
+#endif\r
+\r
/** @endcond */\r
\r
\r
* @brief\r
* Restore oscillators and core clock after having been in EM2 or EM3.\r
******************************************************************************/\r
-static void EMU_Restore(void)\r
+static void emuRestore(void)\r
{\r
uint32_t oscEnCmd;\r
uint32_t cmuLocked;\r
- uint32_t statusClkSelMask;\r
\r
/* Although we could use the CMU API for most of the below handling, we */\r
/* would like this function to be as efficient as possible. */\r
#endif\r
CMU->OSCENCMD = oscEnCmd;\r
\r
- statusClkSelMask =\r
- (CMU_STATUS_HFRCOSEL |\r
- CMU_STATUS_HFXOSEL |\r
- CMU_STATUS_LFRCOSEL |\r
-#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
- CMU_STATUS_USHFRCODIV2SEL |\r
-#endif\r
- CMU_STATUS_LFXOSEL);\r
\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
/* Restore oscillator used for clocking core */\r
- switch (cmuStatus & statusClkSelMask)\r
+ switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)\r
{\r
- case CMU_STATUS_LFRCOSEL:\r
- /* Wait for LFRCO to stabilize */\r
- while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))\r
- ;\r
- CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO;\r
- break;\r
-\r
- case CMU_STATUS_LFXOSEL:\r
- /* Wait for LFXO to stabilize */\r
- while (!(CMU->STATUS & CMU_STATUS_LFXORDY))\r
- ;\r
- CMU->CMD = CMU_CMD_HFCLKSEL_LFXO;\r
- break;\r
-\r
- case CMU_STATUS_HFXOSEL:\r
- /* Wait for HFXO to stabilize */\r
- while (!(CMU->STATUS & CMU_STATUS_HFXORDY))\r
- ;\r
- CMU->CMD = CMU_CMD_HFCLKSEL_HFXO;\r
- break;\r
+ case CMU_HFCLKSTATUS_SELECTED_LFRCO:\r
+ /* HFRCO could only be selected if the autostart HFXO feature is not\r
+ * enabled, otherwise the HFXO would be started and selected automatically.\r
+ * Note: this error hook helps catching erroneous oscillator configurations,\r
+ * when the AUTOSTARTSELEM0EM1 is set in CMU_HFXOCTRL. */\r
+ if (!(CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1))\r
+ {\r
+ /* Wait for LFRCO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))\r
+ ;\r
+ CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO;\r
+ }\r
+ else\r
+ {\r
+ EFM_ASSERT(0);\r
+ }\r
+ break;\r
+\r
+ case CMU_HFCLKSTATUS_SELECTED_LFXO:\r
+ /* Wait for LFXO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_LFXORDY))\r
+ ;\r
+ CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO;\r
+ break;\r
+\r
+ case CMU_HFCLKSTATUS_SELECTED_HFXO:\r
+ /* Wait for HFXO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_HFXORDY))\r
+ ;\r
+ CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;\r
+ break;\r
+\r
+ default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */\r
+ /* If core clock was HFRCO core clock, it is automatically restored to */\r
+ /* state prior to entering energy mode. No need for further action. */\r
+ break;\r
+ }\r
+#else\r
+ switch (cmuStatus & (CMU_STATUS_HFRCOSEL\r
+ | CMU_STATUS_HFXOSEL\r
+ | CMU_STATUS_LFRCOSEL\r
+#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
+ | CMU_STATUS_USHFRCODIV2SEL\r
+#endif\r
+ | CMU_STATUS_LFXOSEL))\r
+ {\r
+ case CMU_STATUS_LFRCOSEL:\r
+ /* Wait for LFRCO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_LFRCORDY))\r
+ ;\r
+ CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO;\r
+ break;\r
+\r
+ case CMU_STATUS_LFXOSEL:\r
+ /* Wait for LFXO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_LFXORDY))\r
+ ;\r
+ CMU->CMD = CMU_CMD_HFCLKSEL_LFXO;\r
+ break;\r
+\r
+ case CMU_STATUS_HFXOSEL:\r
+ /* Wait for HFXO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_HFXORDY))\r
+ ;\r
+ CMU->CMD = CMU_CMD_HFCLKSEL_HFXO;\r
+ break;\r
\r
#if defined( CMU_STATUS_USHFRCODIV2SEL )\r
- case CMU_STATUS_USHFRCODIV2SEL:\r
- /* Wait for USHFRCO to stabilize */\r
- while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY))\r
- ;\r
- CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;\r
- break;\r
+ case CMU_STATUS_USHFRCODIV2SEL:\r
+ /* Wait for USHFRCO to stabilize */\r
+ while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY))\r
+ ;\r
+ CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;\r
+ break;\r
#endif\r
\r
- default: /* CMU_STATUS_HFRCOSEL */\r
- /* If core clock was HFRCO core clock, it is automatically restored to */\r
- /* state prior to entering energy mode. No need for further action. */\r
- break;\r
+ default: /* CMU_STATUS_HFRCOSEL */\r
+ /* If core clock was HFRCO core clock, it is automatically restored to */\r
+ /* state prior to entering energy mode. No need for further action. */\r
+ break;\r
}\r
\r
/* If HFRCO was disabled before entering Energy Mode, turn it off again */\r
{\r
CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS;\r
}\r
-\r
+#endif\r
/* Restore CMU register locking */\r
if (cmuLocked)\r
{\r
}\r
\r
\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
/* Get enable conditions for errata EMU_E107 fix. */\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
static __INLINE bool getErrataFixEmuE107En(void)\r
{\r
- /* SYSTEM_ChipRevisionGet could have been used here, but we would like a faster implementation in this case. */\r
+ /* SYSTEM_ChipRevisionGet could have been used here, but we would like a\r
+ * faster implementation in this case.\r
+ */\r
uint16_t majorMinorRev;\r
\r
/* CHIP MAJOR bit [3:0] */\r
- majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);\r
+ majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)\r
+ >> _ROMTABLE_PID0_REVMAJOR_SHIFT)\r
+ << 8;\r
/* CHIP MINOR bit [7:4] */\r
- majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);\r
+ majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)\r
+ >> _ROMTABLE_PID2_REVMINORMSB_SHIFT)\r
+ << 4;\r
/* CHIP MINOR bit [3:0] */\r
- majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);\r
+ majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)\r
+ >> _ROMTABLE_PID3_REVMINORLSB_SHIFT;\r
\r
-#if defined(_EFM32_GECKO_FAMILY)\r
+#if defined( _EFM32_GECKO_FAMILY )\r
return (majorMinorRev <= 0x0103);\r
-#elif defined(_EFM32_TINY_FAMILY)\r
+#elif defined( _EFM32_TINY_FAMILY )\r
return (majorMinorRev <= 0x0102);\r
-#elif defined(_EFM32_GIANT_FAMILY)\r
+#elif defined( _EFM32_GIANT_FAMILY )\r
return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);\r
-#elif defined(_EFM32_WONDER_FAMILY)\r
+#elif defined( _EFM32_WONDER_FAMILY )\r
return (majorMinorRev == 0x0100);\r
#else\r
/* Zero Gecko and future families are not affected by errata EMU_E107 */\r
}\r
#endif\r
\r
+\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+/* LP prepare / LN restore P/NFET count */\r
+static void maxCurrentUpdate(void);\r
+#define DCDC_LP_PFET_CNT 7\r
+#define DCDC_LP_NFET_CNT 15\r
+void dcdcFetCntSet(bool lpModeSet)\r
+{\r
+ uint32_t tmp;\r
+ static uint32_t emuDcdcMiscCtrlReg;\r
+\r
+ if (lpModeSet)\r
+ {\r
+ emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL;\r
+ tmp = EMU->DCDCMISCCTRL\r
+ & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK);\r
+ tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT)\r
+ | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);\r
+ EMU->DCDCMISCCTRL = tmp;\r
+ maxCurrentUpdate();\r
+ }\r
+ else\r
+ {\r
+ EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;\r
+ maxCurrentUpdate();\r
+ }\r
+}\r
+\r
+void dcdcHsFixLnBlock(void)\r
+{\r
+#define EMU_DCDCSTATUS (* (volatile uint32_t *)(EMU_BASE + 0x7C))\r
+ if (errataFixDcdcHsState == errataFixDcdcHsTrimSet)\r
+ {\r
+ /* Wait for LNRUNNING */\r
+ if ((EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)\r
+ {\r
+ while (!(EMU_DCDCSTATUS & (0x1 << 16)));\r
+ }\r
+ errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
/** @endcond */\r
\r
\r
* If a debugger is attached, the AUXHFRCO will not be disabled if enabled\r
* upon entering EM2. It will thus remain enabled when returning to EM0\r
* regardless of the @p restore parameter.\r
+ * @par\r
+ * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(),\r
+ * the starting and selecting of the core clocks will be identical to the user\r
+ * independently of the value of the @p restore parameter when waking up on\r
+ * the wakeup sources corresponding to the autostart and select setting.\r
*\r
* @param[in] restore\r
* @li true - restore oscillators and clocks, see function details.\r
******************************************************************************/\r
void EMU_EnterEM2(bool restore)\r
{\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
bool errataFixEmuE107En;\r
uint32_t nonWicIntEn[2];\r
#endif\r
/* Auto-update CMU status just in case before entering energy mode. */\r
/* This variable is normally kept up-to-date by the CMU API. */\r
cmuStatus = CMU->STATUS;\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
+ cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);\r
+#endif\r
\r
- /* Enter Cortex-M3 deep sleep mode */\r
+ /* Enter Cortex deep sleep mode */\r
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
\r
/* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.\r
Disable the enabled non-WIC interrupts. */\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
errataFixEmuE107En = getErrataFixEmuE107En();\r
if (errataFixEmuE107En)\r
{\r
}\r
#endif\r
\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+ dcdcFetCntSet(true);\r
+ dcdcHsFixLnBlock();\r
+#endif\r
+\r
__WFI();\r
\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+ dcdcFetCntSet(false);\r
+#endif\r
+\r
/* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
if (errataFixEmuE107En)\r
{\r
NVIC->ISER[0] = nonWicIntEn[0];\r
/* Restore oscillators/clocks if specified */\r
if (restore)\r
{\r
- EMU_Restore();\r
+ emuRestore();\r
}\r
/* If not restoring, and original clock was not HFRCO, we have to */\r
/* update CMSIS core clock variable since core clock has changed */\r
/* to using HFRCO. */\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
+ else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)\r
+ != CMU_HFCLKSTATUS_SELECTED_HFRCO)\r
+#else\r
else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))\r
+#endif\r
{\r
SystemCoreClockUpdate();\r
}\r
{\r
uint32_t cmuLocked;\r
\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
bool errataFixEmuE107En;\r
uint32_t nonWicIntEn[2];\r
#endif\r
/* Auto-update CMU status just in case before entering energy mode. */\r
/* This variable is normally kept up-to-date by the CMU API. */\r
cmuStatus = CMU->STATUS;\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
+ cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);\r
+#endif\r
\r
/* CMU registers may be locked */\r
cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED;\r
CMU_Lock();\r
}\r
\r
- /* Enter Cortex-M3 deep sleep mode */\r
+ /* Enter Cortex deep sleep mode */\r
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
\r
/* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.\r
Disable the enabled non-WIC interrupts. */\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
errataFixEmuE107En = getErrataFixEmuE107En();\r
if (errataFixEmuE107En)\r
{\r
}\r
#endif\r
\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+ dcdcFetCntSet(true);\r
+ dcdcHsFixLnBlock();\r
+#endif\r
+\r
__WFI();\r
\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+ dcdcFetCntSet(false);\r
+#endif\r
+\r
/* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */\r
-#if defined(ERRATA_FIX_EMU_E107_EN)\r
+#if defined( ERRATA_FIX_EMU_E107_EN )\r
if (errataFixEmuE107En)\r
{\r
NVIC->ISER[0] = nonWicIntEn[0];\r
/* Restore oscillators/clocks if specified */\r
if (restore)\r
{\r
- EMU_Restore();\r
+ emuRestore();\r
}\r
/* If not restoring, and original clock was not HFRCO, we have to */\r
/* update CMSIS core clock variable since core clock has changed */\r
/* to using HFRCO. */\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
+ else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)\r
+ != CMU_HFCLKSTATUS_SELECTED_HFRCO)\r
+#else\r
else if (!(cmuStatus & CMU_STATUS_HFRCOSEL))\r
+#endif\r
{\r
SystemCoreClockUpdate();\r
}\r
void EMU_EnterEM4(void)\r
{\r
int i;\r
- uint32_t em4seq2;\r
- uint32_t em4seq3;\r
\r
- em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) | (2 << _EMU_CTRL_EM4CTRL_SHIFT);\r
- em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) | (3 << _EMU_CTRL_EM4CTRL_SHIFT);\r
+#if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )\r
+ uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)\r
+ | (2 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);\r
+ uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)\r
+ | (3 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);\r
+#else\r
+ uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)\r
+ | (2 << _EMU_CTRL_EM4CTRL_SHIFT);\r
+ uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK)\r
+ | (3 << _EMU_CTRL_EM4CTRL_SHIFT);\r
+#endif\r
\r
/* Make sure register write lock is disabled */\r
EMU_Unlock();\r
\r
-#if defined(ERRATA_FIX_EMU_E108_EN)\r
+#if defined( ERRATA_FIX_EMU_E108_EN )\r
/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */\r
__disable_irq();\r
*(volatile uint32_t *)0x400C80E4 = 0;\r
#endif\r
\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+ dcdcFetCntSet(true);\r
+ dcdcHsFixLnBlock();\r
+#endif\r
+\r
for (i = 0; i < 4; i++)\r
{\r
+#if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )\r
+ EMU->EM4CTRL = em4seq2;\r
+ EMU->EM4CTRL = em4seq3;\r
+ }\r
+ EMU->EM4CTRL = em4seq2;\r
+#else\r
EMU->CTRL = em4seq2;\r
EMU->CTRL = em4seq3;\r
}\r
EMU->CTRL = em4seq2;\r
+#endif\r
}\r
\r
\r
* @param[in] blocks\r
* Specifies a logical OR of bits indicating memory blocks to power down.\r
* Bit 0 selects block 1, bit 1 selects block 2, etc. Memory block 0 cannot\r
- * be disabled. Please refer to the EFM32 reference manual for available\r
+ * be disabled. Please refer to the reference manual for available\r
* memory blocks for a device.\r
*\r
* @note\r
******************************************************************************/\r
void EMU_MemPwrDown(uint32_t blocks)\r
{\r
-#if defined(_EMU_MEMCTRL_RESETVALUE)\r
- EFM_ASSERT(blocks <= _EMU_MEMCTRL_MASK);\r
+#if defined( _EMU_MEMCTRL_POWERDOWN_MASK )\r
+ EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK\r
+ >> _EMU_MEMCTRL_POWERDOWN_SHIFT));\r
+ EMU->MEMCTRL = blocks;\r
\r
+#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \\r
+ && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \\r
+ && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK )\r
+ EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK\r
+ | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK\r
+ | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK))\r
+ == blocks);\r
EMU->MEMCTRL = blocks;\r
+\r
+#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK )\r
+ EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks);\r
+ EMU->MEMCTRL = blocks;\r
+\r
+#elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK )\r
+ EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks);\r
+ EMU->RAM0CTRL = blocks;\r
+\r
#else\r
(void)blocks;\r
#endif\r
{\r
/* Fetch current configuration */\r
cmuStatus = CMU->STATUS;\r
+#if defined( _CMU_HFCLKSTATUS_RESETVALUE )\r
+ cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS);\r
+#endif\r
}\r
\r
\r
-#if defined( _EMU_CTRL_EMVREG_MASK ) || defined( _EMU_CTRL_EM23VREG_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Update EMU module with Energy Mode 2 and 3 configuration\r
void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)\r
{\r
#if defined( _EMU_CTRL_EMVREG_MASK )\r
- EMU->CTRL = em23Init->em23Vreg ? (EMU->CTRL | EMU_CTRL_EMVREG) : (EMU->CTRL & ~EMU_CTRL_EMVREG);\r
+ EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG)\r
+ : (EMU->CTRL & ~EMU_CTRL_EMVREG);\r
#elif defined( _EMU_CTRL_EM23VREG_MASK )\r
- EMU->CTRL = em23Init->em23Vreg ? (EMU->CTRL | EMU_CTRL_EM23VREG) : (EMU->CTRL & ~EMU_CTRL_EM23VREG);\r
+ EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG)\r
+ : (EMU->CTRL & ~EMU_CTRL_EM23VREG);\r
+#else\r
+ (void)em23Init;\r
#endif\r
}\r
-#endif\r
\r
\r
-#if defined( _EMU_EM4CONF_MASK )\r
+#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Update EMU module with Energy Mode 4 configuration\r
******************************************************************************/\r
void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)\r
{\r
+#if defined( _EMU_EM4CONF_MASK )\r
+ /* Init for platforms with EMU->EM4CONF register */\r
uint32_t em4conf = EMU->EM4CONF;\r
\r
/* Clear fields that will be reconfigured */\r
- em4conf &= ~(\r
- _EMU_EM4CONF_LOCKCONF_MASK |\r
- _EMU_EM4CONF_OSC_MASK |\r
- _EMU_EM4CONF_BURTCWU_MASK |\r
- _EMU_EM4CONF_VREGEN_MASK);\r
+ em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK\r
+ | _EMU_EM4CONF_OSC_MASK\r
+ | _EMU_EM4CONF_BURTCWU_MASK\r
+ | _EMU_EM4CONF_VREGEN_MASK);\r
\r
/* Configure new settings */\r
- em4conf |= (\r
- (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) |\r
- (em4Init->osc) |\r
- (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) |\r
- (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT));\r
+ em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)\r
+ | (em4Init->osc)\r
+ | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)\r
+ | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);\r
\r
/* Apply configuration. Note that lock can be set after this stage. */\r
EMU->EM4CONF = em4conf;\r
+\r
+#elif defined( _EMU_EM4CTRL_MASK )\r
+ /* Init for platforms with EMU->EM4CTRL register */\r
+\r
+ uint32_t em4ctrl = EMU->EM4CTRL;\r
+\r
+ em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK\r
+ | _EMU_EM4CTRL_RETAINLFRCO_MASK\r
+ | _EMU_EM4CTRL_RETAINULFRCO_MASK\r
+ | _EMU_EM4CTRL_EM4STATE_MASK\r
+ | _EMU_EM4CTRL_EM4IORETMODE_MASK);\r
+\r
+ em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0)\r
+ | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0)\r
+ | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)\r
+ | (em4Init->em4State ? EMU_EM4CTRL_EM4STATE_EM4H : 0)\r
+ | (em4Init->pinRetentionMode);\r
+\r
+ EMU->EM4CTRL = em4ctrl;\r
+#endif\r
}\r
#endif\r
\r
\r
#if defined( BU_PRESENT )\r
-\r
/***************************************************************************//**\r
* @brief\r
* Configure Backup Power Domain settings\r
uint32_t reg;\r
\r
/* Set power connection configuration */\r
- reg = EMU->PWRCONF & ~(\r
- _EMU_PWRCONF_PWRRES_MASK|\r
- _EMU_PWRCONF_VOUTSTRONG_MASK|\r
- _EMU_PWRCONF_VOUTMED_MASK|\r
- _EMU_PWRCONF_VOUTWEAK_MASK);\r
+ reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK\r
+ | _EMU_PWRCONF_VOUTSTRONG_MASK\r
+ | _EMU_PWRCONF_VOUTMED_MASK\r
+ | _EMU_PWRCONF_VOUTWEAK_MASK);\r
\r
- reg |= (bupdInit->resistor|\r
- (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)|\r
- (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)|\r
- (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT));\r
+ reg |= bupdInit->resistor\r
+ | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)\r
+ | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)\r
+ | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT);\r
\r
EMU->PWRCONF = reg;\r
\r
EMU->BUACT = reg;\r
\r
/* Set power control configuration */\r
- reg = EMU->BUCTRL & ~(\r
- _EMU_BUCTRL_PROBE_MASK|\r
- _EMU_BUCTRL_BODCAL_MASK|\r
- _EMU_BUCTRL_STATEN_MASK|\r
- _EMU_BUCTRL_EN_MASK);\r
+ reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK\r
+ | _EMU_BUCTRL_BODCAL_MASK\r
+ | _EMU_BUCTRL_STATEN_MASK\r
+ | _EMU_BUCTRL_EN_MASK);\r
\r
/* Note use of ->enable to both enable BUPD, use BU_VIN pin input and\r
release reset */\r
- reg |= (bupdInit->probe|\r
- (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)|\r
- (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)|\r
- (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT));\r
+ reg |= bupdInit->probe\r
+ | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)\r
+ | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)\r
+ | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT);\r
\r
/* Enable configuration */\r
EMU->BUCTRL = reg;\r
EMU_BUPinEnable(bupdInit->enable);\r
\r
/* If enable is true, release BU reset, if not keep reset asserted */\r
- BITBAND_Peripheral(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);\r
+ BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);\r
}\r
\r
\r
******************************************************************************/\r
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)\r
{\r
+ EFM_ASSERT(value<8);\r
EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));\r
\r
switch(mode)\r
{\r
- case emuBODMode_Active:\r
- EMU->BUACT = (EMU->BUACT & ~(_EMU_BUACT_BUEXTHRES_MASK))|(value<<_EMU_BUACT_BUEXTHRES_SHIFT);\r
- break;\r
- case emuBODMode_Inactive:\r
- EMU->BUINACT = (EMU->BUINACT & ~(_EMU_BUINACT_BUENTHRES_MASK))|(value<<_EMU_BUINACT_BUENTHRES_SHIFT);\r
- break;\r
+ case emuBODMode_Active:\r
+ EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)\r
+ | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);\r
+ break;\r
+ case emuBODMode_Inactive:\r
+ EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)\r
+ | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);\r
+ break;\r
}\r
}\r
\r
******************************************************************************/\r
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value)\r
{\r
+ EFM_ASSERT(value < 4);\r
EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));\r
\r
switch(mode)\r
{\r
- case emuBODMode_Active:\r
- EMU->BUACT = (EMU->BUACT & ~(_EMU_BUACT_BUEXRANGE_MASK))|(value<<_EMU_BUACT_BUEXRANGE_SHIFT);\r
+ case emuBODMode_Active:\r
+ EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)\r
+ | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);\r
+ break;\r
+ case emuBODMode_Inactive:\r
+ EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)\r
+ | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);\r
+ break;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Load DCDC calibration constants from DI page. Const means calibration\r
+ * data that does not change depending on other configuration parameters.\r
+ *\r
+ * @return\r
+ * False if calibration registers are locked\r
+ ******************************************************************************/\r
+static bool ConstCalibrationLoad(void)\r
+{\r
+ uint32_t val;\r
+ volatile uint32_t *reg;\r
+\r
+ /* DI calib data in flash */\r
+ volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038);\r
+ volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040);\r
+ volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048);\r
+ volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050);\r
+ volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058);\r
+ volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060);\r
+\r
+ if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX)\r
+ {\r
+ val = *(diCal_EMU_DCDCLNFREQCTRL + 1);\r
+ reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;\r
+ *reg = val;\r
+\r
+ val = *(diCal_EMU_DCDCLNVCTRL + 1);\r
+ reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL;\r
+ *reg = val;\r
+\r
+ val = *(diCal_EMU_DCDCLPCTRL + 1);\r
+ reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL;\r
+ *reg = val;\r
+\r
+ val = *(diCal_EMU_DCDCLPVCTRL + 1);\r
+ reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL;\r
+ *reg = val;\r
+\r
+ val = *(diCal_EMU_DCDCTRIM0 + 1);\r
+ reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0;\r
+ *reg = val;\r
+\r
+ val = *(diCal_EMU_DCDCTRIM1 + 1);\r
+ reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1;\r
+ *reg = val;\r
+\r
+ return true;\r
+ }\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set recommended and validated current optimization settings\r
+ *\r
+ ******************************************************************************/\r
+void ValidatedConfigSet(void)\r
+{\r
+#define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44))\r
+\r
+ uint32_t dcdcTiming;\r
+ SYSTEM_PartFamily_TypeDef family;\r
+ SYSTEM_ChipRevision_TypeDef rev;\r
+\r
+ /* Enable duty cycling of the bias */\r
+ EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;\r
+\r
+ /* Set low-noise RCO for EFM32 and EFR32 */\r
+#if defined( _EFR_DEVICE )\r
+ /* 7MHz is recommended for all EFR32 parts with DCDC */\r
+ EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)\r
+ | (EMU_DcdcLnRcoBand_7MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);\r
+#else\r
+ /* 3MHz is recommended for all EFM32 parts with DCDC */\r
+ EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)\r
+ | (EMU_DcdcLnRcoBand_3MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);\r
+#endif\r
+\r
+ EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;\r
+\r
+ family = SYSTEM_GetFamily();\r
+ SYSTEM_ChipRevisionGet(&rev);\r
+ if ((((family >= systemPartFamilyMighty1P)\r
+ && (family <= systemPartFamilyFlex1V))\r
+ || (family == systemPartFamilyEfm32Pearl1B)\r
+ || (family == systemPartFamilyEfm32Jade1B))\r
+ && ((rev.major == 1) && (rev.minor < 3))\r
+ && (errataFixDcdcHsState == errataFixDcdcHsInit))\r
+ {\r
+ /* LPCMPWAITDIS = 1 */\r
+ EMU_DCDCSMCTRL |= 1;\r
+\r
+ dcdcTiming = EMU->DCDCTIMING;\r
+ dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK\r
+ |_EMU_DCDCTIMING_LNWAIT_MASK\r
+ |_EMU_DCDCTIMING_BYPWAIT_MASK);\r
+\r
+ dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)\r
+ | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)\r
+ | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));\r
+ EMU->DCDCTIMING = dcdcTiming;\r
+\r
+ errataFixDcdcHsState = errataFixDcdcHsTrimSet;\r
+ }\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Calculate and update EMU->DCDCMISCCTRL for maximum DCDC current based\r
+ * on the slice configuration and user set maximum.\r
+ ******************************************************************************/\r
+static void maxCurrentUpdate(void)\r
+{\r
+ uint32_t lncLimImSel;\r
+ uint32_t lpcLimImSel;\r
+ uint32_t pFetCnt;\r
+\r
+ pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK)\r
+ >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;\r
+\r
+ /* Equation from Reference Manual section 11.5.20, in the register\r
+ field description for LNCLIMILIMSEL and LPCLIMILIMSEL. */\r
+ lncLimImSel = (dcdcMaxCurrent_mA / (5 * (pFetCnt + 1))) - 1;\r
+ /* 80mA as recommended in Application Note AN0948 */\r
+ lpcLimImSel = (80 / (5 * (pFetCnt + 1))) - 1;\r
+\r
+ lncLimImSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT;\r
+ lpcLimImSel <<= _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT;\r
+ EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK\r
+ | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK))\r
+ | (lncLimImSel | lpcLimImSel);\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set static variable that holds the user set maximum current. Update\r
+ * DCDC configuration.\r
+ *\r
+ * @param[in] mAmaxCurrent\r
+ * Maximum allowed current drawn by the DCDC from VREGVDD in mA.\r
+ ******************************************************************************/\r
+static void maxCurrentSet(uint32_t mAmaxCurrent)\r
+{\r
+ dcdcMaxCurrent_mA = mAmaxCurrent;\r
+ maxCurrentUpdate();\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback\r
+ * attenuation and DEVINFOREV.\r
+ *\r
+ * @param[in] attSet\r
+ * LP feedback attenuation.\r
+ * @param[in] lpCmpBias\r
+ * lpCmpBias selection\r
+ ******************************************************************************/\r
+static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias)\r
+{\r
+ uint8_t devinfoRev;\r
+ uint32_t lpcmpHystSel;\r
+\r
+ /* Get calib data revision */\r
+ devinfoRev = SYSTEM_GetDevinfoRev();\r
+\r
+ /* Load LPATT indexed calibration data */\r
+ if (devinfoRev < 4)\r
+ {\r
+ lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0;\r
+\r
+ if (lpAttenuation)\r
+ {\r
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK)\r
+ >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;\r
+ }\r
+ else\r
+ {\r
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)\r
+ >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;\r
+ }\r
+ }\r
+ /* devinfoRev >= 4\r
+ Load LPCMPBIAS indexed calibration data */\r
+ else\r
+ {\r
+ lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1;\r
+ switch (lpCmpBias)\r
+ {\r
+ case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:\r
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK)\r
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;\r
+ break;\r
+\r
+ case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:\r
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK)\r
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;\r
+ break;\r
+\r
+ case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:\r
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK)\r
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;\r
+ break;\r
+\r
+ case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:\r
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK)\r
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+ }\r
+\r
+ /* Make sure the sel value is within the field range. */\r
+ lpcmpHystSel <<= _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT;\r
+ if (lpcmpHystSel & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK)\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+ EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) | lpcmpHystSel;\r
+\r
+ return true;\r
+}\r
+\r
+\r
+/** @endcond */\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set DCDC regulator operating mode\r
+ *\r
+ * @param[in] dcdcMode\r
+ * DCDC mode\r
+ ******************************************************************************/\r
+void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)\r
+{\r
+ while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);\r
+ BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);\r
+ EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Configure DCDC regulator\r
+ *\r
+ * @note\r
+ * Use the function EMU_DCDCPowerDown() to if the power circuit is configured\r
+ * for NODCDC as decribed in Section 11.3.4.3 in the Reference Manual.\r
+ *\r
+ * @param[in] dcdcInit\r
+ * DCDC initialization structure\r
+ *\r
+ * @return\r
+ * True if initialization parameters are valid\r
+ ******************************************************************************/\r
+bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit)\r
+{\r
+ uint32_t lpCmpBiasSel;\r
+\r
+ /* Set external power configuration. This enables writing to the other\r
+ DCDC registers. */\r
+ EMU->PWRCFG = dcdcInit->powerConfig;\r
+\r
+ /* EMU->PWRCFG is write-once and POR reset only. Check that\r
+ we could set the desired power configuration. */\r
+ if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig)\r
+ {\r
+ /* If this assert triggers unexpectedly, please power cycle the\r
+ kit to reset the power configuration. */\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+\r
+ /* Load DCDC calibration data from the DI page */\r
+ ConstCalibrationLoad();\r
+\r
+ /* Check current parameters */\r
+ EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200);\r
+ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA);\r
+\r
+ /* DCDC low-noise supports max 200mA */\r
+ if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise)\r
+ {\r
+ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200);\r
+ }\r
+\r
+ /* EM2, 3 and 4 current above 100uA is not supported */\r
+ EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 100);\r
+\r
+ /* Decode LP comparator bias for EM0/1 and EM2/3 */\r
+ lpCmpBiasSel = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1;\r
+ if (dcdcInit->em234LoadCurrent_uA <= 10)\r
+ {\r
+ lpCmpBiasSel = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0;\r
+ }\r
+\r
+ /* Set DCDC low-power mode comparator bias selection */\r
+ EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK\r
+ | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK))\r
+ | ((uint32_t)lpCmpBiasSel\r
+ | (uint32_t)dcdcInit->lnTransientMode);\r
+\r
+ /* Set recommended and validated current optimization settings */\r
+ ValidatedConfigSet();\r
+\r
+ /* Set the maximum current that the DCDC can draw from the power source */\r
+ maxCurrentSet(dcdcInit->maxCurrent_mA);\r
+\r
+ /* Optimize LN slice based on given load current estimate */\r
+ EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA);\r
+\r
+ /* Set DCDC output voltage */\r
+ dcdcOutput_mVout = dcdcInit->mVout;\r
+ if (!EMU_DCDCOutputVoltageSet(dcdcOutput_mVout, true, true))\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+\r
+ /* Set EM0 DCDC operating mode. Output voltage set in EMU_DCDCOutputVoltageSet()\r
+ above takes effect if mode is changed from bypass here. */\r
+ EMU_DCDCModeSet(dcdcInit->dcdcMode);\r
+\r
+ /* Select analog peripheral power supply */\r
+ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0);\r
+\r
+ return true;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set DCDC output voltage\r
+ *\r
+ * @param[in] mV\r
+ * Target DCDC output voltage in mV\r
+ *\r
+ * @return\r
+ * True if the mV parameter is valid\r
+ ******************************************************************************/\r
+bool EMU_DCDCOutputVoltageSet(uint32_t mV,\r
+ bool setLpVoltage,\r
+ bool setLnVoltage)\r
+{\r
+#if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )\r
+\r
+ bool validOutVoltage;\r
+ uint8_t lnMode;\r
+ bool attSet;\r
+ uint32_t attMask;\r
+ uint32_t vrefLow = 0;\r
+ uint32_t vrefHigh = 0;\r
+ uint32_t vrefVal = 0;\r
+ uint32_t mVlow = 0;\r
+ uint32_t mVhigh = 0;\r
+ uint32_t vrefShift;\r
+ uint32_t lpcmpBias;\r
+ volatile uint32_t* ctrlReg;\r
+\r
+ /* Check that the set voltage is within valid range.\r
+ Voltages are obtained from the datasheet. */\r
+ validOutVoltage = false;\r
+ if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD)\r
+ {\r
+ validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)\r
+ && (mV <= PWRCFG_DCDCTODVDD_VMAX));\r
+ }\r
+\r
+ if (!validOutVoltage)\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+\r
+ /* Populate both LP and LN registers, set control reg pointer and VREF shift. */\r
+ for (lnMode = 0; lnMode <= 1; lnMode++)\r
+ {\r
+ if (((lnMode == 0) && !setLpVoltage)\r
+ || ((lnMode == 1) && !setLnVoltage))\r
+ {\r
+ continue;\r
+ }\r
+\r
+ ctrlReg = (lnMode ? &EMU->DCDCLNVCTRL : &EMU->DCDCLPVCTRL);\r
+ vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT\r
+ : _EMU_DCDCLPVCTRL_LPVREF_SHIFT);\r
+\r
+ /* Set attenuation to use */\r
+ attSet = (mV > 1800);\r
+ if (attSet)\r
+ {\r
+ mVlow = 1800;\r
+ mVhigh = 3000;\r
+ attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT);\r
+ }\r
+ else\r
+ {\r
+ mVlow = 1200;\r
+ mVhigh = 1800;\r
+ attMask = 0;\r
+ }\r
+\r
+ /* Get 2-point calib data from DEVINFO, calculate trimming and set voltege */\r
+ if (lnMode)\r
+ {\r
+ /* Set low-noise DCDC output voltage tuning */\r
+ if (attSet)\r
+ {\r
+ vrefLow = DEVINFO->DCDCLNVCTRL0;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)\r
+ >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)\r
+ >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;\r
+ }\r
+ else\r
+ {\r
+ vrefLow = DEVINFO->DCDCLNVCTRL0;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)\r
+ >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)\r
+ >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set low-power DCDC output voltage tuning */\r
+\r
+ /* Get LPCMPBIAS and make sure masks are not overlayed */\r
+ lpcmpBias = EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK;\r
+ EFM_ASSERT(!(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK & attMask));\r
+ switch (attMask | lpcmpBias)\r
+ {\r
+ case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL2;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL2;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL3;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL3;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL0;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL0;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL1;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT;\r
+ break;\r
+\r
+ case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:\r
+ vrefLow = DEVINFO->DCDCLPVCTRL1;\r
+ vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT;\r
+ vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK)\r
+ >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT;\r
+ break;\r
+\r
+ default:\r
+ EFM_ASSERT(false);\r
+ break;\r
+ }\r
+\r
+ /* Load LP comparator hysteresis calibration */\r
+ if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias >> _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT)))\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+ } /* Low-nise / low-power mode */\r
+\r
+\r
+ /* Check for valid 2-point trim values */\r
+ if ((vrefLow == 0xFF) && (vrefHigh == 0xFF))\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+\r
+ /* Calculate and set voltage trim */\r
+ vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow);\r
+ vrefVal += vrefLow;\r
+\r
+ /* Range check */\r
+ if ((vrefVal > vrefHigh) || (vrefVal < vrefLow))\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+\r
+ /* Update DCDCLNVCTRL/DCDCLPVCTRL */\r
+ *ctrlReg = (vrefVal << vrefShift) | attMask;\r
+ }\r
+#endif\r
+ return true;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Optimize DCDC slice count based on the estimated average load current\r
+ * in EM0\r
+ *\r
+ * @param[in] mAEm0LoadCurrent\r
+ * Estimated average EM0 load current in mA.\r
+ ******************************************************************************/\r
+void EMU_DCDCOptimizeSlice(uint32_t mAEm0LoadCurrent)\r
+{\r
+ uint32_t sliceCount = 0;\r
+ uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)\r
+ >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;\r
+\r
+ /* Set recommended slice count */\r
+ if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= EMU_DcdcLnRcoBand_5MHz))\r
+ {\r
+ if (mAEm0LoadCurrent < 20)\r
+ {\r
+ sliceCount = 4;\r
+ }\r
+ else if ((mAEm0LoadCurrent >= 20) && (mAEm0LoadCurrent < 40))\r
+ {\r
+ sliceCount = 8;\r
+ }\r
+ else\r
+ {\r
+ sliceCount = 16;\r
+ }\r
+ }\r
+ else if ((!(EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))\r
+ {\r
+ if (mAEm0LoadCurrent < 10)\r
+ {\r
+ sliceCount = 4;\r
+ }\r
+ else if ((mAEm0LoadCurrent >= 10) && (mAEm0LoadCurrent < 20))\r
+ {\r
+ sliceCount = 8;\r
+ }\r
+ else\r
+ {\r
+ sliceCount = 16;\r
+ }\r
+ }\r
+ else if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))\r
+ {\r
+ if (mAEm0LoadCurrent < 40)\r
+ {\r
+ sliceCount = 8;\r
+ }\r
+ else\r
+ {\r
+ sliceCount = 16;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* This configuration is not recommended. EMU_DCDCInit() applies a recommended\r
+ configuration. */\r
+ EFM_ASSERT(false);\r
+ }\r
+\r
+ /* The selected silices are PSLICESEL + 1 */\r
+ sliceCount--;\r
+\r
+ /* Apply slice count to both N and P slice */\r
+ sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT\r
+ | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);\r
+ EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK\r
+ | _EMU_DCDCMISCCTRL_NFETCNT_MASK))\r
+ | sliceCount;\r
+\r
+ /* Update current limit configuration as it depends on the slice configuration. */\r
+ maxCurrentUpdate();\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set DCDC Low-noise RCO band.\r
+ *\r
+ * @param[in] band\r
+ * RCO band to set.\r
+ ******************************************************************************/\r
+void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)\r
+{\r
+ EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)\r
+ | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Power off the DCDC regulator.\r
+ *\r
+ * @details\r
+ * This function powers off the DCDC controller. This function should only be\r
+ * used if the external power circuit is wired for no DCDC. If the external power\r
+ * circuit is wired for DCDC usage, then use EMU_DCDCInit() and set the\r
+ * DCDC in bypass mode to disable DCDC.\r
+ *\r
+ * @return\r
+ * Return false if the DCDC could not be disabled.\r
+ ******************************************************************************/\r
+bool EMU_DCDCPowerOff(void)\r
+{\r
+ /* Set power configuration to hard bypass */\r
+ EMU->PWRCFG = 0xF;\r
+ if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != 0xF)\r
+ {\r
+ EFM_ASSERT(false);\r
+ /* Return when assertions are disabled */\r
+ return false;\r
+ }\r
+\r
+ /* Set DCDC to OFF and disable LP in EM2/3/4 */\r
+ EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF;\r
+ return true;\r
+}\r
+#endif\r
+\r
+\r
+#if defined( EMU_STATUS_VMONRDY )\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+__STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(int mV)\r
+{\r
+ return (mV - 1200) / 200;\r
+}\r
+\r
+__STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThreshold)\r
+{\r
+ return (mV - 1200 - (coarseThreshold * 200)) / 20;\r
+}\r
+/** @endcond */\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Initialize VMON channel.\r
+ *\r
+ * @details\r
+ * Initialize a VMON channel without hysteresis. If the channel supports\r
+ * separate rise and fall triggers, both thresholds will be set to the same\r
+ * value.\r
+ *\r
+ * @param[in] vmonInit\r
+ * VMON initialization struct\r
+ ******************************************************************************/\r
+void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit)\r
+{\r
+ uint32_t thresholdCoarse, thresholdFine;\r
+ EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980));\r
+\r
+ thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->threshold);\r
+ thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->threshold, thresholdCoarse);\r
+\r
+ switch(vmonInit->channel)\r
+ {\r
+ case emuVmonChannel_AVDD:\r
+ EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)\r
+ | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)\r
+ | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)\r
+ | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)\r
+ | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)\r
+ | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)\r
+ | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);\r
+ break;\r
+ case emuVmonChannel_ALTAVDD:\r
+ EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)\r
+ | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)\r
+ | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)\r
+ | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)\r
+ | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0);\r
+ break;\r
+ case emuVmonChannel_DVDD:\r
+ EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)\r
+ | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)\r
+ | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)\r
+ | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)\r
+ | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0);\r
break;\r
- case emuBODMode_Inactive:\r
- EMU->BUINACT = (EMU->BUINACT & ~(_EMU_BUINACT_BUENRANGE_MASK))|(value<<_EMU_BUINACT_BUENRANGE_SHIFT);\r
+ case emuVmonChannel_IOVDD0:\r
+ EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)\r
+ | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)\r
+ | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)\r
+ | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)\r
+ | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)\r
+ | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0);\r
break;\r
+ default:\r
+ EFM_ASSERT(false);\r
+ return;\r
}\r
}\r
\r
-#endif\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Initialize VMON channel with hysteresis (separate rise and fall triggers).\r
+ *\r
+ * @details\r
+ * Initialize a VMON channel which supports hysteresis. The AVDD channel is\r
+ * the only channel to support separate rise and fall triggers.\r
+ *\r
+ * @param[in] vmonInit\r
+ * VMON Hysteresis initialization struct\r
+ ******************************************************************************/\r
+void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit)\r
+{\r
+ uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;\r
+ /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */\r
+ EFM_ASSERT((vmonInit->riseThreshold >= 1200) && (vmonInit->riseThreshold < 4000));\r
+ EFM_ASSERT((vmonInit->fallThreshold >= 1200) && (vmonInit->fallThreshold < 4000));\r
+ /* Fall threshold has to be lower than rise threshold */\r
+ EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold);\r
+\r
+ riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->riseThreshold);\r
+ riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->riseThreshold, riseThresholdCoarse);\r
+ fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->fallThreshold);\r
+ fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->fallThreshold, fallThresholdCoarse);\r
+\r
+ switch(vmonInit->channel)\r
+ {\r
+ case emuVmonChannel_AVDD:\r
+ EMU->VMONAVDDCTRL = (riseThresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)\r
+ | (riseThresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)\r
+ | (fallThresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)\r
+ | (fallThresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)\r
+ | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)\r
+ | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)\r
+ | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);\r
+ break;\r
+ default:\r
+ EFM_ASSERT(false);\r
+ return;\r
+ }\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable or disable a VMON channel\r
+ *\r
+ * @param[in] channel\r
+ * VMON channel to enable/disable\r
+ *\r
+ * @param[in] enable\r
+ * Whether to enable or disable\r
+ ******************************************************************************/\r
+void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable)\r
+{\r
+ uint32_t volatile * reg;\r
+ uint32_t bit;\r
+\r
+ switch(channel)\r
+ {\r
+ case emuVmonChannel_AVDD:\r
+ reg = &(EMU->VMONAVDDCTRL);\r
+ bit = _EMU_VMONAVDDCTRL_EN_SHIFT;\r
+ break;\r
+ case emuVmonChannel_ALTAVDD:\r
+ reg = &(EMU->VMONALTAVDDCTRL);\r
+ bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;\r
+ break;\r
+ case emuVmonChannel_DVDD:\r
+ reg = &(EMU->VMONDVDDCTRL);\r
+ bit = _EMU_VMONDVDDCTRL_EN_SHIFT;\r
+ break;\r
+ case emuVmonChannel_IOVDD0:\r
+ reg = &(EMU->VMONIO0CTRL);\r
+ bit = _EMU_VMONIO0CTRL_EN_SHIFT;\r
+ break;\r
+ default:\r
+ EFM_ASSERT(false);\r
+ return;\r
+ }\r
+\r
+ BUS_RegBitWrite(reg, bit, enable);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the status of a voltage monitor channel.\r
+ *\r
+ * @param[in] channel\r
+ * VMON channel to get status for\r
+ *\r
+ * @return\r
+ * Status of the selected VMON channel. True if channel is triggered.\r
+ ******************************************************************************/\r
+bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)\r
+{\r
+ uint32_t bit;\r
+ switch(channel)\r
+ {\r
+ case emuVmonChannel_AVDD:\r
+ bit = _EMU_STATUS_VMONAVDD_SHIFT;\r
+ break;\r
+ case emuVmonChannel_ALTAVDD:\r
+ bit = _EMU_STATUS_VMONALTAVDD_SHIFT;\r
+ break;\r
+ case emuVmonChannel_DVDD:\r
+ bit = _EMU_STATUS_VMONDVDD_SHIFT;\r
+ break;\r
+ case emuVmonChannel_IOVDD0:\r
+ bit = _EMU_STATUS_VMONIO0_SHIFT;\r
+ break;\r
+ default:\r
+ EFM_ASSERT(false);\r
+ bit = 0;\r
+ }\r
\r
+ return BUS_RegBitRead(&EMU->STATUS, bit);\r
+}\r
+#endif /* EMU_STATUS_VMONRDY */\r
\r
/** @} (end addtogroup EMU) */\r
/** @} (end addtogroup EM_Library) */\r
* @file em_gpio.c\r
* @brief General Purpose IO (GPIO) peripheral API\r
* devices.\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
#include "em_gpio.h"\r
\r
#if defined(GPIO_COUNT) && (GPIO_COUNT > 0)\r
+\r
/***************************************************************************//**\r
* @addtogroup EM_Library\r
* @{\r
\r
/** Validation of pin typically usable in assert statements. */\r
#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3)\r
-\r
+#define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \\r
+ ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \\r
+ | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))\r
/** @endcond */\r
\r
\r
#endif\r
}\r
\r
-\r
+#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)\r
/***************************************************************************//**\r
* @brief\r
* Sets the drive mode for a GPIO port.\r
GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK))\r
| (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT);\r
}\r
+#endif\r
\r
\r
+#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK)\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Sets the drive strength for a GPIO port.\r
+ *\r
+ * @param[in] port\r
+ * The GPIO port to access.\r
+ *\r
+ * @param[in] strength\r
+ * Drive strength to use for port.\r
+ ******************************************************************************/\r
+void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,\r
+ GPIO_DriveStrength_TypeDef strength)\r
+{\r
+ EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGHT_VALID(strength));\r
+ BUS_RegMaskedWrite(&GPIO->P[port].CTRL,\r
+ _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK,\r
+ strength);\r
+}\r
+#endif\r
+\r
/***************************************************************************//**\r
* @brief\r
* Configure GPIO interrupt.\r
{\r
uint32_t tmp;\r
\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
\r
/* There are two registers controlling the interrupt configuration:\r
* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls\r
* pins 8-15. */\r
if (pin < 8)\r
{\r
- GPIO->EXTIPSELL = (GPIO->EXTIPSELL & ~(0xF << (4 * pin))) |\r
- (port << (4 * pin));\r
+ BUS_RegMaskedWrite(&GPIO->EXTIPSELL,\r
+ 0xF << (4 * pin),\r
+ port << (4 * pin));\r
}\r
else\r
{\r
tmp = pin - 8;\r
- GPIO->EXTIPSELH = (GPIO->EXTIPSELH & ~(0xF << (4 * tmp))) |\r
- (port << (4 * tmp));\r
+ BUS_RegMaskedWrite(&GPIO->EXTIPSELH,\r
+ 0xF << (4 * tmp),\r
+ port << (4 * tmp));\r
}\r
\r
/* Enable/disable rising edge */\r
- BITBAND_Peripheral(&(GPIO->EXTIRISE), pin, (unsigned int)risingEdge);\r
+ BUS_RegBitWrite(&(GPIO->EXTIRISE), pin, risingEdge);\r
\r
/* Enable/disable falling edge */\r
- BITBAND_Peripheral(&(GPIO->EXTIFALL), pin, (unsigned int)fallingEdge);\r
+ BUS_RegBitWrite(&(GPIO->EXTIFALL), pin, fallingEdge);\r
\r
/* Clear any pending interrupt */\r
GPIO->IFC = 1 << pin;\r
\r
/* Finally enable/disable interrupt */\r
- BITBAND_Peripheral(&(GPIO->IEN), pin, (unsigned int)enable);\r
+ BUS_RegBitWrite(&(GPIO->IEN), pin, enable);\r
}\r
\r
\r
GPIO_Mode_TypeDef mode,\r
unsigned int out)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
\r
/* If disabling pin, do not modify DOUT in order to reduce chance for */\r
/* glitch/spike (may not be sufficient precaution in all use cases) */\r
{\r
if (out)\r
{\r
- GPIO->P[port].DOUTSET = 1 << pin;\r
+ GPIO_PinOutSet(port, pin);\r
}\r
else\r
{\r
- GPIO->P[port].DOUTCLR = 1 << pin;\r
+ GPIO_PinOutClear(port, pin);\r
}\r
}\r
\r
* register controls pins 0-7 and MODEH controls pins 8-15. */\r
if (pin < 8)\r
{\r
- GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xF << (pin * 4))) |\r
- (mode << (pin * 4));\r
+ BUS_RegMaskedWrite(&GPIO->P[port].MODEL,\r
+ 0xF << (pin * 4),\r
+ mode << (pin * 4));\r
}\r
else\r
{\r
- GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xF << ((pin - 8) * 4))) |\r
- (mode << ((pin - 8) * 4));\r
+ BUS_RegMaskedWrite(&GPIO->P[port].MODEH,\r
+ 0xF << ((pin - 8) * 4),\r
+ mode << ((pin - 8) * 4));\r
}\r
\r
if (mode == gpioModeDisabled)\r
{\r
if (out)\r
{\r
- GPIO->P[port].DOUTSET = 1 << pin;\r
+ GPIO_PinOutSet(port, pin);\r
}\r
else\r
{\r
- GPIO->P[port].DOUTCLR = 1 << pin;\r
+ GPIO_PinOutClear(port, pin);\r
}\r
}\r
}\r
\r
+#if defined( _GPIO_EM4WUEN_MASK )\r
+/**************************************************************************//**\r
+ * @brief\r
+ * Enable GPIO pin wake-up from EM4. When the function exits,\r
+ * EM4 mode can be safely entered.\r
+ *\r
+ * @note\r
+ * It is assumed that the GPIO pin modes are set correctly.\r
+ * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.\r
+ *\r
+ * @param[in] pinmask\r
+ * Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.\r
+ * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.\r
+ * @param[in] polaritymask\r
+ * Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.\r
+ * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.\r
+ *****************************************************************************/\r
+void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)\r
+{\r
+ EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);\r
+\r
+#if defined( _GPIO_EM4WUPOL_MASK )\r
+ EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);\r
+ GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */\r
+ GPIO->EM4WUPOL |= pinmask & polaritymask;\r
+#elif defined( _GPIO_EXTILEVEL_MASK )\r
+ EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);\r
+ GPIO->EXTILEVEL &= ~pinmask;\r
+ GPIO->EXTILEVEL |= pinmask & polaritymask;\r
+#endif\r
+ GPIO->EM4WUEN |= pinmask; /* Enable wakeup */\r
+\r
+ GPIO_EM4SetPinRetention(true); /* Enable pin retention */\r
+\r
+#if defined( _GPIO_CMD_EM4WUCLR_MASK )\r
+ GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */\r
+#elif defined( _GPIO_IFC_EM4WU_MASK )\r
+ GPIO_IntClear(pinmask);\r
+#endif\r
+}\r
+#endif\r
+\r
/** @} (end addtogroup GPIO) */\r
/** @} (end addtogroup EM_Library) */\r
\r
/**************************************************************************//**\r
* @file em_int.c\r
* @brief Interrupt enable/disable unit API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
#include <stdint.h>\r
#include "em_int.h"\r
\r
\r
/***************************************************************************//**\r
* @addtogroup INT\r
- * @brief Safe nesting interrupt disable/enable API\r
+ * @brief Safe nesting of interrupt disable/enable API\r
* @{\r
* @details\r
* This module contains functions to safely disable and enable interrupts\r
- * at cpu level. INT_Disable() disables interrupts and increments a lock\r
- * level counter. INT_Enable() decrements the lock level counter and enable\r
- * interrupts if the counter was decremented to zero.\r
+ * at CPU level. INT_Disable() disables interrupts globally and increments a lock\r
+ * level counter (counting semaphore). INT_Enable() decrements the lock level \r
+ * counter and enable interrupts if the counter reaches zero.\r
*\r
- * These functions would normally be used to secure critical regions.\r
+ * These functions would normally be used to secure critical regions, and \r
+ * to make sure that a critical section that calls into another critical \r
+ * section does not unintentionally terminate the callee critical section.\r
*\r
* These functions should also be used inside interrupt handlers:\r
* @verbatim\r
* main with interrupts enabled */\r
uint32_t INT_LockCnt = 0;\r
\r
-\r
/** @} (end addtogroup INT) */\r
/** @} (end addtogroup EM_Library) */\r
/***************************************************************************//**\r
* @file em_lcd.c\r
* @brief Liquid Crystal Display (LCD) Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
#include "em_lcd.h"\r
#if defined(LCD_COUNT) && (LCD_COUNT > 0)\r
#include "em_assert.h"\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
\r
/***************************************************************************//**\r
* @addtogroup EM_Library\r
LCD_Enable(false);\r
\r
/* Make sure we don't touch other bit fields (i.e. voltage boost) */\r
- dispCtrl &= ~(\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- _LCD_DISPCTRL_MUXE_MASK |\r
+ dispCtrl &= ~(0\r
+#if defined(LCD_DISPCTRL_MUXE)\r
+ | _LCD_DISPCTRL_MUXE_MASK\r
#endif\r
- _LCD_DISPCTRL_MUX_MASK |\r
- _LCD_DISPCTRL_BIAS_MASK |\r
- _LCD_DISPCTRL_WAVE_MASK |\r
- _LCD_DISPCTRL_VLCDSEL_MASK |\r
- _LCD_DISPCTRL_CONCONF_MASK);\r
+ | _LCD_DISPCTRL_MUX_MASK\r
+ | _LCD_DISPCTRL_BIAS_MASK\r
+ | _LCD_DISPCTRL_WAVE_MASK\r
+ | _LCD_DISPCTRL_VLCDSEL_MASK\r
+ | _LCD_DISPCTRL_CONCONF_MASK);\r
\r
/* Configure controller according to initialization structure */\r
dispCtrl |= lcdInit->mux; /* also configures MUXE */\r
uint32_t dispctrl = LCD->DISPCTRL;\r
\r
/* Select VEXT or VDD */\r
- dispctrl &= ~(_LCD_DISPCTRL_VLCDSEL_MASK);\r
+ dispctrl &= ~_LCD_DISPCTRL_VLCDSEL_MASK;\r
switch (vlcd)\r
{\r
- case lcdVLCDSelVExtBoost:\r
- dispctrl |= LCD_DISPCTRL_VLCDSEL_VEXTBOOST;\r
- break;\r
- case lcdVLCDSelVDD:\r
- dispctrl |= LCD_DISPCTRL_VLCDSEL_VDD;\r
- break;\r
- default:\r
- break;\r
+ case lcdVLCDSelVExtBoost:\r
+ dispctrl |= LCD_DISPCTRL_VLCDSEL_VEXTBOOST;\r
+ break;\r
+ case lcdVLCDSelVDD:\r
+ dispctrl |= LCD_DISPCTRL_VLCDSEL_VDD;\r
+ break;\r
+ default:\r
+ break;\r
}\r
\r
LCD->DISPCTRL = dispctrl;\r
EFM_ASSERT(fcInit->top < 64);\r
\r
/* Reconfigure frame count configuration */\r
- bactrl &= ~(_LCD_BACTRL_FCTOP_MASK |\r
- _LCD_BACTRL_FCPRESC_MASK);\r
+ bactrl &= ~(_LCD_BACTRL_FCTOP_MASK\r
+ | _LCD_BACTRL_FCPRESC_MASK);\r
bactrl |= (fcInit->top << _LCD_BACTRL_FCTOP_SHIFT);\r
bactrl |= fcInit->prescale;\r
\r
LCD->AREGB = animInit->BReg;\r
\r
/* Configure Animation Shift and Logic */\r
- bactrl &= ~(_LCD_BACTRL_AREGASC_MASK |\r
- _LCD_BACTRL_AREGBSC_MASK |\r
- _LCD_BACTRL_ALOGSEL_MASK);\r
+ bactrl &= ~(_LCD_BACTRL_AREGASC_MASK\r
+ | _LCD_BACTRL_AREGBSC_MASK\r
+ | _LCD_BACTRL_ALOGSEL_MASK);\r
\r
bactrl |= (animInit->AShift << _LCD_BACTRL_AREGASC_SHIFT);\r
bactrl |= (animInit->BShift << _LCD_BACTRL_AREGBSC_SHIFT);\r
bactrl |= animInit->animLogic;\r
\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_BACTRL_ALOC)\r
bactrl &= ~(_LCD_BACTRL_ALOC_MASK);\r
\r
if(animInit->startSeg == 0)\r
******************************************************************************/\r
void LCD_SegmentSet(int com, int bit, bool enable)\r
{\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(_LCD_SEGD7L_MASK)\r
/* Tiny and Giant Family supports up to 8 COM lines */\r
EFM_ASSERT(com < 8);\r
#else\r
EFM_ASSERT(com < 4);\r
#endif\r
\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(_LCD_SEGD0H_MASK)\r
EFM_ASSERT(bit < 40);\r
#else\r
/* Tiny Gecko Family supports only "low" segment registers */\r
/* Use bitband access for atomic bit set/clear of segment */\r
switch (com)\r
{\r
- case 0:\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD0L), bit, (unsigned int)enable);\r
- }\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD0H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 1:\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD1L), bit, (unsigned int)enable);\r
- }\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD1H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 2:\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD2L), bit, (unsigned int)enable);\r
- }\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD2H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 3:\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD3L), bit, (unsigned int)enable);\r
- }\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD3H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 4:\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD4L), bit, (unsigned int)enable);\r
- }\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD4H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 5:\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD5L), bit, (unsigned int)enable);\r
- }\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD5H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 6:\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD6L), bit, (unsigned int)enable);\r
- }\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD6H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
- case 7:\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- if (bit < 32)\r
- {\r
- BITBAND_Peripheral(&(LCD->SEGD7L), bit, (unsigned int)enable);\r
- }\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- else\r
- {\r
- bit -= 32;\r
- BITBAND_Peripheral(&(LCD->SEGD7H), bit, (unsigned int)enable);\r
- }\r
-#endif\r
- break;\r
-\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
+ case 0:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD0L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD0H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD0H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+ case 1:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD1L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD1H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD1H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+ case 2:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD2L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD2H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD2H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+ case 3:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD3L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD3H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD3H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+#if defined(_LCD_SEGD4L_MASK)\r
+ case 4:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD4L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD4H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD4H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD5L_MASK)\r
+ case 5:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD5L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD5H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD5H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+ case 6:\r
+#if defined(_LCD_SEGD6L_MASK)\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD6L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD6H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD6H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD7L_MASK)\r
+ case 7:\r
+ if (bit < 32)\r
+ {\r
+ BUS_RegBitWrite(&(LCD->SEGD7L), bit, enable);\r
+ }\r
+#if defined(_LCD_SEGD7H_MASK)\r
+ else\r
+ {\r
+ bit -= 32;\r
+ BUS_RegBitWrite(&(LCD->SEGD7H), bit, enable);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
}\r
\r
uint32_t segData;\r
\r
/* Maximum number of com lines */\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(_LCD_SEGD7L_MASK)\r
EFM_ASSERT(com < 8);\r
#else\r
/* Gecko Family supports up to 4 COM lines */\r
\r
switch (com)\r
{\r
- case 0:\r
- segData = LCD->SEGD0L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD0L = segData;\r
- break;\r
- case 1:\r
- segData = LCD->SEGD1L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD1L = segData;\r
- break;\r
- case 2:\r
- segData = LCD->SEGD2L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD2L = segData;\r
- break;\r
- case 3:\r
- segData = LCD->SEGD3L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD3L = segData;\r
- break;\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 4:\r
- segData = LCD->SEGD4L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD4L = segData;\r
- break;\r
-#endif\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) \r
- case 5:\r
- segData = LCD->SEGD5L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD5L = segData;\r
- break;\r
-#endif\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 6:\r
- segData = LCD->SEGD6L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD6L = segData;\r
- break;\r
-#endif\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 7:\r
- segData = LCD->SEGD7L;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD7L = segData;\r
- break;\r
-#endif\r
- default:\r
- EFM_ASSERT(0);\r
- break;\r
+ case 0:\r
+ segData = LCD->SEGD0L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD0L = segData;\r
+ break;\r
+ case 1:\r
+ segData = LCD->SEGD1L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD1L = segData;\r
+ break;\r
+ case 2:\r
+ segData = LCD->SEGD2L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD2L = segData;\r
+ break;\r
+ case 3:\r
+ segData = LCD->SEGD3L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD3L = segData;\r
+ break;\r
+#if defined(_LCD_SEGD4L_MASK)\r
+ case 4:\r
+ segData = LCD->SEGD4L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD4L = segData;\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD5L_MASK)\r
+ case 5:\r
+ segData = LCD->SEGD5L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD5L = segData;\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD6L_MASK)\r
+ case 6:\r
+ segData = LCD->SEGD6L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD6L = segData;\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD7L_MASK)\r
+ case 7:\r
+ segData = LCD->SEGD7L;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD7L = segData;\r
+ break;\r
+#endif\r
+ default:\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
}\r
\r
\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(_LCD_SEGD0H_MASK)\r
/***************************************************************************//**\r
* @brief\r
* Updated the high (32-39) segments on a given COM-line in one operation\r
{\r
uint32_t segData;\r
\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(_LCD_SEGD7H_MASK)\r
EFM_ASSERT(com < 8);\r
-#endif\r
-#if defined(_EFM32_GECKO_FAMILY)\r
+#else\r
EFM_ASSERT(com < 4);\r
#endif\r
\r
/* Maximum number of com lines */\r
switch (com)\r
{\r
- case 0:\r
- segData = LCD->SEGD0H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD0H = segData;\r
- break;\r
- case 1:\r
- segData = LCD->SEGD1H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD1H = segData;\r
- break;\r
- case 2:\r
- segData = LCD->SEGD2H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD2H = segData;\r
- break;\r
- case 3:\r
- segData = LCD->SEGD3H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD3H = segData;\r
- break;\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 4:\r
- segData = LCD->SEGD4H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD4H = segData;\r
- break;\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 5:\r
- segData = LCD->SEGD5H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD5H = segData;\r
- break;\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 6:\r
- segData = LCD->SEGD6H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD6H = segData;\r
- break;\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- case 7:\r
- segData = LCD->SEGD7H;\r
- segData &= ~(mask);\r
- segData |= (mask & bits);\r
- LCD->SEGD7H = segData;\r
- break;\r
-#endif\r
- default:\r
- break;\r
+ case 0:\r
+ segData = LCD->SEGD0H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD0H = segData;\r
+ break;\r
+ case 1:\r
+ segData = LCD->SEGD1H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD1H = segData;\r
+ break;\r
+ case 2:\r
+ segData = LCD->SEGD2H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD2H = segData;\r
+ break;\r
+ case 3:\r
+ segData = LCD->SEGD3H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD3H = segData;\r
+ break;\r
+#if defined(_LCD_SEGD4H_MASK)\r
+ case 4:\r
+ segData = LCD->SEGD4H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD4H = segData;\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD5H_MASK)\r
+ case 5:\r
+ segData = LCD->SEGD5H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD5H = segData;\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD6H_MASK)\r
+ case 6:\r
+ segData = LCD->SEGD6H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD6H = segData;\r
+ break;\r
+#endif\r
+#if defined(_LCD_SEGD7H_MASK)\r
+ case 7:\r
+ segData = LCD->SEGD7H;\r
+ segData &= ~(mask);\r
+ segData |= (mask & bits);\r
+ LCD->SEGD7H = segData;\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
}\r
}\r
#endif\r
}\r
\r
\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_CTRL_DSC)\r
/***************************************************************************//**\r
* @brief\r
* Configure bias level for a specific segment line for Direct Segment Control\r
int bitShift;\r
volatile uint32_t *segmentRegister;\r
\r
-#if defined(_EFM32_TINY_FAMILY)\r
+#if !defined(_LCD_SEGD0H_MASK)\r
EFM_ASSERT(segmentLine < 20);\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
- EFM_ASSERT(segmentLine < 40);\r
-#endif\r
-#if defined(_EFM32_TINY_FAMILY)\r
+\r
/* Bias config for 8 segment lines per SEGDnL register */\r
biasRegister = segmentLine / 8;\r
bitShift = (segmentLine % 8) * 4;\r
\r
switch (biasRegister)\r
{\r
- case 0:\r
- segmentRegister = &LCD->SEGD0L;\r
- break;\r
- case 1:\r
- segmentRegister = &LCD->SEGD1L;\r
- break;\r
- case 2:\r
- segmentRegister = &LCD->SEGD2L;\r
- break;\r
- case 3:\r
- segmentRegister = &LCD->SEGD3L;\r
- break;\r
- default:\r
- segmentRegister = (uint32_t *)0x00000000;\r
- EFM_ASSERT(0);\r
- break;\r
+ case 0:\r
+ segmentRegister = &LCD->SEGD0L;\r
+ break;\r
+ case 1:\r
+ segmentRegister = &LCD->SEGD1L;\r
+ break;\r
+ case 2:\r
+ segmentRegister = &LCD->SEGD2L;\r
+ break;\r
+ case 3:\r
+ segmentRegister = &LCD->SEGD3L;\r
+ break;\r
+ default:\r
+ segmentRegister = (uint32_t *)0x00000000;\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
-#endif\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) \r
+#else\r
+ EFM_ASSERT(segmentLine < 40);\r
+\r
/* Bias config for 10 segment lines per SEGDn L+H registers */\r
biasRegister = segmentLine / 10;\r
bitShift = (segmentLine % 10) * 4;\r
\r
switch (biasRegister)\r
{\r
- case 0:\r
- if (bitShift < 32)\r
- {\r
- segmentRegister = &LCD->SEGD0L;\r
- }\r
- else\r
- {\r
- segmentRegister = &LCD->SEGD0H;\r
- bitShift -= 32;\r
- }\r
- break;\r
- case 1:\r
- if (bitShift < 32)\r
- {\r
- segmentRegister = &LCD->SEGD1L;\r
- }\r
- else\r
- {\r
- segmentRegister = &LCD->SEGD1H;\r
- bitShift -= 32;\r
- }\r
- break;\r
- case 2:\r
- if (bitShift < 32)\r
- {\r
- segmentRegister = &LCD->SEGD2L;\r
- }\r
- else\r
- {\r
- segmentRegister = &LCD->SEGD1H;\r
- bitShift -= 32;\r
- }\r
- break;\r
- case 3:\r
- if (bitShift < 32)\r
- {\r
- segmentRegister = &LCD->SEGD3L;\r
- }\r
- else\r
- {\r
- segmentRegister = &LCD->SEGD3H;\r
- bitShift -= 32;\r
- }\r
- break;\r
- default:\r
- segmentRegister = (uint32_t *)0x00000000;\r
- EFM_ASSERT(0);\r
- break;\r
+ case 0:\r
+ if (bitShift < 32)\r
+ {\r
+ segmentRegister = &LCD->SEGD0L;\r
+ }\r
+ else\r
+ {\r
+ segmentRegister = &LCD->SEGD0H;\r
+ bitShift -= 32;\r
+ }\r
+ break;\r
+ case 1:\r
+ if (bitShift < 32)\r
+ {\r
+ segmentRegister = &LCD->SEGD1L;\r
+ }\r
+ else\r
+ {\r
+ segmentRegister = &LCD->SEGD1H;\r
+ bitShift -= 32;\r
+ }\r
+ break;\r
+ case 2:\r
+ if (bitShift < 32)\r
+ {\r
+ segmentRegister = &LCD->SEGD2L;\r
+ }\r
+ else\r
+ {\r
+ segmentRegister = &LCD->SEGD1H;\r
+ bitShift -= 32;\r
+ }\r
+ break;\r
+ case 3:\r
+ if (bitShift < 32)\r
+ {\r
+ segmentRegister = &LCD->SEGD3L;\r
+ }\r
+ else\r
+ {\r
+ segmentRegister = &LCD->SEGD3H;\r
+ bitShift -= 32;\r
+ }\r
+ break;\r
+ default:\r
+ segmentRegister = (uint32_t *)0x00000000;\r
+ EFM_ASSERT(0);\r
+ break;\r
}\r
#endif\r
\r
/* Configure new bias setting */\r
*segmentRegister = (*segmentRegister & ~(0xF << bitShift)) | (biasLevel << bitShift);\r
}\r
+#endif\r
\r
\r
+#if defined(LCD_CTRL_DSC)\r
/***************************************************************************//**\r
* @brief\r
* Configure bias level for a specific segment line\r
* @file em_rmu.c\r
* @brief Reset Management Unit (RMU) peripheral module peripheral API\r
*\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
#include "em_rmu.h"\r
#if defined(RMU_COUNT) && (RMU_COUNT > 0)\r
\r
+#include "em_common.h"\r
#include "em_emu.h"\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
\r
/***************************************************************************//**\r
* @addtogroup EM_Library\r
\r
/* Reset cause "don't care" definitions.\r
1's mark the bits that must be zero, zeros are "don't cares". */\r
+#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL)\r
#define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */\r
#define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */\r
#define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */\r
#define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */\r
#define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */\r
#define NUM_RSTCAUSES (7)\r
-#ifndef _EFM32_GECKO_FAMILY\r
+\r
+#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL)\r
+#define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */\r
+#define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */\r
+#define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */\r
+#define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */\r
+#define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */\r
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */\r
+#define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */\r
#define RMU_RSTCAUSE_EM4RST_XMASK (0x00000719) /**0b0000011100011001 < EM4 Reset */\r
#define RMU_RSTCAUSE_EM4WURST_XMASK (0x00000619) /**0b0000011000011001 < EM4 Wake-up Reset */\r
#define RMU_RSTCAUSE_BODAVDD0_XMASK (0x0000041F) /**0b0000010000011111 < AVDD0 Bod Reset. */\r
#define RMU_RSTCAUSE_BODAVDD1_XMASK (0x0000021F) /**0b0000001000011111 < AVDD1 Bod Reset. */\r
-#undef NUM_RSTCAUSES\r
#define NUM_RSTCAUSES (11)\r
-#endif\r
-#ifdef BU_PRESENT\r
+\r
+#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL)\r
+#define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */\r
+#define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */\r
+#define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */\r
+#define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */\r
+#define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */\r
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */\r
+#define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */\r
+#define RMU_RSTCAUSE_EM4RST_XMASK (0x00000719) /**0b0000011100011001 < EM4 Reset */\r
+#define RMU_RSTCAUSE_EM4WURST_XMASK (0x00000619) /**0b0000011000011001 < EM4 Wake-up Reset */\r
+#define RMU_RSTCAUSE_BODAVDD0_XMASK (0x0000041F) /**0b0000010000011111 < AVDD0 Bod Reset */\r
+#define RMU_RSTCAUSE_BODAVDD1_XMASK (0x0000021F) /**0b0000001000011111 < AVDD1 Bod Reset */\r
#define RMU_RSTCAUSE_BUBODVDDDREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector, VDD_DREG */\r
#define RMU_RSTCAUSE_BUBODBUVIN_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector, BU_VIN */\r
#define RMU_RSTCAUSE_BUBODUNREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector Unregulated Domain */\r
#define RMU_RSTCAUSE_BUBODREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector Regulated Domain */\r
#define RMU_RSTCAUSE_BUMODERST_XMASK (0x00000001) /**0b0000000000000001 < Backup mode reset */\r
-#undef NUM_RSTCAUSES\r
#define NUM_RSTCAUSES (16)\r
+\r
+#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL)\r
+#define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */\r
+#define RMU_RSTCAUSE_BODAVDD_XMASK (0x00000001) /**0b0000000000000001 < AVDD Bod Reset */\r
+#define RMU_RSTCAUSE_BODDVDD_XMASK (0x00000003) /**0b0000000000000011 < DVDD Bod Reset */\r
+#define RMU_RSTCAUSE_BODREGRST_XMASK (0x0000000F) /**0b0000000000001111 < Brown Out Detector Regulated Domain Reset */\r
+#define RMU_RSTCAUSE_EXTRST_XMASK (0x0000000F) /**0b0000000000001111 < External Pin Reset */\r
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000001F) /**0b0000000000011111 < LOCKUP Reset */\r
+#define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000001F) /**0b0000000000011111 < System Request Reset */\r
+#define RMU_RSTCAUSE_WDOGRST_XMASK (0x0000001F) /**0b0000000000011111 < Watchdog Reset */\r
+#define RMU_RSTCAUSE_EM4RST_XMASK (0x00000003) /**0b0000000000000011 < EM4H/S Reset */\r
+#define NUM_RSTCAUSES (9)\r
+\r
+#else\r
+#warning "RMU_RSTCAUSE XMASKs are not defined for this family."\r
#endif\r
\r
/*******************************************************************************\r
/** Reset cause mask type. */\r
typedef struct\r
{\r
- uint32_t resetCauseMask;\r
- uint32_t dontCareMask;\r
+ uint32_t resetCauseMask;\r
+ uint32_t dontCareMask;\r
} RMU_ResetCauseMasks_Typedef;\r
\r
\r
static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =\r
{\r
{ RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },\r
+#if defined(RMU_RSTCAUSE_BODUNREGRST)\r
{ RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_BODREGRST)\r
{ RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_AVDDBOD)\r
+ { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_DVDDBOD)\r
+ { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_DECBOD)\r
+ { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },\r
+#endif\r
{ RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },\r
{ RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },\r
{ RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },\r
{ RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },\r
-#ifndef _EFM32_GECKO_FAMILY\r
+#if defined(RMU_RSTCAUSE_EM4RST)\r
{ RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_EM4WURST)\r
{ RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_BODAVDD0)\r
{ RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },\r
+#endif\r
+#if defined(RMU_RSTCAUSE_BODAVDD1)\r
{ RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },\r
#endif\r
-#ifdef BU_PRESENT\r
+#if defined(BU_PRESENT)\r
{ RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },\r
{ RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },\r
{ RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },\r
/*******************************************************************************\r
******************************** TEST ********************************\r
******************************************************************************/\r
-#ifdef EMLIB_REGRESSION_TEST\r
+#if defined(EMLIB_REGRESSION_TEST)\r
/* Test variable that replaces the RSTCAUSE cause register when testing\r
the RMU_ResetCauseGet function. */\r
extern uint32_t rstCause;\r
*\r
* @param[in] reset Reset types to enable/disable\r
*\r
- * @param[in] enable\r
- * @li false - Disable reset signal or flag\r
- * @li true - Enable reset signal or flag\r
+ * @param[in] mode Reset mode\r
******************************************************************************/\r
-void RMU_ResetControl(RMU_Reset_TypeDef reset, bool enable)\r
+void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)\r
{\r
- BITBAND_Peripheral(&(RMU->CTRL), (uint32_t)reset, (uint32_t)enable);\r
+ /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */\r
+#if defined(_RMU_CTRL_PINRMODE_MASK)\r
+ uint32_t val;\r
+#endif\r
+ uint32_t shift;\r
+\r
+ shift = EFM32_CTZ((uint32_t)reset);\r
+#if defined(_RMU_CTRL_PINRMODE_MASK)\r
+ val = (uint32_t)mode << shift;\r
+ RMU->CTRL = (RMU->CTRL & ~reset) | val;\r
+#else\r
+ BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0);\r
+#endif\r
}\r
\r
\r
******************************************************************************/\r
void RMU_ResetCauseClear(void)\r
{\r
- uint32_t locked;\r
-\r
RMU->CMD = RMU_CMD_RCCLR;\r
\r
- /* Clear some reset causes not cleared with RMU CMD register */\r
- /* (If EMU registers locked, they must be unlocked first) */\r
- locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;\r
- if (locked)\r
+#if defined(EMU_AUXCTRL_HRCCLR)\r
{\r
- EMU_Unlock();\r
- }\r
+ uint32_t locked;\r
\r
- BITBAND_Peripheral(&(EMU->AUXCTRL), 0, 1);\r
- BITBAND_Peripheral(&(EMU->AUXCTRL), 0, 0);\r
+ /* Clear some reset causes not cleared with RMU CMD register */\r
+ /* (If EMU registers locked, they must be unlocked first) */\r
+ locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;\r
+ if (locked)\r
+ {\r
+ EMU_Unlock();\r
+ }\r
\r
- if (locked)\r
- {\r
- EMU_Lock();\r
+ BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);\r
+ BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);\r
+\r
+ if (locked)\r
+ {\r
+ EMU_Lock();\r
+ }\r
}\r
+#endif\r
}\r
\r
\r
* Get the cause of the last reset.\r
*\r
* @details\r
- * In order to be useful, the reset cause must be cleared by SW before a new\r
+ * In order to be useful, the reset cause must be cleared by software before a new\r
* reset occurs, otherwise reset causes may accumulate. See @ref\r
* RMU_ResetCauseClear(). This function call will return the main cause for\r
* reset, which can be a bit mask (several causes), and clear away "noise".\r
*\r
* @return\r
- * The reset cause, a bit mask of (typically, but not always, only one) of:\r
- * @li RMU_RSTCAUSE_PORST - Power on reset\r
- * @li RMU_RSTCAUSE_BODUNREGRST - Brown out detector, unregulated power\r
- * @li RMU_RSTCAUSE_BODREGRST - Brown out detector, regulated power\r
- * @li RMU_RSTCAUSE_EXTRST - External reset\r
- * @li RMU_RSTCAUSE_WDOGRST - Watchdog reset\r
- * @li RMU_RSTCAUSE_LOCKUPRST - Cortex-M3 lockup reset\r
- * @li RMU_RSTCAUSE_SYSREQRST - Cortex-M3 system request reset\r
- * @li RMU_RSTCAUSE_EM4RST - Set if the system has been in EM4\r
- * @li RMU_RSTCAUSE_EM4WURST - Set if the system woke up on a pin from EM4\r
- * @li RMU_RSTCAUSE_BODAVDD0 - Analog power domain 0 brown out detector reset\r
- * @li RMU_RSTCAUSE_BODAVDD1 - Analog power domain 1 brown out detector reset\r
- * @li RMU_RSTCAUSE_BUBODVDDDREG - Backup BOD on VDDD_REG triggered\r
- * @li RMU_RSTCAUSE_BUBODBUVIN - Backup BOD on BU_VIN triggered\r
- * @li RMU_RSTCAUSE_BUBODUNREG - Backup BOD on unregulated power triggered\r
- * @li RMU_RSTCAUSE_BUBODREG - Backup BOD on regulated powered has triggered\r
- * @li RMU_RSTCAUSE_BUMODERST - System has been in Backup mode\r
+ * Reset cause mask. Please consult the reference manual for description\r
+ * of the reset cause mask.\r
******************************************************************************/\r
uint32_t RMU_ResetCauseGet(void)\r
{\r
-#ifndef EMLIB_REGRESSION_TEST\r
- uint32_t rstCause = RMU->RSTCAUSE;\r
+#if !defined(EMLIB_REGRESSION_TEST)\r
+ uint32_t rstCause = RMU->RSTCAUSE;\r
#endif\r
uint32_t validRstCause = 0;\r
- int i;\r
- \r
- for (i=0; i<NUM_RSTCAUSES; i++)\r
+ uint32_t i;\r
+\r
+ for (i = 0; i < NUM_RSTCAUSES; i++)\r
{\r
- //Checks to see if rstCause matches a RSTCAUSE and is not excluded by the X-mask\r
- if ((rstCause & resetCauseMasks[i].resetCauseMask) &&\r
- !(rstCause & resetCauseMasks[i].dontCareMask))\r
+ /* Checks to see if rstCause matches a RSTCAUSE and is not excluded by the X-mask */\r
+ if ((rstCause & resetCauseMasks[i].resetCauseMask)\r
+ && !(rstCause & resetCauseMasks[i].dontCareMask))\r
{\r
- //Adds the reset-cause to list of real reset-causes\r
+ /* Adds the reset-cause to list of real reset-causes */\r
validRstCause |= resetCauseMasks[i].resetCauseMask;\r
}\r
}\r
- \r
return validRstCause;\r
}\r
\r
/***************************************************************************//**\r
* @file em_rtc.c\r
* @brief Real Time Counter (RTC) Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
#include "em_rtc.h"\r
#if defined(RTC_COUNT) && (RTC_COUNT > 0)\r
\r
#include "em_assert.h"\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
\r
/***************************************************************************//**\r
* @addtogroup EM_Library\r
* Bitmask corresponding to SYNCBUSY register defined bits, indicating\r
* registers that must complete any ongoing synchronization.\r
******************************************************************************/\r
-__STATIC_INLINE void RTC_Sync(uint32_t mask)\r
+__STATIC_INLINE void regSync(uint32_t mask)\r
{\r
/* Avoid deadlock if modifying the same register twice when freeze mode is */\r
/* activated. */\r
/* Initialize selected compare value */\r
switch (comp)\r
{\r
- case 0:\r
- ret = RTC->COMP0;\r
- break;\r
-\r
- case 1:\r
- ret = RTC->COMP1;\r
- break;\r
-\r
- default:\r
- /* Unknown compare register selected */\r
- ret = 0;\r
- break;\r
+ case 0:\r
+ ret = RTC->COMP0;\r
+ break;\r
+\r
+ case 1:\r
+ ret = RTC->COMP1;\r
+ break;\r
+\r
+ default:\r
+ /* Unknown compare register selected */\r
+ ret = 0;\r
+ break;\r
}\r
\r
return ret;\r
* low frequency domain. If the same register is modified before a previous\r
* update has completed, this function will stall until the previous\r
* synchronization has completed. This only applies to the Gecko Family, see\r
- * comment in the RTC_Sync() internal function call.\r
+ * comment in the regSync() internal function call.\r
*\r
* @param[in] comp\r
* Compare register to set, either 0 or 1\r
uint32_t syncbusy;\r
#endif\r
\r
- EFM_ASSERT(RTC_COMP_REG_VALID(comp) &&\r
- ((value & ~(_RTC_COMP0_COMP0_MASK >> _RTC_COMP0_COMP0_SHIFT)) == 0));\r
+ EFM_ASSERT(RTC_COMP_REG_VALID(comp)\r
+ && ((value & ~(_RTC_COMP0_COMP0_MASK\r
+ >> _RTC_COMP0_COMP0_SHIFT)) == 0));\r
\r
/* Initialize selected compare value */\r
switch (comp)\r
{\r
- case 0:\r
- compReg = &(RTC->COMP0);\r
+ case 0:\r
+ compReg = &(RTC->COMP0);\r
#if defined(_EFM32_GECKO_FAMILY)\r
- syncbusy = RTC_SYNCBUSY_COMP0;\r
+ syncbusy = RTC_SYNCBUSY_COMP0;\r
#endif\r
- break;\r
+ break;\r
\r
- case 1:\r
- compReg = &(RTC->COMP1);\r
+ case 1:\r
+ compReg = &(RTC->COMP1);\r
#if defined(_EFM32_GECKO_FAMILY)\r
- syncbusy = RTC_SYNCBUSY_COMP1;\r
+ syncbusy = RTC_SYNCBUSY_COMP1;\r
#endif\r
- break;\r
+ break;\r
\r
- default:\r
- /* Unknown compare register selected, abort */\r
- return;\r
+ default:\r
+ /* Unknown compare register selected, abort */\r
+ return;\r
}\r
#if defined(_EFM32_GECKO_FAMILY)\r
/* LF register about to be modified require sync. busy check */\r
- RTC_Sync(syncbusy);\r
+ regSync(syncbusy);\r
#endif\r
\r
*compReg = value;\r
* requires synchronization into the low frequency domain. If this register is\r
* modified before a previous update to the same register has completed, this\r
* function will stall until the previous synchronization has completed. This\r
- * only applies to the Gecko Family, see comment in the RTC_Sync() internal\r
+ * only applies to the Gecko Family, see comment in the regSync() internal\r
* function call.\r
*\r
* @param[in] enable\r
{\r
#if defined(_EFM32_GECKO_FAMILY)\r
/* LF register about to be modified require sync. busy check */\r
- RTC_Sync(RTC_SYNCBUSY_CTRL);\r
+ regSync(RTC_SYNCBUSY_CTRL);\r
#endif\r
\r
- BITBAND_Peripheral(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, (unsigned int) enable);\r
+ BUS_RegBitWrite(&(RTC->CTRL), _RTC_CTRL_EN_SHIFT, enable);\r
\r
#if defined(_EFM32_GECKO_FAMILY)\r
/* Wait for CTRL to be updated before returning, because calling code may\r
depend upon that the CTRL register is updated after this function has\r
returned. */\r
- RTC_Sync(RTC_SYNCBUSY_CTRL);\r
+ regSync(RTC_SYNCBUSY_CTRL);\r
#endif\r
}\r
\r
* synchronization into the low frequency domain. If this register is\r
* modified before a previous update to the same register has completed, this\r
* function will stall until the previous synchronization has completed. This\r
- * only applies to the Gecko Family, see comment in the RTC_Sync() internal\r
+ * only applies to the Gecko Family, see comment in the regSync() internal\r
* function call.\r
*\r
* @param[in] init\r
\r
#if defined(_EFM32_GECKO_FAMILY)\r
/* LF register about to be modified require sync. busy check */\r
- RTC_Sync(RTC_SYNCBUSY_CTRL);\r
+ regSync(RTC_SYNCBUSY_CTRL);\r
#endif\r
\r
RTC->CTRL = tmp;\r
/* Wait for CTRL, COMP0 and COMP1 to be updated before returning, because the\r
calling code may depend upon that the register values are updated after\r
this function has returned. */\r
- RTC_Sync(RTC_SYNCBUSY_CTRL | RTC_SYNCBUSY_COMP0 | RTC_SYNCBUSY_COMP1);\r
+ regSync(RTC_SYNCBUSY_CTRL | RTC_SYNCBUSY_COMP0 | RTC_SYNCBUSY_COMP1);\r
#endif\r
}\r
\r
/***************************************************************************//**\r
* @file em_system.c\r
* @brief System Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
#include "em_system.h"\r
#include "em_assert.h"\r
\r
{\r
uint8_t tmp;\r
\r
- EFM_ASSERT(rev); \r
- \r
+ EFM_ASSERT(rev);\r
+\r
/* CHIP FAMILY bit [5:2] */\r
- tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); \r
+ tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);\r
/* CHIP FAMILY bit [1:0] */\r
- tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); \r
+ tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);\r
rev->family = tmp;\r
\r
/* CHIP MAJOR bit [3:0] */\r
- rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; \r
+ rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;\r
\r
/* CHIP MINOR bit [7:4] */\r
- tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); \r
+ tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);\r
/* CHIP MINOR bit [3:0] */\r
- tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); \r
+ tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);\r
rev->minor = tmp;\r
}\r
\r
+\r
+#if defined(CALIBRATE)\r
/***************************************************************************//**\r
* @brief\r
* Get factory calibration value for a given peripheral register.\r
regCount++;\r
}\r
}\r
+#endif /* defined (CALIBRATE) */\r
\r
/** @} (end addtogroup SYSTEM) */\r
/** @} (end addtogroup EM_Library) */\r
/***************************************************************************//**\r
* @file em_acmp.h\r
* @brief Analog Comparator (ACMP) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_ACMP_H_\r
-#define __SILICON_LABS_EM_ACMP_H_\r
+#ifndef __SILICON_LABS_EM_ACMP_H__\r
+#define __SILICON_LABS_EM_ACMP_H__\r
\r
#include "em_device.h"\r
#if defined(ACMP_COUNT) && (ACMP_COUNT > 0)\r
******************************** ENUMS ************************************\r
******************************************************************************/\r
\r
-/** Resistor values used for capacative sense. See the datasheet for your\r
- * device for details on each resistor value. */\r
+/** Resistor values used for the internal capacative sense resistor. See the\r
+ * datasheet for your device for details on each resistor value. */\r
typedef enum\r
{\r
- /** resistor value 0 */\r
- acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0,\r
- /** resistor value 1 */\r
- acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1,\r
- /** resistor value 2 */\r
- acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2,\r
- /** resistor value 3 */\r
- acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3\r
+ acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */\r
+ acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */\r
+ acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */\r
+ acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3, /**< Resistor value 3 */\r
+#if defined(_ACMP_INPUTSEL_CSRESSEL_RES4)\r
+ acmpResistor4 = _ACMP_INPUTSEL_CSRESSEL_RES4, /**< Resistor value 4 */\r
+ acmpResistor5 = _ACMP_INPUTSEL_CSRESSEL_RES5, /**< Resistor value 5 */\r
+ acmpResistor6 = _ACMP_INPUTSEL_CSRESSEL_RES6, /**< Resistor value 6 */\r
+ acmpResistor7 = _ACMP_INPUTSEL_CSRESSEL_RES7, /**< Resistor value 7 */\r
+#endif\r
} ACMP_CapsenseResistor_TypeDef;\r
\r
/** Hysteresis level. See datasheet for your device for details on each\r
* level. */\r
typedef enum\r
{\r
- acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */\r
- acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */\r
- acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */\r
- acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */\r
- acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */\r
- acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */\r
- acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */\r
- acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7 /**< Hysteresis level 7 */\r
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)\r
+ acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */\r
+ acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */\r
+ acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */\r
+ acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */\r
+ acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */\r
+ acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */\r
+ acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */\r
+ acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7 /**< Hysteresis level 7 */\r
+#endif\r
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)\r
+ acmpHysteresisLevel0 = _ACMP_HYSTERESIS0_HYST_HYST0, /**< Hysteresis level 0 */\r
+ acmpHysteresisLevel1 = _ACMP_HYSTERESIS0_HYST_HYST1, /**< Hysteresis level 1 */\r
+ acmpHysteresisLevel2 = _ACMP_HYSTERESIS0_HYST_HYST2, /**< Hysteresis level 2 */\r
+ acmpHysteresisLevel3 = _ACMP_HYSTERESIS0_HYST_HYST3, /**< Hysteresis level 3 */\r
+ acmpHysteresisLevel4 = _ACMP_HYSTERESIS0_HYST_HYST4, /**< Hysteresis level 4 */\r
+ acmpHysteresisLevel5 = _ACMP_HYSTERESIS0_HYST_HYST5, /**< Hysteresis level 5 */\r
+ acmpHysteresisLevel6 = _ACMP_HYSTERESIS0_HYST_HYST6, /**< Hysteresis level 6 */\r
+ acmpHysteresisLevel7 = _ACMP_HYSTERESIS0_HYST_HYST7, /**< Hysteresis level 7 */\r
+ acmpHysteresisLevel8 = _ACMP_HYSTERESIS0_HYST_HYST8, /**< Hysteresis level 8 */\r
+ acmpHysteresisLevel9 = _ACMP_HYSTERESIS0_HYST_HYST9, /**< Hysteresis level 9 */\r
+ acmpHysteresisLevel10 = _ACMP_HYSTERESIS0_HYST_HYST10, /**< Hysteresis level 10 */\r
+ acmpHysteresisLevel11 = _ACMP_HYSTERESIS0_HYST_HYST11, /**< Hysteresis level 11 */\r
+ acmpHysteresisLevel12 = _ACMP_HYSTERESIS0_HYST_HYST12, /**< Hysteresis level 12 */\r
+ acmpHysteresisLevel13 = _ACMP_HYSTERESIS0_HYST_HYST13, /**< Hysteresis level 13 */\r
+ acmpHysteresisLevel14 = _ACMP_HYSTERESIS0_HYST_HYST14, /**< Hysteresis level 14 */\r
+ acmpHysteresisLevel15 = _ACMP_HYSTERESIS0_HYST_HYST15, /**< Hysteresis level 15 */\r
+#endif\r
} ACMP_HysteresisLevel_TypeDef;\r
\r
+#if defined(_ACMP_CTRL_WARMTIME_MASK)\r
/** ACMP warmup time. The delay is measured in HFPERCLK cycles and should\r
* be at least 10 us. */\r
typedef enum\r
/** 512 HFPERCLK cycles warmup */\r
acmpWarmTime512 = _ACMP_CTRL_WARMTIME_512CYCLES\r
} ACMP_WarmTime_TypeDef;\r
+#endif\r
\r
+#if defined(_ACMP_CTRL_INPUTRANGE_MASK)\r
+/**\r
+ * Adjust performance of the ACMP for a given input voltage range\r
+ */\r
+typedef enum\r
+{\r
+ acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to Vdd */\r
+ acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than Vdd/2 */\r
+ acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than Vdd/2 */\r
+} ACMP_InputRange_TypeDef;\r
+#endif\r
+\r
+#if defined(_ACMP_CTRL_PWRSEL_MASK)\r
+/**\r
+ * ACMP Power source.\r
+ */\r
+typedef enum\r
+{\r
+ acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power the ACMP using the AVDD supply */\r
+ acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */\r
+ acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power the ACMP using the IOVDD/IOVDD0 supply */\r
+ acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power the ACMP using the IOVDD1 supply (if part has two I/O voltages) */\r
+} ACMP_PowerSource_TypeDef;\r
+#endif\r
+\r
+#if defined(_ACMP_CTRL_ACCURACY_MASK)\r
+/**\r
+ * ACMP accuracy mode.\r
+ */\r
+typedef enum\r
+{\r
+ acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode but consume less current */\r
+ acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode but consume more current */\r
+} ACMP_Accuracy_TypeDef;\r
+#endif\r
+\r
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)\r
+/** ACMP Input to the VA divider. This enum is used to select the input for\r
+ * the VA Divider */\r
+typedef enum\r
+{\r
+ acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD,\r
+ acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0,\r
+ acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2,\r
+ acmpVAInputAPORT2YCH4 = _ACMP_INPUTSEL_VASEL_APORT2YCH4,\r
+ acmpVAInputAPORT2YCH6 = _ACMP_INPUTSEL_VASEL_APORT2YCH6,\r
+ acmpVAInputAPORT2YCH8 = _ACMP_INPUTSEL_VASEL_APORT2YCH8,\r
+ acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10,\r
+ acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12,\r
+ acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14,\r
+ acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16,\r
+ acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18,\r
+ acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20,\r
+ acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22,\r
+ acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24,\r
+ acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26,\r
+ acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28,\r
+ acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30,\r
+ acmpVAInputAPORT1XCH0 = _ACMP_INPUTSEL_VASEL_APORT1XCH0,\r
+ acmpVAInputAPORT1YCH1 = _ACMP_INPUTSEL_VASEL_APORT1YCH1,\r
+ acmpVAInputAPORT1XCH2 = _ACMP_INPUTSEL_VASEL_APORT1XCH2,\r
+ acmpVAInputAPORT1YCH3 = _ACMP_INPUTSEL_VASEL_APORT1YCH3,\r
+ acmpVAInputAPORT1XCH4 = _ACMP_INPUTSEL_VASEL_APORT1XCH4,\r
+ acmpVAInputAPORT1YCH5 = _ACMP_INPUTSEL_VASEL_APORT1YCH5,\r
+ acmpVAInputAPORT1XCH6 = _ACMP_INPUTSEL_VASEL_APORT1XCH6,\r
+ acmpVAInputAPORT1YCH7 = _ACMP_INPUTSEL_VASEL_APORT1YCH7,\r
+ acmpVAInputAPORT1XCH8 = _ACMP_INPUTSEL_VASEL_APORT1XCH8,\r
+ acmpVAInputAPORT1YCH9 = _ACMP_INPUTSEL_VASEL_APORT1YCH9,\r
+ acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10,\r
+ acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11,\r
+ acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12,\r
+ acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13,\r
+ acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14,\r
+ acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15,\r
+ acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16,\r
+ acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17,\r
+ acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18,\r
+ acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19,\r
+ acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20,\r
+ acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21,\r
+ acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22,\r
+ acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23,\r
+ acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24,\r
+ acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25,\r
+ acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26,\r
+ acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27,\r
+ acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28,\r
+ acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29,\r
+ acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30,\r
+ acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31\r
+} ACMP_VAInput_TypeDef;\r
+#endif\r
+\r
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)\r
+/**\r
+ * ACMP Input to the VB divider. This enum is used to select the input for\r
+ * the VB divider.\r
+ */\r
+typedef enum\r
+{\r
+ acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25,\r
+ acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5\r
+} ACMP_VBInput_TypeDef;\r
+#endif\r
+\r
+#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)\r
+/**\r
+ * ACMP Low-Power Input Selection.\r
+ */\r
+typedef enum\r
+{\r
+ acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV,\r
+ acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV\r
+} ACMP_VLPInput_Typedef;\r
+#endif\r
+\r
+#if defined(_SILICON_LABS_32B_PLATFORM_2)\r
+/** ACMP Input Selection */\r
+typedef enum\r
+{\r
+ acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0,\r
+ acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1,\r
+ acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2,\r
+ acmpInputAPORT0XCH3 = _ACMP_INPUTSEL_POSSEL_APORT0XCH3,\r
+ acmpInputAPORT0XCH4 = _ACMP_INPUTSEL_POSSEL_APORT0XCH4,\r
+ acmpInputAPORT0XCH5 = _ACMP_INPUTSEL_POSSEL_APORT0XCH5,\r
+ acmpInputAPORT0XCH6 = _ACMP_INPUTSEL_POSSEL_APORT0XCH6,\r
+ acmpInputAPORT0XCH7 = _ACMP_INPUTSEL_POSSEL_APORT0XCH7,\r
+ acmpInputAPORT0XCH8 = _ACMP_INPUTSEL_POSSEL_APORT0XCH8,\r
+ acmpInputAPORT0XCH9 = _ACMP_INPUTSEL_POSSEL_APORT0XCH9,\r
+ acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10,\r
+ acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11,\r
+ acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12,\r
+ acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13,\r
+ acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14,\r
+ acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15,\r
+ acmpInputAPORT0YCH0 = _ACMP_INPUTSEL_POSSEL_APORT0YCH0,\r
+ acmpInputAPORT0YCH1 = _ACMP_INPUTSEL_POSSEL_APORT0YCH1,\r
+ acmpInputAPORT0YCH2 = _ACMP_INPUTSEL_POSSEL_APORT0YCH2,\r
+ acmpInputAPORT0YCH3 = _ACMP_INPUTSEL_POSSEL_APORT0YCH3,\r
+ acmpInputAPORT0YCH4 = _ACMP_INPUTSEL_POSSEL_APORT0YCH4,\r
+ acmpInputAPORT0YCH5 = _ACMP_INPUTSEL_POSSEL_APORT0YCH5,\r
+ acmpInputAPORT0YCH6 = _ACMP_INPUTSEL_POSSEL_APORT0YCH6,\r
+ acmpInputAPORT0YCH7 = _ACMP_INPUTSEL_POSSEL_APORT0YCH7,\r
+ acmpInputAPORT0YCH8 = _ACMP_INPUTSEL_POSSEL_APORT0YCH8,\r
+ acmpInputAPORT0YCH9 = _ACMP_INPUTSEL_POSSEL_APORT0YCH9,\r
+ acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10,\r
+ acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11,\r
+ acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12,\r
+ acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13,\r
+ acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14,\r
+ acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15,\r
+ acmpInputAPORT1XCH0 = _ACMP_INPUTSEL_POSSEL_APORT1XCH0,\r
+ acmpInputAPORT1YCH1 = _ACMP_INPUTSEL_POSSEL_APORT1YCH1,\r
+ acmpInputAPORT1XCH2 = _ACMP_INPUTSEL_POSSEL_APORT1XCH2,\r
+ acmpInputAPORT1YCH3 = _ACMP_INPUTSEL_POSSEL_APORT1YCH3,\r
+ acmpInputAPORT1XCH4 = _ACMP_INPUTSEL_POSSEL_APORT1XCH4,\r
+ acmpInputAPORT1YCH5 = _ACMP_INPUTSEL_POSSEL_APORT1YCH5,\r
+ acmpInputAPORT1XCH6 = _ACMP_INPUTSEL_POSSEL_APORT1XCH6,\r
+ acmpInputAPORT1YCH7 = _ACMP_INPUTSEL_POSSEL_APORT1YCH7,\r
+ acmpInputAPORT1XCH8 = _ACMP_INPUTSEL_POSSEL_APORT1XCH8,\r
+ acmpInputAPORT1YCH9 = _ACMP_INPUTSEL_POSSEL_APORT1YCH9,\r
+ acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10,\r
+ acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11,\r
+ acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12,\r
+ acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13,\r
+ acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14,\r
+ acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15,\r
+ acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16,\r
+ acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17,\r
+ acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18,\r
+ acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19,\r
+ acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20,\r
+ acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21,\r
+ acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22,\r
+ acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23,\r
+ acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24,\r
+ acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25,\r
+ acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26,\r
+ acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27,\r
+ acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28,\r
+ acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29,\r
+ acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30,\r
+ acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31,\r
+ acmpInputAPORT2YCH0 = _ACMP_INPUTSEL_POSSEL_APORT2YCH0,\r
+ acmpInputAPORT2XCH1 = _ACMP_INPUTSEL_POSSEL_APORT2XCH1,\r
+ acmpInputAPORT2YCH2 = _ACMP_INPUTSEL_POSSEL_APORT2YCH2,\r
+ acmpInputAPORT2XCH3 = _ACMP_INPUTSEL_POSSEL_APORT2XCH3,\r
+ acmpInputAPORT2YCH4 = _ACMP_INPUTSEL_POSSEL_APORT2YCH4,\r
+ acmpInputAPORT2XCH5 = _ACMP_INPUTSEL_POSSEL_APORT2XCH5,\r
+ acmpInputAPORT2YCH6 = _ACMP_INPUTSEL_POSSEL_APORT2YCH6,\r
+ acmpInputAPORT2XCH7 = _ACMP_INPUTSEL_POSSEL_APORT2XCH7,\r
+ acmpInputAPORT2YCH8 = _ACMP_INPUTSEL_POSSEL_APORT2YCH8,\r
+ acmpInputAPORT2XCH9 = _ACMP_INPUTSEL_POSSEL_APORT2XCH9,\r
+ acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10,\r
+ acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11,\r
+ acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12,\r
+ acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13,\r
+ acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14,\r
+ acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15,\r
+ acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16,\r
+ acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17,\r
+ acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18,\r
+ acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19,\r
+ acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20,\r
+ acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21,\r
+ acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22,\r
+ acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23,\r
+ acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24,\r
+ acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25,\r
+ acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26,\r
+ acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27,\r
+ acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28,\r
+ acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29,\r
+ acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30,\r
+ acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31,\r
+ acmpInputAPORT3XCH0 = _ACMP_INPUTSEL_POSSEL_APORT3XCH0,\r
+ acmpInputAPORT3YCH1 = _ACMP_INPUTSEL_POSSEL_APORT3YCH1,\r
+ acmpInputAPORT3XCH2 = _ACMP_INPUTSEL_POSSEL_APORT3XCH2,\r
+ acmpInputAPORT3YCH3 = _ACMP_INPUTSEL_POSSEL_APORT3YCH3,\r
+ acmpInputAPORT3XCH4 = _ACMP_INPUTSEL_POSSEL_APORT3XCH4,\r
+ acmpInputAPORT3YCH5 = _ACMP_INPUTSEL_POSSEL_APORT3YCH5,\r
+ acmpInputAPORT3XCH6 = _ACMP_INPUTSEL_POSSEL_APORT3XCH6,\r
+ acmpInputAPORT3YCH7 = _ACMP_INPUTSEL_POSSEL_APORT3YCH7,\r
+ acmpInputAPORT3XCH8 = _ACMP_INPUTSEL_POSSEL_APORT3XCH8,\r
+ acmpInputAPORT3YCH9 = _ACMP_INPUTSEL_POSSEL_APORT3YCH9,\r
+ acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10,\r
+ acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11,\r
+ acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12,\r
+ acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13,\r
+ acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14,\r
+ acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15,\r
+ acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16,\r
+ acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17,\r
+ acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18,\r
+ acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19,\r
+ acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20,\r
+ acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21,\r
+ acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22,\r
+ acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23,\r
+ acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24,\r
+ acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25,\r
+ acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26,\r
+ acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27,\r
+ acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28,\r
+ acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29,\r
+ acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30,\r
+ acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31,\r
+ acmpInputAPORT4YCH0 = _ACMP_INPUTSEL_POSSEL_APORT4YCH0,\r
+ acmpInputAPORT4XCH1 = _ACMP_INPUTSEL_POSSEL_APORT4XCH1,\r
+ acmpInputAPORT4YCH2 = _ACMP_INPUTSEL_POSSEL_APORT4YCH2,\r
+ acmpInputAPORT4XCH3 = _ACMP_INPUTSEL_POSSEL_APORT4XCH3,\r
+ acmpInputAPORT4YCH4 = _ACMP_INPUTSEL_POSSEL_APORT4YCH4,\r
+ acmpInputAPORT4XCH5 = _ACMP_INPUTSEL_POSSEL_APORT4XCH5,\r
+ acmpInputAPORT4YCH6 = _ACMP_INPUTSEL_POSSEL_APORT4YCH6,\r
+ acmpInputAPORT4XCH7 = _ACMP_INPUTSEL_POSSEL_APORT4XCH7,\r
+ acmpInputAPORT4YCH8 = _ACMP_INPUTSEL_POSSEL_APORT4YCH8,\r
+ acmpInputAPORT4XCH9 = _ACMP_INPUTSEL_POSSEL_APORT4XCH9,\r
+ acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10,\r
+ acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11,\r
+ acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12,\r
+ acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13,\r
+ acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16,\r
+ acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17,\r
+ acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18,\r
+ acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19,\r
+ acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20,\r
+ acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21,\r
+ acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22,\r
+ acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23,\r
+ acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24,\r
+ acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25,\r
+ acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26,\r
+ acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27,\r
+ acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28,\r
+ acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29,\r
+ acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30,\r
+ acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14,\r
+ acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15,\r
+ acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31,\r
+ acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0,\r
+ acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1,\r
+ acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP,\r
+ acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV,\r
+ acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV,\r
+ acmpInputVDD = _ACMP_INPUTSEL_POSSEL_VDD,\r
+ acmpInputVSS = _ACMP_INPUTSEL_POSSEL_VSS,\r
+} ACMP_Channel_TypeDef;\r
+#else\r
/** ACMP inputs. Note that scaled VDD and bandgap references can only be used\r
* as negative inputs. */\r
typedef enum\r
/** Scaled VDD reference */\r
acmpChannelVDD = _ACMP_INPUTSEL_NEGSEL_VDD,\r
\r
-#if defined( _ACMP_INPUTSEL_NEGSEL_DAC0CH0 )\r
+#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH0)\r
/** DAC0 channel 0 */\r
acmpChannelDAC0Ch0 = _ACMP_INPUTSEL_NEGSEL_DAC0CH0,\r
#endif\r
\r
-#if defined( _ACMP_INPUTSEL_NEGSEL_DAC0CH1 )\r
+#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1)\r
/** DAC0 channel 1 */\r
acmpChannelDAC0Ch1 = _ACMP_INPUTSEL_NEGSEL_DAC0CH1,\r
#endif\r
\r
-#if defined( _ACMP_INPUTSEL_NEGSEL_CAPSENSE )\r
+#if defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE)\r
/** Capacitive sense mode */\r
acmpChannelCapSense = _ACMP_INPUTSEL_NEGSEL_CAPSENSE,\r
#endif\r
} ACMP_Channel_TypeDef;\r
+#endif\r
\r
/*******************************************************************************\r
****************************** STRUCTS ************************************\r
* the reference manual for details. */\r
bool fullBias;\r
\r
+#if defined(_ACMP_CTRL_HALFBIAS_MASK)\r
/** Half bias current. See the ACMP chapter about bias and response time in\r
* the reference manual for details. */\r
bool halfBias;\r
+#endif\r
\r
/** Bias current. See the ACMP chapter about bias and response time in the\r
- * reference manual for details. Valid values are in the range 0-7. */\r
+ * reference manual for details. */\r
uint32_t biasProg;\r
\r
+#if defined(_ACMP_CTRL_WARMTIME_MASK)\r
/** Warmup time. This is measured in HFPERCLK cycles and should be\r
* about 10us in wall clock time. */\r
ACMP_WarmTime_TypeDef warmTime;\r
+#endif\r
\r
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)\r
/** Hysteresis level */\r
ACMP_HysteresisLevel_TypeDef hysteresisLevel;\r
+#else\r
+ /** Hysteresis level when ACMP output is 0 */\r
+ ACMP_HysteresisLevel_TypeDef hysteresisLevel_0;\r
+\r
+ /** Hysteresis level when ACMP output is 1 */\r
+ ACMP_HysteresisLevel_TypeDef hysteresisLevel_1;\r
+#endif\r
\r
/** Resistor used in the capacative sensing circuit. For values see\r
* your device datasheet. */\r
ACMP_CapsenseResistor_TypeDef resistor;\r
\r
+#if defined(_ACMP_INPUTSEL_LPREF_MASK)\r
/** Low power reference enabled. This setting, if enabled, reduces the\r
* power used by the VDD and bandgap references. */\r
bool lowPowerReferenceEnabled;\r
+#endif\r
\r
- /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.\r
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)\r
+ /** Vdd reference value. VDD_SCALED = (Vdd * VDDLEVEL) / 63.\r
* Valid values are in the range 0-63. */\r
uint32_t vddLevel;\r
+#else\r
+ /**\r
+ * This value configures the upper voltage threshold of the capsense\r
+ * oscillation rail.\r
+ *\r
+ * The voltage threshold is calculated as\r
+ * Vdd * (vddLevelHigh + 1) / 64\r
+ */\r
+ uint32_t vddLevelHigh;\r
+\r
+ /**\r
+ * This value configures the lower voltage threshold of the capsense\r
+ * oscillation rail.\r
+ *\r
+ * The voltage threshold is calculated as\r
+ * Vdd * (vddLevelLow + 1) / 64\r
+ */\r
+ uint32_t vddLevelLow;\r
+#endif\r
\r
/** If true, ACMP is being enabled after configuration. */\r
bool enable;\r
} ACMP_CapsenseInit_TypeDef;\r
\r
/** Default config for capacitive sense mode initialization. */\r
-#define ACMP_CAPSENSE_INIT_DEFAULT \\r
- { false, /* fullBias */ \\r
- false, /* halfBias */ \\r
- 0x7, /* biasProg */ \\r
- acmpWarmTime512, /* 512 cycle warmup to be safe */ \\r
- acmpHysteresisLevel5, \\r
- acmpResistor3, \\r
- false, /* low power reference */ \\r
- 0x3D, /* VDD level */ \\r
- true /* Enable after init. */ \\r
- }\r
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)\r
+#define ACMP_CAPSENSE_INIT_DEFAULT \\r
+{ \\r
+ false, /* Don't use fullBias to lower power consumption */ \\r
+ 0x20, /* Using biasProg value of 0x20 (32) */ \\r
+ acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0 */ \\r
+ acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1 */ \\r
+ acmpResistor5, /* Use internal resistor value 5 */ \\r
+ 0x30, /* VDD level high */ \\r
+ 0x10, /* VDD level low */ \\r
+ true /* Enable after init. */ \\r
+}\r
+#elif defined(_ACMP_CTRL_WARMTIME_MASK)\r
+#define ACMP_CAPSENSE_INIT_DEFAULT \\r
+{ \\r
+ false, /* fullBias */ \\r
+ false, /* halfBias */ \\r
+ 0x7, /* biasProg */ \\r
+ acmpWarmTime512, /* 512 cycle warmup to be safe */ \\r
+ acmpHysteresisLevel5, \\r
+ acmpResistor3, \\r
+ false, /* low power reference */ \\r
+ 0x3D, /* VDD level */ \\r
+ true /* Enable after init. */ \\r
+}\r
+#else\r
+#define ACMP_CAPSENSE_INIT_DEFAULT \\r
+{ \\r
+ false, /* fullBias */ \\r
+ false, /* halfBias */ \\r
+ 0x7, /* biasProg */ \\r
+ acmpHysteresisLevel5, \\r
+ acmpResistor3, \\r
+ false, /* low power reference */ \\r
+ 0x3D, /* VDD level */ \\r
+ true /* Enable after init. */ \\r
+}\r
+#endif\r
\r
/** ACMP initialization structure. */\r
typedef struct\r
* the reference manual for details. */\r
bool fullBias;\r
\r
+#if defined(_ACMP_CTRL_HALFBIAS_MASK)\r
/** Half bias current. See the ACMP chapter about bias and response time in\r
* the reference manual for details. */\r
bool halfBias;\r
+#endif\r
\r
/** Bias current. See the ACMP chapter about bias and response time in the\r
* reference manual for details. Valid values are in the range 0-7. */\r
/** Enable setting the interrupt flag on rising edge */\r
bool interruptOnRisingEdge;\r
\r
+#if defined(_ACMP_CTRL_INPUTRANGE_MASK)\r
+ /** Input range. Adjust this setting to optimize the performance for a\r
+ * given input voltage range. */\r
+ ACMP_InputRange_TypeDef inputRange;\r
+#endif\r
+\r
+#if defined(_ACMP_CTRL_ACCURACY_MASK)\r
+ /** ACMP accuracy mode. Select the accuracy mode that matches the\r
+ * required current usage and accuracy requirement. Low accuracy\r
+ * consumes less current while high accuracy consumes more current. */\r
+ ACMP_Accuracy_TypeDef accuracy;\r
+#endif\r
+\r
+#if defined(_ACMP_CTRL_PWRSEL_MASK)\r
+ /** Select the power source for the ACMP. */\r
+ ACMP_PowerSource_TypeDef powerSource;\r
+#endif\r
+\r
+#if defined(_ACMP_CTRL_WARMTIME_MASK)\r
/** Warmup time. This is measured in HFPERCLK cycles and should be\r
* about 10us in wall clock time. */\r
ACMP_WarmTime_TypeDef warmTime;\r
+#endif\r
\r
+#if defined(_ACMP_CTRL_HYSTSEL_MASK)\r
/** Hysteresis level */\r
ACMP_HysteresisLevel_TypeDef hysteresisLevel;\r
+#else\r
+ /** Hysteresis when ACMP output is 0 */\r
+ ACMP_HysteresisLevel_TypeDef hysteresisLevel_0;\r
+\r
+ /** Hysteresis when ACMP output is 1 */\r
+ ACMP_HysteresisLevel_TypeDef hysteresisLevel_1;\r
+#endif\r
+\r
+#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)\r
+ /** VLP Input source. Select between using VADIV or VBDIV as the VLP\r
+ * source. */\r
+ ACMP_VLPInput_Typedef vlpInput;\r
+#endif\r
\r
/** Inactive value emitted by the ACMP during warmup */\r
bool inactiveValue;\r
\r
+#if defined(_ACMP_INPUTSEL_LPREF_MASK)\r
/** Low power reference enabled. This setting, if enabled, reduces the\r
* power used by the VDD and bandgap references. */\r
bool lowPowerReferenceEnabled;\r
+#endif\r
\r
- /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.\r
+#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)\r
+ /** Vdd reference value. VDD_SCALED = VDD * VDDLEVEL * 50mV/3.8V.\r
* Valid values are in the range 0-63. */\r
uint32_t vddLevel;\r
+#endif\r
\r
/** If true, ACMP is being enabled after configuration. */\r
bool enable;\r
} ACMP_Init_TypeDef;\r
\r
/** Default config for ACMP regular initialization. */\r
-#define ACMP_INIT_DEFAULT \\r
- { false, /* fullBias */ \\r
- false, /* halfBias */ \\r
- 0x7, /* biasProg */ \\r
- false, /* No interrupt on falling edge. */ \\r
- false, /* No interrupt on rising edge. */ \\r
- acmpWarmTime512, /* 512 cycle warmup to be safe */ \\r
- acmpHysteresisLevel5, \\r
- false, /* Disabled emitting inactive value during warmup. */ \\r
- false, /* low power reference */ \\r
- 0x3D, /* VDD level */ \\r
- true /* Enable after init. */ \\r
- }\r
+#if defined(_ACMP_HYSTERESIS0_HYST_MASK)\r
+#define ACMP_INIT_DEFAULT \\r
+{ \\r
+ false, /* fullBias */ \\r
+ 0x7, /* biasProg */ \\r
+ false, /* No interrupt on falling edge. */ \\r
+ false, /* No interrupt on rising edge. */ \\r
+ acmpInputRangeFull, /* Input range from 0 to Vdd. */ \\r
+ acmpAccuracyLow, /* Low accuracy, less current usage. */ \\r
+ acmpPowerSourceAvdd, /* Use the AVDD supply. */ \\r
+ acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \\r
+ acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \\r
+ acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \\r
+ false, /* Output 0 when ACMP is inactive. */ \\r
+ true /* Enable after init. */ \\r
+}\r
+#elif defined(_ACMP_CTRL_WARMTIME_MASK)\r
+#define ACMP_INIT_DEFAULT \\r
+{ \\r
+ false, /* fullBias */ \\r
+ false, /* halfBias */ \\r
+ 0x7, /* biasProg */ \\r
+ false, /* No interrupt on falling edge. */ \\r
+ false, /* No interrupt on rising edge. */ \\r
+ acmpWarmTime512, /* 512 cycle warmup to be safe */ \\r
+ acmpHysteresisLevel5, \\r
+ false, /* Disabled emitting inactive value during warmup. */ \\r
+ false, /* low power reference */ \\r
+ 0x3D, /* VDD level */ \\r
+ true /* Enable after init. */ \\r
+}\r
+#else\r
+#define ACMP_INIT_DEFAULT \\r
+{ \\r
+ false, /* fullBias */ \\r
+ false, /* halfBias */ \\r
+ 0x7, /* biasProg */ \\r
+ false, /* No interrupt on falling edge. */ \\r
+ false, /* No interrupt on rising edge. */ \\r
+ acmpHysteresisLevel5, \\r
+ false, /* Disabled emitting inactive value during warmup. */ \\r
+ false, /* low power reference */ \\r
+ 0x3D, /* VDD level */ \\r
+ true /* Enable after init. */ \\r
+}\r
+#endif\r
+\r
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)\r
+/** VA Configuration structure. This struct is used to configure the\r
+ * VA voltage input source and it's dividers. */\r
+typedef struct\r
+{\r
+ ACMP_VAInput_TypeDef input; /**< VA voltage input source */\r
+\r
+ /**\r
+ * Divider for VA voltage input source when ACMP output is 0. This value is\r
+ * used to divide the VA voltage input source by a specific value. The valid\r
+ * range is between 0 and 63.\r
+ *\r
+ * VA divided = VA input * (div0 + 1) / 64\r
+ */\r
+ uint32_t div0;\r
+\r
+ /**\r
+ * Divider for VA voltage input source when ACMP output is 1. This value is\r
+ * used to divide the VA voltage input source by a specific value. The valid\r
+ * range is between 0 and 63.\r
+ *\r
+ * VA divided = VA input * (div1 + 1) / 64\r
+ */\r
+ uint32_t div1;\r
+} ACMP_VAConfig_TypeDef;\r
+\r
+#define ACMP_VACONFIG_DEFAULT \\r
+{ \\r
+ acmpVAInputVDD, /* Use Vdd as VA voltage input source */ \\r
+ 63, /* No division of the VA source when ACMP output is 0 */ \\r
+ 63, /* No division of the VA source when ACMP output is 1 */ \\r
+}\r
+#endif\r
\r
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)\r
+/** VB Configuration structure. This struct is used to configure the\r
+ * VB voltage input source and it's dividers. */\r
+typedef struct\r
+{\r
+ ACMP_VBInput_TypeDef input; /**< VB Voltage input source */\r
+\r
+ /**\r
+ * Divider for VB voltage input source when ACMP output is 0. This value is\r
+ * used to divide the VB voltage input source by a specific value. The valid\r
+ * range is between 0 and 63.\r
+ *\r
+ * VB divided = VB input * (div0 + 1) / 64\r
+ */\r
+ uint32_t div0;\r
+\r
+ /**\r
+ * Divider for VB voltage input source when ACMP output is 1. This value is\r
+ * used to divide the VB voltage input source by a specific value. The valid\r
+ * range is between 0 and 63.\r
+ *\r
+ * VB divided = VB input * (div1 + 1) / 64\r
+ */\r
+ uint32_t div1;\r
+} ACMP_VBConfig_TypeDef;\r
+\r
+#define ACMP_VBCONFIG_DEFAULT \\r
+{ \\r
+ acmpVBInput1V25, /* Use 1.25 V as VB voltage input source */ \\r
+ 63, /* No division of the VB source when ACMP output is 0 */ \\r
+ 63, /* No division of the VB source when ACMP output is 1 */ \\r
+}\r
+#endif\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert);\r
void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init);\r
void ACMP_Reset(ACMP_TypeDef *acmp);\r
+#if defined(_ACMP_INPUTSEL_VASEL_MASK)\r
+void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig);\r
+#endif\r
+#if defined(_ACMP_INPUTSEL_VBSEL_MASK)\r
+void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig);\r
+#endif\r
\r
/***************************************************************************//**\r
* @brief\r
******************************************************************************/\r
__STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp)\r
{\r
- return(acmp->IF);\r
+ return acmp->IF;\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_ACMP_H_ */\r
+#endif /* __SILICON_LABS_EM_ACMP_H__ */\r
/***************************************************************************//**\r
* @file em_adc.h\r
* @brief Analog to Digital Converter (ADC) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_ADC_H_\r
-#define __SILICON_LABS_EM_ADC_H_\r
+#ifndef __SILICON_LABS_EM_ADC_H__\r
+#define __SILICON_LABS_EM_ADC_H__\r
\r
#include "em_device.h"\r
-#if defined(ADC_COUNT) && (ADC_COUNT > 0)\r
+#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )\r
\r
#include <stdbool.h>\r
\r
adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES /**< 256 clock cycles. */\r
} ADC_AcqTime_TypeDef;\r
\r
-\r
+#if defined( _ADC_CTRL_LPFMODE_MASK )\r
/** Lowpass filter mode. */\r
typedef enum\r
{\r
/** On-chip decoupling capacitor. */\r
adcLPFilterDeCap = _ADC_CTRL_LPFMODE_DECAP\r
} ADC_LPFilter_TypeDef;\r
-\r
+#endif\r
\r
/** Oversample rate select. */\r
typedef enum\r
/** Peripheral Reflex System signal used to trigger single sample. */\r
typedef enum\r
{\r
+#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )\r
adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */\r
adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH11 )\r
adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */\r
#endif\r
+#elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK)\r
+ adcPRSSELCh0 = _ADC_SINGLECTRLX_PRSSEL_PRSCH0, /**< PRS channel 0. */\r
+ adcPRSSELCh1 = _ADC_SINGLECTRLX_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
+ adcPRSSELCh2 = _ADC_SINGLECTRLX_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
+ adcPRSSELCh3 = _ADC_SINGLECTRLX_PRSSEL_PRSCH3, /**< PRS channel 3. */\r
+ adcPRSSELCh4 = _ADC_SINGLECTRLX_PRSSEL_PRSCH4, /**< PRS channel 4. */\r
+ adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */\r
+ adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */\r
+ adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */\r
+ adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */\r
+ adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */\r
+ adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */\r
+ adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */\r
+#if defined( _ADC_SINGLECTRLX_PRSSEL_PRSCH12 )\r
+ adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */\r
+ adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */\r
+ adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14, /**< PRS channel 14. */\r
+ adcPRSSELCh15 = _ADC_SINGLECTRLX_PRSSEL_PRSCH15, /**< PRS channel 15. */\r
+#endif\r
+#endif\r
} ADC_PRSSEL_TypeDef;\r
\r
\r
-/** Reference to ADC sample. */\r
+/** Single and scan mode voltage references. Using unshifted enums and or\r
+ in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */\r
+#if defined( _ADC_SCANCTRLX_VREFSEL_MASK )\r
+#define ADC_CTRLX_VREFSEL_REG 0x80\r
+#endif\r
typedef enum\r
{\r
/** Internal 1.25V reference. */\r
/** Internal differential 5V reference. */\r
adcRef5VDIFF = _ADC_SINGLECTRL_REF_5VDIFF,\r
\r
- /** Single ended ext. ref. from pin 6. */\r
+ /** Single ended external reference from pin 6. */\r
adcRefExtSingle = _ADC_SINGLECTRL_REF_EXTSINGLE,\r
\r
- /** Differential ext. ref. from pin 6 and 7. */\r
+ /** Differential external reference from pin 6 and 7. */\r
adcRef2xExtDiff = _ADC_SINGLECTRL_REF_2XEXTDIFF,\r
\r
/** Unbuffered 2xVDD. */\r
- adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD\r
+ adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD,\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VBGR )\r
+ /** Custom VFS: Internal Bandgap reference */\r
+ adcRefVBGR = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )\r
+ /** Custom VFS: Scaled AVDD: AVDD * VREFATT */\r
+ adcRefVddxAtt = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPWATT )\r
+ /** Custom VFS: Scaled singled ended external reference from pin 6:\r
+ VREFP * VREFATT */\r
+ adcRefVPxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFP )\r
+ /** Custom VFS: Raw single ended external reference from pin 6. */\r
+ adcRefP = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VENTROPY )\r
+ /** Custom VFS: Special mode for entropy generation */\r
+ adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT )\r
+ /** Custom VFS: Scaled differential external Vref from pin 6 and 7:\r
+ (VREFP - VREFN) * VREFATT */\r
+ adcRefVPNxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPN )\r
+ /** Custom VFS: Raw differential external Vref from pin 6 and 7:\r
+ VREFP - VREFN */\r
+ adcRefPN = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG,\r
+#endif\r
} ADC_Ref_TypeDef;\r
\r
\r
} ADC_Res_TypeDef;\r
\r
\r
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )\r
/** Single sample input selection. */\r
typedef enum\r
{\r
/* Differential mode disabled */\r
- adcSingleInpCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */\r
- adcSingleInpCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */\r
- adcSingleInpCh2 = _ADC_SINGLECTRL_INPUTSEL_CH2, /**< Channel 2. */\r
- adcSingleInpCh3 = _ADC_SINGLECTRL_INPUTSEL_CH3, /**< Channel 3. */\r
- adcSingleInpCh4 = _ADC_SINGLECTRL_INPUTSEL_CH4, /**< Channel 4. */\r
- adcSingleInpCh5 = _ADC_SINGLECTRL_INPUTSEL_CH5, /**< Channel 5. */\r
- adcSingleInpCh6 = _ADC_SINGLECTRL_INPUTSEL_CH6, /**< Channel 6. */\r
- adcSingleInpCh7 = _ADC_SINGLECTRL_INPUTSEL_CH7, /**< Channel 7. */\r
- adcSingleInpTemp = _ADC_SINGLECTRL_INPUTSEL_TEMP, /**< Temperature reference. */\r
- adcSingleInpVDDDiv3 = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3, /**< VDD divided by 3. */\r
- adcSingleInpVDD = _ADC_SINGLECTRL_INPUTSEL_VDD, /**< VDD. */\r
- adcSingleInpVSS = _ADC_SINGLECTRL_INPUTSEL_VSS, /**< VSS. */\r
- adcSingleInpVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */\r
- adcSingleInpDACOut0 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */\r
- adcSingleInpDACOut1 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */\r
+ adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */\r
+ adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */\r
+ adcSingleInputCh2 = _ADC_SINGLECTRL_INPUTSEL_CH2, /**< Channel 2. */\r
+ adcSingleInputCh3 = _ADC_SINGLECTRL_INPUTSEL_CH3, /**< Channel 3. */\r
+ adcSingleInputCh4 = _ADC_SINGLECTRL_INPUTSEL_CH4, /**< Channel 4. */\r
+ adcSingleInputCh5 = _ADC_SINGLECTRL_INPUTSEL_CH5, /**< Channel 5. */\r
+ adcSingleInputCh6 = _ADC_SINGLECTRL_INPUTSEL_CH6, /**< Channel 6. */\r
+ adcSingleInputCh7 = _ADC_SINGLECTRL_INPUTSEL_CH7, /**< Channel 7. */\r
+ adcSingleInputTemp = _ADC_SINGLECTRL_INPUTSEL_TEMP, /**< Temperature reference. */\r
+ adcSingleInputVDDDiv3 = _ADC_SINGLECTRL_INPUTSEL_VDDDIV3, /**< VDD divided by 3. */\r
+ adcSingleInputVDD = _ADC_SINGLECTRL_INPUTSEL_VDD, /**< VDD. */\r
+ adcSingleInputVSS = _ADC_SINGLECTRL_INPUTSEL_VSS, /**< VSS. */\r
+ adcSingleInputVrefDiv2 = _ADC_SINGLECTRL_INPUTSEL_VREFDIV2, /**< Vref divided by 2. */\r
+ adcSingleInputDACOut0 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0, /**< DAC output 0. */\r
+ adcSingleInputDACOut1 = _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1, /**< DAC output 1. */\r
/* TBD: Use define when available */\r
- adcSingleInpATEST = 15, /**< ATEST. */\r
+ adcSingleInputATEST = 15, /**< ATEST. */\r
\r
/* Differential mode enabled */\r
- adcSingleInpCh0Ch1 = _ADC_SINGLECTRL_INPUTSEL_CH0CH1, /**< Positive Ch0, negative Ch1. */\r
- adcSingleInpCh2Ch3 = _ADC_SINGLECTRL_INPUTSEL_CH2CH3, /**< Positive Ch2, negative Ch3. */\r
- adcSingleInpCh4Ch5 = _ADC_SINGLECTRL_INPUTSEL_CH4CH5, /**< Positive Ch4, negative Ch5. */\r
- adcSingleInpCh6Ch7 = _ADC_SINGLECTRL_INPUTSEL_CH6CH7, /**< Positive Ch6, negative Ch7. */\r
+ adcSingleInputCh0Ch1 = _ADC_SINGLECTRL_INPUTSEL_CH0CH1, /**< Positive Ch0, negative Ch1. */\r
+ adcSingleInputCh2Ch3 = _ADC_SINGLECTRL_INPUTSEL_CH2CH3, /**< Positive Ch2, negative Ch3. */\r
+ adcSingleInputCh4Ch5 = _ADC_SINGLECTRL_INPUTSEL_CH4CH5, /**< Positive Ch4, negative Ch5. */\r
+ adcSingleInputCh6Ch7 = _ADC_SINGLECTRL_INPUTSEL_CH6CH7, /**< Positive Ch6, negative Ch7. */\r
/* TBD: Use define when available */\r
- adcSingleInpDiff0 = 4 /**< Differential 0. */\r
+ adcSingleInputDiff0 = 4 /**< Differential 0. */\r
} ADC_SingleInput_TypeDef;\r
\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/* Legacy enum names */\r
+#define adcSingleInpCh0 adcSingleInputCh0\r
+#define adcSingleInpCh1 adcSingleInputCh1\r
+#define adcSingleInpCh2 adcSingleInputCh2\r
+#define adcSingleInpCh3 adcSingleInputCh3\r
+#define adcSingleInpCh4 adcSingleInputCh4\r
+#define adcSingleInpCh5 adcSingleInputCh5\r
+#define adcSingleInpCh6 adcSingleInputCh6\r
+#define adcSingleInpCh7 adcSingleInputCh7\r
+#define adcSingleInpTemp adcSingleInputTemp\r
+#define adcSingleInpVDDDiv3 adcSingleInputVDDDiv3\r
+#define adcSingleInpVDD adcSingleInputVDD\r
+#define adcSingleInpVSS adcSingleInputVSS\r
+#define adcSingleInpVrefDiv2 adcSingleInputVrefDiv2\r
+#define adcSingleInpDACOut0 adcSingleInputDACOut0\r
+#define adcSingleInpDACOut1 adcSingleInputDACOut1\r
+#define adcSingleInpATEST adcSingleInputATEST\r
+#define adcSingleInpCh0Ch1 adcSingleInputCh0Ch1\r
+#define adcSingleInpCh2Ch3 adcSingleInputCh2Ch3\r
+#define adcSingleInpCh4Ch5 adcSingleInputCh4Ch5\r
+#define adcSingleInpCh6Ch7 adcSingleInputCh6Ch7\r
+#define adcSingleInpDiff0 adcSingleInputDiff0\r
+/** @endcond */\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRL_POSSEL_MASK )\r
+/** Positive input selection for single and scan coversion. */\r
+typedef enum\r
+{\r
+ adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,\r
+ adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,\r
+ adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,\r
+ adcPosSelAPORT0XCH3 = _ADC_SINGLECTRL_POSSEL_APORT0XCH3,\r
+ adcPosSelAPORT0XCH4 = _ADC_SINGLECTRL_POSSEL_APORT0XCH4,\r
+ adcPosSelAPORT0XCH5 = _ADC_SINGLECTRL_POSSEL_APORT0XCH5,\r
+ adcPosSelAPORT0XCH6 = _ADC_SINGLECTRL_POSSEL_APORT0XCH6,\r
+ adcPosSelAPORT0XCH7 = _ADC_SINGLECTRL_POSSEL_APORT0XCH7,\r
+ adcPosSelAPORT0XCH8 = _ADC_SINGLECTRL_POSSEL_APORT0XCH8,\r
+ adcPosSelAPORT0XCH9 = _ADC_SINGLECTRL_POSSEL_APORT0XCH9,\r
+ adcPosSelAPORT0XCH10 = _ADC_SINGLECTRL_POSSEL_APORT0XCH10,\r
+ adcPosSelAPORT0XCH11 = _ADC_SINGLECTRL_POSSEL_APORT0XCH11,\r
+ adcPosSelAPORT0XCH12 = _ADC_SINGLECTRL_POSSEL_APORT0XCH12,\r
+ adcPosSelAPORT0XCH13 = _ADC_SINGLECTRL_POSSEL_APORT0XCH13,\r
+ adcPosSelAPORT0XCH14 = _ADC_SINGLECTRL_POSSEL_APORT0XCH14,\r
+ adcPosSelAPORT0XCH15 = _ADC_SINGLECTRL_POSSEL_APORT0XCH15,\r
+ adcPosSelAPORT0YCH0 = _ADC_SINGLECTRL_POSSEL_APORT0YCH0,\r
+ adcPosSelAPORT0YCH1 = _ADC_SINGLECTRL_POSSEL_APORT0YCH1,\r
+ adcPosSelAPORT0YCH2 = _ADC_SINGLECTRL_POSSEL_APORT0YCH2,\r
+ adcPosSelAPORT0YCH3 = _ADC_SINGLECTRL_POSSEL_APORT0YCH3,\r
+ adcPosSelAPORT0YCH4 = _ADC_SINGLECTRL_POSSEL_APORT0YCH4,\r
+ adcPosSelAPORT0YCH5 = _ADC_SINGLECTRL_POSSEL_APORT0YCH5,\r
+ adcPosSelAPORT0YCH6 = _ADC_SINGLECTRL_POSSEL_APORT0YCH6,\r
+ adcPosSelAPORT0YCH7 = _ADC_SINGLECTRL_POSSEL_APORT0YCH7,\r
+ adcPosSelAPORT0YCH8 = _ADC_SINGLECTRL_POSSEL_APORT0YCH8,\r
+ adcPosSelAPORT0YCH9 = _ADC_SINGLECTRL_POSSEL_APORT0YCH9,\r
+ adcPosSelAPORT0YCH10 = _ADC_SINGLECTRL_POSSEL_APORT0YCH10,\r
+ adcPosSelAPORT0YCH11 = _ADC_SINGLECTRL_POSSEL_APORT0YCH11,\r
+ adcPosSelAPORT0YCH12 = _ADC_SINGLECTRL_POSSEL_APORT0YCH12,\r
+ adcPosSelAPORT0YCH13 = _ADC_SINGLECTRL_POSSEL_APORT0YCH13,\r
+ adcPosSelAPORT0YCH14 = _ADC_SINGLECTRL_POSSEL_APORT0YCH14,\r
+ adcPosSelAPORT0YCH15 = _ADC_SINGLECTRL_POSSEL_APORT0YCH15,\r
+ adcPosSelAPORT1XCH0 = _ADC_SINGLECTRL_POSSEL_APORT1XCH0,\r
+ adcPosSelAPORT1YCH1 = _ADC_SINGLECTRL_POSSEL_APORT1YCH1,\r
+ adcPosSelAPORT1XCH2 = _ADC_SINGLECTRL_POSSEL_APORT1XCH2,\r
+ adcPosSelAPORT1YCH3 = _ADC_SINGLECTRL_POSSEL_APORT1YCH3,\r
+ adcPosSelAPORT1XCH4 = _ADC_SINGLECTRL_POSSEL_APORT1XCH4,\r
+ adcPosSelAPORT1YCH5 = _ADC_SINGLECTRL_POSSEL_APORT1YCH5,\r
+ adcPosSelAPORT1XCH6 = _ADC_SINGLECTRL_POSSEL_APORT1XCH6,\r
+ adcPosSelAPORT1YCH7 = _ADC_SINGLECTRL_POSSEL_APORT1YCH7,\r
+ adcPosSelAPORT1XCH8 = _ADC_SINGLECTRL_POSSEL_APORT1XCH8,\r
+ adcPosSelAPORT1YCH9 = _ADC_SINGLECTRL_POSSEL_APORT1YCH9,\r
+ adcPosSelAPORT1XCH10 = _ADC_SINGLECTRL_POSSEL_APORT1XCH10,\r
+ adcPosSelAPORT1YCH11 = _ADC_SINGLECTRL_POSSEL_APORT1YCH11,\r
+ adcPosSelAPORT1XCH12 = _ADC_SINGLECTRL_POSSEL_APORT1XCH12,\r
+ adcPosSelAPORT1YCH13 = _ADC_SINGLECTRL_POSSEL_APORT1YCH13,\r
+ adcPosSelAPORT1XCH14 = _ADC_SINGLECTRL_POSSEL_APORT1XCH14,\r
+ adcPosSelAPORT1YCH15 = _ADC_SINGLECTRL_POSSEL_APORT1YCH15,\r
+ adcPosSelAPORT1XCH16 = _ADC_SINGLECTRL_POSSEL_APORT1XCH16,\r
+ adcPosSelAPORT1YCH17 = _ADC_SINGLECTRL_POSSEL_APORT1YCH17,\r
+ adcPosSelAPORT1XCH18 = _ADC_SINGLECTRL_POSSEL_APORT1XCH18,\r
+ adcPosSelAPORT1YCH19 = _ADC_SINGLECTRL_POSSEL_APORT1YCH19,\r
+ adcPosSelAPORT1XCH20 = _ADC_SINGLECTRL_POSSEL_APORT1XCH20,\r
+ adcPosSelAPORT1YCH21 = _ADC_SINGLECTRL_POSSEL_APORT1YCH21,\r
+ adcPosSelAPORT1XCH22 = _ADC_SINGLECTRL_POSSEL_APORT1XCH22,\r
+ adcPosSelAPORT1YCH23 = _ADC_SINGLECTRL_POSSEL_APORT1YCH23,\r
+ adcPosSelAPORT1XCH24 = _ADC_SINGLECTRL_POSSEL_APORT1XCH24,\r
+ adcPosSelAPORT1YCH25 = _ADC_SINGLECTRL_POSSEL_APORT1YCH25,\r
+ adcPosSelAPORT1XCH26 = _ADC_SINGLECTRL_POSSEL_APORT1XCH26,\r
+ adcPosSelAPORT1YCH27 = _ADC_SINGLECTRL_POSSEL_APORT1YCH27,\r
+ adcPosSelAPORT1XCH28 = _ADC_SINGLECTRL_POSSEL_APORT1XCH28,\r
+ adcPosSelAPORT1YCH29 = _ADC_SINGLECTRL_POSSEL_APORT1YCH29,\r
+ adcPosSelAPORT1XCH30 = _ADC_SINGLECTRL_POSSEL_APORT1XCH30,\r
+ adcPosSelAPORT1YCH31 = _ADC_SINGLECTRL_POSSEL_APORT1YCH31,\r
+ adcPosSelAPORT2YCH0 = _ADC_SINGLECTRL_POSSEL_APORT2YCH0,\r
+ adcPosSelAPORT2XCH1 = _ADC_SINGLECTRL_POSSEL_APORT2XCH1,\r
+ adcPosSelAPORT2YCH2 = _ADC_SINGLECTRL_POSSEL_APORT2YCH2,\r
+ adcPosSelAPORT2XCH3 = _ADC_SINGLECTRL_POSSEL_APORT2XCH3,\r
+ adcPosSelAPORT2YCH4 = _ADC_SINGLECTRL_POSSEL_APORT2YCH4,\r
+ adcPosSelAPORT2XCH5 = _ADC_SINGLECTRL_POSSEL_APORT2XCH5,\r
+ adcPosSelAPORT2YCH6 = _ADC_SINGLECTRL_POSSEL_APORT2YCH6,\r
+ adcPosSelAPORT2XCH7 = _ADC_SINGLECTRL_POSSEL_APORT2XCH7,\r
+ adcPosSelAPORT2YCH8 = _ADC_SINGLECTRL_POSSEL_APORT2YCH8,\r
+ adcPosSelAPORT2XCH9 = _ADC_SINGLECTRL_POSSEL_APORT2XCH9,\r
+ adcPosSelAPORT2YCH10 = _ADC_SINGLECTRL_POSSEL_APORT2YCH10,\r
+ adcPosSelAPORT2XCH11 = _ADC_SINGLECTRL_POSSEL_APORT2XCH11,\r
+ adcPosSelAPORT2YCH12 = _ADC_SINGLECTRL_POSSEL_APORT2YCH12,\r
+ adcPosSelAPORT2XCH13 = _ADC_SINGLECTRL_POSSEL_APORT2XCH13,\r
+ adcPosSelAPORT2YCH14 = _ADC_SINGLECTRL_POSSEL_APORT2YCH14,\r
+ adcPosSelAPORT2XCH15 = _ADC_SINGLECTRL_POSSEL_APORT2XCH15,\r
+ adcPosSelAPORT2YCH16 = _ADC_SINGLECTRL_POSSEL_APORT2YCH16,\r
+ adcPosSelAPORT2XCH17 = _ADC_SINGLECTRL_POSSEL_APORT2XCH17,\r
+ adcPosSelAPORT2YCH18 = _ADC_SINGLECTRL_POSSEL_APORT2YCH18,\r
+ adcPosSelAPORT2XCH19 = _ADC_SINGLECTRL_POSSEL_APORT2XCH19,\r
+ adcPosSelAPORT2YCH20 = _ADC_SINGLECTRL_POSSEL_APORT2YCH20,\r
+ adcPosSelAPORT2XCH21 = _ADC_SINGLECTRL_POSSEL_APORT2XCH21,\r
+ adcPosSelAPORT2YCH22 = _ADC_SINGLECTRL_POSSEL_APORT2YCH22,\r
+ adcPosSelAPORT2XCH23 = _ADC_SINGLECTRL_POSSEL_APORT2XCH23,\r
+ adcPosSelAPORT2YCH24 = _ADC_SINGLECTRL_POSSEL_APORT2YCH24,\r
+ adcPosSelAPORT2XCH25 = _ADC_SINGLECTRL_POSSEL_APORT2XCH25,\r
+ adcPosSelAPORT2YCH26 = _ADC_SINGLECTRL_POSSEL_APORT2YCH26,\r
+ adcPosSelAPORT2XCH27 = _ADC_SINGLECTRL_POSSEL_APORT2XCH27,\r
+ adcPosSelAPORT2YCH28 = _ADC_SINGLECTRL_POSSEL_APORT2YCH28,\r
+ adcPosSelAPORT2XCH29 = _ADC_SINGLECTRL_POSSEL_APORT2XCH29,\r
+ adcPosSelAPORT2YCH30 = _ADC_SINGLECTRL_POSSEL_APORT2YCH30,\r
+ adcPosSelAPORT2XCH31 = _ADC_SINGLECTRL_POSSEL_APORT2XCH31,\r
+ adcPosSelAPORT3XCH0 = _ADC_SINGLECTRL_POSSEL_APORT3XCH0,\r
+ adcPosSelAPORT3YCH1 = _ADC_SINGLECTRL_POSSEL_APORT3YCH1,\r
+ adcPosSelAPORT3XCH2 = _ADC_SINGLECTRL_POSSEL_APORT3XCH2,\r
+ adcPosSelAPORT3YCH3 = _ADC_SINGLECTRL_POSSEL_APORT3YCH3,\r
+ adcPosSelAPORT3XCH4 = _ADC_SINGLECTRL_POSSEL_APORT3XCH4,\r
+ adcPosSelAPORT3YCH5 = _ADC_SINGLECTRL_POSSEL_APORT3YCH5,\r
+ adcPosSelAPORT3XCH6 = _ADC_SINGLECTRL_POSSEL_APORT3XCH6,\r
+ adcPosSelAPORT3YCH7 = _ADC_SINGLECTRL_POSSEL_APORT3YCH7,\r
+ adcPosSelAPORT3XCH8 = _ADC_SINGLECTRL_POSSEL_APORT3XCH8,\r
+ adcPosSelAPORT3YCH9 = _ADC_SINGLECTRL_POSSEL_APORT3YCH9,\r
+ adcPosSelAPORT3XCH10 = _ADC_SINGLECTRL_POSSEL_APORT3XCH10,\r
+ adcPosSelAPORT3YCH11 = _ADC_SINGLECTRL_POSSEL_APORT3YCH11,\r
+ adcPosSelAPORT3XCH12 = _ADC_SINGLECTRL_POSSEL_APORT3XCH12,\r
+ adcPosSelAPORT3YCH13 = _ADC_SINGLECTRL_POSSEL_APORT3YCH13,\r
+ adcPosSelAPORT3XCH14 = _ADC_SINGLECTRL_POSSEL_APORT3XCH14,\r
+ adcPosSelAPORT3YCH15 = _ADC_SINGLECTRL_POSSEL_APORT3YCH15,\r
+ adcPosSelAPORT3XCH16 = _ADC_SINGLECTRL_POSSEL_APORT3XCH16,\r
+ adcPosSelAPORT3YCH17 = _ADC_SINGLECTRL_POSSEL_APORT3YCH17,\r
+ adcPosSelAPORT3XCH18 = _ADC_SINGLECTRL_POSSEL_APORT3XCH18,\r
+ adcPosSelAPORT3YCH19 = _ADC_SINGLECTRL_POSSEL_APORT3YCH19,\r
+ adcPosSelAPORT3XCH20 = _ADC_SINGLECTRL_POSSEL_APORT3XCH20,\r
+ adcPosSelAPORT3YCH21 = _ADC_SINGLECTRL_POSSEL_APORT3YCH21,\r
+ adcPosSelAPORT3XCH22 = _ADC_SINGLECTRL_POSSEL_APORT3XCH22,\r
+ adcPosSelAPORT3YCH23 = _ADC_SINGLECTRL_POSSEL_APORT3YCH23,\r
+ adcPosSelAPORT3XCH24 = _ADC_SINGLECTRL_POSSEL_APORT3XCH24,\r
+ adcPosSelAPORT3YCH25 = _ADC_SINGLECTRL_POSSEL_APORT3YCH25,\r
+ adcPosSelAPORT3XCH26 = _ADC_SINGLECTRL_POSSEL_APORT3XCH26,\r
+ adcPosSelAPORT3YCH27 = _ADC_SINGLECTRL_POSSEL_APORT3YCH27,\r
+ adcPosSelAPORT3XCH28 = _ADC_SINGLECTRL_POSSEL_APORT3XCH28,\r
+ adcPosSelAPORT3YCH29 = _ADC_SINGLECTRL_POSSEL_APORT3YCH29,\r
+ adcPosSelAPORT3XCH30 = _ADC_SINGLECTRL_POSSEL_APORT3XCH30,\r
+ adcPosSelAPORT3YCH31 = _ADC_SINGLECTRL_POSSEL_APORT3YCH31,\r
+ adcPosSelAPORT4YCH0 = _ADC_SINGLECTRL_POSSEL_APORT4YCH0,\r
+ adcPosSelAPORT4XCH1 = _ADC_SINGLECTRL_POSSEL_APORT4XCH1,\r
+ adcPosSelAPORT4YCH2 = _ADC_SINGLECTRL_POSSEL_APORT4YCH2,\r
+ adcPosSelAPORT4XCH3 = _ADC_SINGLECTRL_POSSEL_APORT4XCH3,\r
+ adcPosSelAPORT4YCH4 = _ADC_SINGLECTRL_POSSEL_APORT4YCH4,\r
+ adcPosSelAPORT4XCH5 = _ADC_SINGLECTRL_POSSEL_APORT4XCH5,\r
+ adcPosSelAPORT4YCH6 = _ADC_SINGLECTRL_POSSEL_APORT4YCH6,\r
+ adcPosSelAPORT4XCH7 = _ADC_SINGLECTRL_POSSEL_APORT4XCH7,\r
+ adcPosSelAPORT4YCH8 = _ADC_SINGLECTRL_POSSEL_APORT4YCH8,\r
+ adcPosSelAPORT4XCH9 = _ADC_SINGLECTRL_POSSEL_APORT4XCH9,\r
+ adcPosSelAPORT4YCH10 = _ADC_SINGLECTRL_POSSEL_APORT4YCH10,\r
+ adcPosSelAPORT4XCH11 = _ADC_SINGLECTRL_POSSEL_APORT4XCH11,\r
+ adcPosSelAPORT4YCH12 = _ADC_SINGLECTRL_POSSEL_APORT4YCH12,\r
+ adcPosSelAPORT4XCH13 = _ADC_SINGLECTRL_POSSEL_APORT4XCH13,\r
+ adcPosSelAPORT4YCH14 = _ADC_SINGLECTRL_POSSEL_APORT4YCH14,\r
+ adcPosSelAPORT4XCH15 = _ADC_SINGLECTRL_POSSEL_APORT4XCH15,\r
+ adcPosSelAPORT4YCH16 = _ADC_SINGLECTRL_POSSEL_APORT4YCH16,\r
+ adcPosSelAPORT4XCH17 = _ADC_SINGLECTRL_POSSEL_APORT4XCH17,\r
+ adcPosSelAPORT4YCH18 = _ADC_SINGLECTRL_POSSEL_APORT4YCH18,\r
+ adcPosSelAPORT4XCH19 = _ADC_SINGLECTRL_POSSEL_APORT4XCH19,\r
+ adcPosSelAPORT4YCH20 = _ADC_SINGLECTRL_POSSEL_APORT4YCH20,\r
+ adcPosSelAPORT4XCH21 = _ADC_SINGLECTRL_POSSEL_APORT4XCH21,\r
+ adcPosSelAPORT4YCH22 = _ADC_SINGLECTRL_POSSEL_APORT4YCH22,\r
+ adcPosSelAPORT4XCH23 = _ADC_SINGLECTRL_POSSEL_APORT4XCH23,\r
+ adcPosSelAPORT4YCH24 = _ADC_SINGLECTRL_POSSEL_APORT4YCH24,\r
+ adcPosSelAPORT4XCH25 = _ADC_SINGLECTRL_POSSEL_APORT4XCH25,\r
+ adcPosSelAPORT4YCH26 = _ADC_SINGLECTRL_POSSEL_APORT4YCH26,\r
+ adcPosSelAPORT4XCH27 = _ADC_SINGLECTRL_POSSEL_APORT4XCH27,\r
+ adcPosSelAPORT4YCH28 = _ADC_SINGLECTRL_POSSEL_APORT4YCH28,\r
+ adcPosSelAPORT4XCH29 = _ADC_SINGLECTRL_POSSEL_APORT4XCH29,\r
+ adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,\r
+ adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,\r
+ adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD,\r
+ adcPosSelBU = _ADC_SINGLECTRL_POSSEL_BU,\r
+ adcPosSelAREG = _ADC_SINGLECTRL_POSSEL_AREG,\r
+ adcPosSelVREGOUTPA = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,\r
+ adcPosSelPDBU = _ADC_SINGLECTRL_POSSEL_PDBU,\r
+ adcPosSelIO0 = _ADC_SINGLECTRL_POSSEL_IO0,\r
+ adcPosSelIO1 = _ADC_SINGLECTRL_POSSEL_IO1,\r
+ adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP,\r
+ adcPosSelSP0 = _ADC_SINGLECTRL_POSSEL_SP0,\r
+ adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP,\r
+ adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0,\r
+ adcPosSelTESTP = _ADC_SINGLECTRL_POSSEL_TESTP,\r
+ adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1,\r
+ adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2,\r
+ adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1,\r
+ adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB,\r
+ adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT,\r
+ adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS\r
+} ADC_PosSel_TypeDef;\r
+#endif\r
+\r
+\r
+#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )\r
+/** Negative input selection for single and scan coversion. */\r
+typedef enum\r
+{\r
+ adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,\r
+ adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,\r
+ adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,\r
+ adcNegSelAPORT0XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH3,\r
+ adcNegSelAPORT0XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH4,\r
+ adcNegSelAPORT0XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH5,\r
+ adcNegSelAPORT0XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH6,\r
+ adcNegSelAPORT0XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH7,\r
+ adcNegSelAPORT0XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH8,\r
+ adcNegSelAPORT0XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH9,\r
+ adcNegSelAPORT0XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH10,\r
+ adcNegSelAPORT0XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH11,\r
+ adcNegSelAPORT0XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH12,\r
+ adcNegSelAPORT0XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH13,\r
+ adcNegSelAPORT0XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH14,\r
+ adcNegSelAPORT0XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH15,\r
+ adcNegSelAPORT0YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH0,\r
+ adcNegSelAPORT0YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH1,\r
+ adcNegSelAPORT0YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH2,\r
+ adcNegSelAPORT0YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH3,\r
+ adcNegSelAPORT0YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH4,\r
+ adcNegSelAPORT0YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH5,\r
+ adcNegSelAPORT0YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH6,\r
+ adcNegSelAPORT0YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH7,\r
+ adcNegSelAPORT0YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH8,\r
+ adcNegSelAPORT0YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH9,\r
+ adcNegSelAPORT0YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH10,\r
+ adcNegSelAPORT0YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH11,\r
+ adcNegSelAPORT0YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH12,\r
+ adcNegSelAPORT0YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH13,\r
+ adcNegSelAPORT0YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH14,\r
+ adcNegSelAPORT0YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT0YCH15,\r
+ adcNegSelAPORT1XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH0,\r
+ adcNegSelAPORT1YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH1,\r
+ adcNegSelAPORT1XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH2,\r
+ adcNegSelAPORT1YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH3,\r
+ adcNegSelAPORT1XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH4,\r
+ adcNegSelAPORT1YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH5,\r
+ adcNegSelAPORT1XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH6,\r
+ adcNegSelAPORT1YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH7,\r
+ adcNegSelAPORT1XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH8,\r
+ adcNegSelAPORT1YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH9,\r
+ adcNegSelAPORT1XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH10,\r
+ adcNegSelAPORT1YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH11,\r
+ adcNegSelAPORT1XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH12,\r
+ adcNegSelAPORT1YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH13,\r
+ adcNegSelAPORT1XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH14,\r
+ adcNegSelAPORT1YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH15,\r
+ adcNegSelAPORT1XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH16,\r
+ adcNegSelAPORT1YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH17,\r
+ adcNegSelAPORT1XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH18,\r
+ adcNegSelAPORT1YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH19,\r
+ adcNegSelAPORT1XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH20,\r
+ adcNegSelAPORT1YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH21,\r
+ adcNegSelAPORT1XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH22,\r
+ adcNegSelAPORT1YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH23,\r
+ adcNegSelAPORT1XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH24,\r
+ adcNegSelAPORT1YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH25,\r
+ adcNegSelAPORT1XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH26,\r
+ adcNegSelAPORT1YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH27,\r
+ adcNegSelAPORT1XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH28,\r
+ adcNegSelAPORT1YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH29,\r
+ adcNegSelAPORT1XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT1XCH30,\r
+ adcNegSelAPORT1YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT1YCH31,\r
+ adcNegSelAPORT2YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH0,\r
+ adcNegSelAPORT2XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH1,\r
+ adcNegSelAPORT2YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH2,\r
+ adcNegSelAPORT2XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH3,\r
+ adcNegSelAPORT2YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH4,\r
+ adcNegSelAPORT2XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH5,\r
+ adcNegSelAPORT2YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH6,\r
+ adcNegSelAPORT2XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH7,\r
+ adcNegSelAPORT2YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH8,\r
+ adcNegSelAPORT2XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH9,\r
+ adcNegSelAPORT2YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH10,\r
+ adcNegSelAPORT2XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH11,\r
+ adcNegSelAPORT2YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH12,\r
+ adcNegSelAPORT2XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH13,\r
+ adcNegSelAPORT2YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH14,\r
+ adcNegSelAPORT2XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH15,\r
+ adcNegSelAPORT2YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH16,\r
+ adcNegSelAPORT2XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH17,\r
+ adcNegSelAPORT2YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH18,\r
+ adcNegSelAPORT2XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH19,\r
+ adcNegSelAPORT2YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH20,\r
+ adcNegSelAPORT2XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH21,\r
+ adcNegSelAPORT2YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH22,\r
+ adcNegSelAPORT2XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH23,\r
+ adcNegSelAPORT2YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH24,\r
+ adcNegSelAPORT2XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH25,\r
+ adcNegSelAPORT2YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH26,\r
+ adcNegSelAPORT2XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH27,\r
+ adcNegSelAPORT2YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH28,\r
+ adcNegSelAPORT2XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH29,\r
+ adcNegSelAPORT2YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT2YCH30,\r
+ adcNegSelAPORT2XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT2XCH31,\r
+ adcNegSelAPORT3XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH0,\r
+ adcNegSelAPORT3YCH1 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH1,\r
+ adcNegSelAPORT3XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH2,\r
+ adcNegSelAPORT3YCH3 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH3,\r
+ adcNegSelAPORT3XCH4 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH4,\r
+ adcNegSelAPORT3YCH5 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH5,\r
+ adcNegSelAPORT3XCH6 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH6,\r
+ adcNegSelAPORT3YCH7 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH7,\r
+ adcNegSelAPORT3XCH8 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH8,\r
+ adcNegSelAPORT3YCH9 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH9,\r
+ adcNegSelAPORT3XCH10 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH10,\r
+ adcNegSelAPORT3YCH11 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH11,\r
+ adcNegSelAPORT3XCH12 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH12,\r
+ adcNegSelAPORT3YCH13 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH13,\r
+ adcNegSelAPORT3XCH14 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH14,\r
+ adcNegSelAPORT3YCH15 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH15,\r
+ adcNegSelAPORT3XCH16 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH16,\r
+ adcNegSelAPORT3YCH17 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH17,\r
+ adcNegSelAPORT3XCH18 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH18,\r
+ adcNegSelAPORT3YCH19 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH19,\r
+ adcNegSelAPORT3XCH20 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH20,\r
+ adcNegSelAPORT3YCH21 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH21,\r
+ adcNegSelAPORT3XCH22 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH22,\r
+ adcNegSelAPORT3YCH23 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH23,\r
+ adcNegSelAPORT3XCH24 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH24,\r
+ adcNegSelAPORT3YCH25 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH25,\r
+ adcNegSelAPORT3XCH26 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH26,\r
+ adcNegSelAPORT3YCH27 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH27,\r
+ adcNegSelAPORT3XCH28 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH28,\r
+ adcNegSelAPORT3YCH29 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH29,\r
+ adcNegSelAPORT3XCH30 = _ADC_SINGLECTRL_NEGSEL_APORT3XCH30,\r
+ adcNegSelAPORT3YCH31 = _ADC_SINGLECTRL_NEGSEL_APORT3YCH31,\r
+ adcNegSelAPORT4YCH0 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH0,\r
+ adcNegSelAPORT4XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH1,\r
+ adcNegSelAPORT4YCH2 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH2,\r
+ adcNegSelAPORT4XCH3 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH3,\r
+ adcNegSelAPORT4YCH4 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH4,\r
+ adcNegSelAPORT4XCH5 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH5,\r
+ adcNegSelAPORT4YCH6 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH6,\r
+ adcNegSelAPORT4XCH7 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH7,\r
+ adcNegSelAPORT4YCH8 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH8,\r
+ adcNegSelAPORT4XCH9 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH9,\r
+ adcNegSelAPORT4YCH10 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH10,\r
+ adcNegSelAPORT4XCH11 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH11,\r
+ adcNegSelAPORT4YCH12 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH12,\r
+ adcNegSelAPORT4XCH13 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH13,\r
+ adcNegSelAPORT4YCH14 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH14,\r
+ adcNegSelAPORT4XCH15 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH15,\r
+ adcNegSelAPORT4YCH16 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH16,\r
+ adcNegSelAPORT4XCH17 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH17,\r
+ adcNegSelAPORT4YCH18 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH18,\r
+ adcNegSelAPORT4XCH19 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH19,\r
+ adcNegSelAPORT4YCH20 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH20,\r
+ adcNegSelAPORT4XCH21 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH21,\r
+ adcNegSelAPORT4YCH22 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH22,\r
+ adcNegSelAPORT4XCH23 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH23,\r
+ adcNegSelAPORT4YCH24 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH24,\r
+ adcNegSelAPORT4XCH25 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH25,\r
+ adcNegSelAPORT4YCH26 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH26,\r
+ adcNegSelAPORT4XCH27 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH27,\r
+ adcNegSelAPORT4YCH28 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH28,\r
+ adcNegSelAPORT4XCH29 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH29,\r
+ adcNegSelAPORT4YCH30 = _ADC_SINGLECTRL_NEGSEL_APORT4YCH30,\r
+ adcNegSelAPORT4XCH31 = _ADC_SINGLECTRL_NEGSEL_APORT4XCH31,\r
+ adcNegSelTESTN = _ADC_SINGLECTRL_NEGSEL_TESTN,\r
+ adcNegSelDEFAULT = _ADC_SINGLECTRL_NEGSEL_DEFAULT,\r
+ adcNegSelVSS = _ADC_SINGLECTRL_NEGSEL_VSS\r
+} ADC_NegSel_TypeDef;\r
+#endif\r
+\r
+\r
+#if defined( _ADC_SCANINPUTSEL_MASK )\r
+ /* ADC scan input groups */\r
+typedef enum\r
+{\r
+ adcScanInputGroup0 = 0,\r
+ adcScanInputGroup1 = 1,\r
+ adcScanInputGroup2 = 2,\r
+ adcScanInputGroup3 = 3,\r
+} ADC_ScanInputGroup_TypeDef;\r
+\r
+ /* ADC scan alternative negative inputs */\r
+typedef enum\r
+{\r
+ adcScanNegInput1 = 1,\r
+ adcScanNegInput3 = 3,\r
+ adcScanNegInput5 = 5,\r
+ adcScanNegInput7 = 7,\r
+ adcScanNegInput8 = 8,\r
+ adcScanNegInput10 = 10,\r
+ adcScanNegInput12 = 12,\r
+ adcScanNegInput14 = 14,\r
+ adcScanNegInputDefault = 0xFF,\r
+} ADC_ScanNegInput_TypeDef;\r
+#endif\r
+\r
\r
/** ADC Start command. */\r
typedef enum\r
/** ADC shutdown after each conversion. */\r
adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL,\r
\r
+#if defined( _ADC_CTRL_WARMUPMODE_FASTBG )\r
/** Do not warm-up bandgap references. */\r
adcWarmupFastBG = _ADC_CTRL_WARMUPMODE_FASTBG,\r
+#endif\r
\r
+#if defined( _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM )\r
/** Reference selected for scan mode kept warm.*/\r
adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM,\r
+#endif\r
+\r
+#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY )\r
+ /** ADC is kept in standby mode between conversion. 1us warmup time needed\r
+ before next conversion. */\r
+ adcWarmupKeepInStandby = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY,\r
+#endif\r
+\r
+#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC )\r
+ /** ADC is kept in slow acquisition mode between conversions. 1us warmup\r
+ time needed before next conversion. */\r
+ adcWarmupKeepInSlowAcq = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC,\r
+#endif\r
+\r
+ /** ADC and reference selected for scan mode kept warmup, allowing\r
+ continuous conversion. */\r
+ adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,\r
\r
- /** ADC and reference selected for scan mode kept warm.*/\r
- adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM\r
} ADC_Warmup_TypeDef;\r
\r
\r
+#if defined( _ADC_CTRL_ADCCLKMODE_MASK )\r
+ /** ADC EM2 clock configuration */\r
+typedef enum\r
+{\r
+ adcEm2Disabled = 0,\r
+ adcEm2ClockOnDemand = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ASNEEDED,\r
+ adcEm2ClockAlwaysOn = _ADC_CTRL_ADCCLKMODE_ASYNC | _ADC_CTRL_ASYNCCLKEN_ALWAYSON,\r
+} ADC_EM2ClockConfig_TypeDef;\r
+#endif\r
+\r
+\r
/*******************************************************************************\r
******************************* STRUCTS ***********************************\r
******************************************************************************/\r
* Oversampling rate select. In order to have any effect, oversampling must\r
* be enabled for single/scan mode.\r
*/\r
- ADC_OvsRateSel_TypeDef ovsRateSel;\r
+ ADC_OvsRateSel_TypeDef ovsRateSel;\r
\r
+#if defined( _ADC_CTRL_LPFMODE_MASK )\r
/** Lowpass or decoupling capacitor filter to use. */\r
- ADC_LPFilter_TypeDef lpfMode;\r
+ ADC_LPFilter_TypeDef lpfMode;\r
+#endif\r
\r
/** Warm-up mode to use for ADC. */\r
- ADC_Warmup_TypeDef warmUpMode;\r
+ ADC_Warmup_TypeDef warmUpMode;\r
\r
/**\r
* Timebase used for ADC warm up. Select N to give (N+1)HFPERCLK cycles.\r
* is at least 1 us. See ADC_TimebaseCalc() for a way to obtain\r
* a suggested timebase of at least 1 us.\r
*/\r
- uint8_t timebase;\r
+ uint8_t timebase;\r
\r
/** Clock division factor N, ADC clock = HFPERCLK / (N + 1). */\r
- uint8_t prescale;\r
+ uint8_t prescale;\r
\r
/** Enable/disable conversion tailgating. */\r
- bool tailgate;\r
+ bool tailgate;\r
+\r
+ /** ADC EM2 clock configuration */\r
+#if defined( _ADC_CTRL_ADCCLKMODE_MASK )\r
+ ADC_EM2ClockConfig_TypeDef em2ClockConfig;\r
+#endif\r
} ADC_Init_TypeDef;\r
\r
+\r
/** Default config for ADC init structure. */\r
-#define ADC_INIT_DEFAULT \\r
- { adcOvsRateSel2, /* 2x oversampling (if enabled). */ \\r
- adcLPFilterBypass, /* No input filter selected. */ \\r
- adcWarmupNormal, /* ADC shutdown after each conversion. */ \\r
- _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \\r
- _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \\r
- false /* Do not use tailgate. */ \\r
- }\r
+#if defined( _ADC_CTRL_LPFMODE_MASK ) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))\r
+#define ADC_INIT_DEFAULT \\r
+{ \\r
+ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \\r
+ adcLPFilterBypass, /* No input filter selected. */ \\r
+ adcWarmupNormal, /* ADC shutdown after each conversion. */ \\r
+ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \\r
+ _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \\r
+ false /* Do not use tailgate. */ \\r
+}\r
+#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))\r
+#define ADC_INIT_DEFAULT \\r
+{ \\r
+ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \\r
+ adcWarmupNormal, /* ADC shutdown after each conversion. */ \\r
+ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \\r
+ _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \\r
+ false /* Do not use tailgate. */ \\r
+}\r
+#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && defined( _ADC_CTRL_ADCCLKMODE_MASK )\r
+#define ADC_INIT_DEFAULT \\r
+{ \\r
+ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \\r
+ adcWarmupNormal, /* ADC shutdown after each conversion. */ \\r
+ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \\r
+ _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \\r
+ false, /* Do not use tailgate. */ \\r
+ adcEm2Disabled /* ADC disabled in EM2 */ \\r
+}\r
+#endif\r
+\r
+\r
+/** Scan input configuration */\r
+typedef struct\r
+{\r
+ /** Input range select to be applied to ADC_SCANCHCONF. */\r
+ int32_t scanInputSel;\r
+\r
+ /** Input enable mask */\r
+ uint32_t scanInputEn;\r
+\r
+ /** Alternative negative input */\r
+ uint32_t scanNegSel;\r
+} ADC_InitScanInput_TypeDef;\r
\r
\r
/** Scan sequence init structure. */\r
/** Sample resolution. */\r
ADC_Res_TypeDef resolution;\r
\r
+#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )\r
/**\r
- * Input scan selection. If single ended (@p diff is false), use logical\r
+ * Scan input selection. If single ended (@p diff is false), use logical\r
* combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input\r
* (@p diff is true), use logical combination of ADC_SCANCTRL_INPUTMASK_CHxCHy\r
* defines. (Notice underscore prefix for defines used.)\r
*/\r
uint32_t input;\r
+#endif\r
+\r
+#if defined( _ADC_SCANINPUTSEL_MASK )\r
+ /**\r
+ * Scan input configuration. Use ADC_ScanSingleEndedInit() or ADC_ScanDifferentialInit()\r
+ * to write this struct. Note that the diff variable is included in ADC_InitScanInput_TypeDef.\r
+ */\r
+ ADC_InitScanInput_TypeDef scanInputConfig;\r
+#endif\r
\r
/** Select if single ended or differential input. */\r
bool diff;\r
\r
/** Select if continuous conversion until explicit stop. */\r
bool rep;\r
+\r
+ /** When true, DMA is available in EM2 for scan conversion */\r
+#if defined( _ADC_CTRL_SCANDMAWU_MASK )\r
+ bool scanDmaEm2Wu;\r
+#endif\r
+\r
+#if defined( _ADC_SCANCTRLX_FIFOOFACT_MASK )\r
+ /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.\r
+ The SINGLEOF IRQ is triggered in both cases. */\r
+ bool fifoOverwrite;\r
+#endif\r
} ADC_InitScan_TypeDef;\r
\r
/** Default config for ADC scan init structure. */\r
-#define ADC_INITSCAN_DEFAULT \\r
- { adcPRSSELCh0, /* PRS ch0 (if enabled). */ \\r
- adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \\r
- adcRef1V25, /* 1.25V internal reference. */ \\r
- adcRes12Bit, /* 12 bit resolution. */ \\r
- 0, /* No input selected. */ \\r
- false, /* Single ended input. */ \\r
- false, /* PRS disabled. */ \\r
- false, /* Right adjust. */ \\r
- false /* Deactivate conversion after one scan sequence. */ \\r
- }\r
+#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )\r
+#define ADC_INITSCAN_DEFAULT \\r
+{ \\r
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \\r
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \\r
+ adcRef1V25, /* 1.25V internal reference. */ \\r
+ adcRes12Bit, /* 12 bit resolution. */ \\r
+ 0, /* No input selected. */ \\r
+ false, /* Single-ended input. */ \\r
+ false, /* PRS disabled. */ \\r
+ false, /* Right adjust. */ \\r
+ false, /* Deactivate conversion after one scan sequence. */ \\r
+}\r
+#endif\r
+\r
+#if defined( _ADC_SCANINPUTSEL_MASK )\r
+#define ADC_INITSCAN_DEFAULT \\r
+{ \\r
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \\r
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \\r
+ adcRef1V25, /* 1.25V internal reference. */ \\r
+ adcRes12Bit, /* 12 bit resolution. */ \\r
+ 0, /* Default ADC inputs */ \\r
+ 0, /* Default input mask (all off) */ \\r
+ _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */ \\r
+ false, /* Single-ended input. */ \\r
+ false, /* PRS disabled. */ \\r
+ false, /* Right adjust. */ \\r
+ false, /* Deactivate conversion after one scan sequence. */ \\r
+ false, /* No EM2 DMA wakeup from scan FIFO DVL */ \\r
+ false /* Discard new data on full FIFO. */ \\r
+}\r
+#endif\r
\r
\r
/** Single conversion init structure. */\r
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable\r
* is enabled.\r
*/\r
- ADC_PRSSEL_TypeDef prsSel;\r
+ ADC_PRSSEL_TypeDef prsSel;\r
\r
/** Acquisition time (in ADC clock cycles). */\r
- ADC_AcqTime_TypeDef acqTime;\r
+ ADC_AcqTime_TypeDef acqTime;\r
\r
/**\r
* Sample reference selection. Notice that for external references, the\r
* ADC calibration register must be set explicitly.\r
*/\r
- ADC_Ref_TypeDef reference;\r
+ ADC_Ref_TypeDef reference;\r
\r
/** Sample resolution. */\r
- ADC_Res_TypeDef resolution;\r
+ ADC_Res_TypeDef resolution;\r
\r
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )\r
/**\r
* Sample input selection, use single ended or differential input according\r
* to setting of @p diff.\r
*/\r
- ADC_SingleInput_TypeDef input;\r
+ ADC_SingleInput_TypeDef input;\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRL_POSSEL_MASK )\r
+ /** Select positive input for for single channel conversion mode. */\r
+ ADC_PosSel_TypeDef posSel;\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )\r
+ /** Select negative input for single channel conversion mode. Negative input is grounded\r
+ for single ended (non-differential) converison. */\r
+ ADC_NegSel_TypeDef negSel;\r
+#endif\r
\r
/** Select if single ended or differential input. */\r
- bool diff;\r
+ bool diff;\r
\r
/** Peripheral reflex system trigger enable. */\r
- bool prsEnable;\r
+ bool prsEnable;\r
\r
/** Select if left adjustment should be done. */\r
- bool leftAdjust;\r
+ bool leftAdjust;\r
\r
/** Select if continuous conversion until explicit stop. */\r
- bool rep;\r
+ bool rep;\r
+\r
+#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )\r
+ /** When true, DMA is available in EM2 for single conversion */\r
+ bool singleDmaEm2Wu;\r
+#endif\r
+\r
+#if defined( _ADC_SINGLECTRLX_FIFOOFACT_MASK )\r
+ /** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.\r
+ The SCANOF IRQ is triggered in both cases. */\r
+ bool fifoOverwrite;\r
+#endif\r
} ADC_InitSingle_TypeDef;\r
\r
/** Default config for ADC single conversion init structure. */\r
-#define ADC_INITSINGLE_DEFAULT \\r
- { adcPRSSELCh0, /* PRS ch0 (if enabled). */ \\r
- adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \\r
- adcRef1V25, /* 1.25V internal reference. */ \\r
- adcRes12Bit, /* 12 bit resolution. */ \\r
- adcSingleInpCh0, /* CH0 input selected. */ \\r
- false, /* Single ended input. */ \\r
- false, /* PRS disabled. */ \\r
- false, /* Right adjust. */ \\r
- false /* Deactivate conversion after one scan sequence. */ \\r
- }\r
-\r
+#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )\r
+#define ADC_INITSINGLE_DEFAULT \\r
+{ \\r
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \\r
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \\r
+ adcRef1V25, /* 1.25V internal reference. */ \\r
+ adcRes12Bit, /* 12 bit resolution. */ \\r
+ adcSingleInpCh0, /* CH0 input selected. */ \\r
+ false, /* Single ended input. */ \\r
+ false, /* PRS disabled. */ \\r
+ false, /* Right adjust. */ \\r
+ false /* Deactivate conversion after one scan sequence. */ \\r
+}\r
+#else\r
+#define ADC_INITSINGLE_DEFAULT \\r
+{ \\r
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \\r
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \\r
+ adcRef1V25, /* 1.25V internal reference. */ \\r
+ adcRes12Bit, /* 12 bit resolution. */ \\r
+ adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \\r
+ adcNegSelAPORT0XCH1, /* Select node BUS0XCH1 as negSel */ \\r
+ false, /* Single ended input. */ \\r
+ false, /* PRS disabled. */ \\r
+ false, /* Right adjust. */ \\r
+ false, /* Deactivate conversion after one scan sequence. */ \\r
+ false, /* No EM2 DMA wakeup from single FIFO DVL */ \\r
+ false /* Discard new data on full FIFO. */ \\r
+}\r
+#endif\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
* Get single conversion result.\r
*\r
* @note\r
- * Do only use if single conversion data valid.\r
+ * Check data valid flag before calling this function.\r
*\r
* @param[in] adc\r
* Pointer to ADC peripheral register block.\r
*\r
* @return\r
- *\r
+ * Single conversion data.\r
******************************************************************************/\r
__STATIC_INLINE uint32_t ADC_DataSingleGet(ADC_TypeDef *adc)\r
{\r
- return(adc->SINGLEDATA);\r
+ return adc->SINGLEDATA;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Peek single conversion result.\r
+ *\r
+ * @note\r
+ * Check data valid flag before calling this function.\r
+ *\r
+ * @param[in] adc\r
+ * Pointer to ADC peripheral register block.\r
+ *\r
+ * @return\r
+ * Single conversion data.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t ADC_DataSinglePeek(ADC_TypeDef *adc)\r
+{\r
+ return adc->SINGLEDATAP;\r
}\r
\r
\r
* Get scan result.\r
*\r
* @note\r
- * Do only use if scan data valid.\r
+ * Check data valid flag before calling this function.\r
*\r
* @param[in] adc\r
* Pointer to ADC peripheral register block.\r
+ *\r
+ * @return\r
+ * Scan conversion data.\r
******************************************************************************/\r
__STATIC_INLINE uint32_t ADC_DataScanGet(ADC_TypeDef *adc)\r
{\r
- return(adc->SCANDATA);\r
+ return adc->SCANDATA;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Peek scan result.\r
+ *\r
+ * @note\r
+ * Check data valid flag before calling this function.\r
+ *\r
+ * @param[in] adc\r
+ * Pointer to ADC peripheral register block.\r
+ *\r
+ * @return\r
+ * Scan conversion data.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t ADC_DataScanPeek(ADC_TypeDef *adc)\r
+{\r
+ return adc->SCANDATAP;\r
}\r
\r
\r
+#if defined( _ADC_SCANDATAX_MASK )\r
+uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);\r
+#endif\r
+\r
void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init);\r
+void ADC_Reset(ADC_TypeDef *adc);\r
void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init);\r
+\r
+#if defined( _ADC_SCANINPUTSEL_MASK )\r
+void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit);\r
+uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,\r
+ ADC_ScanInputGroup_TypeDef inputGroup,\r
+ ADC_PosSel_TypeDef singleEndedSel);\r
+uint32_t ADC_ScanDifferentialInputAdd(ADC_InitScan_TypeDef *scanInit,\r
+ ADC_ScanInputGroup_TypeDef inputGroup,\r
+ ADC_PosSel_TypeDef posSel,\r
+ ADC_ScanNegInput_TypeDef adcScanNegInput);\r
+#endif\r
+\r
void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init);\r
+uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);\r
+uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);\r
+\r
\r
/***************************************************************************//**\r
* @brief\r
******************************************************************************/\r
__STATIC_INLINE void ADC_IntDisable(ADC_TypeDef *adc, uint32_t flags)\r
{\r
- adc->IEN &= ~(flags);\r
+ adc->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t ADC_IntGet(ADC_TypeDef *adc)\r
{\r
- return(adc->IF);\r
+ return adc->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending ADC interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @param[in] adc\r
+ * Pointer to ADC peripheral register block.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled ADC interrupt sources.\r
+ * The return value is the bitwise AND combination of\r
+ * - the OR combination of enabled interrupt sources in ADCx_IEN_nnn\r
+ * register (ADCx_IEN_nnn) and\r
+ * - the OR combination of valid interrupt flags of the ADC module\r
+ * (ADCx_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t ADC_IntGetEnabled(ADC_TypeDef *adc)\r
+{\r
+ uint32_t ien;\r
+\r
+ /* Store ADCx->IEN in temporary variable in order to define explicit order\r
+ * of volatile accesses. */\r
+ ien = adc->IEN;\r
+\r
+ /* Bitwise AND of pending and enabled interrupts */\r
+ return adc->IF & ien;\r
}\r
\r
\r
adc->IFS = flags;\r
}\r
\r
-uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);\r
-\r
\r
/***************************************************************************//**\r
* @brief\r
adc->CMD = (uint32_t)cmd;\r
}\r
\r
-void ADC_Reset(ADC_TypeDef *adc);\r
-uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);\r
\r
/** @} (end addtogroup ADC) */\r
/** @} (end addtogroup EM_Library) */\r
#endif\r
\r
#endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_ADC_H_ */\r
+#endif /* __SILICON_LABS_EM_ADC_H__ */\r
/***************************************************************************//**\r
* @file em_aes.h\r
- * @brief Advanced encryption standard (AES) accelerator peripheral API for\r
- * EFM32.\r
- * @version 4.0.0\r
+ * @brief Advanced encryption standard (AES) accelerator peripheral API.\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_AES_H_\r
-#define __SILICON_LABS_EM_AES_H_\r
+#ifndef __SILICON_LABS_EM_AES_H__\r
+#define __SILICON_LABS_EM_AES_H__\r
\r
#include "em_device.h"\r
#if defined(AES_COUNT) && (AES_COUNT > 0)\r
******************************************************************************/\r
__STATIC_INLINE uint32_t AES_IntGet(void)\r
{\r
- return(AES->IF);\r
+ return AES->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending AES interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled AES interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in AES_IEN and\r
+ * - the pending interrupt flags AES_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t AES_IntGetEnabled(void)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = AES->IEN;\r
+ return AES->IF & ien;\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(AES_COUNT) && (AES_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_AES_H_ */\r
+#endif /* __SILICON_LABS_EM_AES_H__ */\r
\r
\r
/***************************************************************************//**\r
* @file em_assert.h\r
- * @brief EFM32 peripheral API "assert" implementation.\r
- * @version 4.0.0\r
+ * @brief Emlib peripheral API "assert" implementation.\r
+ * @version 4.2.1\r
*\r
* @details\r
- * By default, EFM32 library assert usage is not included in order to reduce\r
- * footprint and processing overhead. Further, EFM32 assert usage is decoupled\r
+ * By default, emlib library assert usage is not included in order to reduce\r
+ * footprint and processing overhead. Further, emlib assert usage is decoupled\r
* from ISO C assert handling (NDEBUG usage), to allow a user to use ISO C\r
- * assert without including EFM32 assert statements.\r
+ * assert without including emlib assert statements.\r
*\r
- * Below are available defines for controlling EFM32 assert inclusion. The defines\r
+ * Below are available defines for controlling emlib assert inclusion. The defines\r
* are typically defined for a project to be used by the preprocessor.\r
*\r
- * @li If DEBUG_EFM is defined, the internal EFM32 library assert handling will\r
+ * @li If DEBUG_EFM is defined, the internal emlib library assert handling will\r
* be used, which may be a quite rudimentary implementation.\r
*\r
- * @li If DEBUG_EFM_USER is defined instead, the user must provide its own EFM32\r
+ * @li If DEBUG_EFM_USER is defined instead, the user must provide their own\r
* assert handling routine (assertEFM()).\r
*\r
- * As indicated above, if none of the above defines are used, EFM32 assert\r
+ * As indicated above, if none of the above defines are used, emlib assert\r
* statements are not compiled.\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_ASSERT_H_\r
-#define __SILICON_LABS_EM_ASSERT_H_\r
+#ifndef __SILICON_LABS_EM_ASSERT_H__\r
+#define __SILICON_LABS_EM_ASSERT_H__\r
\r
#ifdef __cplusplus\r
extern "C" {\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_ASSERT_H_ */\r
+#endif /* __SILICON_LABS_EM_ASSERT_H__ */\r
/***************************************************************************//**\r
* @file em_bitband.h\r
* @brief Bitband Peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
+#ifndef __SILICON_LABS_EM_BITBAND_H__\r
+#define __SILICON_LABS_EM_BITBAND_H__\r
\r
-#ifndef __SILICON_LABS_EM_BITBAND_H_\r
-#define __SILICON_LABS_EM_BITBAND_H_\r
+#include "em_bus.h"\r
\r
-#include "em_device.h"\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
/***************************************************************************//**\r
* @addtogroup BITBAND\r
- * @brief BITBAND Peripheral API\r
+ * @brief BITBAND Peripheral API (deprecated - use em_bus.h)\r
* @{\r
******************************************************************************/\r
\r
*\r
* @param[in] val Value to set bit to, 0 or 1.\r
******************************************************************************/\r
-__STATIC_INLINE void BITBAND_Peripheral(volatile uint32_t *addr,\r
- uint32_t bit,\r
- uint32_t val)\r
-{\r
-#if defined(BITBAND_PER_BASE)\r
- uint32_t tmp =\r
- BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);\r
-\r
- *((volatile uint32_t *)tmp) = (uint32_t)val;\r
-#else\r
- uint32_t tmp = *addr;\r
- /* Make sure val is not more than 1, because we only want to set one bit. */\r
- val &= 0x1;\r
- *addr = (tmp & ~(1 << bit)) | (val << bit);\r
-#endif /* defined(BITBAND_PER_BASE) */\r
-}\r
+#define BITBAND_Peripheral(addr, bit, val) BUS_RegBitWrite(addr, bit, val)\r
\r
\r
/***************************************************************************//**\r
*\r
* @return Value of the requested bit.\r
******************************************************************************/\r
-__STATIC_INLINE uint32_t BITBAND_PeripheralRead(volatile uint32_t *addr,\r
- uint32_t bit)\r
-{\r
-#if defined(BITBAND_PER_BASE)\r
- uint32_t tmp =\r
- BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);\r
-\r
- return *((volatile uint32_t *)tmp);\r
-#else\r
- return ((*addr) >> bit) & 1;\r
-#endif /* defined(BITBAND_PER_BASE) */\r
-}\r
+#define BITBAND_PeripheralRead(addr, bit) BUS_RegBitRead(addr, bit)\r
\r
\r
/***************************************************************************//**\r
*\r
* @param[in] val Value to set bit to, 0 or 1.\r
******************************************************************************/\r
-__STATIC_INLINE void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)\r
-{\r
-#if defined(BITBAND_RAM_BASE)\r
- uint32_t tmp =\r
- BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) * 32) + (bit * 4);\r
-\r
- *((volatile uint32_t *)tmp) = (uint32_t)val;\r
-#else\r
- uint32_t tmp = *addr;\r
- /* Make sure val is not more than 1, because we only want to set one bit. */\r
- val &= 0x1;\r
- *addr = (tmp & ~(1 << bit)) | (val << bit);\r
-#endif /* defined(BITBAND_RAM_BASE) */\r
-}\r
+#define BITBAND_SRAM(addr, bit, val) BUS_RamBitWrite(addr, bit, val)\r
\r
\r
/***************************************************************************//**\r
*\r
* @return Value of the requested bit.\r
******************************************************************************/\r
-__STATIC_INLINE uint32_t BITBAND_SRAMRead(uint32_t *addr, uint32_t bit)\r
-{\r
-#if defined(BITBAND_RAM_BASE)\r
- uint32_t tmp =\r
- BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) * 32) + (bit * 4);\r
-\r
- return *((volatile uint32_t *)tmp);\r
-#else\r
- return ((*addr) >> bit) & 1;\r
-#endif /* defined(BITBAND_RAM_BASE) */\r
-}\r
+#define BITBAND_SRAMRead(addr, bit) BUS_RamBitRead(addr, bit)\r
\r
/** @} (end addtogroup BITBAND) */\r
/** @} (end addtogroup EM_Library) */\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_BITBAND_H_ */\r
+#endif /* __SILICON_LABS_EM_BITBAND_H__ */\r
/***************************************************************************//**\r
* @file em_burtc.h\r
* @brief Backup Real Time Counter (BURTC) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
+#ifndef __SILICON_LABS_EM_BURTC_H__\r
+#define __SILICON_LABS_EM_BURTC_H__\r
\r
-#ifndef __SILICON_LABS_EM_BURTC_H_\r
-#define __SILICON_LABS_EM_BURTC_H_\r
-\r
-#include <stdbool.h>\r
#include "em_device.h"\r
-\r
#if defined(BURTC_PRESENT)\r
\r
+#include <stdbool.h>\r
#include "em_assert.h"\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
\r
#ifdef __cplusplus\r
extern "C" {\r
} BURTC_Init_TypeDef;\r
\r
/** Default configuration for BURTC init structure */\r
-#define BURTC_INIT_DEFAULT \\r
- { true, \\r
- burtcModeEM2, \\r
- false, \\r
- burtcClkSelULFRCO, \\r
- burtcClkDiv_1, \\r
- 0, \\r
- true, \\r
- false, \\r
- burtcLPDisable, \\r
- }\r
+#define BURTC_INIT_DEFAULT \\r
+{ \\r
+ true, \\r
+ burtcModeEM2, \\r
+ false, \\r
+ burtcClkSelULFRCO, \\r
+ burtcClkDiv_1, \\r
+ 0, \\r
+ true, \\r
+ false, \\r
+ burtcLPDisable, \\r
+}\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
__STATIC_INLINE void BURTC_Enable(bool enable)\r
{\r
/* Note! If mode is disabled, BURTC counter will not start */\r
- EFM_ASSERT(((enable == true) && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) != BURTC_CTRL_MODE_DISABLE))\r
+ EFM_ASSERT(((enable == true)\r
+ && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK)\r
+ != BURTC_CTRL_MODE_DISABLE))\r
|| (enable == false));\r
if (enable)\r
{\r
- BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);\r
+ BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);\r
}\r
else\r
{\r
- BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);\r
+ BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);\r
}\r
}\r
\r
******************************************************************************/\r
__STATIC_INLINE void BURTC_FreezeEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);\r
+ BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void BURTC_Powerdown(bool enable)\r
{\r
- BITBAND_Peripheral(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);\r
+ BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);\r
}\r
\r
\r
#endif\r
\r
#endif /* BURTC_PRESENT */\r
-#endif /* __SILICON_LABS_EM_BURTC_H_ */\r
+#endif /* __SILICON_LABS_EM_BURTC_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file em_bus.h\r
+ * @brief RAM and peripheral bit-field set and clear API\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_EM_BUS__\r
+#define __SILICON_LABS_EM_BUS__\r
+\r
+#include "em_device.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup BUS\r
+ * @brief BUS RAM and register bit/field read/write API\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a single-bit write operation on a 32-bit word in RAM\r
+ *\r
+ * @details\r
+ * This function uses Cortex-M bit-banding hardware to perform an atomic\r
+ * read-modify-write operation on a single bit write on a 32-bit word in RAM.\r
+ * Please refer to the reference manual for further details about bit-banding.\r
+ *\r
+ * @note\r
+ * This function is atomic on Cortex-M cores with bit-banding support. Bit-\r
+ * banding is a multicycle read-modify-write bus operation. RAM bit-banding is\r
+ * performed using the memory alias region at BITBAND_RAM_BASE.\r
+ *\r
+ * @param[in] addr Address of 32-bit word in RAM\r
+ *\r
+ * @param[in] bit Bit position to write, 0-31\r
+ *\r
+ * @param[in] val Value to set bit to, 0 or 1\r
+ ******************************************************************************/\r
+__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,\r
+ unsigned int bit,\r
+ unsigned int val)\r
+{\r
+#if defined( BITBAND_RAM_BASE )\r
+ uint32_t aliasAddr =\r
+ BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);\r
+\r
+ *(volatile uint32_t *)aliasAddr = (uint32_t)val;\r
+#else\r
+ uint32_t tmp = *addr;\r
+\r
+ /* Make sure val is not more than 1, because we only want to set one bit. */\r
+ *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a single-bit read operation on a 32-bit word in RAM\r
+ *\r
+ * @details\r
+ * This function uses Cortex-M bit-banding hardware to perform an atomic\r
+ * read operation on a single register bit. Please refer to the\r
+ * reference manual for further details about bit-banding.\r
+ *\r
+ * @note\r
+ * This function is atomic on Cortex-M cores with bit-banding support.\r
+ * RAM bit-banding is performed using the memory alias region\r
+ * at BITBAND_RAM_BASE.\r
+ *\r
+ * @param[in] addr RAM address\r
+ *\r
+ * @param[in] bit Bit position to read, 0-31\r
+ *\r
+ * @return\r
+ * The requested bit shifted to bit position 0 in the return value\r
+ ******************************************************************************/\r
+__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,\r
+ unsigned int bit)\r
+{\r
+#if defined( BITBAND_RAM_BASE )\r
+ uint32_t aliasAddr =\r
+ BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);\r
+\r
+ return *(volatile uint32_t *)aliasAddr;\r
+#else\r
+ return ((*addr) >> bit) & 1;\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a single-bit write operation on a peripheral register\r
+ *\r
+ * @details\r
+ * This function uses Cortex-M bit-banding hardware to perform an atomic\r
+ * read-modify-write operation on a single register bit. Please refer to the\r
+ * reference manual for further details about bit-banding.\r
+ *\r
+ * @note\r
+ * This function is atomic on Cortex-M cores with bit-banding support. Bit-\r
+ * banding is a multicycle read-modify-write bus operation. Peripheral register\r
+ * bit-banding is performed using the memory alias region at BITBAND_PER_BASE.\r
+ *\r
+ * @param[in] addr Peripheral register address\r
+ *\r
+ * @param[in] bit Bit position to write, 0-31\r
+ *\r
+ * @param[in] val Value to set bit to, 0 or 1\r
+ ******************************************************************************/\r
+__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,\r
+ unsigned int bit,\r
+ unsigned int val)\r
+{\r
+#if defined( BITBAND_PER_BASE )\r
+ uint32_t aliasAddr =\r
+ BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);\r
+\r
+ *(volatile uint32_t *)aliasAddr = (uint32_t)val;\r
+#else\r
+ uint32_t tmp = *addr;\r
+\r
+ /* Make sure val is not more than 1, because we only want to set one bit. */\r
+ *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a single-bit read operation on a peripheral register\r
+ *\r
+ * @details\r
+ * This function uses Cortex-M bit-banding hardware to perform an atomic\r
+ * read operation on a single register bit. Please refer to the\r
+ * reference manual for further details about bit-banding.\r
+ *\r
+ * @note\r
+ * This function is atomic on Cortex-M cores with bit-banding support.\r
+ * Peripheral register bit-banding is performed using the memory alias\r
+ * region at BITBAND_PER_BASE.\r
+ *\r
+ * @param[in] addr Peripheral register address\r
+ *\r
+ * @param[in] bit Bit position to read, 0-31\r
+ *\r
+ * @return\r
+ * The requested bit shifted to bit position 0 in the return value\r
+ ******************************************************************************/\r
+__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,\r
+ unsigned int bit)\r
+{\r
+#if defined( BITBAND_PER_BASE )\r
+ uint32_t aliasAddr =\r
+ BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);\r
+\r
+ return *(volatile uint32_t *)aliasAddr;\r
+#else\r
+ return ((*addr) >> bit) & 1;\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a masked set operation on peripheral register address.\r
+ *\r
+ * @details\r
+ * Peripheral register masked set provides a single-cycle and atomic set\r
+ * operation of a bit-mask in a peripheral register. All 1's in the mask are\r
+ * set to 1 in the register. All 0's in the mask are not changed in the\r
+ * register.\r
+ * RAMs and special peripherals are not supported. Please refer to the\r
+ * reference manual for further details about peripheral register field set.\r
+ *\r
+ * @note\r
+ * This function is single-cycle and atomic on cores with peripheral bit set\r
+ * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE.\r
+ *\r
+ * @param[in] addr Peripheral register address\r
+ *\r
+ * @param[in] mask Mask to set\r
+ ******************************************************************************/\r
+__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,\r
+ uint32_t mask)\r
+{\r
+#if defined( PER_BITSET_MEM_BASE )\r
+ uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);\r
+ *(volatile uint32_t *)aliasAddr = mask;\r
+#else\r
+ *addr |= mask;\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a masked clear operation on peripheral register address.\r
+ *\r
+ * @details\r
+ * Peripheral register masked clear provides a single-cycle and atomic clear\r
+ * operation of a bit-mask in a peripheral register. All 1's in the mask are\r
+ * set to 0 in the register.\r
+ * All 0's in the mask are not changed in the register.\r
+ * RAMs and special peripherals are not supported. Please refer to the\r
+ * reference manual for further details about peripheral register field clear.\r
+ *\r
+ * @note\r
+ * This function is single-cycle and atomic on cores with peripheral bit set\r
+ * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE.\r
+ *\r
+ * @param[in] addr Peripheral register address\r
+ *\r
+ * @param[in] mask Mask to clear\r
+ ******************************************************************************/\r
+__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,\r
+ uint32_t mask)\r
+{\r
+#if defined( PER_BITCLR_MEM_BASE )\r
+ uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);\r
+ *(volatile uint32_t *)aliasAddr = mask;\r
+#else\r
+ *addr &= ~mask;\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform peripheral register masked clear and value write.\r
+ *\r
+ * @details\r
+ * This function first clears the mask in the peripheral register, then\r
+ * writes the value. Typically the mask is a bit-field in the register, and\r
+ * the value val is within the mask.\r
+ *\r
+ * @note\r
+ * This operation is not atomic. Note that the mask is first set to 0 before\r
+ * the val is set.\r
+ *\r
+ * @param[in] addr Peripheral register address\r
+ *\r
+ * @param[in] mask Peripheral register mask\r
+ *\r
+ * @param[in] val Peripheral register value. The value must be shifted to the\r
+ correct bit position in the register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,\r
+ uint32_t mask,\r
+ uint32_t val)\r
+{\r
+#if defined( PER_BITCLR_MEM_BASE )\r
+ BUS_RegMaskedClear(addr, mask);\r
+ BUS_RegMaskedSet(addr, val);\r
+#else\r
+ *addr = (*addr & ~mask) | val;\r
+#endif\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Perform a peripheral register masked read\r
+ *\r
+ * @details\r
+ * Read an unshifted and masked value from a peripheral register.\r
+ *\r
+ * @note\r
+ * This operation is not hardware accelerated.\r
+ *\r
+ * @param[in] addr Peripheral register address\r
+ *\r
+ * @param[in] mask Peripheral register mask\r
+ *\r
+ * @return\r
+ * Unshifted and masked register value\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr,\r
+ uint32_t mask)\r
+{\r
+ return *addr & mask;\r
+}\r
+\r
+\r
+/** @} (end addtogroup BUS) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SILICON_LABS_EM_BUS__ */\r
/***************************************************************************//**\r
* @file em_chip.h\r
* @brief Chip Initialization API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_CHIP_H_\r
-#define __SILICON_LABS_EM_CHIP_H_\r
+#ifndef __SILICON_LABS_EM_CHIP_H__\r
+#define __SILICON_LABS_EM_CHIP_H__\r
\r
#include "em_device.h"\r
#include "em_system.h"\r
* @brief\r
* Chip initialization routine for revision errata workarounds\r
*\r
- * This init function will configure the EFM32 device to a state where it is\r
+ * This init function will configure the device to a state where it is\r
* as similar as later revisions as possible, to improve software compatibility\r
* with newer parts. See the device specific errata for details.\r
*****************************************************************************/\r
#if defined(_EFM32_HAPPY_FAMILY)\r
uint32_t rev;\r
rev = *(volatile uint32_t *)(0x0FE081FC);\r
- \r
+\r
if ((rev >> 24) <= 129)\r
{\r
/* This fixes a mistaken internal connection between PC0 and PC4 */\r
/* This disables an internal pulldown on PC4 */\r
- *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); \r
+ *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);\r
/* This disables an internal LDO test signal driving PC4 */\r
*(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24);\r
}\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_CHIP_H_ */\r
+#endif /* __SILICON_LABS_EM_CHIP_H__ */\r
/***************************************************************************//**\r
* @file em_cmu.h\r
* @brief Clock management unit (CMU) API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
* arising from your use of this Software.\r
*\r
******************************************************************************/\r
-\r
-\r
-#ifndef __SILICON_LABS_EM_CMU_H_\r
-#define __SILICON_LABS_EM_CMU_H_\r
+#ifndef __SILICON_LABS_EM_CMU_H__\r
+#define __SILICON_LABS_EM_CMU_H__\r
\r
#include "em_device.h"\r
#if defined( CMU_PRESENT )\r
\r
#include <stdbool.h>\r
-#include "em_bitband.h"\r
+#include "em_assert.h"\r
+#include "em_bus.h"\r
\r
#ifdef __cplusplus\r
extern "C" {\r
\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
\r
-/* Select register ids, for internal use */\r
+/* Select register id's, for internal use. */\r
#define CMU_NOSEL_REG 0\r
#define CMU_HFCLKSEL_REG 1\r
#define CMU_LFACLKSEL_REG 2\r
#define CMU_LFBCLKSEL_REG 3\r
-#define CMU_DBGCLKSEL_REG 4\r
-#if defined( _CMU_CMD_USBCCLKSEL_MASK )\r
-#define CMU_USBCCLKSEL_REG 5\r
-#endif\r
-#if defined( _CMU_LFCLKSEL_LFC_MASK )\r
-#define CMU_LFCCLKSEL_REG 6\r
-#endif\r
+#define CMU_LFCCLKSEL_REG 4\r
+#define CMU_LFECLKSEL_REG 5\r
+#define CMU_DBGCLKSEL_REG 6\r
+#define CMU_USBCCLKSEL_REG 7\r
\r
#define CMU_SEL_REG_POS 0\r
#define CMU_SEL_REG_MASK 0xf\r
\r
-/* Divisor register ids, for internal use */\r
+/* Divisor/prescaler register id's, for internal use. */\r
#define CMU_NODIV_REG 0\r
-#define CMU_HFPERCLKDIV_REG 1\r
-#define CMU_HFCORECLKDIV_REG 2\r
-#define CMU_LFAPRESC0_REG 3\r
-#define CMU_LFBPRESC0_REG 4\r
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
-#define CMU_HFCLKDIV_REG 5\r
-#endif\r
-#define CMU_DIV_REG_POS 4\r
-#define CMU_DIV_REG_MASK 0xf\r
-\r
-/* Enable register ids, for internal use */\r
+#define CMU_NOPRESC_REG 0\r
+#define CMU_HFPRESC_REG 1\r
+#define CMU_HFCLKDIV_REG 1\r
+#define CMU_HFEXPPRESC_REG 2\r
+#define CMU_HFCLKLEPRESC_REG 3\r
+#define CMU_HFPERPRESC_REG 4\r
+#define CMU_HFPERCLKDIV_REG 4\r
+#define CMU_HFCOREPRESC_REG 5\r
+#define CMU_HFCORECLKDIV_REG 5\r
+#define CMU_HFRADIOPRESC_REG 6\r
+#define CMU_LFAPRESC0_REG 7\r
+#define CMU_LFBPRESC0_REG 8\r
+#define CMU_LFEPRESC0_REG 9\r
+\r
+#define CMU_PRESC_REG_POS 4\r
+#define CMU_DIV_REG_POS CMU_PRESC_REG_POS\r
+#define CMU_PRESC_REG_MASK 0xf\r
+#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK\r
+\r
+/* Enable register id's, for internal use. */\r
#define CMU_NO_EN_REG 0\r
+#define CMU_CTRL_EN_REG 1\r
#define CMU_HFPERCLKDIV_EN_REG 1\r
#define CMU_HFPERCLKEN0_EN_REG 2\r
#define CMU_HFCORECLKEN0_EN_REG 3\r
-#define CMU_LFACLKEN0_EN_REG 4\r
-#define CMU_LFBCLKEN0_EN_REG 5\r
-#define CMU_PCNT_EN_REG 6\r
-#if defined( _CMU_LFCCLKEN0_MASK )\r
-#define CMU_LFCCLKEN0_EN_REG 7\r
-#endif\r
+#define CMU_HFRADIOCLKEN0_EN_REG 4\r
+#define CMU_HFBUSCLKEN0_EN_REG 5\r
+#define CMU_LFACLKEN0_EN_REG 6\r
+#define CMU_LFBCLKEN0_EN_REG 7\r
+#define CMU_LFCCLKEN0_EN_REG 8\r
+#define CMU_LFECLKEN0_EN_REG 9\r
+#define CMU_PCNT_EN_REG 10\r
\r
#define CMU_EN_REG_POS 8\r
#define CMU_EN_REG_MASK 0xf\r
\r
-/* Enable register bit position, for internal use */\r
+/* Enable register bit positions, for internal use. */\r
#define CMU_EN_BIT_POS 12\r
#define CMU_EN_BIT_MASK 0x1f\r
\r
-/* Clock branch bitfield position, for internal use */\r
+/* Clock branch bitfield positions, for internal use. */\r
#define CMU_HF_CLK_BRANCH 0\r
-#define CMU_HFPER_CLK_BRANCH 1\r
-#define CMU_HFCORE_CLK_BRANCH 2\r
-#define CMU_LFA_CLK_BRANCH 3\r
-#define CMU_RTC_CLK_BRANCH 4\r
-#define CMU_LETIMER_CLK_BRANCH 5\r
-#define CMU_LCDPRE_CLK_BRANCH 6\r
-#define CMU_LCD_CLK_BRANCH 7\r
-#define CMU_LESENSE_CLK_BRANCH 8\r
-#define CMU_LFB_CLK_BRANCH 9\r
+#define CMU_HFCORE_CLK_BRANCH 1\r
+#define CMU_HFPER_CLK_BRANCH 2\r
+#define CMU_HFRADIO_CLK_BRANCH 3\r
+#define CMU_HFBUS_CLK_BRANCH 4\r
+#define CMU_HFEXP_CLK_BRANCH 5\r
+#define CMU_DBG_CLK_BRANCH 6\r
+#define CMU_AUX_CLK_BRANCH 7\r
+#define CMU_RTC_CLK_BRANCH 8\r
+#define CMU_RTCC_CLK_BRANCH 8\r
+#define CMU_LETIMER_CLK_BRANCH 9\r
+#define CMU_LETIMER0_CLK_BRANCH 9\r
#define CMU_LEUART0_CLK_BRANCH 10\r
#define CMU_LEUART1_CLK_BRANCH 11\r
-#define CMU_DBG_CLK_BRANCH 12\r
-#define CMU_AUX_CLK_BRANCH 13\r
-#define CMU_USBC_CLK_BRANCH 14\r
-#define CMU_LFC_CLK_BRANCH 15\r
-#define CMU_USBLE_CLK_BRANCH 16\r
+#define CMU_LFA_CLK_BRANCH 12\r
+#define CMU_LFB_CLK_BRANCH 13\r
+#define CMU_LFC_CLK_BRANCH 14\r
+#define CMU_LFE_CLK_BRANCH 15\r
+#define CMU_USBC_CLK_BRANCH 16\r
+#define CMU_USBLE_CLK_BRANCH 17\r
+#define CMU_LCDPRE_CLK_BRANCH 18\r
+#define CMU_LCD_CLK_BRANCH 19\r
+#define CMU_LESENSE_CLK_BRANCH 20\r
\r
#define CMU_CLK_BRANCH_POS 17\r
#define CMU_CLK_BRANCH_MASK 0x1f\r
/** Clock divider configuration */\r
typedef uint32_t CMU_ClkDiv_TypeDef;\r
\r
-/** High frequency RC bands. */\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+/** Clockprescaler configuration */\r
+typedef uint32_t CMU_ClkPresc_TypeDef;\r
+#endif\r
+\r
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )\r
+/** High frequency system RCO bands */\r
typedef enum\r
{\r
- /** 1MHz RC band. */\r
- cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,\r
- /** 7MHz RC band. */\r
- cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,\r
- /** 11MHz RC band. */\r
- cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,\r
- /** 14MHz RC band. */\r
- cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,\r
- /** 21MHz RC band. */\r
- cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,\r
-#if defined( _CMU_HFRCOCTRL_BAND_28MHZ )\r
- /** 28MHz RC band. */\r
- cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ\r
+ cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1MHz HFRCO band */\r
+ cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7MHz HFRCO band */\r
+ cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11MHz HFRCO band */\r
+ cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14MHz HFRCO band */\r
+ cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21MHz HFRCO band */\r
+#if defined( CMU_HFRCOCTRL_BAND_28MHZ )\r
+ cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28MHz HFRCO band */\r
#endif\r
} CMU_HFRCOBand_TypeDef;\r
-\r
+#endif /* _CMU_HFRCOCTRL_BAND_MASK */\r
\r
#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
-/** AUX High frequency RC bands. */\r
+/** AUX High frequency RCO bands */\r
typedef enum\r
{\r
- /** 1MHz RC band. */\r
- cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ,\r
- /** 7MHz RC band. */\r
- cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ,\r
- /** 11MHz RC band. */\r
- cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,\r
- /** 14MHz RC band. */\r
- cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,\r
- /** 21MHz RC band. */\r
- cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,\r
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )\r
- /** 28MHz RC band. */\r
- cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ\r
+ cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1MHz RC band */\r
+ cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7MHz RC band */\r
+ cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11MHz RC band */\r
+ cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14MHz RC band */\r
+ cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21MHz RC band */\r
+#if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )\r
+ cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28MHz RC band */\r
#endif\r
} CMU_AUXHFRCOBand_TypeDef;\r
#endif\r
} CMU_USHFRCOBand_TypeDef;\r
#endif\r
\r
+#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )\r
+/** High frequency system RCO bands */\r
+typedef enum\r
+{\r
+ cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */\r
+ cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */\r
+ cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */\r
+ cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */\r
+ cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */\r
+ cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */\r
+ cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */\r
+ cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */\r
+ cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */\r
+ cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */\r
+ cmuHFRCOFreq_UserDefined = 0,\r
+} CMU_HFRCOFreq_TypeDef;\r
+#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz\r
+#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz\r
+#endif\r
+\r
+#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
+/** AUX High frequency RCO bands */\r
+typedef enum\r
+{\r
+ cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */\r
+ cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */\r
+ cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */\r
+ cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */\r
+ cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */\r
+ cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */\r
+ cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */\r
+ cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */\r
+ cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */\r
+ cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */\r
+ cmuAUXHFRCOFreq_UserDefined = 0,\r
+} CMU_AUXHFRCOFreq_TypeDef;\r
+#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz\r
+#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz\r
+#endif\r
+\r
\r
/** Clock points in CMU. Please refer to CMU overview in reference manual. */\r
typedef enum\r
/*******************/\r
\r
/** High frequency clock */\r
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )\r
- cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#if defined( _CMU_CTRL_HFCLKDIV_MASK ) \\r
+ || defined( _CMU_HFPRESC_MASK )\r
+ cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#else\r
- cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
/** Debug clock */\r
- cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
/** AUX clock */\r
- cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+\r
+#if defined( _CMU_HFEXPPRESC_MASK )\r
+ /**********************/\r
+ /* HF export sub-branch */\r
+ /**********************/\r
+\r
+ /** Export clock */\r
+ cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( _CMU_HFBUSCLKEN0_MASK )\r
+/**********************************/\r
+ /* HF bus clock sub-branch */\r
+ /**********************************/\r
+\r
+ /** High frequency bus clock. */\r
+ cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+\r
+#if defined( CMU_HFBUSCLKEN0_CRYPTO )\r
+ /** Cryptography accelerator clock. */\r
+ cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFBUSCLKEN0_LDMA )\r
+ /** Direct memory access controller clock. */\r
+ cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFBUSCLKEN0_GPCRC )\r
+ /** General purpose cyclic redundancy checksum clock. */\r
+ cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFBUSCLKEN0_GPIO )\r
+ /** General purpose input/output clock. */\r
+ cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+ /** Low energy clocking module clock. */\r
+ cmuClock_CORELE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+\r
+#if defined( CMU_HFBUSCLKEN0_PRS )\r
+ /** Peripheral reflex system clock. */\r
+ cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+#endif\r
\r
/**********************************/\r
/* HF peripheral clock sub-branch */\r
/**********************************/\r
\r
/** High frequency peripheral clock */\r
- cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#if defined( _CMU_HFPRESC_MASK )\r
+ cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#else\r
+ cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_USART0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_USART0 )\r
/** Universal sync/async receiver/transmitter 0 clock. */\r
- cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_USARTRF0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_USARTRF0 )\r
/** Universal sync/async receiver/transmitter 0 clock. */\r
- cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_USART1_MASK)\r
+#if defined( CMU_HFPERCLKEN0_USARTRF1 )\r
+ /** Universal sync/async receiver/transmitter 0 clock. */\r
+ cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFPERCLKEN0_USART1 )\r
/** Universal sync/async receiver/transmitter 1 clock. */\r
- cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_USART2_MASK)\r
+#if defined( CMU_HFPERCLKEN0_USART2 )\r
/** Universal sync/async receiver/transmitter 2 clock. */\r
- cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFPERCLKEN0_USART3 )\r
+ /** Universal sync/async receiver/transmitter 3 clock. */\r
+ cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_UART0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_USART4 )\r
+ /** Universal sync/async receiver/transmitter 4 clock. */\r
+ cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFPERCLKEN0_USART5 )\r
+ /** Universal sync/async receiver/transmitter 5 clock. */\r
+ cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+\r
+#if defined( CMU_HFPERCLKEN0_UART0 )\r
/** Universal async receiver/transmitter 0 clock. */\r
- cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_UART1_MASK)\r
+#if defined( CMU_HFPERCLKEN0_UART1 )\r
/** Universal async receiver/transmitter 1 clock. */\r
- cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_TIMER0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_TIMER0 )\r
/** Timer 0 clock. */\r
- cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_TIMER1_MASK)\r
+#if defined( CMU_HFPERCLKEN0_TIMER1 )\r
/** Timer 1 clock. */\r
- cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_TIMER2_MASK)\r
+#if defined( CMU_HFPERCLKEN0_TIMER2 )\r
/** Timer 2 clock. */\r
- cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_TIMER3_MASK)\r
+#if defined( CMU_HFPERCLKEN0_TIMER3 )\r
/** Timer 3 clock. */\r
- cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFPERCLKEN0_CRYOTIMER )\r
+ /** CRYOtimer clock. */\r
+ cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_ACMP0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_ACMP0 )\r
/** Analog comparator 0 clock. */\r
- cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_ACMP1_MASK)\r
+#if defined( CMU_HFPERCLKEN0_ACMP1 )\r
/** Analog comparator 1 clock. */\r
- cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_PRS_MASK)\r
+#if defined( CMU_HFPERCLKEN0_PRS )\r
/** Peripheral reflex system clock. */\r
- cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_DAC0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_DAC0 )\r
/** Digital to analog converter 0 clock. */\r
- cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_IDAC0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_IDAC0 )\r
/** Digital to analog converter 0 clock. */\r
- cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(GPIO_PRESENT)\r
+#if defined( CMU_HFPERCLKEN0_GPIO )\r
/** General purpose input/output clock. */\r
- cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(VCMP_PRESENT)\r
+#if defined( CMU_HFPERCLKEN0_VCMP )\r
/** Voltage comparator clock. */\r
- cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_ADC0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_ADC0 )\r
/** Analog to digital converter 0 clock. */\r
- cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_I2C0_MASK)\r
+#if defined( CMU_HFPERCLKEN0_I2C0 )\r
/** I2C 0 clock. */\r
- cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_HFPERCLKEN0_I2C1_MASK)\r
+#if defined( CMU_HFPERCLKEN0_I2C1 )\r
/** I2C 1 clock. */\r
- cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFPERCLKEN0_I2C2 )\r
+ /** I2C 2 clock. */\r
+ cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
/**********************/\r
/**********************/\r
\r
/** Core clock */\r
- cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
-#if defined(AES_PRESENT)\r
+#if defined( CMU_HFCORECLKEN0_AES )\r
/** Advanced encryption standard accelerator clock. */\r
- cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(DMA_PRESENT)\r
+#if defined( CMU_HFCORECLKEN0_DMA )\r
/** Direct memory access controller clock. */\r
- cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
- /** Low energy clocking module clock. */\r
- cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
-#if defined(EBI_PRESENT)\r
+#if defined( CMU_HFCORECLKEN0_LE )\r
+/** Low energy clocking module clock. */\r
+ cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFCORECLKEN0_EBI )\r
/** External bus interface clock. */\r
- cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(USB_PRESENT)\r
+#if defined( CMU_HFCORECLKEN0_USBC )\r
/** USB Core clock. */\r
- cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
#endif\r
\r
-#if defined(USB_PRESENT)\r
+#if defined( CMU_HFCORECLKEN0_USB )\r
/** USB clock. */\r
- cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_CTRL_HFRADIOCLKEN )\r
+ /**********************************/\r
+ /* HF radio clock sub-branch */\r
+ /**********************************/\r
+\r
+ /** High frequency radio clock. */\r
+ cmuClock_RADIO = (CMU_HFRADIOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_CTRL_HFRADIOCLKEN_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_MODEM )\r
+ /** Modulator/demodulator clock. */\r
+ cmuClock_MODEM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_MODEM_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_PROTIMER )\r
+ /** Protocol timer clock. */\r
+ cmuClock_PROTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_PROTIMER_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_CRC )\r
+ /** Cyclic Redundancy Check clock. */\r
+ cmuClock_CRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_CRC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_AGC )\r
+ /** Automatic Gain Control clock. */\r
+ cmuClock_AGC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_AGC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_FRC )\r
+ /** Frame Controller clock. */\r
+ cmuClock_FRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_FRC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_SYNTH )\r
+ /** Frequency Synthesizer clock. */\r
+ cmuClock_SYNTH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_SYNTH_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_BUFC )\r
+ /** Buffer Controller Check clock. */\r
+ cmuClock_BUFC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_BUFC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+\r
+#if defined( CMU_HFRADIOCLKEN0_RAC )\r
+ /** Radio Controller clock. */\r
+ cmuClock_RAC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_HFRADIOCLKEN0_RAC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
#endif\r
\r
/***************/\r
/***************/\r
\r
/** Low frequency A clock */\r
- cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
-#if defined(RTC_PRESENT)\r
+#if defined( CMU_LFACLKEN0_RTC )\r
/** Real time counter clock. */\r
- cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_LFACLKEN0_LETIMER0_MASK)\r
+#if defined( CMU_LFACLKEN0_LETIMER0 )\r
/** Low energy timer 0 clock. */\r
- cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_LFACLKEN0_LCD_MASK)\r
+#if defined( CMU_LFACLKEN0_LCD )\r
/** Liquid crystal display, pre FDIV clock. */\r
- cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
/** Liquid crystal display clock. Please notice that FDIV prescaler\r
* must be set by special API. */\r
- cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)\r
+#if defined( CMU_PCNTCTRL_PCNT0CLKEN )\r
/** Pulse counter 0 clock. */\r
- cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)\r
+#if defined( CMU_PCNTCTRL_PCNT1CLKEN )\r
/** Pulse counter 1 clock. */\r
- cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)\r
+#if defined( CMU_PCNTCTRL_PCNT2CLKEN )\r
/** Pulse counter 2 clock. */\r
- cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
-#if defined(_CMU_LFACLKEN0_LESENSE_MASK)\r
+#if defined( CMU_LFACLKEN0_LESENSE )\r
/** LESENSE clock. */\r
- cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
/***************/\r
/***************/\r
\r
/** Low frequency B clock */\r
- cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
-#if defined(_CMU_LFBCLKEN0_LEUART0_MASK)\r
+#if defined( CMU_LFBCLKEN0_LEUART0 )\r
/** Low energy universal asynchronous receiver/transmitter 0 clock. */\r
- cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
-#if defined(_CMU_LFBCLKEN0_LEUART1_MASK)\r
+#if defined( CMU_LFBCLKEN0_LEUART1 )\r
/** Low energy universal asynchronous receiver/transmitter 1 clock. */\r
- cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |\r
- (CMU_NOSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
#endif\r
\r
+#if defined( _CMU_LFCCLKEN0_MASK )\r
/***************/\r
/* LF C branch */\r
/***************/\r
\r
/** Low frequency C clock */\r
-#if defined( _CMU_LFCLKSEL_LFC_MASK )\r
- cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_NO_EN_REG << CMU_EN_REG_POS) |\r
- (0 << CMU_EN_BIT_POS) |\r
- (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
-#endif\r
+ cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
\r
-#if defined(_CMU_LFCCLKEN0_USBLE_MASK)\r
+#if defined( CMU_LFCCLKEN0_USBLE )\r
/** USB LE clock. */\r
- cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |\r
- (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |\r
- (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) |\r
- (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) |\r
- (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+ cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)\r
+ | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
+#endif\r
+\r
+#if defined( _CMU_LFECLKEN0_MASK )\r
+ /***************/\r
+ /* LF E branch */\r
+ /***************/\r
+\r
+ /** Low frequency A clock */\r
+ cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)\r
+ | (0 << CMU_EN_BIT_POS)\r
+ | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+\r
+ /** Real time counter and calendar clock. */\r
+#if defined ( CMU_LFECLKEN0_RTCC )\r
+ cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)\r
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)\r
+ | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)\r
+ | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)\r
+ | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),\r
+#endif\r
#endif\r
\r
} CMU_Clock_TypeDef;\r
#if defined( _CMU_STATUS_USHFRCOENS_MASK )\r
cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */\r
#endif\r
-#if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )\r
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )\r
cmuOsc_ULFRCO /**< Ultra low frequency RC oscillator. */\r
#endif\r
} CMU_Osc_TypeDef;\r
cmuSelect_LFRCO, /**< Low frequency RC oscillator. */\r
cmuSelect_HFXO, /**< High frequency crystal oscillator. */\r
cmuSelect_HFRCO, /**< High frequency RC oscillator. */\r
+#if defined( CMU_LFACLKSEL_LFA_HFCLKLE ) || defined( CMU_LFBCLKSEL_LFB_HFCLKLE )\r
+ cmuSelect_HFCLKLE, /**< High frequency clock to LE divided by 2 or 4. */\r
+#endif\r
cmuSelect_CORELEDIV2, /**< Core low energy clock divided by 2. */\r
cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */\r
cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on Tiny Gecko and for USBC (not used on Gecko) */\r
-#if defined( _CMU_STATUS_USHFRCOENS_MASK )\r
+#if defined( CMU_STATUS_USHFRCOENS )\r
cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */\r
#endif\r
-#if defined( _CMU_CMD_HFCLKSEL_USHFRCODIV2 )\r
+#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )\r
cmuSelect_USHFRCODIV2,/**< USB high frequency RC oscillator */\r
#endif\r
-#if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )\r
+#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )\r
cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */\r
#endif\r
} CMU_Select_TypeDef;\r
\r
\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+#if defined( _CMU_LFXOCTRL_MASK )\r
+/** LFXO initialization structure. Init values should be obtained from a configuration tool,\r
+ app note or xtal datasheet */\r
+typedef struct\r
+{\r
+ uint8_t ctune; /**< CTUNE (load capacitance) value */\r
+ uint8_t gain; /**< Gain / max startup margin */\r
+ uint8_t timeout; /**< Startup delay */\r
+} CMU_LFXOInit_TypeDef;\r
+\r
+/** Default LFXO initialization */\r
+#define CMU_LFXOINIT_DEFAULT \\r
+ { \\r
+ _CMU_LFXOCTRL_TUNING_DEFAULT, \\r
+ _CMU_LFXOCTRL_GAIN_DEFAULT, \\r
+ _CMU_LFXOCTRL_TIMEOUT_DEFAULT, \\r
+ }\r
+#endif\r
+\r
+#if defined( _CMU_HFXOCTRL_MASK )\r
+/** HFXO initialization structure. Init values should be obtained from a configuration tool,\r
+ app note or xtal datasheet */\r
+typedef struct\r
+{\r
+ bool lowPowerMode; /**< Enable low-power mode */\r
+ bool autoStartEm01; /**< Enable auto-start on entry to EM0/1 */\r
+ bool autoSelEm01; /**< Enable auto-select on entry to EM0/1 */\r
+ bool autoStartSelOnRacWakeup; /**< Enable auto-start and select on RAC wakeup */\r
+ uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */\r
+ uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */\r
+ uint8_t regIshStartup; /**< Shunt startup current */\r
+ uint8_t regIshSteadyState; /**< Shunt steady-state current */\r
+ uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */\r
+ uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */\r
+ uint8_t thresholdPeakDetect; /**< Peak detection threshold */\r
+ uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */\r
+ uint8_t timeoutPeakDetect; /**< Timeout - peak detection */\r
+ uint8_t timeoutWarmSteady; /**< Timeout - warmup */\r
+ uint8_t timeoutSteady; /**< Timeout - steady-state */\r
+ uint8_t timeoutStartup; /**< Timeout - startup */\r
+} CMU_HFXOInit_TypeDef;\r
+\r
+/** Default HFXO initialization */\r
+#if defined( _EFR_DEVICE )\r
+#define CMU_HFXOINIT_DEFAULT \\r
+{ \\r
+ false, /* Low-noise mode for EFR32 */ \\r
+ false, /* Disable auto-start on EM0/1 entry */ \\r
+ false, /* Disable auto-select on EM0/1 entry */ \\r
+ false, /* Disable auto-start and select on RAC wakeup */ \\r
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \\r
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \\r
+ _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT, \\r
+ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \\r
+ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \\r
+ 0x7, /* Recommended steady-state XO core bias current */ \\r
+ 0x6, /* Recommended peak detection threshold */ \\r
+ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \\r
+ 0xA, /* Recommended peak detection timeout */ \\r
+ _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT, \\r
+ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \\r
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \\r
+}\r
+/* EFM32 device */\r
+#else\r
+#define CMU_HFXOINIT_DEFAULT \\r
+{ \\r
+ true, /* Low-power mode for EFM32 */ \\r
+ false, /* Disable auto-start on EM0/1 entry */ \\r
+ false, /* Disable auto-select on EM0/1 entry */ \\r
+ false, /* Disable auto-start and select on RAC wakeup */ \\r
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \\r
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \\r
+ _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT, \\r
+ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \\r
+ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \\r
+ 0x7, /* Recommended steady-state osc core bias current */ \\r
+ 0x6, /* Recommended peak detection threshold */ \\r
+ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \\r
+ 0xA, /* Recommended peak detection timeout */ \\r
+ _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT, \\r
+ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \\r
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \\r
+}\r
+#endif\r
+#endif /* _CMU_HFXOCTRL_MASK */\r
+\r
+\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
******************************************************************************/\r
\r
-void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);\r
-uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);\r
-CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);\r
-CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);\r
-void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);\r
-void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);\r
+#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
+CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);\r
+void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);\r
+\r
+#elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )\r
+CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void);\r
+void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freqEnum);\r
+#endif\r
+\r
+uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);\r
\r
+#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )\r
+void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,\r
+ CMU_Osc_TypeDef upSel);\r
+#endif\r
+\r
+uint32_t CMU_CalibrateCountGet(void);\r
+void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);\r
+CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);\r
+void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);\r
+uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);\r
+\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
+void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);\r
+uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);\r
+#endif\r
+\r
+void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);\r
+CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);\r
+void CMU_FreezeEnable(bool enable);\r
+\r
+#if defined( _CMU_HFRCOCTRL_BAND_MASK )\r
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);\r
-void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);\r
+void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);\r
\r
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )\r
-CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);\r
-void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);\r
+#elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )\r
+CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void);\r
+void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freqEnum);\r
+#endif\r
+\r
+uint32_t CMU_HFRCOStartupDelayGet(void);\r
+void CMU_HFRCOStartupDelaySet(uint32_t delay);\r
+\r
+#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )\r
+void CMU_HFXOAutostartEnable(bool enRACStartSel,\r
+ bool enEM0EM1Start,\r
+ bool enEM0EM1StartSel);\r
+#endif\r
+\r
+#if defined( _CMU_HFXOCTRL_MASK )\r
+void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit);\r
+#endif\r
+\r
+\r
+uint32_t CMU_LCDClkFDIVGet(void);\r
+void CMU_LCDClkFDIVSet(uint32_t div);\r
+\r
+#if defined( _CMU_LFXOCTRL_MASK )\r
+void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit);\r
#endif\r
\r
+void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);\r
+uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);\r
+void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);\r
+bool CMU_PCNTClockExternalGet(unsigned int instance);\r
+void CMU_PCNTClockExternalSet(unsigned int instance, bool external);\r
+\r
#if defined( _CMU_USHFRCOCONF_BAND_MASK )\r
-CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);\r
-void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);\r
+CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);\r
+void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);\r
#endif\r
\r
-void CMU_HFRCOStartupDelaySet(uint32_t delay);\r
-uint32_t CMU_HFRCOStartupDelayGet(void);\r
\r
-void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);\r
-uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);\r
-void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);\r
+#if defined( CMU_CALCTRL_CONT )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Configures continuous calibration mode\r
+ * @param[in] enable\r
+ * If true, enables continuous calibration, if false disables continuous\r
+ * calibrartion\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CMU_CalibrateCont(bool enable)\r
+{\r
+ BUS_RegBitWrite(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);\r
+}\r
+#endif\r
\r
-bool CMU_PCNTClockExternalGet(unsigned int inst);\r
-void CMU_PCNTClockExternalSet(unsigned int inst, bool external);\r
\r
-uint32_t CMU_LCDClkFDIVGet(void);\r
-void CMU_LCDClkFDIVSet(uint32_t div);\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Starts calibration\r
+ * @note\r
+ * This call is usually invoked after CMU_CalibrateConfig() and possibly\r
+ * CMU_CalibrateCont()\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CMU_CalibrateStart(void)\r
+{\r
+ CMU->CMD = CMU_CMD_CALSTART;\r
+}\r
\r
-void CMU_FreezeEnable(bool enable);\r
-uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);\r
\r
-#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )\r
-void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,\r
- CMU_Osc_TypeDef upSel);\r
+#if defined( CMU_CMD_CALSTOP )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Stop the calibration counters\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CMU_CalibrateStop(void)\r
+{\r
+ CMU->CMD = CMU_CMD_CALSTOP;\r
+}\r
#endif\r
\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Convert dividend to logarithmic value. Only works for even\r
+ * numbers equal to 2^n.\r
+ *\r
+ * @param[in] div\r
+ * Unscaled dividend.\r
+ *\r
+ * @return\r
+ * Logarithm of 2, as used by fixed prescalers.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)\r
+{\r
+ uint32_t log2;\r
+\r
+ /* Fixed 2^n prescalers take argument of 32768 or less. */\r
+ EFM_ASSERT((div > 0U) && (div <= 32768U));\r
+\r
+ /* Count leading zeroes and "reverse" result */\r
+ log2 = (31U - __CLZ(div));\r
+\r
+ return log2;\r
+}\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Clear one or more pending CMU interrupts.\r
* The event bits are not cleared by the use of this function.\r
*\r
* @return\r
- * Pending and enabled CMU interrupt sources.\r
- * The return value is the bitwise AND combination of\r
- * - the OR combination of enabled interrupt sources in CMU_IEN_nnn\r
- * register (CMU_IEN_nnn) and\r
- * - the OR combination of valid interrupt flags of the CMU module\r
- * (CMU_IF_nnn).\r
+ * Pending and enabled CMU interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in CMU_IEN and\r
+ * - the pending interrupt flags CMU_IF\r
******************************************************************************/\r
__STATIC_INLINE uint32_t CMU_IntGetEnabled(void)\r
{\r
- uint32_t tmp = 0U;\r
-\r
+ uint32_t ien;\r
\r
- /* Store LESENSE->IEN in temporary variable in order to define explicit order\r
- * of volatile accesses. */\r
- tmp = CMU->IEN;\r
-\r
- /* Bitwise AND of pending and enabled interrupts */\r
- return CMU->IF & tmp;\r
+ ien = CMU->IEN;\r
+ return CMU->IF & ien;\r
}\r
\r
\r
/**************************************************************************//**\r
* @brief\r
- * Set one or more pending CMU interrupts from SW.\r
+ * Set one or more pending CMU interrupts.\r
*\r
* @param[in] flags\r
* CMU interrupt sources to set to pending.\r
\r
/***************************************************************************//**\r
* @brief\r
- * Unlock the CMU so that writing to locked registers again is possible.\r
+ * Convert logarithm of 2 prescaler to division factor.\r
+ *\r
+ * @param[in] log2\r
+ * Logarithm of 2, as used by fixed prescalers.\r
+ *\r
+ * @return\r
+ * Dividend.\r
******************************************************************************/\r
-__STATIC_INLINE void CMU_Unlock(void)\r
+__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)\r
{\r
- CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;\r
+ return 1 << log2;\r
}\r
\r
\r
+#if defined( _SILICON_LABS_32B_PLATFORM_2 )\r
/***************************************************************************//**\r
* @brief\r
- * Get calibration count register\r
- * @note\r
- * If continuous calibrartion mode is active, calibration busy will allmost\r
- * always be on, and we just need to read the value, where the normal case\r
- * would be that this function call has been triggered by the CALRDY\r
- * interrupt flag.\r
+ * Convert prescaler dividend to logarithmic value. Only works for even\r
+ * numbers equal to 2^n.\r
+ *\r
+ * @param[in] presc\r
+ * Unscaled dividend (dividend = presc + 1).\r
+ *\r
* @return\r
- * Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)\r
- * in the period of DOWNSEL oscillator clock cycles configured by a previous\r
- * write operation to CMU->CALCNT\r
+ * Logarithm of 2, as used by fixed 2^n prescalers.\r
******************************************************************************/\r
-__STATIC_INLINE uint32_t CMU_CalibrateCountGet(void)\r
+__STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)\r
{\r
- /* Wait until calibration completes, UNLESS continuous calibration mode is */\r
- /* active */\r
-#if defined( CMU_CALCTRL_CONT )\r
- if (!(CMU->CALCTRL & CMU_CALCTRL_CONT))\r
- {\r
- while (CMU->STATUS & CMU_STATUS_CALBSY)\r
- ;\r
- }\r
-#else\r
- while (CMU->STATUS & CMU_STATUS_CALBSY)\r
- ;\r
-#endif\r
- return CMU->CALCNT;\r
-}\r
+ uint32_t log2;\r
\r
+ /* Integer prescalers take argument less than 32768. */\r
+ EFM_ASSERT(presc < 32768U);\r
\r
-/***************************************************************************//**\r
- * @brief\r
- * Starts calibration\r
- * @note\r
- * This call is usually invoked after CMU_CalibrateConfig() and possibly\r
- * CMU_CalibrateCont()\r
- ******************************************************************************/\r
-__STATIC_INLINE void CMU_CalibrateStart(void)\r
-{\r
- CMU->CMD = CMU_CMD_CALSTART;\r
-}\r
+ /* Count leading zeroes and "reverse" result */\r
+ log2 = (31U - __CLZ(presc + 1));\r
\r
+ /* Check that presc is a 2^n number */\r
+ EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1));\r
\r
-#if defined( CMU_CMD_CALSTOP )\r
-/***************************************************************************//**\r
- * @brief\r
- * Stop the calibration counters\r
- ******************************************************************************/\r
-__STATIC_INLINE void CMU_CalibrateStop(void)\r
-{\r
- CMU->CMD = CMU_CMD_CALSTOP;\r
+ return log2;\r
}\r
#endif\r
\r
\r
-#if defined( CMU_CALCTRL_CONT )\r
/***************************************************************************//**\r
* @brief\r
- * Configures continuous calibration mode\r
- * @param[in] enable\r
- * If true, enables continuous calibration, if false disables continuous\r
- * calibrartion\r
+ * Unlock the CMU so that writing to locked registers again is possible.\r
******************************************************************************/\r
-__STATIC_INLINE void CMU_CalibrateCont(bool enable)\r
+__STATIC_INLINE void CMU_Unlock(void)\r
{\r
- BITBAND_Peripheral(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);\r
+ CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;\r
}\r
-#endif\r
\r
/** @} (end addtogroup CMU) */\r
/** @} (end addtogroup EM_Library) */\r
#endif\r
\r
#endif /* defined( CMU_PRESENT ) */\r
-#endif /* __SILICON_LABS_EM_CMU_H_ */\r
+#endif /* __SILICON_LABS_EM_CMU_H__ */\r
/***************************************************************************//**\r
* @file em_common.h\r
- * @brief EFM32 general purpose utilities.\r
- * @version 4.0.0\r
+ * @brief Emlib general purpose utilities.\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
+#ifndef __SILICON_LABS_EM_COMMON_H__\r
+#define __SILICON_LABS_EM_COMMON_H__\r
\r
-#ifndef __SILICON_LABS_EM_COMMON_H_\r
-#define __SILICON_LABS_EM_COMMON_H_\r
-\r
-#include <stdint.h>\r
+#include "em_device.h"\r
#include <stdbool.h>\r
\r
-\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
/***************************************************************************//**\r
* @addtogroup COMMON\r
- * @brief EFM32 general purpose utilities.\r
+ * @brief Emlib general purpose utilities.\r
* @{\r
******************************************************************************/\r
\r
#define EFM32_ALIGN(X) _Pragma( STRINGIZE( data_alignment=X ) )\r
#endif\r
\r
-#else\r
+#else // !defined(__GNUC__)\r
\r
/** Macro for getting minimum value. No sideeffects, a and b are evaluated once only. */\r
#define EFM32_MIN(a, b) ({ __typeof__(a) _a = (a); __typeof__(b) _b = (b); _a < _b ? _a : _b; })\r
*/\r
#define EFM32_ALIGN(X)\r
\r
+#endif // !defined(__GNUC__)\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Count trailing number of zero's.\r
+ *\r
+ * @note\r
+ * Disabling SWDClk will disable the debug interface, which may result in\r
+ * a lockout if done early in startup (before debugger is able to halt core).\r
+ *\r
+ * @param[in] value\r
+ * Data value to check for number of trailing zero bits.\r
+ *\r
+ * @return\r
+ * Number of trailing zero's in value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value)\r
+{\r
+#if (__CORTEX_M >= 3)\r
+ return __CLZ(__RBIT(value));\r
+\r
+#else\r
+ uint32_t zeros;\r
+ for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1);\r
+ return zeros;\r
#endif\r
+}\r
\r
/** @} (end addtogroup COMMON) */\r
/** @} (end addtogroup EM_Library) */\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_COMMON_H_ */\r
+#endif /* __SILICON_LABS_EM_COMMON_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief Cyclic Redundancy Check (CRC) API.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_EM_CRC_H__\r
+#define __SILICON_LABS_EM_CRC_H__\r
+\r
+#include "em_device.h"\r
+#if defined(CRC_COUNT) && (CRC_COUNT > 0)\r
+\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup CRC\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ ******************************** ENUMS ************************************\r
+ ******************************************************************************/\r
+\r
+/** CRC width values. */\r
+typedef enum\r
+{\r
+ /** 8 bit (1 byte) CRC code. */\r
+ crcWidth8 = CRC_CTRL_CRCWIDTH_CRCWIDTH8,\r
+\r
+ /** 16 bit (2 byte) CRC code. */\r
+ crcWidth16 = CRC_CTRL_CRCWIDTH_CRCWIDTH16,\r
+\r
+ /** 24 bit (3 byte) CRC code. */\r
+ crcWidth24 = CRC_CTRL_CRCWIDTH_CRCWIDTH24,\r
+\r
+ /** 32 bit (4 byte) CRC code. */\r
+ crcWidth32 = CRC_CTRL_CRCWIDTH_CRCWIDTH32\r
+} CRC_Width_TypeDef;\r
+\r
+\r
+/** CRC byte reverse values. */\r
+typedef enum\r
+{\r
+ /** Most significant CRC bytes are transferred first over air via the Frame\r
+ * Controller (FRC). */\r
+ crcByteOrderNormal = CRC_CTRL_BYTEREVERSE_NORMAL,\r
+\r
+ /** Least significant CRC bytes are transferred first over air via the Frame\r
+ * Controller (FRC). */\r
+ crcByteOrderReversed = CRC_CTRL_BYTEREVERSE_REVERSED\r
+} CRC_ByteOrder_TypeDef;\r
+\r
+\r
+/** CRC bit order values. */\r
+typedef enum\r
+{\r
+ /** Least significant data bit (LSB) is fed first to the CRC generator. */\r
+ crcBitOrderLSBFirst = CRC_CTRL_INPUTBITORDER_LSBFIRST,\r
+\r
+ /** Most significant data bit (MSB) is fed first to the CRC generator. */\r
+ crcBitOrderMSBFirst = CRC_CTRL_INPUTBITORDER_MSBFIRST\r
+} CRC_BitOrder_TypeDef;\r
+\r
+\r
+/** CRC bit reverse values. */\r
+typedef enum\r
+{\r
+ /** The bit ordering of CRC data is the same as defined by the BITORDER field\r
+ * in the Frame Controller. */\r
+ crcBitReverseNormal = CRC_CTRL_BITREVERSE_NORMAL,\r
+\r
+ /** The bit ordering of CRC data is the opposite as defined by the BITORDER\r
+ * field in the Frame Controller. */\r
+ crcBitReverseReversed = CRC_CTRL_BITREVERSE_REVERSED\r
+} CRC_BitReverse_TypeDef;\r
+\r
+\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+/** CRC initialization structure. */\r
+typedef struct\r
+{\r
+ /** Width of the CRC code. */\r
+ CRC_Width_TypeDef crcWidth;\r
+\r
+ /** CRC polynomial value. This value defines POLY[31:0], which is used as the\r
+ * polynomial (in reversed order) during the CRC calculation. If the CRC\r
+ * width is less than 32 bits, the most significant part of this register\r
+ * remains unused.\r
+ * - Set the bit to 1 in the register to get the corresponding degree term\r
+ * appear in the polynomial with a coefficient of 1.\r
+ * - Set the bit to 0 in the register to get the corresponding degree term\r
+ * appear in the polynomial with a coefficient of 0.\r
+ * Note: If a CRC polynomial of size less than 32 bits is to be used, the\r
+ * polynomial value must be shifted so that the highest degree term is\r
+ * located in DATA[0]!\r
+ * Please refer to the CRC sub-chapter "CRC Polynomial" in the documentation\r
+ * for more details! */\r
+ uint32_t crcPoly;\r
+\r
+ /** CRC initialization value. Loaded into the CRC_DATA register upon issuing\r
+ * the INIT command by calling CRC_InitCommand(), or when the Frame\r
+ * Controller (FRC) uses the CRC for automatic CRC calculation and\r
+ * verification. */\r
+ uint32_t initValue;\r
+\r
+ /** Number of bits per input word. This value defines the number of valid\r
+ * input bits in the CRC_INPUTDATA register, or in data coming from the Frame\r
+ * Controller (FRC). The number of bits in each word equals to\r
+ * (BITSPERWORD + EXTRABITSPERWORD + 1), where EXTRABITSPERWORD is taken from\r
+ * the currently active Frame Control Descriptor (FCD). */\r
+ uint8_t bitsPerWord;\r
+\r
+ /** If true, the byte order is reversed and the least significant CRC bytes\r
+ * are transferred first over the air. (description TBD) */\r
+ CRC_ByteOrder_TypeDef byteReverse;\r
+\r
+ /** Bit order. Defines the order in which bits are fed to the CRC generator.\r
+ * This setting applies both to data written to the CRC_INPUTDATA register,\r
+ * and data coming from the Frame Controller (FRC). */\r
+ CRC_BitOrder_TypeDef inputBitOrder;\r
+\r
+ /** Output bit reverse. In most cases, the bit ordering of the CRC value\r
+ * corresponds to the bit ordering of other data transmitted over air. When\r
+ * set, the BITREVERSE field has the possibility to reverse this bit ordering\r
+ * to comply with some protocols. Note that this field does not affect the\r
+ * way the CRC value is calculated, only how it is transmitted over air. */\r
+ CRC_BitReverse_TypeDef bitReverse;\r
+\r
+ /** Enable/disable CRC input data padding. When set, CRC input data is zero-\r
+ * padded, such that the number of bytes over which the CRC value is\r
+ * calculated at least equals the length of the calculated CRC value. If not\r
+ * set, no zero-padding of CRC input data is applied. */\r
+ bool inputPadding;\r
+\r
+ /** If true, CRC input is inverted. */\r
+ bool invInput;\r
+\r
+ /** If true, CRC output to the Frame Controller (FRC) is inverted. */\r
+ bool invOutput;\r
+} CRC_Init_TypeDef;\r
+\r
+/** Default configuration for CRC_Init_TypeDef structure. */\r
+#define CRC_INIT_DEFAULT \\r
+{ \\r
+ crcWidth16, /* CRC width is 16 bits. */ \\r
+ 0x00008408UL, /* Polynomial value of IEEE 802.15.4-2006. */ \\r
+ 0x00000000UL, /* Initialization value. */ \\r
+ 8U, /* 8 bits per word. */ \\r
+ crcByteOrderNormal, /* Byte order is normal. */ \\r
+ crcBitOrderLSBFirst, /* Bit order (TBD). */ \\r
+ crcBitReverseNormal, /* Bit order is not reversed on output. */ \\r
+ false, /* No zero-padding. */ \\r
+ false, /* Input is not inverted. */ \\r
+ false /* Output is not inverted. */ \\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+ ****************************** PROTOTYPES *********************************\r
+ ******************************************************************************/\r
+\r
+void CRC_Init(CRC_Init_TypeDef const *init);\r
+void CRC_Reset(void);\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Issues a command to initialize the CRC calculation.\r
+ *\r
+ * @details\r
+ * This function issues the command INITIALIZE in CRC_CMD that initializes the\r
+ * CRC calculation by writing the initial values to the DATA register.\r
+ *\r
+ * @note\r
+ * Internal notes:\r
+ * Initialize in CRC_CMD\r
+ * Conclude on reference of parameters. Register names or config struct members?\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRC_InitCommand(void)\r
+{\r
+ CRC->CMD = CRC_CMD_INITIALIZE;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the initialization value of the CRC.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRC_InitValueSet(uint32_t initValue)\r
+{\r
+ CRC->INIT = initValue;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Writes data to the input data register of the CRC.\r
+ *\r
+ * @details\r
+ * Use this function to write input data to the CRC when the FRC is not being\r
+ * used for automatic handling of the CRC. The CRC calculation is based on\r
+ * the provided input data using the configured CRC polynomial.\r
+ *\r
+ * @param[in] data\r
+ * Data to be written to the input data register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRC_InputDataWrite(uint16_t data)\r
+{\r
+ CRC->INPUTDATA = (uint32_t)data;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Reads the data register of the CRC.\r
+ *\r
+ * @details\r
+ * Use this function to read the calculated CRC value.\r
+ *\r
+ * @return\r
+ * Content of the CRC data register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRC_DataRead(void)\r
+{\r
+ return CRC->DATA;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Gets if the CRC is busy.\r
+ *\r
+ * @details\r
+ * Returns true when the CRC module is busy, false otherwise.\r
+ *\r
+ * @return\r
+ * CRC busy flag.\r
+ * @li true - CRC module is busy.\r
+ * @li false - CRC module is not busy.\r
+ ******************************************************************************/\r
+__STATIC_INLINE bool CRC_BusyGet(void)\r
+{\r
+ return (bool)((CRC->STATUS & _CRC_STATUS_BUSY_MASK)\r
+ >> _CRC_STATUS_BUSY_SHIFT);\r
+}\r
+\r
+\r
+/** @} (end addtogroup CRC) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* defined(CRC_COUNT) && (CRC_COUNT > 0) */\r
+#endif /* __SILICON_LABS_EM_CRC_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file em_cryotimer.h\r
+ * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef EM_CRYOTIMER_H__\r
+#define EM_CRYOTIMER_H__\r
+\r
+#include <stdbool.h>\r
+#include "em_device.h"\r
+#include "em_bus.h"\r
+\r
+#if defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1)\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup CRYOTIMER\r
+ * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) Peripheral API\r
+ *\r
+ * @details\r
+ * The user is responsible for choosing which oscillator to use for the\r
+ * CRYOTIMER. The oscillator that is choosen must be enabled and ready before\r
+ * calling this @ref CRYOTIMER_Init function. See @ref CMU_OscillatorEnable\r
+ * for details of how to enable and wait for an oscillator to become ready.\r
+ * Note that ULFRCO is always ready while LFRCO and LFXO must be enable by\r
+ * the user.\r
+ *\r
+ * @details\r
+ * Note that the only oscillator which is running in EM3 is ULFRCO. Keep this\r
+ * in mind when choosing which oscillator to use for the CRYOTIMER.\r
+ *\r
+ * @details\r
+ * Special care must be taken if the user wants the CRYOTIMER to run during\r
+ * EM4. All the low frequency oscillators can be used in EM4, however the\r
+ * oscillator that is used must be be configured to be retained when going\r
+ * into EM4. This can be configured by using functions in the @ref EMU module.\r
+ * See @ref EMU_EM4Init and @ref EMU_EM4Init_TypeDef. If an oscillator is\r
+ * retained in EM4 the user is also responsible for unlatching the retained\r
+ * configuration on a wakeup from EM4.\r
+ *\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ ********************************* ENUM ************************************\r
+ ******************************************************************************/\r
+\r
+/** Prescaler selection. */\r
+typedef enum\r
+{\r
+ cryotimerPresc_1 = _CRYOTIMER_CTRL_PRESC_DIV1, /**< Divide clock by 1. */\r
+ cryotimerPresc_2 = _CRYOTIMER_CTRL_PRESC_DIV2, /**< Divide clock by 2. */\r
+ cryotimerPresc_4 = _CRYOTIMER_CTRL_PRESC_DIV4, /**< Divide clock by 4. */\r
+ cryotimerPresc_8 = _CRYOTIMER_CTRL_PRESC_DIV8, /**< Divide clock by 8. */\r
+ cryotimerPresc_16 = _CRYOTIMER_CTRL_PRESC_DIV16, /**< Divide clock by 16. */\r
+ cryotimerPresc_32 = _CRYOTIMER_CTRL_PRESC_DIV32, /**< Divide clock by 32. */\r
+ cryotimerPresc_64 = _CRYOTIMER_CTRL_PRESC_DIV64, /**< Divide clock by 64. */\r
+ cryotimerPresc_128 = _CRYOTIMER_CTRL_PRESC_DIV128, /**< Divide clock by 128. */\r
+} CRYOTIMER_Presc_TypeDef;\r
+\r
+/** Low frequency oscillator selection. */\r
+typedef enum \r
+{\r
+ cryotimerOscLFRCO = _CRYOTIMER_CTRL_OSCSEL_LFRCO, /**< Select Low Frequency RC Oscillator. */\r
+ cryotimerOscLFXO = _CRYOTIMER_CTRL_OSCSEL_LFXO, /**< Select Low Frequency Crystal Oscillator. */\r
+ cryotimerOscULFRCO = _CRYOTIMER_CTRL_OSCSEL_ULFRCO, /**< Select Ultra Low Frequency RC Oscillator. */\r
+} CRYOTIMER_Osc_TypeDef;\r
+\r
+/** Period selection value */\r
+typedef enum\r
+{\r
+ cryotimerPeriod_1 = 0, /**< Wakeup event after every Pre-scaled clock cycle. */\r
+ cryotimerPeriod_2 = 1, /**< Wakeup event after 2 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_4 = 2, /**< Wakeup event after 4 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_8 = 3, /**< Wakeup event after 8 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_16 = 4, /**< Wakeup event after 16 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_32 = 5, /**< Wakeup event after 32 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_64 = 6, /**< Wakeup event after 64 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_128 = 7, /**< Wakeup event after 128 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_256 = 8, /**< Wakeup event after 256 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_512 = 9, /**< Wakeup event after 512 Pre-scaled clock cycles. */\r
+ cryotimerPeriod_1k = 10, /**< Wakeup event after 1k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_2k = 11, /**< Wakeup event after 2k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_4k = 12, /**< Wakeup event after 4k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_8k = 13, /**< Wakeup event after 8k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_16k = 14, /**< Wakeup event after 16k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_32k = 15, /**< Wakeup event after 32k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_64k = 16, /**< Wakeup event after 64k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_128k = 17, /**< Wakeup event after 128k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_256k = 18, /**< Wakeup event after 256k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_512k = 19, /**< Wakeup event after 512k Pre-scaled clock cycles. */\r
+ cryotimerPeriod_1m = 20, /**< Wakeup event after 1m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_2m = 21, /**< Wakeup event after 2m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_4m = 22, /**< Wakeup event after 4m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_8m = 23, /**< Wakeup event after 8m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_16m = 24, /**< Wakeup event after 16m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_32m = 25, /**< Wakeup event after 32m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_64m = 26, /**< Wakeup event after 64m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_128m = 27, /**< Wakeup event after 128m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_256m = 28, /**< Wakeup event after 256m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_512m = 29, /**< Wakeup event after 512m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_1024m = 30, /**< Wakeup event after 1024m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_2048m = 31, /**< Wakeup event after 2048m Pre-scaled clock cycles. */\r
+ cryotimerPeriod_4096m = 32, /**< Wakeup event after 4096m Pre-scaled clock cycles. */\r
+} CRYOTIMER_Period_TypeDef;\r
+\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+/** CRYOTIMER initialization structure. */\r
+typedef struct\r
+{\r
+ /** Enable/disable counting when initialization is completed. */\r
+ bool enable;\r
+\r
+ /** Enable/disable timer counting during debug halt. */\r
+ bool debugRun;\r
+\r
+ /** Enable/disable EM4 Wakeup. */\r
+ bool em4Wakeup;\r
+\r
+ /** Select the oscillator for the CRYOTIMER. */\r
+ CRYOTIMER_Osc_TypeDef osc;\r
+\r
+ /** Prescaler. */\r
+ CRYOTIMER_Presc_TypeDef presc;\r
+\r
+ /** Period between wakeup event/interrupt. */\r
+ CRYOTIMER_Period_TypeDef period;\r
+} CRYOTIMER_Init_TypeDef;\r
+\r
+/*******************************************************************************\r
+ ******************************* DEFINES ***********************************\r
+ ******************************************************************************/\r
+\r
+/** Default CRYOTIMER init structure. */\r
+#define CRYOTIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Start counting when init done. */ \\r
+ false, /* Disable CRYOTIMER during debug halt. */ \\r
+ false, /* Disable EM4 wakeup. */ \\r
+ cryotimerOscLFRCO, /* Select Low Frequency RC Oscillator. */ \\r
+ cryotimerPresc_1, /* LF Oscillator frequency undivided. */ \\r
+ cryotimerPeriod_4096m, /* Wakeup event after 4096M pre-scaled clock cycles. */ \\r
+}\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear the CRYOTIMER period interrupt.\r
+ *\r
+ * @param[in] flags\r
+ * CRYOTIMER interrupt sources to clear. Use CRYOTIMER_IFC_PERIOD\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_IntClear(uint32_t flags)\r
+{\r
+ CRYOTIMER->IFC = flags & _CRYOTIMER_IFC_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the CRYOTIMER interrupt flag.\r
+ * \r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending CRYOTIMER interrupt sources.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRYOTIMER_IntGet(void)\r
+{\r
+ return CRYOTIMER->IF;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending CRYOTIMER interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled CRYOTIMER interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in CRYOTIMER_IEN and\r
+ * - the pending interrupt flags CRYOTIMER_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRYOTIMER_IntGetEnabled(void)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = CRYOTIMER->IEN & _CRYOTIMER_IEN_MASK;\r
+ return CRYOTIMER->IF & ien;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more CRYOTIMER interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * CRYOTIMER interrupt sources to enable. Use CRYOTIMER_IEN_PERIOD.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_IntEnable(uint32_t flags)\r
+{\r
+ CRYOTIMER->IEN |= (flags & _CRYOTIMER_IEN_MASK);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more CRYOTIMER interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * CRYOTIMER interrupt sources to disable. Use CRYOTIMER_IEN_PERIOD.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_IntDisable(uint32_t flags)\r
+{\r
+ CRYOTIMER->IEN &= ~(flags & _CRYOTIMER_IEN_MASK);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the CRYOTIMER period interrupt flag.\r
+ *\r
+ * @note\r
+ * Writes 1 to the interrupt flag set register.\r
+ *\r
+ * @param[in] flags\r
+ * CRYOTIMER interrupt sources to set to pending. Use CRYOTIMER_IFS_PERIOD.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_IntSet(uint32_t flags)\r
+{\r
+ CRYOTIMER->IFS = flags & _CRYOTIMER_IFS_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the CRYOTIMER period select\r
+ *\r
+ * @note\r
+ * Sets the duration between the Interrupts/Wakeup events based on \r
+ * the pre-scaled clock.\r
+ *\r
+ * @param[in] period\r
+ * 2^period is the number of clock cycles before a wakeup event or \r
+ * interrupt is triggered. The CRYOTIMER_Periodsel_TypeDef enum can \r
+ * be used a convenience type when calling this function.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_PeriodSet(uint32_t period)\r
+{\r
+ CRYOTIMER->PERIODSEL = period & _CRYOTIMER_PERIODSEL_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the CRYOTIMER period select value\r
+ *\r
+ * @note\r
+ * Gets the duration between the Interrupts/Wakeup events in the \r
+ * CRYOTIMER.\r
+ *\r
+ * @return\r
+ * Duration between the interrupts/wakeup events. Returns the value\r
+ * of the PERIODSEL register. The number of clock cycles can be calculated\r
+ * as the 2^n where n is the return value of this function.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRYOTIMER_PeriodGet(void)\r
+{\r
+ return CRYOTIMER->PERIODSEL;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the CRYOTIMER counter value\r
+ *\r
+ * @return\r
+ * Returns the current CRYOTIMER counter value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRYOTIMER_CounterGet(void)\r
+{\r
+ return CRYOTIMER->CNT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable/disable EM4 wakeup capability.\r
+ *\r
+ * @param[in] enable\r
+ * True to enable EM4 wakeup, false to disable.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_EM4WakeupEnable(bool enable)\r
+{\r
+ BUS_RegBitWrite((&CRYOTIMER->EM4WUEN), _CRYOTIMER_EM4WUEN_EM4WU_SHIFT, enable);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable/disable the CRYOTIMER.\r
+ *\r
+ * @param[in] enable\r
+ * True to enable the CRYOTIMER, false to disable.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYOTIMER_Enable(bool enable)\r
+{\r
+ BUS_RegBitWrite((&CRYOTIMER->CTRL), _CRYOTIMER_CTRL_EN_SHIFT, enable);\r
+}\r
+\r
+void CRYOTIMER_Init(const CRYOTIMER_Init_TypeDef *init);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @} (end addtogroup CRYOTIMER) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#endif /* defined(CRYOTIMER_PRESENT) && (CRYOTIMER_COUNT == 1) */\r
+#endif /* EM_CRYOTIMER_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file em_crypto.h\r
+ * @brief Cryptography accelerator peripheral API\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+#ifndef __SILICON_LABS_EM_CRYPTO_H__\r
+#define __SILICON_LABS_EM_CRYPTO_H__\r
+\r
+#include "em_device.h"\r
+\r
+#if defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0)\r
+\r
+#include "em_bus.h"\r
+#include <stdbool.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup CRYPTO\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+ /*******************************************************************************\r
+ ****************************** DEFINES ***********************************\r
+ ******************************************************************************/\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/** Data sizes used by CRYPTO operations. */\r
+#define CRYPTO_DATA_SIZE_IN_BITS (128)\r
+#define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS/8)\r
+#define CRYPTO_DATA_SIZE_IN_32BIT_WORDS (CRYPTO_DATA_SIZE_IN_BYTES/sizeof(uint32_t))\r
+\r
+#define CRYPTO_KEYBUF_SIZE_IN_BITS (256)\r
+#define CRYPTO_KEYBUF_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS/8)\r
+#define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))\r
+\r
+#define CRYPTO_DDATA_SIZE_IN_BITS (256)\r
+#define CRYPTO_DDATA_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS/8)\r
+#define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))\r
+\r
+#define CRYPTO_QDATA_SIZE_IN_BITS (512)\r
+#define CRYPTO_QDATA_SIZE_IN_BYTES (CRYPTO_QDATA_SIZE_IN_BITS/8)\r
+#define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS (CRYPTO_QDATA_SIZE_IN_BYTES/sizeof(uint32_t))\r
+\r
+#define CRYPTO_DATA260_SIZE_IN_32BIT_WORDS (9)\r
+\r
+/** SHA-1 digest sizes */\r
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_BITS (160)\r
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS/8)\r
+\r
+/** SHA-256 digest sizes */\r
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_BITS (256)\r
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS/8)\r
+\r
+/**\r
+ * Read and write all 260 bits of DDATA0 when in 260 bit mode.\r
+ */\r
+#define CRYPTO_DDATA0_260_BITS_READ(bigint260) CRYPTO_DData0Read260(bigint260)\r
+#define CRYPTO_DDATA0_260_BITS_WRITE(bigint260) CRYPTO_DData0Write260(bigint260)\r
+/** @endcond */\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/**\r
+ * Instruction sequence load macros CRYPTO_SEQ_LOAD_X (where X is in the range\r
+ * 1-20). E.g. @ref CRYPTO_SEQ_LOAD_20.\r
+ * Use these macros in order for faster execution than the function API.\r
+ */\r
+#define CRYPTO_SEQ_LOAD_1(a1) { \\r
+ CRYPTO->SEQ0 = a1 | (CRYPTO_CMD_INSTR_END<<8);}\r
+#define CRYPTO_SEQ_LOAD_2(a1, a2) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_END<<16);}\r
+#define CRYPTO_SEQ_LOAD_3(a1, a2, a3) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_END<<24);}\r
+#define CRYPTO_SEQ_LOAD_4(a1, a2, a3, a4) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = CRYPTO_CMD_INSTR_END;}\r
+#define CRYPTO_SEQ_LOAD_5(a1, a2, a3, a4, a5) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (CRYPTO_CMD_INSTR_END<<8);}\r
+#define CRYPTO_SEQ_LOAD_6(a1, a2, a3, a4, a5, a6) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_END<<16);}\r
+#define CRYPTO_SEQ_LOAD_7(a1, a2, a3, a4, a5, a6, a7) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_END<<24);}\r
+#define CRYPTO_SEQ_LOAD_8(a1, a2, a3, a4, a5, a6, a7, a8) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = CRYPTO_CMD_INSTR_END;}\r
+#define CRYPTO_SEQ_LOAD_9(a1, a2, a3, a4, a5, a6, a7, a8, a9) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (CRYPTO_CMD_INSTR_END<<8);}\r
+#define CRYPTO_SEQ_LOAD_10(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_END<<16);}\r
+#define CRYPTO_SEQ_LOAD_11(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_END<<24);}\r
+#define CRYPTO_SEQ_LOAD_12(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = CRYPTO_CMD_INSTR_END;}\r
+#define CRYPTO_SEQ_LOAD_13(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END<<8);}\r
+#define CRYPTO_SEQ_LOAD_14(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_END<<16);}\r
+#define CRYPTO_SEQ_LOAD_15(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_END<<24);}\r
+#define CRYPTO_SEQ_LOAD_16(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = CRYPTO_CMD_INSTR_END;}\r
+#define CRYPTO_SEQ_LOAD_17(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END<<8);}\r
+#define CRYPTO_SEQ_LOAD_18(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_END<<16);}\r
+#define CRYPTO_SEQ_LOAD_19(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_END<<24);}\r
+#define CRYPTO_SEQ_LOAD_20(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24);}\r
+/** @endcond */\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+/**\r
+ * Instruction sequence execution macros CRYPTO_EXECUTE_X (where X is in the range\r
+ * 1-20). E.g. @ref CRYPTO_EXECUTE_19.\r
+ * Use these macros in order for faster execution than the function API.\r
+ */\r
+#define CRYPTO_EXECUTE_1(a1) { \\r
+ CRYPTO->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC<<8); }\r
+#define CRYPTO_EXECUTE_2(a1, a2) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }\r
+#define CRYPTO_EXECUTE_3(a1, a2, a3) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }\r
+#define CRYPTO_EXECUTE_4(a1, a2, a3, a4) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = CRYPTO_CMD_INSTR_EXEC; }\r
+#define CRYPTO_EXECUTE_5(a1, a2, a3, a4, a5) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC<<8); }\r
+#define CRYPTO_EXECUTE_6(a1, a2, a3, a4, a5, a6) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }\r
+#define CRYPTO_EXECUTE_7(a1, a2, a3, a4, a5, a6, a7) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }\r
+#define CRYPTO_EXECUTE_8(a1, a2, a3, a4, a5, a6, a7, a8) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = CRYPTO_CMD_INSTR_EXEC; }\r
+#define CRYPTO_EXECUTE_9(a1, a2, a3, a4, a5, a6, a7, a8, a9) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC<<8); }\r
+#define CRYPTO_EXECUTE_10(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }\r
+#define CRYPTO_EXECUTE_11(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }\r
+#define CRYPTO_EXECUTE_12(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = CRYPTO_CMD_INSTR_EXEC; }\r
+#define CRYPTO_EXECUTE_13(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC<<8); }\r
+#define CRYPTO_EXECUTE_14(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }\r
+#define CRYPTO_EXECUTE_15(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }\r
+#define CRYPTO_EXECUTE_16(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = CRYPTO_CMD_INSTR_EXEC; }\r
+#define CRYPTO_EXECUTE_17(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC<<8); }\r
+#define CRYPTO_EXECUTE_18(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }\r
+#define CRYPTO_EXECUTE_19(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }\r
+#define CRYPTO_EXECUTE_20(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \\r
+ CRYPTO->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \\r
+ CRYPTO->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \\r
+ CRYPTO->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \\r
+ CRYPTO->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \\r
+ CRYPTO->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24); \\r
+ CRYPTO_InstructionSequenceExecute();}\r
+/** @endcond */\r
+\r
+/*******************************************************************************\r
+ ****************************** TYPEDEFS ***********************************\r
+ ******************************************************************************/\r
+\r
+/**\r
+ * CRYPTO data types used for data load functions. This data type is\r
+ * capable of storing a 128 bits value as used in the crypto DATA\r
+ * registers\r
+ */\r
+typedef uint32_t CRYPTO_Data_TypeDef[CRYPTO_DATA_SIZE_IN_32BIT_WORDS];\r
+\r
+/**\r
+ * CRYPTO data type used for data load functions. This data type\r
+ * is capable of storing a 256 bits value as used in the crypto DDATA\r
+ * registers\r
+ */\r
+typedef uint32_t CRYPTO_DData_TypeDef[CRYPTO_DDATA_SIZE_IN_32BIT_WORDS];\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+typedef uint32_t* CRYPTO_DDataPtr_TypeDef;\r
+/** @endcond */\r
+\r
+/**\r
+ * CRYPTO data type used for data load functions. This data type is\r
+ * capable of storing a 512 bits value as used in the crypto QDATA\r
+ * registers\r
+ */\r
+typedef uint32_t CRYPTO_QData_TypeDef[CRYPTO_QDATA_SIZE_IN_32BIT_WORDS];\r
+\r
+/**\r
+ * CRYPTO data type used for data load functions. This data type is\r
+ * capable of storing a 260 bits value as used by the @ref CRYPTO_DData0Write260\r
+ * function.\r
+ *\r
+ * Note that this data type is multiple of 32 bit words, so the\r
+ * actual storage used by this type is 32x9=288 bits.\r
+ */\r
+typedef uint32_t CRYPTO_Data260_TypeDef[CRYPTO_DATA260_SIZE_IN_32BIT_WORDS];\r
+\r
+/**\r
+ * CRYPTO data type used for data load functions. This data type is\r
+ * capable of storing 256 bits as used in the crypto KEYBUF register.\r
+ */\r
+typedef uint32_t CRYPTO_KeyBuf_TypeDef[CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS];\r
+\r
+/**\r
+ * CRYPTO Data registers. These register are used to load 128 bit values as\r
+ * input and output data for cryptographic and big integer arithmetic\r
+ * functions of the CRYPTO module.\r
+ */\r
+typedef enum\r
+{\r
+ cryptoRegDATA0 = (uint32_t) &CRYPTO->DATA0, /**< 128 bit DATA0 register */\r
+ cryptoRegDATA1 = (uint32_t) &CRYPTO->DATA1, /**< 128 bit DATA1 register */\r
+ cryptoRegDATA2 = (uint32_t) &CRYPTO->DATA2, /**< 128 bit DATA2 register */\r
+ cryptoRegDATA3 = (uint32_t) &CRYPTO->DATA3, /**< 128 bit DATA3 register */\r
+ cryptoRegDATA0XOR = (uint32_t) &CRYPTO->DATA0XOR, /**< 128 bit DATA0XOR register */\r
+} CRYPTO_DataReg_TypeDef;\r
+\r
+/**\r
+ * CRYPTO DData (Double Data) registers. These registers are used to load\r
+ * 256 bit values as input and output data for cryptographic and big integer\r
+ * arithmetic functions of the CRYPTO module.\r
+ */\r
+typedef enum\r
+{\r
+ cryptoRegDDATA0 = (uint32_t) &CRYPTO->DDATA0, /**< 256 bit DDATA0 register */\r
+ cryptoRegDDATA1 = (uint32_t) &CRYPTO->DDATA1, /**< 256 bit DDATA1 register */\r
+ cryptoRegDDATA2 = (uint32_t) &CRYPTO->DDATA2, /**< 256 bit DDATA2 register */\r
+ cryptoRegDDATA3 = (uint32_t) &CRYPTO->DDATA3, /**< 256 bit DDATA3 register */\r
+ cryptoRegDDATA4 = (uint32_t) &CRYPTO->DDATA4, /**< 256 bit DDATA4 register */\r
+ cryptoRegDDATA0BIG = (uint32_t) &CRYPTO->DDATA0BIG, /**< 256 bit DDATA0BIG register, big endian access to DDATA0 */\r
+} CRYPTO_DDataReg_TypeDef;\r
+\r
+/**\r
+ * CRYPTO QData (Quad data) registers. These registers are used to load 512 bit\r
+ * values as input and output data for cryptographic and big integer arithmetic\r
+ * functions of the CRYPTO module.\r
+ */\r
+typedef enum\r
+{\r
+ cryptoRegQDATA0 = (uint32_t) &CRYPTO->QDATA0, /**< 512 bit QDATA0 register */\r
+ cryptoRegQDATA1 = (uint32_t) &CRYPTO->QDATA1, /**< 512 bit QDATA1 register */\r
+ cryptoRegQDATA1BIG = (uint32_t) &CRYPTO->QDATA1BIG, /**< 512 bit QDATA1BIG register, big-endian access to QDATA1 */\r
+} CRYPTO_QDataReg_TypeDef;\r
+\r
+/** CRYPTO modulus types. */\r
+typedef enum\r
+{\r
+ cryptoModulusBin256 = CRYPTO_WAC_MODULUS_BIN256, /**< Generic 256 bit modulus 2^256 */\r
+ cryptoModulusBin128 = CRYPTO_WAC_MODULUS_BIN128, /**< Generic 128 bit modulus 2^128 */\r
+ cryptoModulusGcmBin128 = CRYPTO_WAC_MODULUS_GCMBIN128, /**< GCM 128 bit modulus = 2^128 + 2^7 + 2^2 + 2 + 1 */\r
+ cryptoModulusEccB233 = CRYPTO_WAC_MODULUS_ECCBIN233P, /**< ECC B233 prime modulus = 2^233 + 2^74 + 1 */\r
+ cryptoModulusEccB163 = CRYPTO_WAC_MODULUS_ECCBIN163P, /**< ECC B163 prime modulus = 2^163 + 2^7 + 2^6 + 2^3 + 1 */\r
+ cryptoModulusEccP256 = CRYPTO_WAC_MODULUS_ECCPRIME256P, /**< ECC P256 prime modulus = 2^256 - 2^224 + 2^192 + 2^96 - 1 */\r
+ cryptoModulusEccP224 = CRYPTO_WAC_MODULUS_ECCPRIME224P, /**< ECC P224 prime modulus = 2^224 - 2^96 - 1 */\r
+ cryptoModulusEccP192 = CRYPTO_WAC_MODULUS_ECCPRIME192P, /**< ECC P192 prime modulus = 2^192 - 2^64 - 1 */\r
+ cryptoModulusEccB233Order = CRYPTO_WAC_MODULUS_ECCBIN233N, /**< ECC B233 order modulus */\r
+ cryptoModulusEccB233KOrder = CRYPTO_WAC_MODULUS_ECCBIN233KN, /**< ECC B233K order modulus */\r
+ cryptoModulusEccB163Order = CRYPTO_WAC_MODULUS_ECCBIN163N, /**< ECC B163 order modulus */\r
+ cryptoModulusEccB163KOrder = CRYPTO_WAC_MODULUS_ECCBIN163KN, /**< ECC B163K order modulus */\r
+ cryptoModulusEccP256Order = CRYPTO_WAC_MODULUS_ECCPRIME256N, /**< ECC P256 order modulus */\r
+ cryptoModulusEccP224Order = CRYPTO_WAC_MODULUS_ECCPRIME224N, /**< ECC P224 order modulus */\r
+ cryptoModulusEccP192Order = CRYPTO_WAC_MODULUS_ECCPRIME192N /**< ECC P192 order modulus */\r
+} CRYPTO_ModulusType_TypeDef;\r
+\r
+/** CRYPTO multiplication widths for wide arithmetic operations. */\r
+typedef enum\r
+{\r
+ cryptoMulOperand256Bits = CRYPTO_WAC_MULWIDTH_MUL256, /**< 256 bits operands */\r
+ cryptoMulOperand128Bits = CRYPTO_WAC_MULWIDTH_MUL128, /**< 128 bits operands */\r
+ cryptoMulOperandModulusBits = CRYPTO_WAC_MULWIDTH_MULMOD /**< MUL operand width\r
+ is specified by the\r
+ modulus type.*/\r
+} CRYPTO_MulOperandWidth_TypeDef;\r
+\r
+/** CRYPTO result widths for MUL operations. */\r
+typedef enum\r
+{\r
+ cryptoResult128Bits = CRYPTO_WAC_RESULTWIDTH_128BIT, /**< Multiplication result width is 128 bits*/\r
+ cryptoResult256Bits = CRYPTO_WAC_RESULTWIDTH_256BIT, /**< Multiplication result width is 256 bits*/\r
+ cryptoResult260Bits = CRYPTO_WAC_RESULTWIDTH_260BIT /**< Multiplication result width is 260 bits*/\r
+} CRYPTO_ResultWidth_TypeDef;\r
+\r
+/** CRYPTO result widths for MUL operations. */\r
+typedef enum\r
+{\r
+ cryptoInc1byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH1, /**< inc width is 1 byte*/\r
+ cryptoInc2byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH2, /**< inc width is 2 byte*/\r
+ cryptoInc3byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH3, /**< inc width is 3 byte*/\r
+ cryptoInc4byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH4 /**< inc width is 4 byte*/\r
+} CRYPTO_IncWidth_TypeDef;\r
+\r
+/** CRYPTO key width. */\r
+typedef enum\r
+{\r
+ cryptoKey128Bits = 8, /**< Key width is 128 bits*/\r
+ cryptoKey256Bits = 16, /**< Key width is 256 bits*/\r
+} CRYPTO_KeyWidth_TypeDef;\r
+\r
+/**\r
+ * The max number of crypto instructions in an instruction sequence\r
+ */\r
+#define CRYPTO_MAX_SEQUENCE_INSTRUCTIONS (20)\r
+\r
+/**\r
+ * Instruction sequence type.\r
+ * The user should fill in the desired operations from step1, then step2 etc.\r
+ * The CRYPTO_CMD_INSTR_END marks the end of the sequence.\r
+ * Bit fields are used to format the memory layout of the struct equal to the\r
+ * sequence registers in the CRYPTO module.\r
+ */\r
+typedef uint8_t CRYPTO_InstructionSequence_TypeDef[CRYPTO_MAX_SEQUENCE_INSTRUCTIONS];\r
+\r
+/** Default instruction sequence consisting of all ENDs. The user can\r
+ initialize the instruction sequence with this default value set, and fill\r
+ in the desired operations from step 1. The first END instruction marks\r
+ the end of the sequence. */\r
+#define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT \\r
+ {CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \\r
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \\r
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \\r
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \\r
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \\r
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \\r
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END}\r
+\r
+/** SHA-1 Digest type. */\r
+typedef uint8_t CRYPTO_SHA1_Digest_TypeDef[CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES];\r
+\r
+/** SHA-256 Digest type. */\r
+typedef uint8_t CRYPTO_SHA256_Digest_TypeDef[CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES];\r
+\r
+/**\r
+ * @brief\r
+ * AES counter modification function pointer.\r
+ *\r
+ * @note\r
+ * This is defined in order for backwards compatibility with EFM32 em_aes.h.\r
+ * The CRYPTO implementation of Counter mode does not support counter update\r
+ * callbacks.\r
+ * \r
+ * @param[in] ctr Counter value to be modified.\r
+ */\r
+typedef void (*CRYPTO_AES_CtrFuncPtr_TypeDef)(uint8_t * ctr);\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the modulus type used for wide arithmetic operations.\r
+ *\r
+ * @details\r
+ * This function sets the modulus type to be used by the Modulus instructions\r
+ * of the CRYPTO module.\r
+ *\r
+ * @param[in] modType Modulus type.\r
+ ******************************************************************************/\r
+void CRYPTO_ModulusSet(CRYPTO_ModulusType_TypeDef modType);\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the number of bits in the operands of the MUL instruction.\r
+ *\r
+ * @details\r
+ * This function sets the number of bits to be used in the operands of\r
+ * the MUL instruction.\r
+ *\r
+ * @param[in] mulOperandWidth Multiplication width in bits.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_MulOperandWidthSet(CRYPTO_MulOperandWidth_TypeDef mulOperandWidth)\r
+{\r
+ uint32_t temp = CRYPTO->WAC & (~_CRYPTO_WAC_MULWIDTH_MASK);\r
+ CRYPTO->WAC = temp | mulOperandWidth;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the width of the results of the non-modulus instructions.\r
+ *\r
+ * @details\r
+ * This function sets the result width of the non-modulus instructions.\r
+ *\r
+ * @param[in] resultWidth Result width of non-modulus instructions.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_ResultWidthSet(CRYPTO_ResultWidth_TypeDef resultWidth)\r
+{\r
+ uint32_t temp = CRYPTO->WAC & (~_CRYPTO_WAC_RESULTWIDTH_MASK);\r
+ CRYPTO->WAC = temp | resultWidth;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the width of the DATA1 increment instruction DATA1INC.\r
+ *\r
+ * @details\r
+ * This function sets the width of the DATA1 increment instruction\r
+ * @ref CRYPTO_CMD_INSTR_DATA1INC.\r
+ *\r
+ * @param[in] incWidth incrementation width.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_IncWidthSet(CRYPTO_IncWidth_TypeDef incWidth)\r
+{\r
+ uint32_t temp = CRYPTO->CTRL & (~_CRYPTO_CTRL_INCWIDTH_MASK);\r
+ CRYPTO->CTRL = temp | incWidth;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Write a 128 bit value into a crypto register.\r
+ *\r
+ * @note\r
+ * This function provide a low-level api for writing to the multi-word\r
+ * registers in the crypto peripheral. Applications should prefer to use\r
+ * @ref CRYPTO_DataWrite, @ref CRYPTO_DDataWrite or @ref CRYPTO_QDataWrite\r
+ * for writing to the DATA, DDATA and QDATA registers.\r
+ *\r
+ * @param[in] reg\r
+ * Pointer to the crypto register.\r
+ *\r
+ * @param[in] val\r
+ * This is a pointer to 4 32 bit integers that contains the 128 bit value\r
+ * which will be written to the crypto register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_BurstToCrypto(volatile uint32_t * reg, const uint32_t * val)\r
+{\r
+ /* Load data from memory into local registers. */\r
+ register uint32_t v0 = val[0];\r
+ register uint32_t v1 = val[1];\r
+ register uint32_t v2 = val[2];\r
+ register uint32_t v3 = val[3];\r
+ /* Store data to CRYPTO */\r
+ *reg = v0;\r
+ *reg = v1;\r
+ *reg = v2;\r
+ *reg = v3;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Read a 128 bit value from a crypto register.\r
+ *\r
+ * @note\r
+ * This function provide a low-level api for reading one of the multi-word\r
+ * registers in the crypto peripheral. Applications should prefer to use\r
+ * @ref CRYPTO_DataRead, @ref CRYPTO_DDataRead or @ref CRYPTO_QDataRead\r
+ * for reading the value of the DATA, DDATA and QDATA registers.\r
+ *\r
+ * @param[in] reg\r
+ * Pointer to the crypto register.\r
+ *\r
+ * @param[out] val\r
+ * This is a pointer to an array that is capable of holding 4 32 bit integers\r
+ * that will be filled with the 128 bit value from the crypto register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_BurstFromCrypto(volatile uint32_t * reg, uint32_t * val)\r
+{\r
+ /* Load data from CRYPTO into local registers. */\r
+ register uint32_t v0 = *reg;\r
+ register uint32_t v1 = *reg;\r
+ register uint32_t v2 = *reg;\r
+ register uint32_t v3 = *reg;\r
+ /* Store data to memory */\r
+ val[0] = v0;\r
+ val[1] = v1;\r
+ val[2] = v2;\r
+ val[3] = v3;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Write 128 bits of data to a DATAX register in the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Write 128 bits of data to a DATAX register in the crypto module. The data\r
+ * value is typically input to a big integer operation (see crypto\r
+ * instructions).\r
+ *\r
+ * @param[in] dataReg The 128 bit DATA register.\r
+ * @param[in] val Value of the data to write to the DATA register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_DataWrite(CRYPTO_DataReg_TypeDef dataReg,\r
+ const CRYPTO_Data_TypeDef val)\r
+{\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)dataReg, val);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Read 128 bits of data from a DATAX register in the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Read 128 bits of data from a DATAX register in the crypto module. The data\r
+ * value is typically output from a big integer operation (see crypto\r
+ * instructions)\r
+ *\r
+ * @param[in] dataReg The 128 bit DATA register.\r
+ * @param[out] val Location where to store the value in memory.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_DataRead(CRYPTO_DataReg_TypeDef dataReg,\r
+ CRYPTO_Data_TypeDef val)\r
+{\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)dataReg, val);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Write 256 bits of data to a DDATAX register in the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Write 256 bits of data into a DDATAX (Double Data) register in the crypto\r
+ * module. The data value is typically input to a big integer operation (see\r
+ * crypto instructions).\r
+ *\r
+ * @param[in] ddataReg The 256 bit DDATA register.\r
+ * @param[in] val Value of the data to write to the DDATA register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_DDataWrite(CRYPTO_DDataReg_TypeDef ddataReg,\r
+ const CRYPTO_DData_TypeDef val)\r
+{\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)ddataReg, &val[0]);\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)ddataReg, &val[4]);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Read 256 bits of data from a DDATAX register in the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Read 256 bits of data from a DDATAX (Double Data) register in the crypto\r
+ * module. The data value is typically output from a big integer operation\r
+ * (see crypto instructions).\r
+ *\r
+ * @param[in] ddataReg The 256 bit DDATA register.\r
+ * @param[out] val Location where to store the value in memory.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_DDataRead(CRYPTO_DDataReg_TypeDef ddataReg,\r
+ CRYPTO_DData_TypeDef val)\r
+{\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)ddataReg, &val[0]);\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)ddataReg, &val[4]);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Write 512 bits of data to a QDATAX register in the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Write 512 bits of data into a QDATAX (Quad Data) register in the crypto module\r
+ * The data value is typically input to a big integer operation (see crypto\r
+ * instructions).\r
+ *\r
+ * @param[in] qdataReg The 512 bits QDATA register.\r
+ * @param[in] val Value of the data to write to the QDATA register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_QDataWrite(CRYPTO_QDataReg_TypeDef qdataReg,\r
+ CRYPTO_QData_TypeDef val)\r
+{\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[0]);\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[4]);\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[8]);\r
+ CRYPTO_BurstToCrypto((volatile uint32_t *)qdataReg, &val[12]);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Read 512 bits of data from a QDATAX register in the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Read 512 bits of data from a QDATAX register in the crypto module. The data\r
+ * value is typically input to a big integer operation (see crypto\r
+ * instructions).\r
+ *\r
+ * @param[in] qdataReg The 512 bits QDATA register.\r
+ * @param[in] val Value of the data to write to the QDATA register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_QDataRead(CRYPTO_QDataReg_TypeDef qdataReg,\r
+ CRYPTO_QData_TypeDef val)\r
+{\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[0]);\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[4]);\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[8]);\r
+ CRYPTO_BurstFromCrypto((volatile uint32_t *)qdataReg, &val[12]);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the key value to be used by the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Write 128 or 256 bit key to the KEYBUF register in the crypto module.\r
+ *\r
+ * @param[in] val Value of the data to write to the KEYBUF register.\r
+ * @param[in] keyWidth Key width - 128 or 256 bits\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_KeyBufWrite(CRYPTO_KeyBuf_TypeDef val,\r
+ CRYPTO_KeyWidth_TypeDef keyWidth)\r
+{\r
+ if (keyWidth == cryptoKey256Bits)\r
+ {\r
+ /* Set AES-256 mode */\r
+ BUS_RegBitWrite(&CRYPTO->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256);\r
+ /* Load key in KEYBUF register (= DDATA4) */\r
+ CRYPTO_DDataWrite(cryptoRegDDATA4, (uint32_t *)val);\r
+ }\r
+ else\r
+ {\r
+ /* Set AES-128 mode */\r
+ BUS_RegBitWrite(&CRYPTO->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128);\r
+ CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, &val[0]);\r
+ }\r
+}\r
+\r
+void CRYPTO_KeyRead(CRYPTO_KeyBuf_TypeDef val,\r
+ CRYPTO_KeyWidth_TypeDef keyWidth);\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Quick write 128 bit key to the CRYPTO module.\r
+ *\r
+ * @details\r
+ * Quick write 128 bit key to the KEYBUF register in the CRYPTO module.\r
+ *\r
+ * @param[in] val Value of the data to write to the KEYBUF register.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_KeyBuf128Write(const uint32_t * val)\r
+{\r
+ CRYPTO_BurstToCrypto(&CRYPTO->KEYBUF, val);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Quick read access of the Carry bit from arithmetic operations.\r
+ *\r
+ * @details\r
+ * This function reads the carry bit of the CRYPTO ALU.\r
+ *\r
+ * @return\r
+ * Returns 'true' if carry is 1, and 'false' if carry is 0.\r
+ ******************************************************************************/\r
+__STATIC_INLINE bool CRYPTO_CarryIsSet(void)\r
+{\r
+ return (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_CARRY_MASK)\r
+ >> _CRYPTO_DSTATUS_CARRY_SHIFT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Quick read access of the 4 LSbits of the DDATA0 register.\r
+ *\r
+ * @details\r
+ * This function quickly retrieves the 4 least significant bits of the\r
+ * DDATA0 register via the DDATA0LSBS bit field in the DSTATUS register.\r
+ *\r
+ * @return\r
+ * Returns the 4 LSbits of DDATA0.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint8_t CRYPTO_DData0_4LSBitsRead(void)\r
+{\r
+ return (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_DDATA0LSBS_MASK)\r
+ >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Read 260 bits from the DDATA0 register.\r
+ *\r
+ * @details\r
+ * This functions reads 260 bits from the DDATA0 register in the CRYPTO\r
+ * module. The data value is typically output from a big integer operation\r
+ * (see crypto instructions) when the result width is set to 260 bits by\r
+ * calling @ref CRYPTO_ResultWidthSet(cryptoResult260Bits);\r
+ *\r
+ * @param[out] val Location where to store the value in memory.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_DData0Read260(CRYPTO_Data260_TypeDef val)\r
+{ \r
+ CRYPTO_DDataRead(cryptoRegDDATA0, val);\r
+ val[8] = (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_DDATA0MSBS_MASK)\r
+ >> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Write 260 bits to the DDATA0 register.\r
+ *\r
+ * @details\r
+ * This functions writes 260 bits to the DDATA0 register in the CRYPTO\r
+ * module. The data value is typically input to a big integer operation\r
+ * (see crypto instructions) when the result width is set to 260 bits by\r
+ * calling @ref CRYPTO_ResultWidthSet(cryptoResult260Bits);\r
+ *\r
+ * @param[out] val Location where of the value in memory.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_DData0Write260(const CRYPTO_Data260_TypeDef val)\r
+{\r
+ CRYPTO_DDataWrite(cryptoRegDDATA0, val);\r
+ CRYPTO->DDATA0BYTE32 = val[8] & _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Quick read the MSbit of the DDATA1 register.\r
+ *\r
+ * @details\r
+ * This function reads the most significant bit (bit 255) of the DDATA1\r
+ * register via the DDATA1MSB bit field in the DSTATUS register. This can\r
+ * be used to quickly check the signedness of a big integer resident in the\r
+ * CRYPTO module.\r
+ *\r
+ * @return\r
+ * Returns 'true' if MSbit is 1, and 'false' if MSbit is 0.\r
+ ******************************************************************************/\r
+__STATIC_INLINE bool CRYPTO_DData1_MSBitRead(void)\r
+{\r
+ return (CRYPTO->DSTATUS & _CRYPTO_DSTATUS_DDATA1MSB_MASK)\r
+ >> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Load a sequence of instructions to be executed on the current values in\r
+ * the data registers.\r
+ *\r
+ * @details\r
+ * This function loads a sequence of instructions to the crypto module. The\r
+ * instructions will be executed when the CRYPTO_InstructionSequenceExecute\r
+ * function is called. The first END marks the end of the sequence.\r
+ *\r
+ * @param[in] instructionSequence Instruction sequence to load.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_InstructionSequenceLoad(const CRYPTO_InstructionSequence_TypeDef instructionSequence)\r
+{\r
+ const uint32_t * pas = (const uint32_t *) instructionSequence;\r
+\r
+ CRYPTO->SEQ0 = pas[0];\r
+ CRYPTO->SEQ1 = pas[1];\r
+ CRYPTO->SEQ2 = pas[2];\r
+ CRYPTO->SEQ3 = pas[3];\r
+ CRYPTO->SEQ4 = pas[4];\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Execute the current programmed instruction sequence.\r
+ *\r
+ * @details\r
+ * This function starts the execution of the current instruction sequence\r
+ * in the CRYPTO module.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_InstructionSequenceExecute(void)\r
+{\r
+ /* Start the command sequence. */\r
+ CRYPTO->CMD = CRYPTO_CMD_SEQSTART;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Check whether the execution of an instruction sequence has completed.\r
+ *\r
+ * @details\r
+ * This function checks whether an instruction sequence has completed.\r
+ *\r
+ * @return\r
+ * Returns 'true' if the instruction sequence is done, and 'false' if not.\r
+ ******************************************************************************/\r
+__STATIC_INLINE bool CRYPTO_InstructionSequenceDone(void)\r
+{\r
+ /* Return true if operation has completed. */\r
+ return !(CRYPTO->STATUS\r
+ & (CRYPTO_STATUS_INSTRRUNNING | CRYPTO_STATUS_SEQRUNNING));\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Wait for completion of the current sequence of instructions.\r
+ *\r
+ * @details\r
+ * This function "busy"-waits until the execution of the ongoing instruction\r
+ * sequence has completed.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_InstructionSequenceWait(void)\r
+{\r
+ while (!CRYPTO_InstructionSequenceDone())\r
+ ;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Wait for completion of the current command.\r
+ *\r
+ * @details\r
+ * This function "busy"-waits until the execution of the ongoing instruction\r
+ * has completed.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_InstructionWait(void)\r
+{\r
+ /* Wait for completion */\r
+ while (!(CRYPTO->IF & CRYPTO_IF_INSTRDONE))\r
+ ;\r
+ CRYPTO->IFC = CRYPTO_IF_INSTRDONE;\r
+}\r
+\r
+void CRYPTO_SHA_1(const uint8_t * msg,\r
+ uint64_t msgLen,\r
+ CRYPTO_SHA1_Digest_TypeDef digest);\r
+\r
+void CRYPTO_SHA_256(const uint8_t * msg,\r
+ uint64_t msgLen,\r
+ CRYPTO_SHA256_Digest_TypeDef digest);\r
+\r
+void CRYPTO_Mul(uint32_t * A, int aSize,\r
+ uint32_t * B, int bSize,\r
+ uint32_t * R, int rSize);\r
+\r
+void CRYPTO_AES_CBC128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt);\r
+\r
+void CRYPTO_AES_CBC256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt);\r
+\r
+void CRYPTO_AES_CFB128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt);\r
+\r
+void CRYPTO_AES_CFB256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt);\r
+\r
+void CRYPTO_AES_CTR128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ uint8_t * ctr,\r
+ CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc);\r
+\r
+void CRYPTO_AES_CTR256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ uint8_t * ctr,\r
+ CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc);\r
+\r
+void CRYPTO_AES_CTRUpdate32Bit(uint8_t * ctr);\r
+void CRYPTO_AES_DecryptKey128(uint8_t * out, const uint8_t * in);\r
+void CRYPTO_AES_DecryptKey256(uint8_t * out, const uint8_t * in);\r
+\r
+void CRYPTO_AES_ECB128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ bool encrypt);\r
+\r
+void CRYPTO_AES_ECB256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ bool encrypt);\r
+\r
+void CRYPTO_AES_OFB128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv);\r
+\r
+void CRYPTO_AES_OFB256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv);\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear one or more pending CRYPTO interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * Pending CRYPTO interrupt source to clear. Use a bitwise logic OR combination of\r
+ * valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_IntClear(uint32_t flags)\r
+{\r
+ CRYPTO->IFC = flags;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more CRYPTO interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * CRYPTO interrupt sources to disable. Use a bitwise logic OR combination of\r
+ * valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_IntDisable(uint32_t flags)\r
+{\r
+ CRYPTO->IEN &= ~(flags);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more CRYPTO interrupts.\r
+ *\r
+ * @note\r
+ * Depending on the use, a pending interrupt may already be set prior to\r
+ * enabling the interrupt. Consider using CRYPTO_IntClear() prior to enabling\r
+ * if such a pending interrupt should be ignored.\r
+ *\r
+ * @param[in] flags\r
+ * CRYPTO interrupt sources to enable. Use a bitwise logic OR combination of\r
+ * valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_IntEnable(uint32_t flags)\r
+{\r
+ CRYPTO->IEN |= flags;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get pending CRYPTO interrupt flags.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * CRYPTO interrupt sources pending. A bitwise logic OR combination of valid\r
+ * interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRYPTO_IntGet(void)\r
+{\r
+ return CRYPTO->IF;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending CRYPTO interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled CRYPTO interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in CRYPTO_IEN and\r
+ * - the pending interrupt flags CRYPTO_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t CRYPTO_IntGetEnabled(void)\r
+{\r
+ return CRYPTO->IF & CRYPTO->IEN;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set one or more pending CRYPTO interrupts from SW.\r
+ *\r
+ * @param[in] flags\r
+ * CRYPTO interrupt sources to set to pending. Use a bitwise logic OR combination\r
+ * of valid interrupt flags for the CRYPTO module (CRYPTO_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void CRYPTO_IntSet(uint32_t flags)\r
+{\r
+ CRYPTO->IFS = flags;\r
+}\r
+\r
+/*******************************************************************************\r
+ ***** Static inline wrappers for CRYPTO AES functions in order to *****\r
+ ***** preserve backwards compatibility with AES module API functions. *****\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Cipher-block chaining (CBC) cipher mode encryption/decryption,\r
+ * 128 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CBC128 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CBC128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt)\r
+{\r
+ CRYPTO_AES_CBC128(out, in, len, key, iv, encrypt);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit\r
+ * key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CBC256 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CBC256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt)\r
+{\r
+ CRYPTO_AES_CBC256(out, in, len, key, iv, encrypt);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CFB128 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CFB128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt)\r
+{\r
+ CRYPTO_AES_CFB128(out, in, len, key, iv, encrypt);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CFB256 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CFB256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv,\r
+ bool encrypt)\r
+{\r
+ CRYPTO_AES_CFB256(out, in, len, key, iv, encrypt);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Counter (CTR) cipher mode encryption/decryption, 128 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CTR128 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CTR128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ uint8_t * ctr,\r
+ CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)\r
+{\r
+ CRYPTO_AES_CTR128(out, in, len, key, ctr, ctrFunc);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Counter (CTR) cipher mode encryption/decryption, 256 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CTR256 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CTR256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ uint8_t * ctr,\r
+ CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)\r
+{\r
+ CRYPTO_AES_CTR256(out, in, len, key, ctr, ctrFunc);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Update last 32 bits of 128 bit counter, by incrementing with 1.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_CTRUpdate32Bit instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_CTRUpdate32Bit(uint8_t * ctr)\r
+{\r
+ CRYPTO_AES_CTRUpdate32Bit(ctr);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Generate 128 bit AES decryption key from 128 bit encryption key. The\r
+ * decryption key is used for some cipher modes when decrypting.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_DecryptKey128 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)\r
+{\r
+ CRYPTO_AES_DecryptKey128(out, in);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Generate 256 bit AES decryption key from 256 bit encryption key. The\r
+ * decryption key is used for some cipher modes when decrypting.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_DecryptKey256 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_DecryptKey256(uint8_t * out, const uint8_t * in)\r
+{\r
+ CRYPTO_AES_DecryptKey256(out, in);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Electronic Codebook (ECB) cipher mode encryption/decryption,\r
+ * 128 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_ECB128 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_ECB128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ bool encrypt)\r
+{\r
+ CRYPTO_AES_ECB128(out, in, len, key, encrypt);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Electronic Codebook (ECB) cipher mode encryption/decryption,\r
+ * 256 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_ECB256 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_ECB256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ bool encrypt)\r
+{\r
+ CRYPTO_AES_ECB256(out, in, len, key, encrypt);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Output feedback (OFB) cipher mode encryption/decryption, 128 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_OFB128 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_OFB128(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv)\r
+{\r
+ CRYPTO_AES_OFB128(out, in, len, key, iv);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * AES Output feedback (OFB) cipher mode encryption/decryption, 256 bit key.\r
+ *\r
+ * @deprecated\r
+ * This function is present to preserve backwards compatibility. Use\r
+ * @ref CRYPTO_AES_OFB256 instead.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void AES_OFB256(uint8_t * out,\r
+ const uint8_t * in,\r
+ unsigned int len,\r
+ const uint8_t * key,\r
+ const uint8_t * iv)\r
+{\r
+ CRYPTO_AES_OFB256(out, in, len, key, iv);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @} (end addtogroup CRYPTO) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#endif /* defined(CRYPTO_COUNT) && (CRYPTO_COUNT > 0) */\r
+\r
+#endif /* __SILICON_LABS_EM_CRYPTO_H__ */\r
/***************************************************************************//**\r
* @file em_dac.h\r
* @brief Digital to Analog Converter (DAC) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __EM_DAC_H\r
-#define __EM_DAC_H\r
+#ifndef __SILICON_LABS_EM_DAC_H__\r
+#define __SILICON_LABS_EM_DAC_H__\r
\r
#include "em_device.h"\r
-#include "em_assert.h"\r
\r
#if defined(DAC_COUNT) && (DAC_COUNT > 0)\r
\r
+#include "em_assert.h"\r
#include <stdbool.h>\r
\r
#ifdef __cplusplus\r
} DAC_Init_TypeDef;\r
\r
/** Default config for DAC init structure. */\r
-#define DAC_INIT_DEFAULT \\r
- { dacRefresh8, /* Refresh every 8 prescaled cycles. */ \\r
- dacRef1V25, /* 1.25V internal reference. */ \\r
- dacOutputPin, /* Output to pin only. */ \\r
- dacConvModeContinuous, /* Continuous mode. */ \\r
- 0, /* No prescaling. */ \\r
- false, /* Do not enable low pass filter. */ \\r
- false, /* Do not reset prescaler on ch0 start. */ \\r
- false, /* DAC output enable always on. */ \\r
- false, /* Disable sine mode. */ \\r
- false /* Single ended mode. */ \\r
- }\r
+#define DAC_INIT_DEFAULT \\r
+{ \\r
+ dacRefresh8, /* Refresh every 8 prescaled cycles. */ \\r
+ dacRef1V25, /* 1.25V internal reference. */ \\r
+ dacOutputPin, /* Output to pin only. */ \\r
+ dacConvModeContinuous, /* Continuous mode. */ \\r
+ 0, /* No prescaling. */ \\r
+ false, /* Do not enable low pass filter. */ \\r
+ false, /* Do not reset prescaler on ch0 start. */ \\r
+ false, /* DAC output enable always on. */ \\r
+ false, /* Disable sine mode. */ \\r
+ false /* Single ended mode. */ \\r
+}\r
\r
\r
/** DAC channel init structure. */\r
} DAC_InitChannel_TypeDef;\r
\r
/** Default config for DAC channel init structure. */\r
-#define DAC_INITCHANNEL_DEFAULT \\r
- { false, /* Leave channel disabled when init done. */ \\r
- false, /* Disable PRS triggering. */ \\r
- false, /* Channel not refreshed automatically. */ \\r
- dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \\r
- }\r
+#define DAC_INITCHANNEL_DEFAULT \\r
+{ \\r
+ false, /* Leave channel disabled when init done. */ \\r
+ false, /* Disable PRS triggering. */ \\r
+ false, /* Channel not refreshed automatically. */ \\r
+ dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \\r
+}\r
\r
\r
/*******************************************************************************\r
******************************************************************************/\r
__STATIC_INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)\r
{\r
- dac->IEN &= ~(flags);\r
+ dac->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)\r
{\r
- return(dac->IF);\r
+ return dac->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending DAC interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @param[in] dac\r
+ * Pointer to DAC peripheral register block.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled DAC interrupt sources.\r
+ * The return value is the bitwise AND combination of\r
+ * - the OR combination of enabled interrupt sources in DACx_IEN_nnn\r
+ * register (DACx_IEN_nnn) and\r
+ * - the OR combination of valid interrupt flags of the DAC module\r
+ * (DACx_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t DAC_IntGetEnabled(DAC_TypeDef *dac)\r
+{\r
+ uint32_t ien;\r
+\r
+ /* Store DAC->IEN in temporary variable in order to define explicit order\r
+ * of volatile accesses. */\r
+ ien = dac->IEN;\r
+\r
+ /* Bitwise AND of pending and enabled interrupts */\r
+ return dac->IF & ien;\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */\r
-\r
-#endif /* __EM_DAC_H */\r
+#endif /* __SILICON_LABS_EM_DAC_H__ */\r
/***************************************************************************//**\r
* @file em_dbg.h\r
* @brief Debug (DBG) API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
******************************************************************************/\r
\r
\r
-#ifndef __SILICON_LABS_EM_DBG_H_\r
-#define __SILICON_LABS_EM_DBG_H_\r
+#ifndef __SILICON_LABS_EM_DBG_H__\r
+#define __SILICON_LABS_EM_DBG_H__\r
\r
#include <stdbool.h>\r
#include "em_device.h"\r
\r
-#if defined ( CoreDebug_DHCSR_C_DEBUGEN_Msk )\r
+#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )\r
\r
#ifdef __cplusplus\r
extern "C" {\r
***************************** PROTOTYPES **********************************\r
******************************************************************************/\r
\r
-#if defined( GPIO_ROUTE_SWCLKPEN )\r
+#if defined( GPIO_ROUTE_SWCLKPEN ) || defined( GPIO_ROUTEPEN_SWCLKTCKPEN )\r
/***************************************************************************//**\r
* @brief\r
* Check if a debugger is connected (and debug session activated)\r
******************************************************************************/\r
__STATIC_INLINE bool DBG_Connected(void)\r
{\r
- return ((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false);\r
+ return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false;\r
}\r
#endif\r
\r
\r
-#if defined( GPIO_ROUTE_SWOPEN )\r
+#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )\r
void DBG_SWOEnable(unsigned int location);\r
#endif\r
\r
}\r
#endif\r
\r
-#endif /* defined ( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */\r
+#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */\r
\r
-#endif /* __SILICON_LABS_EM_DBG_H_ */\r
+#endif /* __SILICON_LABS_EM_DBG_H__ */\r
/***************************************************************************//**\r
* @file em_dma.h\r
* @brief Direct memory access (DMA) API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-\r
-#ifndef __SILICON_LABS_EM_DMA_H_\r
-#define __SILICON_LABS_EM_DMA_H_\r
+#ifndef __SILICON_LABS_EM_DMA_H__\r
+#define __SILICON_LABS_EM_DMA_H__\r
\r
#include "em_device.h"\r
#if defined( DMA_PRESENT )\r
/* Clean loop copy operation */\r
switch(channel)\r
{\r
- case 0:\r
- DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;\r
- break;\r
- case 1:\r
- DMA->LOOP1 = _DMA_LOOP1_RESETVALUE;\r
- break;\r
- default:\r
- break;\r
+ case 0:\r
+ DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;\r
+ break;\r
+ case 1:\r
+ DMA->LOOP1 = _DMA_LOOP1_RESETVALUE;\r
+ break;\r
+ default:\r
+ break;\r
}\r
}\r
#endif\r
bool last);\r
void DMA_Reset(void);\r
\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear one or more pending DMA interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * Pending DMA interrupt sources to clear. Use one or more valid\r
+ * interrupt flags for the DMA module (DMA_IFC_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DMA_IntClear(uint32_t flags)\r
+{\r
+ DMA->IFC = flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more DMA interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * DMA interrupt sources to disable. Use one or more valid\r
+ * interrupt flags for the DMA module (DMA_IEN_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DMA_IntDisable(uint32_t flags)\r
+{\r
+ DMA->IEN &= ~flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more DMA interrupts.\r
+ *\r
+ * @note\r
+ * Depending on the use, a pending interrupt may already be set prior to\r
+ * enabling the interrupt. Consider using DMA_IntClear() prior to enabling\r
+ * if such a pending interrupt should be ignored.\r
+ *\r
+ * @param[in] flags\r
+ * DMA interrupt sources to enable. Use one or more valid\r
+ * interrupt flags for the DMA module (DMA_IEN_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DMA_IntEnable(uint32_t flags)\r
+{\r
+ DMA->IEN |= flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get pending DMA interrupt flags.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * DMA interrupt sources pending. Returns one or more valid\r
+ * interrupt flags for the DMA module (DMA_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t DMA_IntGet(void)\r
+{\r
+ return DMA->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending DMA interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled DMA interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in DMA_IEN and\r
+ * - the pending interrupt flags DMA_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t DMA_IntGetEnabled(void)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = DMA->IEN;\r
+ return DMA->IF & ien;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set one or more pending DMA interrupts\r
+ *\r
+ * @param[in] flags\r
+ * DMA interrupt sources to set to pending. Use one or more valid\r
+ * interrupt flags for the DMA module (DMA_IFS_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void DMA_IntSet(uint32_t flags)\r
+{\r
+ DMA->IFS = flags;\r
+}\r
+\r
/** @} (end addtogroup DMA) */\r
/** @} (end addtogroup EM_Library) */\r
\r
#endif\r
\r
#endif /* defined( DMA_PRESENT ) */\r
-#endif /* __SILICON_LABS_EM_DMA_H_ */\r
+#endif /* __SILICON_LABS_EM_DMA_H__ */\r
/***************************************************************************//**\r
* @file em_ebi.h\r
* @brief External Bus Iterface (EBI) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_EBI_H_\r
-#define __SILICON_LABS_EM_EBI_H_\r
+#ifndef __SILICON_LABS_EM_EBI_H__\r
+#define __SILICON_LABS_EM_EBI_H__\r
\r
#include "em_device.h"\r
-\r
#if defined(EBI_COUNT) && (EBI_COUNT > 0)\r
-#include "em_assert.h"\r
\r
#include <stdint.h>\r
#include <stdbool.h>\r
+#include "em_assert.h"\r
\r
#ifdef __cplusplus\r
extern "C" {\r
* @verbatim\r
*\r
* --------- ---------\r
- * | EBI | /| |\ | Ext. |\r
- * | | / --------- \ | Async |\r
- * |(EFM32)| \ --------- / | Device|\r
+ * | | /| |\ | Ext. |\r
+ * | EBI | / --------- \ | Async |\r
+ * | | \ --------- / | Device|\r
* | | \| |/ | |\r
* --------- ---------\r
* Parallel interface\r
\r
/** Default config for EBI init structures */\r
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
-#define EBI_INIT_DEFAULT \\r
- { ebiModeD8A8, /* 8 bit address, 8 bit data */ \\r
- ebiActiveLow, /* ARDY polarity */ \\r
- ebiActiveLow, /* ALE polarity */ \\r
- ebiActiveLow, /* WE polarity */ \\r
- ebiActiveLow, /* RE polarity */ \\r
- ebiActiveLow, /* CS polarity */ \\r
- ebiActiveLow, /* BL polarity */ \\r
- false, /* enable BL */ \\r
- false, /* enable NOIDLE */ \\r
- false, /* enable ARDY */ \\r
- false, /* don't disable ARDY timeout */ \\r
- EBI_BANK0, /* enable bank 0 */ \\r
- EBI_CS0, /* enable chip select 0 */ \\r
- 0, /* addr setup cycles */ \\r
- 1, /* addr hold cycles */ \\r
- false, /* do not enable half cycle ALE strobe */ \\r
- 0, /* read setup cycles */ \\r
- 0, /* read strobe cycles */ \\r
- 0, /* read hold cycles */ \\r
- false, /* disable page mode */ \\r
- false, /* disable prefetch */ \\r
- false, /* do not enable half cycle REn strobe */ \\r
- 0, /* write setup cycles */ \\r
- 0, /* write strobe cycles */ \\r
- 1, /* write hold cycles */ \\r
- false, /* do not disable the write buffer */ \\r
- false, /* do not enable halc cycle WEn strobe */ \\r
- ebiALowA0, /* ALB - Low bound, address lines */ \\r
- ebiAHighA0, /* APEN - High bound, address lines */ \\r
- ebiLocation0, /* Use Location 0 */ \\r
- true, /* enable EBI */ \\r
- }\r
+#define EBI_INIT_DEFAULT \\r
+{ \\r
+ ebiModeD8A8, /* 8 bit address, 8 bit data */ \\r
+ ebiActiveLow, /* ARDY polarity */ \\r
+ ebiActiveLow, /* ALE polarity */ \\r
+ ebiActiveLow, /* WE polarity */ \\r
+ ebiActiveLow, /* RE polarity */ \\r
+ ebiActiveLow, /* CS polarity */ \\r
+ ebiActiveLow, /* BL polarity */ \\r
+ false, /* enable BL */ \\r
+ false, /* enable NOIDLE */ \\r
+ false, /* enable ARDY */ \\r
+ false, /* don't disable ARDY timeout */ \\r
+ EBI_BANK0, /* enable bank 0 */ \\r
+ EBI_CS0, /* enable chip select 0 */ \\r
+ 0, /* addr setup cycles */ \\r
+ 1, /* addr hold cycles */ \\r
+ false, /* do not enable half cycle ALE strobe */ \\r
+ 0, /* read setup cycles */ \\r
+ 0, /* read strobe cycles */ \\r
+ 0, /* read hold cycles */ \\r
+ false, /* disable page mode */ \\r
+ false, /* disable prefetch */ \\r
+ false, /* do not enable half cycle REn strobe */ \\r
+ 0, /* write setup cycles */ \\r
+ 0, /* write strobe cycles */ \\r
+ 1, /* write hold cycles */ \\r
+ false, /* do not disable the write buffer */ \\r
+ false, /* do not enable halc cycle WEn strobe */ \\r
+ ebiALowA0, /* ALB - Low bound, address lines */ \\r
+ ebiAHighA0, /* APEN - High bound, address lines */ \\r
+ ebiLocation0, /* Use Location 0 */ \\r
+ true, /* enable EBI */ \\r
+}\r
#else\r
-#define EBI_INIT_DEFAULT \\r
- { ebiModeD8A8, /* 8 bit address, 8 bit data */ \\r
- ebiActiveLow, /* ARDY polarity */ \\r
- ebiActiveLow, /* ALE polarity */ \\r
- ebiActiveLow, /* WE polarity */ \\r
- ebiActiveLow, /* RE polarity */ \\r
- ebiActiveLow, /* CS polarity */ \\r
- false, /* enable ARDY */ \\r
- false, /* don't disable ARDY timeout */ \\r
- EBI_BANK0, /* enable bank 0 */ \\r
- EBI_CS0, /* enable chip select 0 */ \\r
- 0, /* addr setup cycles */ \\r
- 1, /* addr hold cycles */ \\r
- 0, /* read setup cycles */ \\r
- 0, /* read strobe cycles */ \\r
- 0, /* read hold cycles */ \\r
- 0, /* write setup cycles */ \\r
- 0, /* write strobe cycles */ \\r
- 1, /* write hold cycles */ \\r
- true, /* enable EBI */ \\r
- }\r
+#define EBI_INIT_DEFAULT \\r
+{ \\r
+ ebiModeD8A8, /* 8 bit address, 8 bit data */ \\r
+ ebiActiveLow, /* ARDY polarity */ \\r
+ ebiActiveLow, /* ALE polarity */ \\r
+ ebiActiveLow, /* WE polarity */ \\r
+ ebiActiveLow, /* RE polarity */ \\r
+ ebiActiveLow, /* CS polarity */ \\r
+ false, /* enable ARDY */ \\r
+ false, /* don't disable ARDY timeout */ \\r
+ EBI_BANK0, /* enable bank 0 */ \\r
+ EBI_CS0, /* enable chip select 0 */ \\r
+ 0, /* addr setup cycles */ \\r
+ 1, /* addr hold cycles */ \\r
+ 0, /* read setup cycles */ \\r
+ 0, /* read strobe cycles */ \\r
+ 0, /* read hold cycles */ \\r
+ 0, /* write setup cycles */ \\r
+ 0, /* write strobe cycles */ \\r
+ 1, /* write hold cycles */ \\r
+ true, /* enable EBI */ \\r
+}\r
#endif\r
\r
#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
} EBI_TFTInit_TypeDef;\r
\r
/** Default configuration for EBI TFT init structure */\r
-#define EBI_TFTINIT_DEFAULT \\r
- { ebiTFTBank0, /* Select EBI Bank 0 */ \\r
- ebiTFTWidthHalfWord, /* Select 2-byte increments */ \\r
- ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \\r
- ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \\r
- ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \\r
- false, /* Drive DCLK from negative edge of internal clock */ \\r
- ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \\r
- ebiTFTDDModeExternal, /* Drive from external memory */ \\r
- ebiActiveLow, /* CS Active Low polarity */ \\r
- ebiActiveLow, /* DCLK Active Low polarity */ \\r
- ebiActiveLow, /* DATAEN Active Low polarity */ \\r
- ebiActiveLow, /* HSYNC Active Low polarity */ \\r
- ebiActiveLow, /* VSYNC Active Low polarity */ \\r
- 320, /* Horizontal size in pixels */ \\r
- 1, /* Horizontal Front Porch */ \\r
- 29, /* Horizontal Back Porch */ \\r
- 2, /* Horizontal Synchronization Pulse Width */ \\r
- 240, /* Vertical size in pixels */ \\r
- 1, /* Vertical Front Porch */ \\r
- 4, /* Vertical Back Porch */ \\r
- 2, /* Vertical Synchronization Pulse Width */ \\r
- 0x0000, /* Address offset to EBI memory base */ \\r
- 5, /* DCLK Period */ \\r
- 2, /* DCLK Start */ \\r
- 1, /* DCLK Setup cycles */ \\r
- 1, /* DCLK Hold cycles */ \\r
- }\r
+#define EBI_TFTINIT_DEFAULT \\r
+{ \\r
+ ebiTFTBank0, /* Select EBI Bank 0 */ \\r
+ ebiTFTWidthHalfWord, /* Select 2-byte increments */ \\r
+ ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \\r
+ ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \\r
+ ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \\r
+ false, /* Drive DCLK from negative edge of internal clock */ \\r
+ ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \\r
+ ebiTFTDDModeExternal, /* Drive from external memory */ \\r
+ ebiActiveLow, /* CS Active Low polarity */ \\r
+ ebiActiveLow, /* DCLK Active Low polarity */ \\r
+ ebiActiveLow, /* DATAEN Active Low polarity */ \\r
+ ebiActiveLow, /* HSYNC Active Low polarity */ \\r
+ ebiActiveLow, /* VSYNC Active Low polarity */ \\r
+ 320, /* Horizontal size in pixels */ \\r
+ 1, /* Horizontal Front Porch */ \\r
+ 29, /* Horizontal Back Porch */ \\r
+ 2, /* Horizontal Synchronization Pulse Width */ \\r
+ 240, /* Vertical size in pixels */ \\r
+ 1, /* Vertical Front Porch */ \\r
+ 4, /* Vertical Back Porch */ \\r
+ 2, /* Vertical Synchronization Pulse Width */ \\r
+ 0x0000, /* Address offset to EBI memory base */ \\r
+ 5, /* DCLK Period */ \\r
+ 2, /* DCLK Start */ \\r
+ 1, /* DCLK Setup cycles */ \\r
+ 1, /* DCLK Hold cycles */ \\r
+}\r
\r
#endif\r
/*******************************************************************************\r
\r
/***************************************************************************//**\r
* @brief\r
- * Set one or more pending EBI interrupts from SW.\r
+ * Set one or more pending EBI interrupts.\r
*\r
* @param[in] flags\r
* EBI interrupt sources to set to pending. Use a logical OR combination of\r
\r
/***************************************************************************//**\r
* @brief\r
- * Disable one or more EBI interrupts\r
+ * Disable one or more EBI interrupts.\r
*\r
* @param[in] flags\r
* EBI interrupt sources to disable. Use logical OR combination of valid\r
\r
/***************************************************************************//**\r
* @brief\r
- * Enable one or more EBI interrupts\r
+ * Enable one or more EBI interrupts.\r
*\r
* @param[in] flags\r
* EBI interrupt sources to enable. Use logical OR combination of valid\r
\r
/***************************************************************************//**\r
* @brief\r
- * Get pending EBI interrupt flags\r
+ * Get pending EBI interrupt flags.\r
*\r
* @note\r
* The event bits are not cleared by the use of this function\r
******************************************************************************/\r
__STATIC_INLINE uint32_t EBI_IntGet(void)\r
{\r
- return(EBI->IF);\r
+ return EBI->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending EBI interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled EBI interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in EBI_IEN and\r
+ * - the pending interrupt flags EBI_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t EBI_IntGetEnabled(void)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = EBI->IEN;\r
+ return EBI->IF & ien;\r
}\r
\r
\r
\r
#endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */\r
\r
-#endif /* __SILICON_LABS_EM_EBI_H_ */\r
+#endif /* __SILICON_LABS_EM_EBI_H__ */\r
/***************************************************************************//**\r
* @file em_emu.h\r
* @brief Energy management unit (EMU) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
#ifndef __SILICON_LABS_EM_EMU_H__\r
#define __SILICON_LABS_EM_EMU_H__\r
\r
#if defined( EMU_PRESENT )\r
\r
#include <stdbool.h>\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
\r
#ifdef __cplusplus\r
extern "C" {\r
******************************** ENUMS ************************************\r
******************************************************************************/\r
\r
-typedef enum\r
-{\r
- /** Enable EM2 and 3 voltage regulator reduced drive strength (reduced leakage current) */\r
-#if defined( _EMU_CTRL_EM23VREG_MASK )\r
- emuEM23Vreg_REDUCED = EMU_CTRL_EM23VREG_REDUCED,\r
-#elif defined( _EMU_CTRL_EMVREG_MASK )\r
- emuEM23Vreg_REDUCED = EMU_CTRL_EMVREG_REDUCED,\r
-#endif\r
- /** Enable EM2 and 3 voltage regulator full drive strength (faster startup) */\r
-#if defined( _EMU_CTRL_EM23VREG_MASK )\r
- emuEM23Vreg_FULL = EMU_CTRL_EM23VREG_FULL,\r
-#elif defined( _EMU_CTRL_EMVREG_MASK )\r
- emuEM23Vreg_FULL = EMU_CTRL_EMVREG_FULL,\r
-#endif\r
-} EMU_EM23VregMode;\r
-\r
#if defined( _EMU_EM4CONF_OSC_MASK )\r
/** EM4 duty oscillator */\r
typedef enum\r
emuBODMode_Inactive,\r
} EMU_BODMode_TypeDef;\r
\r
+#if defined( _EMU_EM4CTRL_EM4STATE_MASK )\r
+/** EM4 modes */\r
+typedef enum\r
+{\r
+ /** EM4 Hibernate */\r
+ emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,\r
+ /** EM4 Shutoff */\r
+ emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,\r
+} EMU_EM4State_TypeDef;\r
+#endif\r
+\r
\r
+#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )\r
+typedef enum\r
+{\r
+ /** No Retention: Pads enter reset state when entering EM4 */\r
+ emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,\r
+ /** Retention through EM4: Pads enter reset state when exiting EM4 */\r
+ emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,\r
+ /** Retention through EM4 and wakeup: call EMU_UnlatchPinRetention() to\r
+ release pins from retention after EM4 wakeup */\r
+ emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,\r
+} EMU_EM4PinRetention_TypeDef;\r
+#endif\r
+\r
+\r
+#if defined( _EMU_PWRCFG_MASK )\r
+/** Power configurations */\r
+typedef enum\r
+{\r
+ /** DCDC is connected to DVDD */\r
+ emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD,\r
+} EMU_PowerConfig_TypeDef;\r
+#endif\r
+\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+/** DCDC operating modes */\r
+typedef enum\r
+{\r
+ /** DCDC regulator bypass */\r
+ emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,\r
+ /** DCDC low-noise mode */\r
+ emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,\r
+} EMU_DcdcMode_TypeDef;\r
+#endif\r
+\r
+#if defined( _EMU_PWRCTRL_MASK )\r
+/** DCDC to DVDD mode analog peripheral power supply select */\r
+typedef enum\r
+{\r
+ /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */\r
+ emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,\r
+ /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */\r
+ emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD\r
+} EMU_DcdcAnaPeripheralPower_TypeDef;\r
+#endif\r
+\r
+#if defined( _EMU_DCDCMISCCTRL_MASK )\r
+/** DCDC Low-noise efficiency mode */\r
+typedef enum\r
+{\r
+#if defined( _EFM_DEVICE )\r
+ /** High efficiency mode */\r
+ emuDcdcLnHighEfficiency = 0,\r
+#endif\r
+ /** Fast transient response mode */\r
+ emuDcdcLnFastTransient = EMU_DCDCMISCCTRL_LNFORCECCM,\r
+} EMU_DcdcLnTransientMode_TypeDef;\r
+#endif\r
+\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+/** DCDC Low-noise RCO band select */\r
+typedef enum\r
+{\r
+ /** Set RCO to 3MHz */\r
+ EMU_DcdcLnRcoBand_3MHz = 0,\r
+ /** Set RCO to 4MHz */\r
+ EMU_DcdcLnRcoBand_4MHz = 1,\r
+ /** Set RCO to 5MHz */\r
+ EMU_DcdcLnRcoBand_5MHz = 2,\r
+ /** Set RCO to 6MHz */\r
+ EMU_DcdcLnRcoBand_6MHz = 3,\r
+ /** Set RCO to 7MHz */\r
+ EMU_DcdcLnRcoBand_7MHz = 4,\r
+ /** Set RCO to 8MHz */\r
+ EMU_DcdcLnRcoBand_8MHz = 5,\r
+ /** Set RCO to 9MHz */\r
+ EMU_DcdcLnRcoBand_9MHz = 6,\r
+ /** Set RCO to 10MHz */\r
+ EMU_DcdcLnRcoBand_10MHz = 7,\r
+} EMU_DcdcLnRcoBand_TypeDef;\r
+\r
+#endif\r
+\r
+#if defined( EMU_STATUS_VMONRDY )\r
+/** VMON channels */\r
+typedef enum\r
+{\r
+ emuVmonChannel_AVDD,\r
+ emuVmonChannel_ALTAVDD,\r
+ emuVmonChannel_DVDD,\r
+ emuVmonChannel_IOVDD0\r
+} EMU_VmonChannel_TypeDef;\r
+#endif /* EMU_STATUS_VMONRDY */\r
\r
/*******************************************************************************\r
******************************* STRUCTS ***********************************\r
/** Energy Mode 2 and 3 initialization structure */\r
typedef struct\r
{\r
- bool em23Vreg;\r
+ bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */\r
} EMU_EM23Init_TypeDef;\r
\r
/** Default initialization of EM2 and 3 configuration */\r
#define EMU_EM23INIT_DEFAULT \\r
- { false } /* Reduced voltage regulator drive strength in EM2 and EM3 */\r
+{ false } /* Reduced voltage regulator drive strength in EM2 and EM3 */\r
\r
\r
+#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )\r
/** Energy Mode 4 initialization structure */\r
typedef struct\r
{\r
- /* Init parameters for platforms with EMU->EM4CONF register */\r
#if defined( _EMU_EM4CONF_MASK )\r
- bool lockConfig; /** Lock configuration of regulator, BOD and oscillator */\r
- bool buBodRstDis; /** When set, no reset will be asserted due to Brownout when in EM4 */\r
- EMU_EM4Osc_TypeDef osc; /** EM4 duty oscillator */\r
- bool buRtcWakeup; /** Wake up on EM4 BURTC interrupt */\r
- bool vreg; /** Enable EM4 voltage regulator */\r
-#else\r
- bool reserved; /** Placeholder for empty structs */\r
+ /* Init parameters for platforms with EMU->EM4CONF register */\r
+ bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */\r
+ bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */\r
+ EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */\r
+ bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */\r
+ bool vreg; /**< Enable EM4 voltage regulator */\r
+\r
+#elif defined( _EMU_EM4CTRL_MASK )\r
+ /* Init parameters for platforms with EMU->EM4CTRL register */\r
+ bool retainLfxo; /**< Disable the LFXO upon EM4 entry */\r
+ bool retainLfrco; /**< Disable the LFRCO upon EM4 entry */\r
+ bool retainUlfrco; /**< Disable the ULFRCO upon EM4 entry */\r
+ EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state */\r
+ EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */\r
#endif\r
} EMU_EM4Init_TypeDef;\r
+#endif\r
\r
/** Default initialization of EM4 configuration */\r
#if defined( _EMU_EM4CONF_MASK )\r
-#define EMU_EM4INIT_DEFAULT \\r
- { false, /* Dont't lock configuration after it's been set */ \\r
- false, /* No reset will be asserted due to Brownout when in EM4 */ \\r
- emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \\r
- true, /* Wake up on EM4 BURTC interrupt */ \\r
- true, /* Enable VREG */ \\r
- }\r
-#else\r
- #define EMU_EM4INIT_DEFAULT \\r
- { false, /* Placeholder default value */ \\r
- }\r
+#define EMU_EM4INIT_DEFAULT \\r
+{ \\r
+ false, /* Dont't lock configuration after it's been set */ \\r
+ false, /* No reset will be asserted due to Brownout when in EM4 */ \\r
+ emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \\r
+ true, /* Wake up on EM4 BURTC interrupt */ \\r
+ true, /* Enable VREG */ \\r
+}\r
+#endif\r
+#if defined( _EMU_EM4CTRL_MASK )\r
+#define EMU_EM4INIT_DEFAULT \\r
+{ \\r
+ false, /* Retain LFXO configuration upon EM4 entry */ \\r
+ false, /* Retain LFRCO configuration upon EM4 entry */ \\r
+ false, /* Retain ULFRCO configuration upon EM4 entry */ \\r
+ emuEM4Shutoff, /* Use EM4 shutoff state */ \\r
+ emuPinRetentionDisable, /* Do not retain pins in EM4 */ \\r
+}\r
#endif\r
-\r
\r
#if defined( BU_PRESENT )\r
/** Backup Power Domain Initialization structure */\r
bool enable;\r
} EMU_BUPDInit_TypeDef;\r
\r
-/** Default */\r
-#define EMU_BUPDINIT_DEFAULT \\r
- { emuProbe_Disable, /* Do not enable voltage probe */ \\r
- false, /* Disable BOD calibration mode */ \\r
- false, /* Disable BU_STAT pin for backup mode indication */ \\r
- \\r
- emuRes_Res0, /* RES0 series resistance between main and backup power */ \\r
- false, /* Don't enable strong switch */ \\r
- false, /* Don't enable medium switch */ \\r
- false, /* Don't enable weak switch */ \\r
- \\r
- emuPower_None, /* No connection between main and backup power (inactive mode) */ \\r
- emuPower_None, /* No connection between main and backup power (active mode) */ \\r
- true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \\r
- }\r
+/** Default Backup Power Domain configuration */\r
+#define EMU_BUPDINIT_DEFAULT \\r
+{ \\r
+ emuProbe_Disable, /* Do not enable voltage probe */ \\r
+ false, /* Disable BOD calibration mode */ \\r
+ false, /* Disable BU_STAT pin for backup mode indication */ \\r
+ \\r
+ emuRes_Res0, /* RES0 series resistance between main and backup power */ \\r
+ false, /* Don't enable strong switch */ \\r
+ false, /* Don't enable medium switch */ \\r
+ false, /* Don't enable weak switch */ \\r
+ \\r
+ emuPower_None, /* No connection between main and backup power (inactive mode) */ \\r
+ emuPower_None, /* No connection between main and backup power (active mode) */ \\r
+ true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \\r
+}\r
#endif\r
\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+/** DCDC initialization structure */\r
+typedef struct\r
+{\r
+ EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration */\r
+ EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0 */\r
+ uint16_t mVout; /**< Target output voltage (mV) */\r
+ uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0 (mA).\r
+ This estimate is also used for EM1 optimization,\r
+ so if EM1 current is expected to be higher than EM0,\r
+ then this parameter should hold the higher EM1 current. */\r
+ uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA).\r
+ This estimate is also used for EM3 and 4 optimization,\r
+ so if EM3 or 4 current is expected to be higher than EM2,\r
+ then this parameter should hold the higher EM3 or 4 current. */\r
+ uint16_t maxCurrent_mA; /**< Maximum peak DCDC output current (mA).\r
+ This can be set to the maximum for the power source,\r
+ for example the maximum for a battery. */\r
+ EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower;/**< Select analog peripheral power in DCDC-to-DVDD mode */\r
+ EMU_DcdcLnTransientMode_TypeDef lnTransientMode; /**< Low-noise transient mode */\r
+\r
+} EMU_DCDCInit_TypeDef;\r
+\r
+/** Default DCDC initialization */\r
+#if defined( _EFM_DEVICE )\r
+#define EMU_DCDCINIT_DEFAULT \\r
+{ \\r
+ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \\r
+ emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \\r
+ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \\r
+ 5, /* Nominal EM0 load current of less than 5mA */ \\r
+ 10, /* Nominal EM2/3 load current less than 10uA */ \\r
+ 160, /* Maximum peak current of 160mA */ \\r
+ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \\r
+ emuDcdcLnHighEfficiency, /* Use low-noise high-efficiency mode (ignored if emuDcdcMode_LowPower) */ \\r
+}\r
+#else /* EFR32 device */\r
+#define EMU_DCDCINIT_DEFAULT \\r
+{ \\r
+ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \\r
+ emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \\r
+ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \\r
+ 15, /* Nominal EM0 load current of less than 5mA */ \\r
+ 10, /* Nominal EM2/3 load current less than 10uA */ \\r
+ 160, /* Maximum peak current of 160mA */ \\r
+ emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply (less noise) */ \\r
+ emuDcdcLnFastTransient, /* Use low-noise fast-transient mode */ \\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+#if defined( EMU_STATUS_VMONRDY )\r
+/** VMON initialization structure */\r
+typedef struct\r
+{\r
+ EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */\r
+ int threshold; /**< Trigger threshold (mV) */\r
+ bool riseWakeup; /**< Wake up from EM4H on rising edge */\r
+ bool fallWakeup; /**< Wake up from EM4H on falling edge */\r
+ bool enable; /**< Enable VMON channel */\r
+ bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only) */\r
+} EMU_VmonInit_TypeDef;\r
+\r
+/** Default VMON initialization structure */\r
+#define EMU_VMONINIT_DEFAULT \\r
+{ \\r
+ emuVmonChannel_AVDD, /* AVDD VMON channel */ \\r
+ 3200, /* 3.2 V threshold */ \\r
+ false, /* Don't wake from EM4H on rising edge */ \\r
+ false, /* Don't wake from EM4H on falling edge */ \\r
+ true, /* Enable VMON channel */ \\r
+ false /* Don't disable IO0 retention */ \\r
+}\r
+\r
+/** VMON Hysteresis initialization structure */\r
+typedef struct\r
+{\r
+ EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */\r
+ int riseThreshold; /**< Rising threshold (mV) */\r
+ int fallThreshold; /**< Falling threshold (mV) */\r
+ bool riseWakeup; /**< Wake up from EM4H on rising edge */\r
+ bool fallWakeup; /**< Wake up from EM4H on falling edge */\r
+ bool enable; /**< Enable VMON channel */\r
+} EMU_VmonHystInit_TypeDef;\r
+\r
+/** Default VMON Hysteresis initialization structure */\r
+#define EMU_VMONHYSTINIT_DEFAULT \\r
+{ \\r
+ emuVmonChannel_AVDD, /* AVDD VMON channel */ \\r
+ 3200, /* 3.2 V rise threshold */ \\r
+ 3200, /* 3.2 V fall threshold */ \\r
+ false, /* Don't wake from EM4H on rising edge */ \\r
+ false, /* Don't wake from EM4H on falling edge */ \\r
+ true /* Enable VMON channel */ \\r
+}\r
+#endif /* EMU_STATUS_VMONRDY */\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
******************************************************************************/\r
__STATIC_INLINE void EMU_EnterEM1(void)\r
{\r
- /* Just enter Cortex-M3 sleep mode */\r
+ /* Enter sleep mode */\r
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;\r
__WFI();\r
}\r
\r
void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init);\r
-#if defined( _EMU_EM4CONF_MASK )\r
+#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )\r
void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init);\r
#endif\r
void EMU_EnterEM2(bool restore);\r
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);\r
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);\r
#endif\r
+#if defined( _EMU_DCDCCTRL_MASK )\r
+bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit);\r
+void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);\r
+bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);\r
+void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent);\r
+void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);\r
+bool EMU_DCDCPowerOff(void);\r
+#endif\r
+#if defined( EMU_STATUS_VMONRDY )\r
+void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit);\r
+void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit);\r
+void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);\r
+bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);\r
\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the status of the voltage monitor (VMON).\r
+ *\r
+ * @return\r
+ * Status of the VMON. True if all the enabled channels are ready, false if\r
+ * one or more of the enabled channels are not ready.\r
+ ******************************************************************************/\r
+__STATIC_INLINE bool EMU_VmonStatusGet(void)\r
+{\r
+ return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT);\r
+}\r
+#endif /* EMU_STATUS_VMONRDY */\r
\r
#if defined( _EMU_IF_MASK )\r
/***************************************************************************//**\r
******************************************************************************/\r
__STATIC_INLINE void EMU_IntDisable(uint32_t flags)\r
{\r
- EMU->IEN &= ~(flags);\r
+ EMU->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void EMU_EM4Lock(bool enable)\r
{\r
- BITBAND_Peripheral(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);\r
+ BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);\r
}\r
#endif\r
\r
-\r
#if defined( _EMU_STATUS_BURDY_MASK )\r
/***************************************************************************//**\r
* @brief\r
******************************************************************************/\r
__STATIC_INLINE void EMU_BUReady(void)\r
{\r
- while(!(EMU->STATUS & EMU_STATUS_BURDY));\r
+ while(!(EMU->STATUS & EMU_STATUS_BURDY))\r
+ ;\r
}\r
#endif\r
\r
-\r
#if defined( _EMU_ROUTE_BUVINPEN_MASK )\r
/***************************************************************************//**\r
* @brief\r
******************************************************************************/\r
__STATIC_INLINE void EMU_BUPinEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);\r
+ BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);\r
}\r
#endif\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
- * Lock the EMU in order to protect all its registers against unintended\r
+ * Lock the EMU in order to protect its registers against unintended\r
* modification.\r
*\r
* @note\r
* If locking the EMU registers, they must be unlocked prior to using any\r
- * EMU API functions modifying EMU registers. An exception to this is the\r
- * energy mode entering API (EMU_EnterEMn()), which can be used when the\r
- * EMU registers are locked.\r
+ * EMU API functions modifying EMU registers, excluding interrupt control\r
+ * and regulator control if the architecture has a EMU_PWRCTRL register.\r
+ * An exception to this is the energy mode entering API (EMU_EnterEMn()),\r
+ * which can be used when the EMU registers are locked.\r
******************************************************************************/\r
__STATIC_INLINE void EMU_Lock(void)\r
{\r
EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;\r
}\r
\r
+\r
+#if defined( _EMU_PWRLOCK_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Lock the EMU regulator control registers in order to protect against\r
+ * unintended modification.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void EMU_PowerLock(void)\r
+{\r
+ EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Unlock the EMU power control registers so that writing to\r
+ * locked registers again is possible.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void EMU_PowerUnlock(void)\r
+{\r
+ EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;\r
+}\r
+#endif\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Block entering EM2 or higher number energy modes.\r
******************************************************************************/\r
__STATIC_INLINE void EMU_EM2Block(void)\r
{\r
- BITBAND_Peripheral(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);\r
+ BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);\r
}\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Unblock entering EM2 or higher number energy modes.\r
******************************************************************************/\r
__STATIC_INLINE void EMU_EM2UnBlock(void)\r
{\r
- BITBAND_Peripheral(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);\r
+ BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);\r
}\r
\r
+#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained\r
+ * through EM4 entry and wakeup. The pin state is released by calling this function.\r
+ * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset),\r
+ * and when the initialization is done, this function can release pins and return control\r
+ * to the peripherals or GPIO.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void EMU_UnlatchPinRetention(void)\r
+{\r
+ EMU->CMD = EMU_CMD_EM4UNLATCH;\r
+}\r
+#endif\r
\r
/** @} (end addtogroup EMU) */\r
/** @} (end addtogroup EM_Library) */\r
#endif\r
\r
#endif /* defined( EMU_PRESENT ) */\r
-#endif /* __EM_EMU_H */\r
+#endif /* __SILICON_LABS_EM_EMU_H__ */\r
/***************************************************************************//**\r
* @file em_gpio.h\r
* @brief General Purpose IO (GPIO) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
******************************************************************************/\r
\r
\r
-#ifndef __SILICON_LABS_EM_GPIO_H_\r
-#define __SILICON_LABS_EM_GPIO_H_\r
+#ifndef __SILICON_LABS_EM_GPIO_H__\r
+#define __SILICON_LABS_EM_GPIO_H__\r
\r
#include "em_device.h"\r
#if defined(GPIO_COUNT) && (GPIO_COUNT > 0)\r
\r
#include <stdbool.h>\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
#include "em_assert.h"\r
\r
#ifdef __cplusplus\r
* @{\r
******************************************************************************/\r
\r
+/*******************************************************************************\r
+ ******************************* DEFINES ***********************************\r
+ ******************************************************************************/\r
+\r
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
+#if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 14\r
+#define _GPIO_PORT_B_PIN_COUNT 10\r
+#define _GPIO_PORT_C_PIN_COUNT 16\r
+#define _GPIO_PORT_D_PIN_COUNT 9\r
+#define _GPIO_PORT_E_PIN_COUNT 12\r
+#define _GPIO_PORT_F_PIN_COUNT 6\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0xF77F\r
+#define _GPIO_PORT_B_PIN_MASK 0x79F8\r
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_D_PIN_MASK 0x01FF\r
+#define _GPIO_PORT_E_PIN_MASK 0xFFF0\r
+#define _GPIO_PORT_F_PIN_MASK 0x003F\r
+\r
+#elif defined( _EFM32_HAPPY_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 6\r
+#define _GPIO_PORT_B_PIN_COUNT 5\r
+#define _GPIO_PORT_C_PIN_COUNT 12\r
+#define _GPIO_PORT_D_PIN_COUNT 4\r
+#define _GPIO_PORT_E_PIN_COUNT 4\r
+#define _GPIO_PORT_F_PIN_COUNT 6\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0x0707\r
+#define _GPIO_PORT_B_PIN_MASK 0x6980\r
+#define _GPIO_PORT_C_PIN_MASK 0xEF1F\r
+#define _GPIO_PORT_D_PIN_MASK 0x00F0\r
+#define _GPIO_PORT_E_PIN_MASK 0x3C00\r
+#define _GPIO_PORT_F_PIN_MASK 0x003F\r
+\r
+#elif defined( _EFM32_GIANT_FAMILY ) \\r
+ || defined( _EFM32_WONDER_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 16\r
+#define _GPIO_PORT_B_PIN_COUNT 16\r
+#define _GPIO_PORT_C_PIN_COUNT 16\r
+#define _GPIO_PORT_D_PIN_COUNT 16\r
+#define _GPIO_PORT_E_PIN_COUNT 16\r
+#define _GPIO_PORT_F_PIN_COUNT 13\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_F_PIN_MASK 0x1FFF\r
+\r
+#elif defined( _EFM32_GECKO_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 16\r
+#define _GPIO_PORT_B_PIN_COUNT 16\r
+#define _GPIO_PORT_C_PIN_COUNT 16\r
+#define _GPIO_PORT_D_PIN_COUNT 16\r
+#define _GPIO_PORT_E_PIN_COUNT 16\r
+#define _GPIO_PORT_F_PIN_COUNT 10\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF\r
+#define _GPIO_PORT_F_PIN_MASK 0x03FF\r
+\r
+#elif defined( _EFR32_MIGHTY_FAMILY ) \\r
+ || defined( _EFR32_BLUE_FAMILY ) \\r
+ || defined( _EFR32_FLEX_FAMILY ) \\r
+ || defined( _EFR32_ZAPPY_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 6\r
+#define _GPIO_PORT_B_PIN_COUNT 5\r
+#define _GPIO_PORT_C_PIN_COUNT 6\r
+#define _GPIO_PORT_D_PIN_COUNT 3\r
+#define _GPIO_PORT_E_PIN_COUNT 0\r
+#define _GPIO_PORT_F_PIN_COUNT 8\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0x003F\r
+#define _GPIO_PORT_B_PIN_MASK 0xF800\r
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0\r
+#define _GPIO_PORT_D_PIN_MASK 0xE000\r
+#define _GPIO_PORT_E_PIN_MASK 0x0000\r
+#define _GPIO_PORT_F_PIN_MASK 0x00FF\r
+\r
+#elif defined( _EFM32_PEARL_FAMILY ) \\r
+ || defined( _EFM32_JADE_FAMILY )\r
+\r
+#define _GPIO_PORT_A_PIN_COUNT 6\r
+#define _GPIO_PORT_B_PIN_COUNT 5\r
+#define _GPIO_PORT_C_PIN_COUNT 6\r
+#define _GPIO_PORT_D_PIN_COUNT 7\r
+#define _GPIO_PORT_E_PIN_COUNT 0\r
+#define _GPIO_PORT_F_PIN_COUNT 8\r
+\r
+#define _GPIO_PORT_A_PIN_MASK 0x003F\r
+#define _GPIO_PORT_B_PIN_MASK 0xF800\r
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0\r
+#define _GPIO_PORT_D_PIN_MASK 0xFE00\r
+#define _GPIO_PORT_E_PIN_MASK 0x0000\r
+#define _GPIO_PORT_F_PIN_MASK 0x00FF\r
+\r
+#else\r
+#warning "Port and pin masks are not defined for this family."\r
+#endif\r
+\r
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )\r
+#define _GPIO_PORT_SIZE(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \\r
+ (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \\r
+ (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \\r
+ 0)\r
+#else\r
+#define _GPIO_PORT_SIZE(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \\r
+ 0)\r
+#endif\r
+\r
+#if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK )\r
+#define _GPIO_PORT_MASK(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \\r
+ (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \\r
+ (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \\r
+ 0)\r
+#else\r
+#define _GPIO_PORT_MASK(port) ( \\r
+ (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \\r
+ (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \\r
+ (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \\r
+ (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \\r
+ (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \\r
+ (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \\r
+ 0)\r
+#endif\r
+\r
+/** Validation of port and pin */\r
+#define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) )\r
+#define GPIO_PORT_PIN_VALID(port, pin) ((( _GPIO_PORT_MASK(port)) >> (pin)) & 0x1 )\r
+\r
+/** Highest GPIO pin number */\r
+#define GPIO_PIN_MAX 15\r
+\r
+/** Highest GPIO port number */\r
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT )\r
+#define GPIO_PORT_MAX 7\r
+#else\r
+#define GPIO_PORT_MAX 5\r
+#endif\r
+/** @endcond */\r
+\r
/*******************************************************************************\r
******************************** ENUMS ************************************\r
******************************************************************************/\r
\r
-/** GPIO ports identificator. */\r
+/** GPIO ports ids. */\r
typedef enum\r
{\r
- gpioPortA = 0, /**< Port A */\r
- gpioPortB = 1, /**< Port B */\r
- gpioPortC = 2, /**< Port C */\r
- gpioPortD = 3, /**< Port D */\r
- gpioPortE = 4, /**< Port E */\r
- gpioPortF = 5 /**< Port F */\r
+#if ( _GPIO_PORT_A_PIN_COUNT > 0 )\r
+ gpioPortA = 0,\r
+#endif\r
+#if ( _GPIO_PORT_B_PIN_COUNT > 0 )\r
+ gpioPortB = 1,\r
+#endif\r
+#if ( _GPIO_PORT_C_PIN_COUNT > 0 )\r
+ gpioPortC = 2,\r
+#endif\r
+#if ( _GPIO_PORT_D_PIN_COUNT > 0 )\r
+ gpioPortD = 3,\r
+#endif\r
+#if ( _GPIO_PORT_E_PIN_COUNT > 0 )\r
+ gpioPortE = 4,\r
+#endif\r
+#if ( _GPIO_PORT_F_PIN_COUNT > 0 )\r
+ gpioPortF = 5\r
+#endif\r
+#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 )\r
+ gpioPortG = 6\r
+#endif\r
+#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 )\r
+ gpioPortH = 7\r
+#endif\r
} GPIO_Port_TypeDef;\r
\r
+#if defined( _GPIO_P_CTRL_DRIVEMODE_MASK )\r
/** GPIO drive mode. */\r
typedef enum\r
{\r
/** 2 mA */\r
gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW\r
} GPIO_DriveMode_TypeDef;\r
+#endif\r
+\r
+#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK ) && defined( _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK )\r
+/** GPIO drive strength. */\r
+typedef enum\r
+{\r
+ /** GPIO weak 1mA and alternate function weak 1mA */\r
+ gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,\r
+\r
+ /** GPIO weak 1mA and alternate function strong 10mA */\r
+ gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,\r
\r
-/** Pin mode. For more details on each mode, please refer to the EFM32\r
+ /** GPIO strong 10mA and alternate function weak 1mA */\r
+ gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,\r
+\r
+ /** GPIO strong 10mA and alternate function strong 10mA */\r
+ gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,\r
+} GPIO_DriveStrength_TypeDef;\r
+/* For legacy support */\r
+#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong\r
+#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak\r
+#endif\r
+\r
+/** Pin mode. For more details on each mode, please refer to the\r
* reference manual. */\r
typedef enum\r
{\r
gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER,\r
/** Push-pull output */\r
gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL,\r
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )\r
/** Push-pull output with drive-strength set by DRIVEMODE */\r
gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE,\r
+#endif\r
+#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLALT )\r
+ /** Push-pull using alternate control */\r
+ gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT,\r
+#endif\r
/** Wired-or output */\r
- gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR,\r
+ gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR,\r
/** Wired-or output with pull-down */\r
- gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN,\r
+ gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN,\r
/** Open-drain output */\r
- gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND,\r
+ gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND,\r
/** Open-drain output with filter */\r
- gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER,\r
+ gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER,\r
/** Open-drain output with pullup */\r
- gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,\r
+ gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,\r
/** Open-drain output with filter and pullup */\r
- gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,\r
+ gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,\r
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )\r
/** Open-drain output with drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,\r
+ gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,\r
/** Open-drain output with filter and drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,\r
+ gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER,\r
/** Open-drain output with pullup and drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,\r
+ gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP,\r
/** Open-drain output with filter, pullup and drive-strength set by DRIVEMODE */\r
- gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER\r
+ gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER\r
+#endif\r
+#if defined( _GPIO_P_MODEL_MODE0_WIREDANDALT )\r
+ /** Open-drain output using alternate control */\r
+ gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT,\r
+ /** Open-drain output using alternate control with filter */\r
+ gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER,\r
+ /** Open-drain output using alternate control with pullup */\r
+ gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP,\r
+ /** Open-drain output uisng alternate control with filter and pullup */\r
+ gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER,\r
+#endif\r
} GPIO_Mode_TypeDef;\r
\r
-\r
-/*******************************************************************************\r
- ******************************* DEFINES ***********************************\r
- ******************************************************************************/\r
-\r
-/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
-\r
-/** Validation of pin typically usable in assert statements. */\r
-#define GPIO_PIN_VALID(pin) ((pin) < 16)\r
-\r
-/** Validation of port typically usable in assert statements. */\r
-#define GPIO_PORT_VALID(port) ((port) <= gpioPortF)\r
-\r
-/** @endcond */\r
-\r
-\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
******************************************************************************/\r
GPIO_Mode_TypeDef mode,\r
unsigned int out);\r
\r
-# if defined( GPIO_CTRL_EM4RET )\r
-__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable);\r
+# if defined( _GPIO_EM4WUEN_MASK )\r
+void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);\r
#endif\r
\r
/***************************************************************************//**\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, (unsigned int)enable);\r
+#if defined( _GPIO_ROUTE_SWCLKPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable);\r
+#elif defined( _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, enable);\r
+#else\r
+#warning "ROUTE enable for SWCLK pin is not defined."\r
+#endif\r
}\r
\r
\r
/***************************************************************************//**\r
* @brief\r
- * Enable/disable serial wire data pin.\r
+ * Enable/disable serial wire data I/O pin.\r
*\r
* @note\r
* Disabling SWDClk will disable the debug interface, which may result in\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, (unsigned int)enable);\r
+#if defined( _GPIO_ROUTE_SWDIOPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable);\r
+#elif defined( _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, enable);\r
+#else\r
+#warning "ROUTE enable for SWDIO pin is not defined."\r
+#endif\r
}\r
\r
\r
-#if defined( GPIO_ROUTE_SWOPEN )\r
+#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )\r
/***************************************************************************//**\r
* @brief\r
* Enable/Disable serial wire output pin.\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)\r
{\r
- BITBAND_Peripheral(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, (unsigned int)enable);\r
+#if defined( _GPIO_ROUTE_SWOPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable);\r
+#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )\r
+ BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable);\r
+#else\r
+#warning "ROUTE enable for SWO/SWV pin is not defined."\r
+#endif\r
}\r
#endif\r
\r
+#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)\r
void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);\r
+#endif\r
\r
+#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK )\r
+void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength);\r
+#endif\r
\r
# if defined( _GPIO_EM4WUEN_MASK )\r
/**************************************************************************//**\r
#endif\r
\r
\r
-# if defined( _GPIO_EM4WUEN_MASK )\r
-/**************************************************************************//**\r
- * @brief\r
- * Enable GPIO pin wake-up from EM4. When the function exits,\r
- * EM4 mode can be safely entered.\r
- *\r
- * @note\r
- * It is assumed that the GPIO pin modes are set correctly.\r
- * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.\r
- *\r
- * @param[in] pinmask\r
- * Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.\r
- * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.\r
- * @param[in] polaritymask\r
- * Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.\r
- * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.\r
- *****************************************************************************/\r
-__STATIC_INLINE void GPIO_EM4EnablePinWakeup(uint32_t pinmask,\r
- uint32_t polaritymask)\r
-{\r
- EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);\r
- EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);\r
-\r
- GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */\r
- GPIO->EM4WUPOL |= pinmask & polaritymask;\r
- GPIO->EM4WUEN |= pinmask; /* Enable wakeup */\r
-\r
- GPIO_EM4SetPinRetention(true); /* Enable pin retention */\r
-\r
- GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */\r
-}\r
-#endif\r
-\r
-#if defined( _GPIO_EM4WUCAUSE_MASK )\r
+#if defined( _GPIO_EM4WUCAUSE_MASK ) || defined( _RMU_RSTCAUSE_EM4RST_MASK )\r
/**************************************************************************//**\r
* @brief\r
* Check which GPIO pin(s) that caused a wake-up from EM4.\r
*****************************************************************************/\r
__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)\r
{\r
+#if defined( _GPIO_EM4WUCAUSE_MASK )\r
return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;\r
+#else\r
+ return RMU->RSTCAUSE & _RMU_RSTCAUSE_EM4RST_MASK;\r
+#endif\r
}\r
#endif\r
\r
\r
-# if defined( GPIO_CTRL_EM4RET )\r
+#if defined( GPIO_CTRL_EM4RET ) || defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )\r
/**************************************************************************//**\r
* @brief\r
* Enable GPIO pin retention of output enable, output value, pull enable and\r
* pull direction in EM4.\r
+ * \r
+ * @note\r
+ * For platform 2 parts, EMU_EM4Init() and EMU_UnlatchPinRetention() offers \r
+ * more pin retention features. This function implements the EM4EXIT retention\r
+ * mode on platform 2.\r
*\r
* @param[in] enable\r
* @li true - enable EM4 pin retention.\r
{\r
if (enable)\r
{\r
+#if defined( GPIO_CTRL_EM4RET )\r
GPIO->CTRL |= GPIO_CTRL_EM4RET;\r
+#else\r
+ EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)\r
+ | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT;\r
+#endif\r
}\r
else\r
{\r
+#if defined( GPIO_CTRL_EM4RET )\r
GPIO->CTRL &= ~GPIO_CTRL_EM4RET;\r
+#else\r
+ EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)\r
+ | EMU_EM4CTRL_EM4IORETMODE_DISABLE;\r
+#endif\r
}\r
}\r
#endif\r
* @li GPIO_INSENSE_PRS - peripheral reflex system input sensing.\r
*\r
* @param[in] mask\r
- * Mask containing bitwise logic OR of bits similar as for @p val used to indicate\r
- * which input sense options to disable/enable.\r
+ * Mask containing bitwise logic OR of bits similar as for @p val used to\r
+ * indicate which input sense options to disable/enable.\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask)\r
{\r
******************************************************************************/\r
__STATIC_INLINE uint32_t GPIO_IntGet(void)\r
{\r
- return(GPIO->IF);\r
+ return GPIO->IF;\r
}\r
\r
\r
* @return\r
* The pin value, 0 or 1.\r
******************************************************************************/\r
-__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, unsigned int pin)\r
+__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port,\r
+ unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
- return((unsigned int)((GPIO->P[port].DIN >> pin) & 0x1));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+ return BUS_RegBitRead(&GPIO->P[port].DIN, pin);\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+#if defined( _GPIO_P_DOUTCLR_MASK )\r
GPIO->P[port].DOUTCLR = 1 << pin;\r
+#else\r
+ BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);\r
+#endif\r
}\r
\r
\r
* @return\r
* The DOUT setting for the requested pin, 0 or 1.\r
******************************************************************************/\r
-__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, unsigned int pin)\r
+__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port,\r
+ unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
- return((unsigned int)((GPIO->P[port].DOUT >> pin) & 0x1));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+ return BUS_RegBitRead(&GPIO->P[port].DOUT, pin);\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
-\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
+#if defined( _GPIO_P_DOUTSET_MASK )\r
GPIO->P[port].DOUTSET = 1 << pin;\r
+#else\r
+ BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);\r
+#endif\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin)\r
{\r
- EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));\r
+ EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));\r
\r
GPIO->P[port].DOUTTGL = 1 << pin;\r
}\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
- return(GPIO->P[port].DIN & _GPIO_P_DIN_DIN_MASK);\r
+ return GPIO->P[port].DIN;\r
}\r
\r
\r
__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
-\r
- GPIO->P[port].DOUTCLR = pins & _GPIO_P_DOUTCLR_DOUTCLR_MASK;\r
+#if defined( _GPIO_P_DOUTCLR_MASK )\r
+ GPIO->P[port].DOUTCLR = pins;\r
+#else\r
+ BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins);\r
+#endif\r
}\r
\r
\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
- return(GPIO->P[port].DOUT & _GPIO_P_DOUT_DOUT_MASK);\r
+ return GPIO->P[port].DOUT;\r
}\r
\r
\r
__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
-\r
- GPIO->P[port].DOUTSET = pins & _GPIO_P_DOUTSET_DOUTSET_MASK;\r
+#if defined( _GPIO_P_DOUTSET_MASK )\r
+ GPIO->P[port].DOUTSET = pins;\r
+#else\r
+ BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins);\r
+#endif\r
}\r
\r
\r
* @param[in] mask\r
* Mask indicating which bits to modify.\r
******************************************************************************/\r
-__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, uint32_t val, uint32_t mask)\r
+__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port,\r
+ uint32_t val,\r
+ uint32_t mask)\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
\r
/***************************************************************************//**\r
* @brief\r
- * Toggle a single pin in GPIO port data out register.\r
+ * Toggle pins in GPIO port data out register.\r
*\r
* @note\r
* In order for the setting to take effect on the output pad, the pin must\r
{\r
EFM_ASSERT(GPIO_PORT_VALID(port));\r
\r
- GPIO->P[port].DOUTTGL = pins & _GPIO_P_DOUTTGL_DOUTTGL_MASK;\r
+ GPIO->P[port].DOUTTGL = pins;\r
}\r
\r
\r
GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK;\r
}\r
\r
-\r
/** @} (end addtogroup GPIO) */\r
/** @} (end addtogroup EM_Library) */\r
\r
#endif\r
\r
#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_GPIO_H_ */\r
+#endif /* __SILICON_LABS_EM_GPIO_H__ */\r
/***************************************************************************//**\r
* @file em_i2c.h\r
* @brief Inter-intergrated circuit (I2C) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_I2C_H_\r
-#define __SILICON_LABS_EM_I2C_H_\r
+#ifndef __SILICON_LABS_EM_I2C_H__\r
+#define __SILICON_LABS_EM_I2C_H__\r
\r
#include "em_device.h"\r
#if defined(I2C_COUNT) && (I2C_COUNT > 0)\r
#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY) \\r
|| defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)\r
#define I2C_FREQ_STANDARD_MAX 93000\r
-\r
#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
#define I2C_FREQ_STANDARD_MAX 92000\r
-\r
+#elif defined(_SILICON_LABS_32B_PLATFORM_2)\r
+// None of the chips on this platform has been characterized on this parameter.\r
+// Use same value as on Wonder until further notice.\r
+#define I2C_FREQ_STANDARD_MAX 92000\r
#else\r
#error "Unknown device family."\r
#endif\r
} I2C_Init_TypeDef;\r
\r
/** Suggested default config for I2C init structure. */\r
-#define I2C_INIT_DEFAULT \\r
- { true, /* Enable when init done */ \\r
- true, /* Set to master mode */ \\r
- 0, /* Use currently configured reference clock */ \\r
- I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \\r
- /* within I2C spec */ \\r
- i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \\r
- }\r
+#define I2C_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable when init done */ \\r
+ true, /* Set to master mode */ \\r
+ 0, /* Use currently configured reference clock */ \\r
+ I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \\r
+ /* within I2C spec */ \\r
+ i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \\r
+}\r
\r
\r
/**\r
\r
uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c);\r
void I2C_BusFreqSet(I2C_TypeDef *i2c,\r
- uint32_t refFreq,\r
- uint32_t freq,\r
- I2C_ClockHLR_TypeDef type);\r
+ uint32_t freqRef,\r
+ uint32_t freqScl,\r
+ I2C_ClockHLR_TypeDef i2cMode);\r
void I2C_Enable(I2C_TypeDef *i2c, bool enable);\r
void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init);\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)\r
{\r
- return(i2c->IF);\r
+ return i2c->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending I2C interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @param[in] i2c\r
+ * Pointer to I2C peripheral register block.\r
+ *\r
+ * @return\r
+ * Pending and enabled I2C interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in I2Cn_IEN and\r
+ * - the pending interrupt flags I2Cn_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = i2c->IEN;\r
+ return i2c->IF & ien;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)\r
{\r
- return((uint8_t)(i2c->SADDR));\r
+ return ((uint8_t)(i2c->SADDR));\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)\r
{\r
- return((uint8_t)(i2c->SADDRMASK));\r
+ return ((uint8_t)(i2c->SADDRMASK));\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_I2C_H_ */\r
+#endif /* __SILICON_LABS_EM_I2C_H__ */\r
/***************************************************************************//**\r
* @file em_idac.h\r
* @brief Current Digital to Analog Converter (IDAC) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_IDAC_H_\r
-#define __SILICON_LABS_EM_IDAC_H_\r
+#ifndef __SILICON_LABS_EM_IDAC_H__\r
+#define __SILICON_LABS_EM_IDAC_H__\r
\r
#include "em_device.h"\r
\r
/** Output mode. */\r
typedef enum\r
{\r
+#if defined( _IDAC_CTRL_OUTMODE_MASK )\r
idacOutputPin = IDAC_CTRL_OUTMODE_PIN, /**< Output to IDAC OUT pin */\r
idacOutputADC = IDAC_CTRL_OUTMODE_ADC /**< Output to ADC */\r
+#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )\r
+ idacOutputAPORT1XCH0 = IDAC_CTRL_APORTOUTSEL_APORT1XCH0, /**< Output to APORT 1X CH0 */\r
+ idacOutputAPORT1YCH1 = IDAC_CTRL_APORTOUTSEL_APORT1YCH1, /**< Output to APORT 1Y CH1 */\r
+ idacOutputAPORT1XCH2 = IDAC_CTRL_APORTOUTSEL_APORT1XCH2, /**< Output to APORT 1X CH2 */\r
+ idacOutputAPORT1YCH3 = IDAC_CTRL_APORTOUTSEL_APORT1YCH3, /**< Output to APORT 1Y CH3 */\r
+ idacOutputAPORT1XCH4 = IDAC_CTRL_APORTOUTSEL_APORT1XCH4, /**< Output to APORT 1X CH4 */\r
+ idacOutputAPORT1YCH5 = IDAC_CTRL_APORTOUTSEL_APORT1YCH5, /**< Output to APORT 1Y CH5 */\r
+ idacOutputAPORT1XCH6 = IDAC_CTRL_APORTOUTSEL_APORT1XCH6, /**< Output to APORT 1X CH6 */\r
+ idacOutputAPORT1YCH7 = IDAC_CTRL_APORTOUTSEL_APORT1YCH7, /**< Output to APORT 1Y CH7 */\r
+ idacOutputAPORT1XCH8 = IDAC_CTRL_APORTOUTSEL_APORT1XCH8, /**< Output to APORT 1X CH8 */\r
+ idacOutputAPORT1YCH9 = IDAC_CTRL_APORTOUTSEL_APORT1YCH9, /**< Output to APORT 1Y CH9 */\r
+ idacOutputAPORT1XCH10 = IDAC_CTRL_APORTOUTSEL_APORT1XCH10, /**< Output to APORT 1X CH10 */\r
+ idacOutputAPORT1YCH11 = IDAC_CTRL_APORTOUTSEL_APORT1YCH11, /**< Output to APORT 1Y CH11 */\r
+ idacOutputAPORT1XCH12 = IDAC_CTRL_APORTOUTSEL_APORT1XCH12, /**< Output to APORT 1X CH12 */\r
+ idacOutputAPORT1YCH13 = IDAC_CTRL_APORTOUTSEL_APORT1YCH13, /**< Output to APORT 1Y CH13 */\r
+ idacOutputAPORT1XCH14 = IDAC_CTRL_APORTOUTSEL_APORT1XCH14, /**< Output to APORT 1X CH14 */\r
+ idacOutputAPORT1YCH15 = IDAC_CTRL_APORTOUTSEL_APORT1YCH15, /**< Output to APORT 1Y CH15 */\r
+ idacOutputAPORT1XCH16 = IDAC_CTRL_APORTOUTSEL_APORT1XCH16, /**< Output to APORT 1X CH16 */\r
+ idacOutputAPORT1YCH17 = IDAC_CTRL_APORTOUTSEL_APORT1YCH17, /**< Output to APORT 1Y CH17 */\r
+ idacOutputAPORT1XCH18 = IDAC_CTRL_APORTOUTSEL_APORT1XCH18, /**< Output to APORT 1X CH18 */\r
+ idacOutputAPORT1YCH19 = IDAC_CTRL_APORTOUTSEL_APORT1YCH19, /**< Output to APORT 1Y CH19 */\r
+ idacOutputAPORT1XCH20 = IDAC_CTRL_APORTOUTSEL_APORT1XCH20, /**< Output to APORT 1X CH20 */\r
+ idacOutputAPORT1YCH21 = IDAC_CTRL_APORTOUTSEL_APORT1YCH21, /**< Output to APORT 1Y CH21 */\r
+ idacOutputAPORT1XCH22 = IDAC_CTRL_APORTOUTSEL_APORT1XCH22, /**< Output to APORT 1X CH22 */\r
+ idacOutputAPORT1YCH23 = IDAC_CTRL_APORTOUTSEL_APORT1YCH23, /**< Output to APORT 1Y CH23 */\r
+ idacOutputAPORT1XCH24 = IDAC_CTRL_APORTOUTSEL_APORT1XCH24, /**< Output to APORT 1X CH24 */\r
+ idacOutputAPORT1YCH25 = IDAC_CTRL_APORTOUTSEL_APORT1YCH25, /**< Output to APORT 1Y CH25 */\r
+ idacOutputAPORT1XCH26 = IDAC_CTRL_APORTOUTSEL_APORT1XCH26, /**< Output to APORT 1X CH26 */\r
+ idacOutputAPORT1YCH27 = IDAC_CTRL_APORTOUTSEL_APORT1YCH27, /**< Output to APORT 1Y CH27 */\r
+ idacOutputAPORT1XCH28 = IDAC_CTRL_APORTOUTSEL_APORT1XCH28, /**< Output to APORT 1X CH28 */\r
+ idacOutputAPORT1YCH29 = IDAC_CTRL_APORTOUTSEL_APORT1YCH29, /**< Output to APORT 1Y CH29 */\r
+ idacOutputAPORT1XCH30 = IDAC_CTRL_APORTOUTSEL_APORT1XCH30, /**< Output to APORT 1X CH30 */\r
+ idacOutputAPORT1YCH31 = IDAC_CTRL_APORTOUTSEL_APORT1YCH31, /**< Output to APORT 1Y CH31 */\r
+#endif\r
} IDAC_OutMode_TypeDef;\r
\r
\r
idacPRSSELCh1 = IDAC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
idacPRSSELCh2 = IDAC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
idacPRSSELCh3 = IDAC_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH4 )\r
+#if defined( IDAC_CTRL_PRSSEL_PRSCH4 )\r
idacPRSSELCh4 = IDAC_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */\r
-#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH5 )\r
idacPRSSELCh5 = IDAC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */\r
#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH6 )\r
+#if defined( IDAC_CTRL_PRSSEL_PRSCH6 )\r
idacPRSSELCh6 = IDAC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */\r
-#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH7 )\r
idacPRSSELCh7 = IDAC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */\r
-#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH8 )\r
idacPRSSELCh8 = IDAC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */\r
-#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH9 )\r
idacPRSSELCh9 = IDAC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */\r
-#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH10 )\r
idacPRSSELCh10 = IDAC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 */\r
-#endif\r
-#if defined( IDAC_CTRL_PRSSEL_PRSCH11 )\r
idacPRSSELCh11 = IDAC_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 */\r
#endif\r
} IDAC_PRSSEL_TypeDef;\r
} IDAC_Init_TypeDef;\r
\r
/** Default config for IDAC init structure. */\r
-#define IDAC_INIT_DEFAULT \\r
- { false, /* Leave IDAC disabled when init done. */ \\r
- idacOutputPin, /* Output to IDAC OUT pin. */ \\r
- false, /* Disable PRS triggering. */ \\r
- idacPRSSELCh0, /* Select PRS ch0 (if PRS triggering enabled). */ \\r
- false /* Disable current sink mode. */ \\r
- }\r
+#if defined( _IDAC_CTRL_OUTMODE_MASK )\r
+#define IDAC_INIT_DEFAULT \\r
+{ \\r
+ false, /**< Leave IDAC disabled when init done. */ \\r
+ idacOutputPin, /**< Output to IDAC output pin. */ \\r
+ false, /**< Disable PRS triggering. */ \\r
+ idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \\r
+ false /**< Disable current sink mode. */ \\r
+}\r
+#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )\r
+#define IDAC_INIT_DEFAULT \\r
+{ \\r
+ false, /**< Leave IDAC disabled when init done. */ \\r
+ idacOutputAPORT1XCH0, /**< Output to APORT. */ \\r
+ false, /**< Disable PRS triggering. */ \\r
+ idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \\r
+ false /**< Disable current sink mode. */ \\r
+}\r
+#endif\r
\r
\r
/*******************************************************************************\r
void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable);\r
\r
\r
+#if defined( _IDAC_IEN_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear one or more pending IDAC interrupts.\r
+ *\r
+ * @param[in] IDAC\r
+ * Pointer to IDAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * Pending IDAC interrupt source(s) to clear. Use one or more valid\r
+ * interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void IDAC_IntClear(IDAC_TypeDef *idac, uint32_t flags)\r
+{\r
+ idac->IFC = flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more IDAC interrupts.\r
+ *\r
+ * @param[in] IDAC\r
+ * Pointer to IDAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * IDAC interrupt source(s) to disable. Use one or more valid\r
+ * interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void IDAC_IntDisable(IDAC_TypeDef *idac, uint32_t flags)\r
+{\r
+ idac->IEN &= ~flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more IDAC interrupts.\r
+ *\r
+ * @note\r
+ * Depending on the use, a pending interrupt may already be set prior to\r
+ * enabling the interrupt. Consider using IDAC_IntClear() prior to enabling\r
+ * if such a pending interrupt should be ignored.\r
+ *\r
+ * @param[in] IDAC\r
+ * Pointer to IDAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * IDAC interrupt source(s) to enable. Use one or more valid\r
+ * interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void IDAC_IntEnable(IDAC_TypeDef *idac, uint32_t flags)\r
+{\r
+ idac->IEN |= flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get pending IDAC interrupt flags.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @param[in] IDAC\r
+ * Pointer to IDAC peripheral register block.\r
+ *\r
+ * @return\r
+ * IDAC interrupt source(s) pending. Returns one or more valid\r
+ * interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t IDAC_IntGet(IDAC_TypeDef *idac)\r
+{\r
+ return idac->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending IDAC interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @param[in] IDAC\r
+ * Pointer to IDAC peripheral register block.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled IDAC interrupt sources.\r
+ * The return value is the bitwise AND combination of\r
+ * - the OR combination of enabled interrupt sources in IDACx_IEN_nnn\r
+ * register (IDACx_IEN_nnn) and\r
+ * - the OR combination of valid interrupt flags of the IDAC module\r
+ * (IDACx_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t IDAC_IntGetEnabled(IDAC_TypeDef *idac)\r
+{\r
+ uint32_t ien;\r
+\r
+ /* Store flags in temporary variable in order to define explicit order\r
+ * of volatile accesses. */\r
+ ien = idac->IEN;\r
+\r
+ /* Bitwise AND of pending and enabled interrupts */\r
+ return idac->IF & ien;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set one or more pending IDAC interrupts from SW.\r
+ *\r
+ * @param[in] IDAC\r
+ * Pointer to IDAC peripheral register block.\r
+ *\r
+ * @param[in] flags\r
+ * IDAC interrupt source(s) to set to pending. Use one or more valid\r
+ * interrupt flags for the IDAC module (IDAC_IF_nnn) OR'ed together.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void IDAC_IntSet(IDAC_TypeDef *idac, uint32_t flags)\r
+{\r
+ idac->IFS = flags;\r
+}\r
+#endif\r
+\r
+\r
/** @} (end addtogroup IDAC) */\r
/** @} (end addtogroup EM_Library) */\r
\r
\r
#endif /* defined(IDAC_COUNT) && (IDAC_COUNT > 0) */\r
\r
-#endif /* __SILICON_LABS_EM_IDAC_H_ */\r
+#endif /* __SILICON_LABS_EM_IDAC_H__ */\r
/***************************************************************************//**\r
* @file em_int.h\r
* @brief Interrupt enable/disable unit API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_INT_H_\r
-#define __SILICON_LABS_EM_INT_H_\r
+#ifndef __SILICON_LABS_EM_INT_H__\r
+#define __SILICON_LABS_EM_INT_H__\r
\r
#include "em_device.h"\r
\r
* Disable interrupts and increment lock level counter.\r
*\r
* @return\r
- * The resulting interrupt nesting level.\r
+ * The resulting interrupt disable nesting level.\r
*\r
******************************************************************************/\r
__STATIC_INLINE uint32_t INT_Disable(void)\r
* Enable interrupts.\r
*\r
* @return\r
- * The resulting interrupt nesting level.\r
+ * The resulting interrupt disable nesting level.\r
*\r
* @details\r
* Decrement interrupt lock level counter and enable interrupts if counter\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_INT_H_ */\r
+#endif /* __SILICON_LABS_EM_INT_H__ */\r
/***************************************************************************//**\r
* @file em_lcd.h\r
* @brief Liquid Crystal Display (LCD) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_LCD_H_\r
-#define __SILICON_LABS_EM_LCD_H_\r
+#ifndef __SILICON_LABS_EM_LCD_H__\r
+#define __SILICON_LABS_EM_LCD_H__\r
\r
#include "em_device.h"\r
\r
lcdMuxTriplex = LCD_DISPCTRL_MUX_TRIPLEX,\r
/** Quadruplex / 1/4 Duty cycle (segments can be multiplexed with LCD_COM[0:3]) */\r
lcdMuxQuadruplex = LCD_DISPCTRL_MUX_QUADRUPLEX,\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_DISPCTRL_MUXE_MUXE)\r
/** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */\r
lcdMuxSextaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,\r
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */\r
lcdBiasOneHalf = LCD_DISPCTRL_BIAS_ONEHALF,\r
/** 1/3 Bias (4 levels) */\r
lcdBiasOneThird = LCD_DISPCTRL_BIAS_ONETHIRD,\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_DISPCTRL_BIAS_ONEFOURTH)\r
/** 1/4 Bias (5 levels) */\r
lcdBiasOneFourth = LCD_DISPCTRL_BIAS_ONEFOURTH,\r
#endif\r
lcdSegment16_19 = (1 << 4),\r
/** Select segment lines 20 to 23 */\r
lcdSegment20_23 = (1 << 5),\r
-#if defined(_EFM32_TINY_FAMILY)\r
+#if defined(_LCD_SEGD0L_MASK) && (_LCD_SEGD0L_MASK == 0x00FFFFFFUL)\r
/** Select all segment lines */\r
lcdSegmentAll = (0x003f)\r
-#endif\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#elif defined(_LCD_SEGD0H_MASK) && (_LCD_SEGD0H_MASK == 0x000000FFUL)\r
/** Select segment lines 24 to 27 */\r
lcdSegment24_27 = (1 << 6),\r
/** Select segment lines 28 to 31 */\r
LCD_AnimShift_TypeDef BShift;\r
/** A and B Logical Operation to use for mixing and outputting resulting segments */\r
LCD_AnimLogic_TypeDef animLogic;\r
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_BACTRL_ALOC)\r
/** Number of first segment to animate. Options are 0 or 8 for Giant/Leopard. End is startSeg+7 */\r
int startSeg;\r
#endif\r
\r
/** Default config for LCD init structure, enables 160 segments */\r
#define LCD_INIT_DEFAULT \\r
- { true, \\r
- lcdMuxQuadruplex, \\r
- lcdBiasOneThird, \\r
- lcdWaveLowPower, \\r
- lcdVLCDSelVDD, \\r
- lcdConConfVLCD \\r
- }\r
+{ \\r
+ true, \\r
+ lcdMuxQuadruplex, \\r
+ lcdBiasOneThird, \\r
+ lcdWaveLowPower, \\r
+ lcdVLCDSelVDD, \\r
+ lcdConConfVLCD \\r
+}\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segment, bool enable);\r
void LCD_SegmentSet(int com, int bit, bool enable);\r
void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits);\r
-#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(_LCD_SEGD0H_MASK)\r
void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits);\r
#endif\r
void LCD_ContrastSet(int level);\r
void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost);\r
\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_CTRL_DSC)\r
void LCD_BiasSegmentSet(int segment, int biasLevel);\r
void LCD_BiasComSet(int com, int biasLevel);\r
#endif\r
\r
-__STATIC_INLINE void LCD_Enable(bool enable);\r
-__STATIC_INLINE void LCD_AnimEnable(bool enable);\r
-__STATIC_INLINE void LCD_BlinkEnable(bool enable);\r
-__STATIC_INLINE void LCD_BlankEnable(bool enable);\r
-__STATIC_INLINE void LCD_FrameCountEnable(bool enable);\r
-__STATIC_INLINE int LCD_AnimState(void);\r
-__STATIC_INLINE int LCD_BlinkState(void);\r
-__STATIC_INLINE void LCD_FreezeEnable(bool enable);\r
-__STATIC_INLINE uint32_t LCD_SyncBusyGet(void);\r
-__STATIC_INLINE void LCD_SyncBusyDelay(uint32_t flags);\r
-__STATIC_INLINE uint32_t LCD_IntGet(void);\r
-__STATIC_INLINE uint32_t LCD_IntGetEnabled(void);\r
-__STATIC_INLINE void LCD_IntSet(uint32_t flags);\r
-__STATIC_INLINE void LCD_IntEnable(uint32_t flags);\r
-__STATIC_INLINE void LCD_IntDisable(uint32_t flags);\r
-__STATIC_INLINE void LCD_IntClear(uint32_t flags);\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
-__STATIC_INLINE void LCD_DSCEnable(bool enable);\r
-#endif\r
-\r
/***************************************************************************//**\r
* @brief\r
* Enable or disable LCD controller\r
}\r
else\r
{\r
- LCD->CTRL &= ~(LCD_CTRL_EN);\r
+ LCD->CTRL &= ~LCD_CTRL_EN;\r
}\r
}\r
\r
}\r
else\r
{\r
- LCD->BACTRL &= ~(LCD_BACTRL_AEN);\r
+ LCD->BACTRL &= ~LCD_BACTRL_AEN;\r
}\r
}\r
\r
}\r
else\r
{\r
- LCD->BACTRL &= ~(LCD_BACTRL_BLINKEN);\r
+ LCD->BACTRL &= ~LCD_BACTRL_BLINKEN;\r
}\r
}\r
\r
}\r
else\r
{\r
- LCD->BACTRL &= ~(LCD_BACTRL_BLANK);\r
+ LCD->BACTRL &= ~LCD_BACTRL_BLANK;\r
}\r
}\r
\r
}\r
else\r
{\r
- LCD->BACTRL &= ~(LCD_BACTRL_FCEN);\r
+ LCD->BACTRL &= ~LCD_BACTRL_FCEN;\r
}\r
}\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t LCD_SyncBusyGet(void)\r
{\r
- return(LCD->SYNCBUSY);\r
+ return LCD->SYNCBUSY;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t LCD_IntGet(void)\r
{\r
- return(LCD->IF);\r
+ return LCD->IF;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t LCD_IntGetEnabled(void)\r
{\r
- uint32_t tmp = 0U;\r
+ uint32_t ien;\r
\r
/* Store LCD->IEN in temporary variable in order to define explicit order\r
* of volatile accesses. */\r
- tmp = LCD->IEN;\r
+ ien = LCD->IEN;\r
\r
/* Bitwise AND of pending and enabled interrupts */\r
- return LCD->IF & tmp;\r
+ return LCD->IF & ien;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void LCD_IntDisable(uint32_t flags)\r
{\r
- LCD->IEN &= ~(flags);\r
+ LCD->IEN &= ~flags;\r
}\r
\r
\r
}\r
\r
\r
-#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)\r
+#if defined(LCD_CTRL_DSC)\r
/***************************************************************************//**\r
* @brief\r
* Enable or disable LCD Direct Segment Control\r
}\r
else\r
{\r
- LCD->CTRL &= ~(LCD_CTRL_DSC);\r
+ LCD->CTRL &= ~LCD_CTRL_DSC;\r
}\r
}\r
#endif\r
\r
#endif /* defined(LCD_COUNT) && (LCD_COUNT > 0) */\r
\r
-#endif /* __SILICON_LABS_EM_LCD_H_ */\r
+#endif /* __SILICON_LABS_EM_LCD_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file em_ldma.h\r
+ * @brief Direct memory access (LDMA) API\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.@n\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.@n\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_EM_LDMA_H__\r
+#define __SILICON_LABS_EM_LDMA_H__\r
+\r
+#include "em_device.h"\r
+\r
+#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )\r
+\r
+#include <stdbool.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup LDMA\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ ******************************** ENUMS ************************************\r
+ ******************************************************************************/\r
+\r
+/**\r
+ * This value controls the number of unit data transfers per arbitration\r
+ * cycle, providing a means to balance DMA channels' load on the controller.\r
+ */\r
+typedef enum\r
+{\r
+ ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */\r
+ ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */\r
+ ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */\r
+} LDMA_CtrlBlockSize_t;\r
+\r
+/** DMA structure type. */\r
+typedef enum\r
+{\r
+ ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */\r
+ ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */\r
+ ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */\r
+} LDMA_CtrlStructType_t;\r
+\r
+/** DMA transfer block or cycle selector. */\r
+typedef enum\r
+{\r
+ ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */\r
+ ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */\r
+} LDMA_CtrlReqMode_t;\r
+\r
+/** Source address increment unit size. */\r
+typedef enum\r
+{\r
+ ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */\r
+ ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */\r
+ ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */\r
+ ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment the source address. */\r
+} LDMA_CtrlSrcInc_t;\r
+\r
+/** DMA transfer unit size. */\r
+typedef enum\r
+{\r
+ ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */\r
+ ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */\r
+ ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */\r
+} LDMA_CtrlSize_t;\r
+\r
+/** Destination address increment unit size. */\r
+typedef enum\r
+{\r
+ ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */\r
+ ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */\r
+ ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */\r
+ ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment the destination address. */\r
+} LDMA_CtrlDstInc_t;\r
+\r
+/** Source addressing mode. */\r
+typedef enum\r
+{\r
+ ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */\r
+ ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */\r
+} LDMA_CtrlSrcAddrMode_t;\r
+\r
+/** Destination addressing mode. */\r
+typedef enum\r
+{\r
+ ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */\r
+ ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */\r
+} LDMA_CtrlDstAddrMode_t;\r
+\r
+/** DMA linkload address mode. */\r
+typedef enum\r
+{\r
+ ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */\r
+ ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement releative address. */\r
+} LDMA_LinkMode_t;\r
+\r
+/** Insert extra arbitration slots to increase channel arbitration priority. */\r
+typedef enum\r
+{\r
+ ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */\r
+ ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */\r
+ ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */\r
+ ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */\r
+} LDMA_CfgArbSlots_t;\r
+\r
+/** Source address increment sign. */\r
+typedef enum\r
+{\r
+ ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */\r
+ ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */\r
+} LDMA_CfgSrcIncSign_t;\r
+\r
+/** Destination address increment sign. */\r
+typedef enum\r
+{\r
+ ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */\r
+ ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */\r
+} LDMA_CfgDstIncSign_t;\r
+\r
+/** Peripherals that can trigger LDMA transfers. */\r
+typedef enum\r
+{\r
+ ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )\r
+ ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )\r
+ ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )\r
+ ldmaPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )\r
+ ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )\r
+ ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )\r
+ ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )\r
+ ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )\r
+ ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )\r
+ ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )\r
+ ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )\r
+ ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )\r
+ ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )\r
+ ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )\r
+ ldmaPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )\r
+ ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )\r
+ ldmaPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )\r
+ ldmaPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )\r
+ ldmaPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )\r
+ ldmaPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )\r
+ ldmaPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )\r
+ ldmaPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )\r
+ ldmaPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )\r
+ ldmaPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )\r
+ ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )\r
+ ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )\r
+ ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )\r
+ ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )\r
+ ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )\r
+ ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )\r
+ ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )\r
+ ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )\r
+ ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )\r
+ ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )\r
+ ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )\r
+ ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )\r
+ ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )\r
+ ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )\r
+ ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )\r
+ ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )\r
+ ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )\r
+ ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT.\r
+ #endif\r
+ #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )\r
+ ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1 ///< Trig on USART1_TXEMPTY.\r
+ #endif\r
+} LDMA_PeripheralSignal_t;\r
+\r
+\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor.\r
+ * @details\r
+ * The LDMA DMA controller supports three different DMA descriptors. Each\r
+ * consist of four WORD's which map directly onto hw control registers for a\r
+ * given DMA channel. The three descriptor types are XFER, SYNC and WRI.\r
+ * Refer to the reference manual for further information.\r
+ */\r
+typedef union\r
+{\r
+ /**\r
+ * TRANSFER DMA descriptor, this is the only descriptor type which can be\r
+ * used to start a DMA transfer.\r
+ */\r
+ struct\r
+ {\r
+ uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */\r
+ uint32_t reserved0 : 1;\r
+ uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */\r
+ uint32_t xferCnt : 11; /**< Transfer count minus one. */\r
+ uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */\r
+ uint32_t blockSize : 4; /**< Number of unit transfers per arb. cycle. */\r
+ uint32_t doneIfs : 1; /**< Generate interrupt when done. */\r
+ uint32_t reqMode : 1; /**< Block or cycle transfer selector. */\r
+ uint32_t decLoopCnt : 1; /**< Enable looped transfers. */\r
+ uint32_t ignoreSrec : 1; /**< Ignore single requests. */\r
+ uint32_t srcInc : 2; /**< Source address increment unit size. */\r
+ uint32_t size : 2; /**< DMA transfer unit size. */\r
+ uint32_t dstInc : 2; /**< Destination address increment unit size. */\r
+ uint32_t srcAddrMode: 1; /**< Source addressing mode. */\r
+ uint32_t dstAddrMode: 1; /**< Destination addressing mode. */\r
+\r
+ uint32_t srcAddr; /**< DMA source address. */\r
+ uint32_t dstAddr; /**< DMA destination address. */\r
+\r
+ uint32_t linkMode : 1; /**< Select absolute or relative link address.*/\r
+ uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */\r
+ int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */\r
+ } xfer;\r
+\r
+ /** SYNCHRONIZE DMA descriptor, used for intra channel transfer\r
+ * syncronization.\r
+ */\r
+ struct\r
+ {\r
+ uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */\r
+ uint32_t reserved0 : 1;\r
+ uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */\r
+ uint32_t xferCnt : 11; /**< Transfer count minus one. */\r
+ uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */\r
+ uint32_t blockSize : 4; /**< Number of unit transfers per arb. cycle. */\r
+ uint32_t doneIfs : 1; /**< Generate interrupt when done. */\r
+ uint32_t reqMode : 1; /**< Block or cycle transfer selector. */\r
+ uint32_t decLoopCnt : 1; /**< Enable looped transfers. */\r
+ uint32_t ignoreSrec : 1; /**< Ignore single requests. */\r
+ uint32_t srcInc : 2; /**< Source address increment unit size. */\r
+ uint32_t size : 2; /**< DMA transfer unit size. */\r
+ uint32_t dstInc : 2; /**< Destination address increment unit size. */\r
+ uint32_t srcAddrMode: 1; /**< Source addressing mode. */\r
+ uint32_t dstAddrMode: 1; /**< Destination addressing mode. */\r
+\r
+ uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */\r
+ uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register*/\r
+ uint32_t reserved3 : 16;\r
+ uint32_t matchVal : 8; /**< Sync trig match value. */\r
+ uint32_t matchEn : 8; /**< Sync trig match enable. */\r
+ uint32_t reserved4 : 16;\r
+\r
+ uint32_t linkMode : 1; /**< Select absolute or relative link address.*/\r
+ uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */\r
+ int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */\r
+ } sync;\r
+\r
+ /** WRITE DMA descriptor, used for write immediate operations. */\r
+ struct\r
+ {\r
+ uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type.*/\r
+ uint32_t reserved0 : 1;\r
+ uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */\r
+ uint32_t xferCnt : 11; /**< Transfer count minus one. */\r
+ uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */\r
+ uint32_t blockSize : 4; /**< Number of unit transfers per arb. cycle. */\r
+ uint32_t doneIfs : 1; /**< Generate interrupt when done. */\r
+ uint32_t reqMode : 1; /**< Block or cycle transfer selector. */\r
+ uint32_t decLoopCnt : 1; /**< Enable looped transfers. */\r
+ uint32_t ignoreSrec : 1; /**< Ignore single requests. */\r
+ uint32_t srcInc : 2; /**< Source address increment unit size. */\r
+ uint32_t size : 2; /**< DMA transfer unit size. */\r
+ uint32_t dstInc : 2; /**< Destination address increment unit size. */\r
+ uint32_t srcAddrMode: 1; /**< Source addressing mode. */\r
+ uint32_t dstAddrMode: 1; /**< Destination addressing mode. */\r
+\r
+ uint32_t immVal; /**< Data to be written at dstAddr. */\r
+ uint32_t dstAddr; /**< DMA write destination address. */\r
+\r
+ uint32_t linkMode : 1; /**< Select absolute or relative link address.*/\r
+ uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */\r
+ int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */\r
+ } wri;\r
+} LDMA_Descriptor_t;\r
+\r
+/** @brief LDMA initialization configuration structure. */\r
+typedef struct\r
+{\r
+ uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator.*/\r
+ uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */\r
+ uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */\r
+ uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */\r
+} LDMA_Init_t;\r
+\r
+/**\r
+ * @brief\r
+ * DMA transfer configuration structure.\r
+ * @details\r
+ * This struct configures all aspects of a DMA transfer.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ldmaReqSel; /**< Selects DMA trigger source. */\r
+ uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */\r
+ uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */\r
+ uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */\r
+ uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */\r
+ bool ldmaReqDis; /**< Mask the PRS trigger input. */\r
+ bool ldmaDbgHalt; /**< Dis. DMA trig when cpu is halted. */\r
+ uint8_t ldmaCfgArbSlots; /**< Arbitration slot number. */\r
+ uint8_t ldmaCfgSrcIncSign; /**< Source addr. increment sign. */\r
+ uint8_t ldmaCfgDstIncSign; /**< Dest. addr. increment sign. */\r
+ uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */\r
+} LDMA_TransferCfg_t;\r
+\r
+\r
+/*******************************************************************************\r
+ ************************** STRUCT INITIALIZERS ****************************\r
+ ******************************************************************************/\r
+\r
+\r
+/** @brief Default DMA initialization structure. */\r
+#define LDMA_INIT_DEFAULT \\r
+{ \\r
+ .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT, /* Fixed priority arbitration. */ \\r
+ .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \\r
+ .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \\r
+ .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * Generic DMA transfer configuration for memory to memory transfers.\r
+ */\r
+#define LDMA_TRANSFER_CFG_MEMORY() \\r
+{ \\r
+ 0, 0, 0, 0, 0, \\r
+ false, false, ldmaCfgArbSlotsAs1, \\r
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * Generic DMA transfer configuration for looped memory to memory transfers.\r
+ */\r
+#define LDMA_TRANSFER_CFG_MEMORY_LOOP( loopCnt) \\r
+{ \\r
+ 0, 0, 0, 0, 0, \\r
+ false, false, ldmaCfgArbSlotsAs1, \\r
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \\r
+ loopCnt \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * Generic DMA transfer configuration for memory to/from peripheral transfers.\r
+ */\r
+#define LDMA_TRANSFER_CFG_PERIPHERAL( signal ) \\r
+{ \\r
+ signal, 0, 0, 0, 0, \\r
+ false, false, ldmaCfgArbSlotsAs1, \\r
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * Generic DMA transfer configuration for looped memory to/from peripheral transfers.\r
+ */\r
+#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP( signal, loopCnt ) \\r
+{ \\r
+ signal, 0, 0, 0, 0, \\r
+ false, false, ldmaCfgArbSlotsAs1, \\r
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for single memory to memory word transfer.\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of words to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeWord, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for single memory to memory half-word transfer.\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of half-words to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeHalf, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for single memory to memory byte transfer.\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for linked memory to memory word transfer.\r
+ *\r
+ * The link address must be an absolute address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is not\r
+ * initialized.\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of words to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 0, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeWord, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeAbs, \\r
+ .link = 1, \\r
+ .linkAddr = 0 /* Must be set runtime ! */ \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for linked memory to memory half-word transfer.\r
+ *\r
+ * The link address must be an absolute address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is not\r
+ * initialized.\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of half-words to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 0, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeHalf, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeAbs, \\r
+ .link = 1, \\r
+ .linkAddr = 0 /* Must be set runtime ! */ \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for linked memory to memory byte transfer.\r
+ *\r
+ * The link address must be an absolute address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is not\r
+ * initialized.\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 0, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeAbs, \\r
+ .link = 1, \\r
+ .linkAddr = 0 /* Must be set runtime ! */ \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for linked memory to memory word transfer.\r
+ *\r
+ * The link address is a relative address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is\r
+ * initialized to 4, assuming that the next descriptor immediately follows\r
+ * this descriptor (in memory).\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of words to transfer.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD( src, dest, count, linkjmp ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 0, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeWord, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for linked memory to memory half-word transfer.\r
+ *\r
+ * The link address is a relative address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is\r
+ * initialized to 4, assuming that the next descriptor immediately follows\r
+ * this descriptor (in memory).\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of half-words to transfer.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src, dest, count, linkjmp ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 0, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeHalf, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for linked memory to memory byte transfer.\r
+ *\r
+ * The link address is a relative address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is\r
+ * initialized to 4, assuming that the next descriptor immediately follows\r
+ * this descriptor (in memory).\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE( src, dest, count, linkjmp ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 1, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 0, \\r
+ .reqMode = ldmaCtrlReqModeAll, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for byte transfers from a peripheral to memory.\r
+ * @param[in] src Peripheral data source register address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 0, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeBlock, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncNone, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for byte transfers from memory to a peripheral\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Peripheral data register destination address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE( src, dest, count ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 0, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeBlock, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncNone, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for byte transfers from a peripheral to memory.\r
+ * @param[in] src Peripheral data source register address.\r
+ * @param[in] dest Destination data address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( src, dest, count, linkjmp ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 0, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeBlock, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncNone, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncOne, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for byte transfers from memory to a peripheral\r
+ * @param[in] src Source data address.\r
+ * @param[in] dest Peripheral data register destination address.\r
+ * @param[in] count Number of bytes to transfer.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE( src, dest, count, linkjmp ) \\r
+{ \\r
+ .xfer = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeXfer, \\r
+ .structReq = 0, \\r
+ .xferCnt = ( count ) - 1, \\r
+ .byteSwap = 0, \\r
+ .blockSize = ldmaCtrlBlockSizeUnit1, \\r
+ .doneIfs = 1, \\r
+ .reqMode = ldmaCtrlReqModeBlock, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = ldmaCtrlSrcIncOne, \\r
+ .size = ldmaCtrlSizeByte, \\r
+ .dstInc = ldmaCtrlDstIncNone, \\r
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \\r
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \\r
+ .srcAddr = (uint32_t)(src), \\r
+ .dstAddr = (uint32_t)(dest), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for Immediate WRITE transfer\r
+ * @param[in] value Immediate value to write.\r
+ * @param[in] address Write sddress.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_WRITE( value, address ) \\r
+{ \\r
+ .wri = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeWrite, \\r
+ .structReq = 1, \\r
+ .xferCnt = 0, \\r
+ .byteSwap = 0, \\r
+ .blockSize = 0, \\r
+ .doneIfs = 1, \\r
+ .reqMode = 0, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = 0, \\r
+ .size = 0, \\r
+ .dstInc = 0, \\r
+ .srcAddrMode = 0, \\r
+ .dstAddrMode = 0, \\r
+ .immVal = (value), \\r
+ .dstAddr = (uint32_t)(address), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for Immediate WRITE transfer\r
+ *\r
+ * The link address must be an absolute address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is not\r
+ * initialized.\r
+ * @param[in] value Immediate value to write.\r
+ * @param[in] address Write sddress.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKABS_WRITE( value, address ) \\r
+{ \\r
+ .wri = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeWrite, \\r
+ .structReq = 1, \\r
+ .xferCnt = 0, \\r
+ .byteSwap = 0, \\r
+ .blockSize = 0, \\r
+ .doneIfs = 0, \\r
+ .reqMode = 0, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = 0, \\r
+ .size = 0, \\r
+ .dstInc = 0, \\r
+ .srcAddrMode = 0, \\r
+ .dstAddrMode = 0, \\r
+ .immVal = (value), \\r
+ .dstAddr = (uint32_t)(address), \\r
+ .linkMode = ldmaLinkModeAbs, \\r
+ .link = 1, \\r
+ .linkAddr = 0 /* Must be set runtime ! */ \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for Immediate WRITE transfer\r
+ * @param[in] value Immediate value to write.\r
+ * @param[in] address Write sddress.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_WRITE( value, address, linkjmp ) \\r
+{ \\r
+ .wri = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeWrite, \\r
+ .structReq = 1, \\r
+ .xferCnt = 0, \\r
+ .byteSwap = 0, \\r
+ .blockSize = 0, \\r
+ .doneIfs = 0, \\r
+ .reqMode = 0, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = 0, \\r
+ .size = 0, \\r
+ .dstInc = 0, \\r
+ .srcAddrMode = 0, \\r
+ .dstAddrMode = 0, \\r
+ .immVal = (value), \\r
+ .dstAddr = (uint32_t)(address), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for SYNC transfer\r
+ * @param[in] set Sync pattern bits to set.\r
+ * @param[in] clr Sync pattern bits to clear.\r
+ * @param[in] matchValue Sync pattern to match.\r
+ * @param[in] matchEnable Sync pattern bits to enable for match.\r
+ */\r
+#define LDMA_DESCRIPTOR_SINGLE_SYNC( set, clr, matchValue, matchEnable ) \\r
+{ \\r
+ .sync = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeSync, \\r
+ .structReq = 1, \\r
+ .xferCnt = 0, \\r
+ .byteSwap = 0, \\r
+ .blockSize = 0, \\r
+ .doneIfs = 1, \\r
+ .reqMode = 0, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = 0, \\r
+ .size = 0, \\r
+ .dstInc = 0, \\r
+ .srcAddrMode = 0, \\r
+ .dstAddrMode = 0, \\r
+ .syncSet = (set), \\r
+ .syncClr = (clr), \\r
+ .matchVal = (matchValue), \\r
+ .matchEn = (matchEnable), \\r
+ .linkMode = 0, \\r
+ .link = 0, \\r
+ .linkAddr = 0 \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for SYNC transfer\r
+ *\r
+ * The link address must be an absolute address.\r
+ * @note\r
+ * The linkAddr member of the transfer descriptor is not\r
+ * initialized.\r
+ * @param[in] set Sync pattern bits to set.\r
+ * @param[in] clr Sync pattern bits to clear.\r
+ * @param[in] matchValue Sync pattern to match.\r
+ * @param[in] matchEnable Sync pattern bits to enable for match.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKABS_SYNC( set, clr, matchValue, matchEnable ) \\r
+{ \\r
+ .sync = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeSync, \\r
+ .structReq = 1, \\r
+ .xferCnt = 0, \\r
+ .byteSwap = 0, \\r
+ .blockSize = 0, \\r
+ .doneIfs = 0, \\r
+ .reqMode = 0, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = 0, \\r
+ .size = 0, \\r
+ .dstInc = 0, \\r
+ .srcAddrMode = 0, \\r
+ .dstAddrMode = 0, \\r
+ .syncSet = (set), \\r
+ .syncClr = (clr), \\r
+ .matchVal = (matchValue), \\r
+ .matchEn = (matchEnable), \\r
+ .linkMode = ldmaLinkModeAbs, \\r
+ .link = 1, \\r
+ .linkAddr = 0 /* Must be set runtime ! */ \\r
+ } \\r
+}\r
+\r
+/**\r
+ * @brief\r
+ * DMA descriptor initializer for SYNC transfer\r
+ * @param[in] set Sync pattern bits to set.\r
+ * @param[in] clr Sync pattern bits to clear.\r
+ * @param[in] matchValue Sync pattern to match.\r
+ * @param[in] matchEnable Sync pattern bits to enable for match.\r
+ * @param[in] linkjmp Address of descriptor to link to expressed as a\r
+ * signed number of descriptors from "here".\r
+ * 1=one descriptor forward in memory,\r
+ * 0=one this descriptor,\r
+ * -1=one descriptor back in memory.\r
+ */\r
+#define LDMA_DESCRIPTOR_LINKREL_SYNC( set, clr, matchValue, matchEnable, linkjmp ) \\r
+{ \\r
+ .sync = \\r
+ { \\r
+ .structType = ldmaCtrlStructTypeSync, \\r
+ .structReq = 1, \\r
+ .xferCnt = 0, \\r
+ .byteSwap = 0, \\r
+ .blockSize = 0, \\r
+ .doneIfs = 0, \\r
+ .reqMode = 0, \\r
+ .decLoopCnt = 0, \\r
+ .ignoreSrec = 0, \\r
+ .srcInc = 0, \\r
+ .size = 0, \\r
+ .dstInc = 0, \\r
+ .srcAddrMode = 0, \\r
+ .dstAddrMode = 0, \\r
+ .syncSet = (set), \\r
+ .syncClr = (clr), \\r
+ .matchVal = (matchValue), \\r
+ .matchEn = (matchEnable), \\r
+ .linkMode = ldmaLinkModeRel, \\r
+ .link = 1, \\r
+ .linkAddr = ( linkjmp ) * 4 \\r
+ } \\r
+}\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+void LDMA_DeInit( void );\r
+void LDMA_Init( LDMA_Init_t *init );\r
+void LDMA_StartTransfer( int ch,\r
+ LDMA_TransferCfg_t *transfer,\r
+ LDMA_Descriptor_t *descriptor );\r
+void LDMA_StopTransfer( int ch );\r
+bool LDMA_TransferDone( int ch );\r
+uint32_t LDMA_TransferRemainingCount( int ch );\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear one or more pending LDMA interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * Pending LDMA interrupt sources to clear. Use one or more valid\r
+ * interrupt flags for the LDMA module (LDMA_IFC_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void LDMA_IntClear(uint32_t flags)\r
+{\r
+ LDMA->IFC = flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more LDMA interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * LDMA interrupt sources to disable. Use one or more valid\r
+ * interrupt flags for the LDMA module (LDMA_IEN_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void LDMA_IntDisable(uint32_t flags)\r
+{\r
+ LDMA->IEN &= ~flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more LDMA interrupts.\r
+ *\r
+ * @note\r
+ * Depending on the use, a pending interrupt may already be set prior to\r
+ * enabling the interrupt. Consider using LDMA_IntClear() prior to enabling\r
+ * if such a pending interrupt should be ignored.\r
+ *\r
+ * @param[in] flags\r
+ * LDMA interrupt sources to enable. Use one or more valid\r
+ * interrupt flags for the LDMA module (LDMA_IEN_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void LDMA_IntEnable(uint32_t flags)\r
+{\r
+ LDMA->IEN |= flags;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get pending LDMA interrupt flags.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * LDMA interrupt sources pending. Returns one or more valid\r
+ * interrupt flags for the LDMA module (LDMA_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t LDMA_IntGet(void)\r
+{\r
+ return LDMA->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending LDMA interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled LDMA interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in LDMA_IEN and\r
+ * - the pending interrupt flags LDMA_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = LDMA->IEN;\r
+ return LDMA->IF & ien;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set one or more pending LDMA interrupts\r
+ *\r
+ * @param[in] flags\r
+ * LDMA interrupt sources to set to pending. Use one or more valid\r
+ * interrupt flags for the LDMA module (LDMA_IFS_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void LDMA_IntSet(uint32_t flags)\r
+{\r
+ LDMA->IFS = flags;\r
+}\r
+\r
+/** @} (end addtogroup LDMA) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */\r
+#endif /* __SILICON_LABS_EM_LDMA_H__ */\r
/***************************************************************************//**\r
* @file em_lesense.h\r
* @brief Low Energy Sensor (LESENSE) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_LESENSE_H_\r
-#define __SILICON_LABS_EM_LESENSE_H_\r
+#ifndef __SILICON_LABS_EM_LESENSE_H__\r
+#define __SILICON_LABS_EM_LESENSE_H__\r
\r
#include "em_device.h"\r
\r
} LESENSE_CoreCtrlDesc_TypeDef;\r
\r
/** Default configuration for LESENSE_CtrlDesc_TypeDef structure. */\r
-#define LESENSE_CORECTRL_DESC_DEFAULT \\r
- { \\r
- lesenseScanStartPeriodic, /* Start new scan each time the period counter overflows. */ \\r
- lesensePRSCh0, /* Default PRS channel is selected. */ \\r
- lesenseScanConfDirMap, /* Direct mapping SCANCONF register usage strategy. */ \\r
- false, /* Don't invert ACMP0 output. */ \\r
- false, /* Don't invert ACMP1 output. */ \\r
- false, /* Disable dual sampling. */ \\r
- true, /* Store scan result after each scan. */ \\r
- true, /* Overwrite result buffer register even if it is full. */ \\r
- lesenseBufTrigHalf, /* Trigger interrupt and DMA request if result buffer is half full. */ \\r
- lesenseDMAWakeUpDisable, /* Don't wake up on DMA from EM2. */ \\r
- lesenseBiasModeDontTouch, /* Don't touch bias configuration. */ \\r
- true /* Keep LESENSE running in debug mode. */ \\r
- }\r
+#define LESENSE_CORECTRL_DESC_DEFAULT \\r
+{ \\r
+ lesenseScanStartPeriodic, /* Start new scan each time the period counter overflows. */ \\r
+ lesensePRSCh0, /* Default PRS channel is selected. */ \\r
+ lesenseScanConfDirMap, /* Direct mapping SCANCONF register usage strategy. */ \\r
+ false, /* Don't invert ACMP0 output. */ \\r
+ false, /* Don't invert ACMP1 output. */ \\r
+ false, /* Disable dual sampling. */ \\r
+ true, /* Store scan result after each scan. */ \\r
+ true, /* Overwrite result buffer register even if it is full. */ \\r
+ lesenseBufTrigHalf, /* Trigger interrupt and DMA request if result buffer is half full. */ \\r
+ lesenseDMAWakeUpDisable, /* Don't wake up on DMA from EM2. */ \\r
+ lesenseBiasModeDontTouch, /* Don't touch bias configuration. */ \\r
+ true /* Keep LESENSE running in debug mode. */ \\r
+}\r
\r
\r
/** LESENSE timing control descriptor structure. */\r
} LESENSE_TimeCtrlDesc_TypeDef;\r
\r
/** Default configuration for LESENSE_TimeCtrlDesc_TypeDef structure. */\r
-#define LESENSE_TIMECTRL_DESC_DEFAULT \\r
- { \\r
- 0U /* No sensor interaction delay. */ \\r
- }\r
+#define LESENSE_TIMECTRL_DESC_DEFAULT \\r
+{ \\r
+ 0U /* No sensor interaction delay. */ \\r
+}\r
\r
\r
/** LESENSE peripheral control descriptor structure. */\r
} LESENSE_PerCtrlDesc_TypeDef;\r
\r
/** Default configuration for LESENSE_PerCtrl_TypeDef structure. */\r
-#define LESENSE_PERCTRL_DESC_DEFAULT \\r
- { \\r
- lesenseDACIfData, /**/ \\r
- lesenseDACConvModeDisable, /**/ \\r
- lesenseDACOutModeDisable, /**/ \\r
- lesenseDACIfData, /**/ \\r
- lesenseDACConvModeDisable, /**/ \\r
- lesenseDACOutModeDisable, /**/ \\r
- 0U, /**/ \\r
- lesenseDACRefVdd, /**/ \\r
- lesenseACMPModeMuxThres, /**/ \\r
- lesenseACMPModeMuxThres, /**/ \\r
- lesenseWarmupModeKeepWarm, /**/ \\r
- }\r
+#define LESENSE_PERCTRL_DESC_DEFAULT \\r
+{ \\r
+ lesenseDACIfData, /**/ \\r
+ lesenseDACConvModeDisable, /**/ \\r
+ lesenseDACOutModeDisable, /**/ \\r
+ lesenseDACIfData, /**/ \\r
+ lesenseDACConvModeDisable, /**/ \\r
+ lesenseDACOutModeDisable, /**/ \\r
+ 0U, /**/ \\r
+ lesenseDACRefVdd, /**/ \\r
+ lesenseACMPModeMuxThres, /**/ \\r
+ lesenseACMPModeMuxThres, /**/ \\r
+ lesenseWarmupModeKeepWarm, /**/ \\r
+}\r
\r
\r
/** LESENSE decoder control descriptor structure. */\r
} LESENSE_DecCtrlDesc_TypeDef;\r
\r
/** Default configuration for LESENSE_PerCtrl_TypeDef structure. */\r
-#define LESENSE_DECCTRL_DESC_DEFAULT \\r
- { \\r
- lesenseDecInputSensorSt, /**/ \\r
- 0U, /**/ \\r
- false, /**/ \\r
- true, /**/ \\r
- true, /**/ \\r
- true, /**/ \\r
- true, /**/ \\r
- true, /**/ \\r
- false, /**/ \\r
- lesensePRSCh0, /**/ \\r
- lesensePRSCh1, /**/ \\r
- lesensePRSCh2, /**/ \\r
- lesensePRSCh3, /**/ \\r
- }\r
+#define LESENSE_DECCTRL_DESC_DEFAULT \\r
+{ \\r
+ lesenseDecInputSensorSt, /**/ \\r
+ 0U, /**/ \\r
+ false, /**/ \\r
+ true, /**/ \\r
+ true, /**/ \\r
+ true, /**/ \\r
+ true, /**/ \\r
+ true, /**/ \\r
+ false, /**/ \\r
+ lesensePRSCh0, /**/ \\r
+ lesensePRSCh1, /**/ \\r
+ lesensePRSCh2, /**/ \\r
+ lesensePRSCh3, /**/ \\r
+}\r
\r
\r
/** LESENSE module initialization structure. */\r
} LESENSE_Init_TypeDef;\r
\r
/** Default configuration for LESENSE_Init_TypeDef structure. */\r
-#define LESENSE_INIT_DEFAULT \\r
- { \\r
- .coreCtrl = LESENSE_CORECTRL_DESC_DEFAULT, /* Default core control parameters. */ \\r
- .timeCtrl = LESENSE_TIMECTRL_DESC_DEFAULT, /* Default time control parameters. */ \\r
- .perCtrl = LESENSE_PERCTRL_DESC_DEFAULT, /* Default peripheral control parameters. */ \\r
- .decCtrl = LESENSE_DECCTRL_DESC_DEFAULT /* Default decoder control parameters. */ \\r
- }\r
+#define LESENSE_INIT_DEFAULT \\r
+{ \\r
+ .coreCtrl = LESENSE_CORECTRL_DESC_DEFAULT, /* Default core control parameters. */ \\r
+ .timeCtrl = LESENSE_TIMECTRL_DESC_DEFAULT, /* Default time control parameters. */ \\r
+ .perCtrl = LESENSE_PERCTRL_DESC_DEFAULT, /* Default peripheral control parameters. */ \\r
+ .decCtrl = LESENSE_DECCTRL_DESC_DEFAULT /* Default decoder control parameters. */ \\r
+}\r
\r
\r
/** Channel descriptor structure. */\r
} LESENSE_ChAll_TypeDef;\r
\r
/** Default configuration for scan channel. */\r
-#define LESENSE_CH_CONF_DEFAULT \\r
- { \\r
- true, /* Enable scan channel. */ \\r
- true, /* Enable the assigned pin on scan channel. */ \\r
- true, /* Enable interrupts on channel. */ \\r
- lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \\r
- lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \\r
- false, /* Don't use alternate excitation pins for excitation. */ \\r
- false, /* Disabled to shift results from this channel to the decoder register. */ \\r
- false, /* Disabled to invert the scan result bit. */ \\r
- false, /* Disabled to store counter value in the result buffer. */ \\r
- lesenseClkLF, /* Use the LF clock for excitation timing. */ \\r
- lesenseClkLF, /* Use the LF clock for sample timing. */ \\r
- 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \\r
- 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \\r
- 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \\r
- 0x00U, /* ACMP threshold has been set to 0. */ \\r
- lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \\r
- lesenseSetIntNone, /* No interrupt is generated by the channel. */ \\r
- 0xFFU, /* Counter threshold has bee set to 0xFF. */ \\r
- lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \\r
- }\r
+#define LESENSE_CH_CONF_DEFAULT \\r
+{ \\r
+ true, /* Enable scan channel. */ \\r
+ true, /* Enable the assigned pin on scan channel. */ \\r
+ true, /* Enable interrupts on channel. */ \\r
+ lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \\r
+ lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \\r
+ false, /* Don't use alternate excitation pins for excitation. */ \\r
+ false, /* Disabled to shift results from this channel to the decoder register. */ \\r
+ false, /* Disabled to invert the scan result bit. */ \\r
+ false, /* Disabled to store counter value in the result buffer. */ \\r
+ lesenseClkLF, /* Use the LF clock for excitation timing. */ \\r
+ lesenseClkLF, /* Use the LF clock for sample timing. */ \\r
+ 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \\r
+ 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \\r
+ 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \\r
+ 0x00U, /* ACMP threshold has been set to 0. */ \\r
+ lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \\r
+ lesenseSetIntNone, /* No interrupt is generated by the channel. */ \\r
+ 0xFFU, /* Counter threshold has bee set to 0xFF. */ \\r
+ lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \\r
+}\r
\r
/** Default configuration for all sensor channels. */\r
-#define LESENSE_SCAN_CONF_DEFAULT \\r
- { \\r
- { \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 0. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 1. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 2. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 3. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 4. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 5. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 6. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 7. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 8. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 9. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 10. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 11. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 12. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 13. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 14. */ \\r
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 15. */ \\r
- } \\r
- }\r
+#define LESENSE_SCAN_CONF_DEFAULT \\r
+{ \\r
+ { \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 0. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 1. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 2. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 3. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 4. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 5. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 6. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 7. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 8. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 9. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 10. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 11. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 12. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 13. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 14. */ \\r
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 15. */ \\r
+ } \\r
+}\r
\r
\r
/** Alternate excitation descriptor structure. */\r
\r
\r
/** Default configuration for alternate excitation channel. */\r
-#define LESENSE_ALTEX_CH_CONF_DEFAULT \\r
- { \\r
- true, /* Alternate excitation enabled.*/ \\r
- lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \\r
- false /* Excite only for corresponding channel. */ \\r
- }\r
+#define LESENSE_ALTEX_CH_CONF_DEFAULT \\r
+{ \\r
+ true, /* Alternate excitation enabled.*/ \\r
+ lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \\r
+ false /* Excite only for corresponding channel. */ \\r
+}\r
\r
/** Default configuration for all alternate excitation channels. */\r
-#define LESENSE_ALTEX_CONF_DEFAULT \\r
- { \\r
- lesenseAltExMapACMP, \\r
- { \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \\r
- LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \\r
- } \\r
- }\r
+#define LESENSE_ALTEX_CONF_DEFAULT \\r
+{ \\r
+ lesenseAltExMapACMP, \\r
+ { \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \\r
+ LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \\r
+ } \\r
+}\r
\r
\r
/** Decoder state condition descriptor structure. */\r
} LESENSE_DecStCond_TypeDef;\r
\r
/** Default configuration for decoder state condition. */\r
-#define LESENSE_ST_CONF_DEFAULT \\r
- { \\r
- 0x0FU, /* Compare value set to 0x0F. */ \\r
- 0x00U, /* All decoder inputs masked. */ \\r
- 0U, /* Next state is state 0. */ \\r
- lesenseTransActNone, /* No PRS action performed on compare match. */ \\r
- false /* No interrupt triggered on compare match. */ \\r
- }\r
+#define LESENSE_ST_CONF_DEFAULT \\r
+{ \\r
+ 0x0FU, /* Compare value set to 0x0F. */ \\r
+ 0x00U, /* All decoder inputs masked. */ \\r
+ 0U, /* Next state is state 0. */ \\r
+ lesenseTransActNone, /* No PRS action performed on compare match. */ \\r
+ false /* No interrupt triggered on compare match. */ \\r
+}\r
\r
\r
/** Decoder state x configuration structure. */\r
} LESENSE_DecStAll_TypeDef;\r
\r
/** Default configuration for all decoder states. */\r
-#define LESENSE_DECODER_CONF_DEFAULT \\r
- { /* chain | Descriptor A | Descriptor B */ \\r
- { \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \\r
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \\r
- } \\r
- }\r
+#define LESENSE_DECODER_CONF_DEFAULT \\r
+{ /* chain | Descriptor A | Descriptor B */ \\r
+ { \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \\r
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \\r
+ } \\r
+}\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
void LESENSE_DecoderStart(void);\r
void LESENSE_ResultBufferClear(void);\r
\r
-__STATIC_INLINE void LESENSE_DecoderStop(void);\r
-__STATIC_INLINE uint32_t LESENSE_StatusGet(void);\r
-__STATIC_INLINE void LESENSE_StatusWait(uint32_t flag);\r
-__STATIC_INLINE uint32_t LESENSE_ChannelActiveGet(void);\r
-__STATIC_INLINE uint32_t LESENSE_ScanResultGet(void);\r
-__STATIC_INLINE uint32_t LESENSE_ScanResultDataGet(void);\r
-__STATIC_INLINE uint32_t LESENSE_ScanResultDataBufferGet(uint32_t idx);\r
-__STATIC_INLINE uint32_t LESENSE_SensorStateGet(void);\r
-__STATIC_INLINE void LESENSE_RAMPowerDown(void);\r
-\r
-__STATIC_INLINE void LESENSE_IntClear(uint32_t flags);\r
-__STATIC_INLINE void LESENSE_IntEnable(uint32_t flags);\r
-__STATIC_INLINE void LESENSE_IntDisable(uint32_t flags);\r
-__STATIC_INLINE void LESENSE_IntSet(uint32_t flags);\r
-__STATIC_INLINE uint32_t LESENSE_IntGet(void);\r
-__STATIC_INLINE uint32_t LESENSE_IntGetEnabled(void);\r
-\r
\r
/***************************************************************************//**\r
* @brief\r
*\r
* @details\r
* This function shuts off the LESENSE RAM in order to decrease the leakage\r
- * current of EFM32 if LESENSE is not used in your application.\r
+ * current of the mcu if LESENSE is not used in your application.\r
*\r
* @note\r
* Warning! Once the LESENSE RAM is powered down, it cannot be powered up\r
******************************************************************************/\r
__STATIC_INLINE void LESENSE_IntDisable(uint32_t flags)\r
{\r
- LESENSE->IEN &= ~(flags);\r
+ LESENSE->IEN &= ~flags;\r
}\r
\r
\r
\r
#endif /* defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) */\r
\r
-#endif /* __SILICON_LABS_EM_LESENSE_H_ */\r
+#endif /* __SILICON_LABS_EM_LESENSE_H__ */\r
/***************************************************************************//**\r
* @file em_letimer.h\r
* @brief Low Energy Timer (LETIMER) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_LETIMER_H_\r
-#define __SILICON_LABS_EM_LETIMER_H_\r
+#ifndef __SILICON_LABS_EM_LETIMER_H__\r
+#define __SILICON_LABS_EM_LETIMER_H__\r
\r
#include <stdbool.h>\r
#include "em_device.h"\r
{\r
bool enable; /**< Start counting when init completed. */\r
bool debugRun; /**< Counter shall keep running during debug halt. */\r
+#if defined(LETIMER_CTRL_RTCC0TEN)\r
bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */\r
bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */\r
+#endif\r
bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */\r
bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */\r
uint8_t out0Pol; /**< Idle value for output 0. */\r
} LETIMER_Init_TypeDef;\r
\r
/** Default config for LETIMER init structure. */\r
-#define LETIMER_INIT_DEFAULT \\r
- { true, /* Enable timer when init complete. */ \\r
- false, /* Stop counter during debug halt. */ \\r
- false, /* Do not start counting on RTC COMP0 match. */ \\r
- false, /* Do not start counting on RTC COMP1 match. */ \\r
- false, /* Do not load COMP0 into CNT on underflow. */ \\r
- false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \\r
- 0, /* Idle value 0 for output 0. */ \\r
- 0, /* Idle value 0 for output 1. */ \\r
- letimerUFOANone, /* No action on underflow on output 0. */ \\r
- letimerUFOANone, /* No action on underflow on output 1. */ \\r
- letimerRepeatFree /* Count until stopped by SW. */ \\r
- }\r
-\r
+#if defined(LETIMER_CTRL_RTCC0TEN)\r
+#define LETIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable timer when init complete. */ \\r
+ false, /* Stop counter during debug halt. */ \\r
+ false, /* Do not start counting on RTC COMP0 match. */ \\r
+ false, /* Do not start counting on RTC COMP1 match. */ \\r
+ false, /* Do not load COMP0 into CNT on underflow. */ \\r
+ false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \\r
+ 0, /* Idle value 0 for output 0. */ \\r
+ 0, /* Idle value 0 for output 1. */ \\r
+ letimerUFOANone, /* No action on underflow on output 0. */ \\r
+ letimerUFOANone, /* No action on underflow on output 1. */ \\r
+ letimerRepeatFree /* Count until stopped by SW. */ \\r
+}\r
+#else\r
+#define LETIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable timer when init complete. */ \\r
+ false, /* Stop counter during debug halt. */ \\r
+ false, /* Do not load COMP0 into CNT on underflow. */ \\r
+ false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \\r
+ 0, /* Idle value 0 for output 0. */ \\r
+ 0, /* Idle value 0 for output 1. */ \\r
+ letimerUFOANone, /* No action on underflow on output 0. */ \\r
+ letimerUFOANone, /* No action on underflow on output 1. */ \\r
+ letimerRepeatFree /* Count until stopped by SW. */ \\r
+}\r
+#endif\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
\r
\r
void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable);\r
+#if defined(_LETIMER_FREEZE_MASK)\r
void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable);\r
+#endif\r
void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init);\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags)\r
{\r
- letimer->IEN &= ~(flags);\r
+ letimer->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer)\r
{\r
- return(letimer->IF);\r
+ return letimer->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending LETIMER interrupt flags.\r
+ *\r
+ * @details\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @param[in] letimer\r
+ * Pointer to LETIMER peripheral register block.\r
+ *\r
+ * @return\r
+ * Pending and enabled LETIMER interrupt sources.\r
+ * The return value is the bitwise AND combination of\r
+ * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn\r
+ * register (LETIMER_IEN_nnn) and\r
+ * - the OR combination of valid interrupt flags of the LETIMER module\r
+ * (LETIMER_IF_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer)\r
+{\r
+ uint32_t ien;\r
+\r
+\r
+ /* Store flags in temporary variable in order to define explicit order\r
+ * of volatile accesses. */\r
+ ien = letimer->IEN;\r
+\r
+ /* Bitwise AND of pending and enabled interrupts */\r
+ return letimer->IF & ien;\r
}\r
\r
\r
letimer->IFS = flags;\r
}\r
\r
+\r
uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep);\r
void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,\r
unsigned int rep,\r
#endif\r
\r
#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */\r
-\r
-#endif /* __SILICON_LABS_EM_LETIMER_H_ */\r
+#endif /* __SILICON_LABS_EM_LETIMER_H__ */\r
* @file em_leuart.h\r
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)\r
* peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_LEUART_H_\r
-#define __SILICON_LABS_EM_LEUART_H_\r
+#ifndef __SILICON_LABS_EM_LEUART_H__\r
+#define __SILICON_LABS_EM_LEUART_H__\r
\r
#include "em_device.h"\r
#if defined(LEUART_COUNT) && (LEUART_COUNT > 0)\r
} LEUART_Init_TypeDef;\r
\r
/** Default config for LEUART init structure. */\r
-#define LEUART_INIT_DEFAULT \\r
- { leuartEnable, /* Enable RX/TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 9600, /* 9600 bits/s. */ \\r
- leuartDatabits8, /* 8 databits. */ \\r
- leuartNoParity, /* No parity. */ \\r
- leuartStopbits1 /* 1 stopbit. */ \\r
- }\r
+#define LEUART_INIT_DEFAULT \\r
+{ \\r
+ leuartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 9600, /* 9600 bits/s. */ \\r
+ leuartDatabits8, /* 8 databits. */ \\r
+ leuartNoParity, /* No parity. */ \\r
+ leuartStopbits1 /* 1 stopbit. */ \\r
+}\r
\r
\r
/*******************************************************************************\r
******************************************************************************/\r
__STATIC_INLINE void LEUART_IntDisable(LEUART_TypeDef *leuart, uint32_t flags)\r
{\r
- leuart->IEN &= ~(flags);\r
+ leuart->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t LEUART_IntGet(LEUART_TypeDef *leuart)\r
{\r
- return(leuart->IF);\r
+ return leuart->IF;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint8_t LEUART_RxDataGet(LEUART_TypeDef *leuart)\r
{\r
- return (uint8_t) (leuart->RXDATA);\r
+ return (uint8_t)leuart->RXDATA;\r
}\r
\r
\r
* Receive one 8-9 bit frame, with extended information.\r
*\r
* @details\r
- * This function is used to quickly receive one 8-9 bit frame with extended \r
- * information by reading the RXDATAX register directly, without checking the \r
- * STATUS register for the RXDATAV flag. This can be useful from the RXDATAV \r
- * interrupt handler, i.e. waiting is superfluous, in order to quickly read \r
+ * This function is used to quickly receive one 8-9 bit frame with extended\r
+ * information by reading the RXDATAX register directly, without checking the\r
+ * STATUS register for the RXDATAV flag. This can be useful from the RXDATAV\r
+ * interrupt handler, i.e. waiting is superfluous, in order to quickly read\r
* the received data.\r
*\r
* @note\r
******************************************************************************/\r
__STATIC_INLINE uint16_t LEUART_RxDataXGet(LEUART_TypeDef *leuart)\r
{\r
- return (uint16_t) (leuart->RXDATAX);\r
+ return (uint16_t)leuart->RXDATAX;\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(LEUART_COUNT) && (LEUART_COUNT > 0) */\r
-\r
-#endif /* __SILICON_LABS_EM_LEUART_H_ */\r
+#endif /* __SILICON_LABS_EM_LEUART_H__ */\r
/***************************************************************************//**\r
* @file em_mpu.h\r
* @brief Memory protection unit (MPU) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_MPU_H_\r
-#define __SILICON_LABS_EM_MPU_H_\r
+#ifndef __SILICON_LABS_EM_MPU_H__\r
+#define __SILICON_LABS_EM_MPU_H__\r
\r
#include "em_device.h"\r
\r
} MPU_RegionInit_TypeDef;\r
\r
/** Default configuration of MPU region init structure for flash memory. */\r
-#define MPU_INIT_FLASH_DEFAULT \\r
- { \\r
- true, /* Enable MPU region. */ \\r
- 0, /* MPU Region number. */ \\r
- FLASH_MEM_BASE, /* Flash base address. */ \\r
- mpuRegionSize1Mb, /* Size - Set to max. */ \\r
- mpuRegionApFullAccess, /* Access permissions. */ \\r
- false, /* Execution allowed. */ \\r
- false, /* Not shareable. */ \\r
- true, /* Cacheable. */ \\r
- false, /* Not bufferable. */ \\r
- 0, /* No subregions. */ \\r
- 0 /* No TEX attributes. */ \\r
- }\r
+#define MPU_INIT_FLASH_DEFAULT \\r
+{ \\r
+ true, /* Enable MPU region. */ \\r
+ 0, /* MPU Region number. */ \\r
+ FLASH_MEM_BASE, /* Flash base address. */ \\r
+ mpuRegionSize1Mb, /* Size - Set to max. */ \\r
+ mpuRegionApFullAccess, /* Access permissions. */ \\r
+ false, /* Execution allowed. */ \\r
+ false, /* Not shareable. */ \\r
+ true, /* Cacheable. */ \\r
+ false, /* Not bufferable. */ \\r
+ 0, /* No subregions. */ \\r
+ 0 /* No TEX attributes. */ \\r
+}\r
\r
\r
/** Default configuration of MPU region init structure for sram memory. */\r
-#define MPU_INIT_SRAM_DEFAULT \\r
- { \\r
- true, /* Enable MPU region. */ \\r
- 1, /* MPU Region number. */ \\r
- RAM_MEM_BASE, /* SRAM base address. */ \\r
- mpuRegionSize128Kb, /* Size - Set to max. */ \\r
- mpuRegionApFullAccess, /* Access permissions. */ \\r
- false, /* Execution allowed. */ \\r
- true, /* Shareable. */ \\r
- true, /* Cacheable. */ \\r
- false, /* Not bufferable. */ \\r
- 0, /* No subregions. */ \\r
- 0 /* No TEX attributes. */ \\r
- }\r
+#define MPU_INIT_SRAM_DEFAULT \\r
+{ \\r
+ true, /* Enable MPU region. */ \\r
+ 1, /* MPU Region number. */ \\r
+ RAM_MEM_BASE, /* SRAM base address. */ \\r
+ mpuRegionSize128Kb, /* Size - Set to max. */ \\r
+ mpuRegionApFullAccess, /* Access permissions. */ \\r
+ false, /* Execution allowed. */ \\r
+ true, /* Shareable. */ \\r
+ true, /* Cacheable. */ \\r
+ false, /* Not bufferable. */ \\r
+ 0, /* No subregions. */ \\r
+ 0 /* No TEX attributes. */ \\r
+}\r
\r
\r
/** Default configuration of MPU region init structure for onchip peripherals.*/\r
-#define MPU_INIT_PERIPHERAL_DEFAULT \\r
- { \\r
- true, /* Enable MPU region. */ \\r
- 0, /* MPU Region number. */ \\r
- 0, /* Region base address. */ \\r
- mpuRegionSize32b, /* Size - Set to minimum */ \\r
- mpuRegionApFullAccess, /* Access permissions. */ \\r
- true, /* Execution not allowed. */ \\r
- true, /* Shareable. */ \\r
- false, /* Not cacheable. */ \\r
- true, /* Bufferable. */ \\r
- 0, /* No subregions. */ \\r
- 0 /* No TEX attributes. */ \\r
- }\r
+#define MPU_INIT_PERIPHERAL_DEFAULT \\r
+{ \\r
+ true, /* Enable MPU region. */ \\r
+ 0, /* MPU Region number. */ \\r
+ 0, /* Region base address. */ \\r
+ mpuRegionSize32b, /* Size - Set to minimum */ \\r
+ mpuRegionApFullAccess, /* Access permissions. */ \\r
+ true, /* Execution not allowed. */ \\r
+ true, /* Shareable. */ \\r
+ false, /* Not cacheable. */ \\r
+ true, /* Bufferable. */ \\r
+ 0, /* No subregions. */ \\r
+ 0 /* No TEX attributes. */ \\r
+}\r
\r
\r
/*******************************************************************************\r
******************************************************************************/\r
__STATIC_INLINE void MPU_Enable(uint32_t flags)\r
{\r
- EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk |\r
- MPU_CTRL_HFNMIENA_Msk |\r
- MPU_CTRL_ENABLE_Msk)));\r
+ EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk\r
+ | MPU_CTRL_HFNMIENA_Msk\r
+ | MPU_CTRL_ENABLE_Msk)));\r
\r
MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */\r
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */\r
\r
#endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */\r
\r
-#endif /* __SILICON_LABS_EM_MPU_H_ */\r
+#endif /* __SILICON_LABS_EM_MPU_H__ */\r
/***************************************************************************//**\r
* @file em_msc.h\r
* @brief Flash controller module (MSC) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
\r
#include <stdint.h>\r
#include <stdbool.h>\r
-#include "em_bitband.h"\r
+#include "em_bus.h"\r
\r
#ifdef __cplusplus\r
extern "C" {\r
*/\r
#define MSC_PROGRAM_TIMEOUT 10000000ul\r
\r
+/**\r
+ * @brief\r
+ * By compiling with the define EM_MSC_RUN_FROM_FLASH the Flash\r
+ * controller (MSC) peripheral will remain in and execute from flash.\r
+ * This is useful for targets that don't want to allocate RAM space to\r
+ * hold the flash functions. Without this define the MSC peripheral\r
+ * functions will be copied into and run out of RAM.\r
+ * @note\r
+ * This define is commented out by default so the MSC controller API\r
+ * will run from RAM by default.\r
+ *\r
+ */\r
+#if defined( DOXY_DOC_ONLY )\r
+#define EM_MSC_RUN_FROM_FLASH\r
+#else\r
+//#define EM_MSC_RUN_FROM_FLASH\r
+#endif\r
+\r
/*******************************************************************************\r
************************* TYPEDEFS ****************************************\r
******************************************************************************/\r
\r
#if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )\r
/** Strategy for prioritized bus access */\r
-typedef enum {\r
+typedef enum\r
+{\r
mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */\r
mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */\r
mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */\r
} MSC_BusStrategy_Typedef;\r
#endif\r
\r
+/** Code execution configuration */\r
+typedef struct\r
+{\r
+ bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch */\r
+ bool prefetchEn; /**< Enable MSC prefetching */\r
+ bool ifcDis; /**< Disable instruction cache */\r
+ bool aiDis; /**< Disable automatic cache invalidation on write or erase */\r
+ bool iccDis; /**< Disable automatic caching of fetches in interrupt context */\r
+ bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not */\r
+} MSC_ExecConfig_TypeDef;\r
+\r
+/** Default MSC ExecConfig initialization */\r
+#define MSC_EXECCONFIG_DEFAULT \\r
+{ \\r
+ false, \\r
+ true, \\r
+ false, \\r
+ false, \\r
+ false, \\r
+ false, \\r
+}\r
+\r
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */\r
/* Legacy type names */\r
#define mscBusStrategy_Typedef MSC_BusStrategy_Typedef\r
\r
void MSC_Init(void);\r
void MSC_Deinit(void);\r
+#if !defined( _EFM32_GECKO_FAMILY )\r
+void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig);\r
+#endif\r
\r
/***************************************************************************//**\r
* @brief\r
******************************************************************************/\r
__STATIC_INLINE void MSC_EnableCache(bool enable)\r
{\r
- BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, ~enable);\r
+ BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable);\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void MSC_EnableCacheIRQs(bool enable)\r
{\r
- BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, ~enable);\r
+ BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable);\r
}\r
#endif\r
\r
******************************************************************************/\r
__STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable)\r
{\r
- BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, ~enable);\r
+ BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable);\r
}\r
#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */\r
\r
}\r
#endif\r
\r
-\r
-#ifdef __CC_ARM /* MDK-ARM compiler */\r
-MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes);\r
-#if !defined( _EFM32_GECKO_FAMILY )\r
-MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes);\r
+#if defined(EM_MSC_RUN_FROM_FLASH)\r
+#define MSC_FUNC_PREFIX\r
+#define MSC_FUNC_POSTFIX\r
+#elif defined(__CC_ARM)\r
+#define MSC_FUNC_PREFIX\r
+#define MSC_FUNC_POSTFIX\r
+#elif defined(__ICCARM__)\r
+#define MSC_FUNC_PREFIX __ramfunc\r
+#define MSC_FUNC_POSTFIX\r
+#elif defined(__GNUC__) && defined(__CROSSWORKS_ARM)\r
+#define MSC_FUNC_PREFIX\r
+#define MSC_FUNC_POSTFIX __attribute__ ((section(".fast")))\r
+#elif defined(__GNUC__)\r
+#define MSC_FUNC_PREFIX\r
+#define MSC_FUNC_POSTFIX __attribute__ ((section(".ram")))\r
#endif\r
-MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress);\r
\r
-#if defined( _MSC_MASSLOCK_MASK )\r
-MSC_Status_TypeDef MSC_MassErase(void);\r
-#endif\r
-#endif /* __CC_ARM */\r
-\r
-#ifdef __ICCARM__ /* IAR compiler */\r
-__ramfunc MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes);\r
-#if !defined( _EFM32_GECKO_FAMILY )\r
-__ramfunc MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes);\r
-#endif\r
-__ramfunc MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress);\r
\r
-#if defined( _MSC_MASSLOCK_MASK )\r
-__ramfunc MSC_Status_TypeDef MSC_MassErase(void);\r
-#endif\r
-#endif /* __ICCARM__ */\r
+MSC_FUNC_PREFIX MSC_Status_TypeDef\r
+ MSC_WriteWord(uint32_t *address,\r
+ void const *data,\r
+ uint32_t numBytes) MSC_FUNC_POSTFIX;\r
\r
-#ifdef __GNUC__ /* GCC based compilers */\r
-#ifdef __CROSSWORKS_ARM /* Rowley Crossworks (GCC based) */\r
-MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".fast")));\r
#if !defined( _EFM32_GECKO_FAMILY )\r
-MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".fast")));\r
-#endif\r
-MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".fast")));\r
+MSC_FUNC_PREFIX MSC_Status_TypeDef\r
+ MSC_WriteWordFast(uint32_t *address,\r
+ void const *data,\r
+ uint32_t numBytes) MSC_FUNC_POSTFIX;\r
\r
-#if defined( _MSC_MASSLOCK_MASK )\r
-MSC_Status_TypeDef MSC_MassErase(void) __attribute__ ((section(".fast")));\r
#endif\r
\r
-#else /* GCC */\r
-MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".ram")));\r
-#if !defined( _EFM32_GECKO_FAMILY )\r
-MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".ram")));\r
-#endif\r
-MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".ram")));\r
+MSC_FUNC_PREFIX MSC_Status_TypeDef\r
+ MSC_ErasePage(uint32_t *startAddress) MSC_FUNC_POSTFIX;\r
\r
#if defined( _MSC_MASSLOCK_MASK )\r
-MSC_Status_TypeDef MSC_MassErase(void) __attribute__ ((section(".ram")));\r
+MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_MassErase(void) MSC_FUNC_POSTFIX;\r
#endif\r
\r
-#endif /* __GNUC__ */\r
-#endif /* __CROSSWORKS_ARM */\r
-\r
/** @} (end addtogroup MSC) */\r
/** @} (end addtogroup EM_Library) */\r
\r
/**************************************************************************//**\r
* @file em_opamp.h\r
* @brief Operational Amplifier (OPAMP) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_OPAMP_H_\r
-#define __SILICON_LABS_EM_OPAMP_H_\r
+#ifndef __SILICON_LABS_EM_OPAMP_H__\r
+#define __SILICON_LABS_EM_OPAMP_H__\r
\r
#include "em_device.h"\r
#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)\r
uint32_t offset; /**< Opamp offset value when @ref defaultOffset is false.*/\r
} OPAMP_Init_TypeDef;\r
\r
-/** Configuration of OPA0/1 in unity gain voltage follower mode. */\r
-#define OPA_INIT_UNITY_GAIN \\r
- { \\r
- opaNegSelUnityGain, /* Unity gain. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelDefault, /* Resistor ladder is not used. */ \\r
- opaResInMuxDisable, /* Resistor ladder disabled. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA2 in unity gain voltage follower mode. */\r
-#define OPA_INIT_UNITY_GAIN_OPA2 \\r
- { \\r
- opaNegSelUnityGain, /* Unity gain. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelDefault, /* Resistor ladder is not used. */ \\r
- opaResInMuxDisable, /* Resistor ladder disabled. */ \\r
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
+/** Configuration of OPA0/1 in unity gain voltage follower mode. */\r
+#define OPA_INIT_UNITY_GAIN \\r
+{ \\r
+ opaNegSelUnityGain, /* Unity gain. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelDefault, /* Resistor ladder is not used. */ \\r
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA2 in unity gain voltage follower mode. */\r
+#define OPA_INIT_UNITY_GAIN_OPA2 \\r
+{ \\r
+ opaNegSelUnityGain, /* Unity gain. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelDefault, /* Resistor ladder is not used. */ \\r
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \\r
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
\r
/** Configuration of OPA0/1 in non-inverting amplifier mode. */\r
-#define OPA_INIT_NON_INVERTING \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- true, /* Neg pad enabled, used as signal ground. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA2 in non-inverting amplifier mode. */\r
-#define OPA_INIT_NON_INVERTING_OPA2 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- true, /* Neg pad enabled, used as signal ground. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA0/1 in inverting amplifier mode. */\r
-#define OPA_INIT_INVERTING \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- true, /* Neg pad enabled, used as signal input. */ \\r
- true, /* Pos pad enabled, used as signal ground. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA2 in inverting amplifier mode. */\r
-#define OPA_INIT_INVERTING_OPA2 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- true, /* Neg pad enabled, used as signal input. */ \\r
- true, /* Pos pad enabled, used as signal ground. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */\r
-#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA1). */ \\r
- true, /* Neg pad enabled, used as signal ground. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */\r
-#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelOpaIn, /* Pos input from OPA0 output. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA2). */ \\r
- true, /* Neg pad enabled, used as signal ground. */ \\r
- false, /* Pos pad disabled. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */\r
-#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelOpaIn, /* Pos input from OPA1 output. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- true, /* Neg pad enabled, used as signal ground. */ \\r
- false, /* Pos pad disabled. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA0 in cascaded inverting amplifier mode. */\r
-#define OPA_INIT_CASCADED_INVERTING_OPA0 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA1). */ \\r
- true, /* Neg pad enabled, used as signal input. */ \\r
- true, /* Pos pad enabled, used as signal ground. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA1 in cascaded inverting amplifier mode. */\r
-#define OPA_INIT_CASCADED_INVERTING_OPA1 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA2). */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal ground. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA2 in cascaded inverting amplifier mode. */\r
-#define OPA_INIT_CASCADED_INVERTING_OPA2 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \\r
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal ground. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA0 in two-opamp differential driver mode. */\r
-#define OPA_INIT_DIFF_DRIVER_OPA0 \\r
- { \\r
- opaNegSelUnityGain, /* Unity gain. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelDefault, /* Resistor ladder is not used. */ \\r
- opaResInMuxDisable, /* Resistor ladder disabled. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA1). */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA1 in two-opamp differential driver mode. */\r
-#define OPA_INIT_DIFF_DRIVER_OPA1 \\r
- { \\r
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal ground. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA0 in three-opamp differential receiver mode. */\r
-#define OPA_INIT_DIFF_RECEIVER_OPA0 \\r
- { \\r
- opaNegSelUnityGain, /* Unity gain. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA2). */ \\r
- true, /* Neg pad enabled, used as signal ground. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA1 in three-opamp differential receiver mode. */\r
-#define OPA_INIT_DIFF_RECEIVER_OPA1 \\r
- { \\r
- opaNegSelUnityGain, /* Unity gain. */ \\r
- opaPosSelPosPad, /* Pos input from pad. */ \\r
- opaOutModeAll, /* Both main and alternate outputs. */ \\r
- opaResSelDefault, /* Resistor ladder is not used. */ \\r
- opaResInMuxDisable, /* Disable resistor ladder. */ \\r
- 0, /* No alternate outputs enabled. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- true, /* Pass output to next stage (OPA2). */ \\r
- false, /* Neg pad disabled. */ \\r
- true, /* Pos pad enabled, used as signal input. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
-\r
-/** Configuration of OPA2 in three-opamp differential receiver mode. */\r
-#define OPA_INIT_DIFF_RECEIVER_OPA2 \\r
- { \\r
- opaNegSelResTap, /* Input from resistor ladder tap. */ \\r
- opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \\r
- opaOutModeMain, /* Main output enabled. */ \\r
- opaResSelR2eqR1, /* R2 = R1 */ \\r
- opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \\r
- DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \\r
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
- false, /* No low pass filter on pos pad. */ \\r
- false, /* No low pass filter on neg pad. */ \\r
- false, /* No nextout output enabled. */ \\r
- false, /* Neg pad disabled. */ \\r
- false, /* Pos pad disabled. */ \\r
- false, /* No shorting of inputs. */ \\r
- false, /* Rail-to-rail input enabled. */ \\r
- true, /* Use factory calibrated opamp offset. */ \\r
- 0 /* Opamp offset value (not used). */ \\r
- }\r
+#define OPA_INIT_NON_INVERTING \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ true, /* Neg pad enabled, used as signal ground. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA2 in non-inverting amplifier mode. */\r
+#define OPA_INIT_NON_INVERTING_OPA2 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ true, /* Neg pad enabled, used as signal ground. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA0/1 in inverting amplifier mode. */\r
+#define OPA_INIT_INVERTING \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ true, /* Neg pad enabled, used as signal input. */ \\r
+ true, /* Pos pad enabled, used as signal ground. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA2 in inverting amplifier mode. */\r
+#define OPA_INIT_INVERTING_OPA2 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ true, /* Neg pad enabled, used as signal input. */ \\r
+ true, /* Pos pad enabled, used as signal ground. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */\r
+#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA1). */ \\r
+ true, /* Neg pad enabled, used as signal ground. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */\r
+#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelOpaIn, /* Pos input from OPA0 output. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA2). */ \\r
+ true, /* Neg pad enabled, used as signal ground. */ \\r
+ false, /* Pos pad disabled. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */\r
+#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelOpaIn, /* Pos input from OPA1 output. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ true, /* Neg pad enabled, used as signal ground. */ \\r
+ false, /* Pos pad disabled. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA0 in cascaded inverting amplifier mode. */\r
+#define OPA_INIT_CASCADED_INVERTING_OPA0 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA1). */ \\r
+ true, /* Neg pad enabled, used as signal input. */ \\r
+ true, /* Pos pad enabled, used as signal ground. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA1 in cascaded inverting amplifier mode. */\r
+#define OPA_INIT_CASCADED_INVERTING_OPA1 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA2). */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal ground. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA2 in cascaded inverting amplifier mode. */\r
+#define OPA_INIT_CASCADED_INVERTING_OPA2 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \\r
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal ground. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA0 in two-opamp differential driver mode. */\r
+#define OPA_INIT_DIFF_DRIVER_OPA0 \\r
+{ \\r
+ opaNegSelUnityGain, /* Unity gain. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelDefault, /* Resistor ladder is not used. */ \\r
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA1). */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA1 in two-opamp differential driver mode. */\r
+#define OPA_INIT_DIFF_DRIVER_OPA1 \\r
+{ \\r
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal ground. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA0 in three-opamp differential receiver mode. */\r
+#define OPA_INIT_DIFF_RECEIVER_OPA0 \\r
+{ \\r
+ opaNegSelUnityGain, /* Unity gain. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA2). */ \\r
+ true, /* Neg pad enabled, used as signal ground. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA1 in three-opamp differential receiver mode. */\r
+#define OPA_INIT_DIFF_RECEIVER_OPA1 \\r
+{ \\r
+ opaNegSelUnityGain, /* Unity gain. */ \\r
+ opaPosSelPosPad, /* Pos input from pad. */ \\r
+ opaOutModeAll, /* Both main and alternate outputs. */ \\r
+ opaResSelDefault, /* Resistor ladder is not used. */ \\r
+ opaResInMuxDisable, /* Disable resistor ladder. */ \\r
+ 0, /* No alternate outputs enabled. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ true, /* Pass output to next stage (OPA2). */ \\r
+ false, /* Neg pad disabled. */ \\r
+ true, /* Pos pad enabled, used as signal input. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
+\r
+/** Configuration of OPA2 in three-opamp differential receiver mode. */\r
+#define OPA_INIT_DIFF_RECEIVER_OPA2 \\r
+{ \\r
+ opaNegSelResTap, /* Input from resistor ladder tap. */ \\r
+ opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \\r
+ opaOutModeMain, /* Main output enabled. */ \\r
+ opaResSelR2eqR1, /* R2 = R1 */ \\r
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \\r
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \\r
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \\r
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \\r
+ false, /* No low pass filter on pos pad. */ \\r
+ false, /* No low pass filter on neg pad. */ \\r
+ false, /* No nextout output enabled. */ \\r
+ false, /* Neg pad disabled. */ \\r
+ false, /* Pos pad disabled. */ \\r
+ false, /* No shorting of inputs. */ \\r
+ false, /* Rail-to-rail input enabled. */ \\r
+ true, /* Use factory calibrated opamp offset. */ \\r
+ 0 /* Opamp offset value (not used). */ \\r
+}\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
#endif\r
\r
#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */\r
-#endif /* __SILICON_LABS_EM_OPAMP_H_ */\r
+#endif /* __SILICON_LABS_EM_OPAMP_H__ */\r
/***************************************************************************//**\r
* @file em_part.h\r
* @brief Verify that part specific main header files are supported and included\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_PART_H_\r
-#define __SILICON_LABS_EM_PART_H_\r
+#ifndef __SILICON_LABS_EM_PART_H__\r
+#define __SILICON_LABS_EM_PART_H__\r
\r
/* This file is kept for backwards compatibility. */\r
+#warning "Using em_part.h is deprecated. Please use em_device.h instead."\r
\r
#include "em_device.h"\r
\r
-#endif /* __SILICON_LABS_EM_PART_H_ */\r
+#endif /* __SILICON_LABS_EM_PART_H__ */\r
/***************************************************************************//**\r
* @file em_pcnt.h\r
* @brief Pulse Counter (PCNT) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_PCNT_H_\r
-#define __SILICON_LABS_EM_PCNT_H_\r
+#ifndef __SILICON_LABS_EM_PCNT_H__\r
+#define __SILICON_LABS_EM_PCNT_H__\r
\r
#include "em_device.h"\r
#if defined(PCNT_COUNT) && (PCNT_COUNT > 0)\r
/*******************************************************************************\r
******************************* DEFINES ***********************************\r
******************************************************************************/\r
-/** PCNT Counter register sizes. */\r
-#if defined _EFM32_GECKO_FAMILY\r
-#define PCNT0_CNT_SIZE (8) /** PCNT0 counter is 8 bits. */\r
+/** PCNT0 Counter register size. */\r
+#if defined(_EFM32_GECKO_FAMILY)\r
+#define PCNT0_CNT_SIZE (8) /* PCNT0 counter is 8 bits. */\r
#else\r
-#define PCNT0_CNT_SIZE (16) /** PCNT0 counter is 16 bits. */\r
+#define PCNT0_CNT_SIZE (16) /* PCNT0 counter is 16 bits. */\r
#endif\r
+\r
#ifdef PCNT1\r
-#define PCNT1_CNT_SIZE (8) /** PCNT1 counter is 8 bits. */\r
+/** PCNT1 Counter register size. */\r
+#define PCNT1_CNT_SIZE (8) /* PCNT1 counter is 8 bits. */\r
#endif\r
+\r
#ifdef PCNT2\r
-#define PCNT2_CNT_SIZE (8) /** PCNT2 counter is 8 bits. */\r
+/** PCNT2 Counter register size. */\r
+#define PCNT2_CNT_SIZE (8) /* PCNT2 counter is 8 bits. */\r
#endif\r
\r
\r
pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE,\r
\r
/** Externally clocked quadrature decoder mode (available in EM0-EM3). */\r
- pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD\r
+ pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD,\r
+ \r
+#if defined(_PCNT_CTRL_MODE_OVSQUAD1X)\r
+ /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */\r
+ pcntModeOvsQuad1 = _PCNT_CTRL_MODE_OVSQUAD1X,\r
+ \r
+ /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */\r
+ pcntModeOvsQuad2 = _PCNT_CTRL_MODE_OVSQUAD2X,\r
+ \r
+ /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */\r
+ pcntModeOvsQuad4 = _PCNT_CTRL_MODE_OVSQUAD4X,\r
+#endif\r
} PCNT_Mode_TypeDef;\r
\r
\r
-#if defined( _PCNT_CTRL_CNTEV_MASK)\r
+#if defined(_PCNT_CTRL_CNTEV_MASK)\r
/** Counter event selection.\r
* Note: unshifted values are being used for enumeration because multiple\r
* configuration structure members use this type definition. */\r
#endif\r
\r
\r
-#if defined( _PCNT_INPUT_MASK )\r
+#if defined(_PCNT_INPUT_MASK)\r
/** PRS sources for @p s0PRS and @p s1PRS. */\r
typedef enum\r
{\r
pcntPRSCh1 = 1, /**< PRS channel 1. */\r
pcntPRSCh2 = 2, /**< PRS channel 2. */\r
pcntPRSCh3 = 3, /**< PRS channel 3. */\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH4 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH4)\r
pcntPRSCh4 = 4, /**< PRS channel 4. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH5 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH5)\r
pcntPRSCh5 = 5, /**< PRS channel 5. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH6 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH6)\r
pcntPRSCh6 = 6, /**< PRS channel 6. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH7 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH7)\r
pcntPRSCh7 = 7, /**< PRS channel 7. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH8 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH8)\r
pcntPRSCh8 = 8, /**< PRS channel 8. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH9 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH9)\r
pcntPRSCh9 = 9, /**< PRS channel 9. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH10 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH10)\r
pcntPRSCh10 = 10, /**< PRS channel 10. */\r
#endif\r
-#if defined( PCNT_INPUT_S0PRSSEL_PRSCH11 )\r
+#if defined(PCNT_INPUT_S0PRSSEL_PRSCH11)\r
pcntPRSCh11 = 11 /**< PRS channel 11. */\r
#endif\r
} PCNT_PRSSel_TypeDef;\r
/** Counting direction, only applicable for #pcntModeOvsSingle and\r
* #pcntModeExtSingle modes. */\r
bool countDown;\r
-\r
- /** Enable filter, only available in #pcntModeOvsSingle mode. */\r
+ \r
+ /** Enable filter, only available in #pcntModeOvs* modes. */\r
bool filter;\r
\r
-#if defined( PCNT_CTRL_HYST )\r
+#if defined(PCNT_CTRL_HYST)\r
/** Set to true to enable hysteresis. When its enabled, the PCNT will always\r
* overflow and underflow to TOP/2. */\r
bool hyst;\r
\r
/** Set to true to enable S1 to determine the direction of counting in\r
- * OVSSINGLE or EXTCLKSINGLE modes.\r
+ * OVSSINGLE or EXTCLKSINGLE modes. @n\r
* When S1 is high, the count direction is given by CNTDIR, and when S1 is\r
* low, the count direction is the opposite. */\r
bool s1CntDir;\r
#endif\r
} PCNT_Init_TypeDef;\r
\r
-#if !defined ( PCNT_CTRL_HYST )\r
+#if !defined(PCNT_CTRL_HYST)\r
/** Default config for PCNT init structure. */\r
-#define PCNT_INIT_DEFAULT \\r
- { pcntModeDisable, /* Disabled by default. */ \\r
- _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \\r
- _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \\r
- false, /* Use positive edge. */ \\r
- false, /* Up-counting. */ \\r
- false /* Filter disabled. */ \\r
- }\r
+#define PCNT_INIT_DEFAULT \\r
+{ \\r
+ pcntModeDisable, /* Disabled by default. */ \\r
+ _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \\r
+ _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \\r
+ false, /* Use positive edge. */ \\r
+ false, /* Up-counting. */ \\r
+ false /* Filter disabled. */ \\r
+}\r
#else\r
/** Default config for PCNT init structure. */\r
-#define PCNT_INIT_DEFAULT \\r
- { pcntModeDisable, /* Disabled by default. */ \\r
- _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \\r
- _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \\r
- false, /* Use positive edge. */ \\r
- false, /* Up-counting. */ \\r
- false, /* Filter disabled. */ \\r
- false, /* Hysteresis disabled. */ \\r
- true, /* Counter direction is given by CNTDIR. */ \\r
- pcntCntEventUp, /* Regular counter counts up on upcount events. */ \\r
- pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \\r
- pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \\r
- pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \\r
- }\r
+#define PCNT_INIT_DEFAULT \\r
+{ \\r
+ pcntModeDisable, /* Disabled by default. */ \\r
+ _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \\r
+ _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \\r
+ false, /* Use positive edge. */ \\r
+ false, /* Up-counting. */ \\r
+ false, /* Filter disabled. */ \\r
+ false, /* Hysteresis disabled. */ \\r
+ true, /* Counter direction is given by CNTDIR. */ \\r
+ pcntCntEventUp, /* Regular counter counts up on upcount events. */ \\r
+ pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \\r
+ pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \\r
+ pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \\r
+}\r
+#endif\r
+\r
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)\r
+/** Filter initialization structure */\r
+typedef struct \r
+{\r
+ /** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable the filter through\r
+ * setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */\r
+ uint8_t filtLen;\r
+ \r
+ /** When set, removes flutter from Quaddecoder inputs S0IN and S1IN. \r
+ * Available only in OVSQUAD1X-4X modes. */\r
+ bool flutterrm;\r
+} PCNT_Filter_TypeDef;\r
+#endif\r
+\r
+/** Default config for PCNT init structure. */\r
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)\r
+#define PCNT_FILTER_DEFAULT \\r
+{ \\r
+ 0, /* Default length is 5 LFACLK cycles */ \\r
+ false /* No flutter removal */ \\r
+} \r
#endif\r
\r
+#if defined(PCNT_CTRL_TCCMODE_DEFAULT)\r
+\r
+/** Modes for Triggered Compare and Clear module */\r
+typedef enum \r
+{\r
+ /** Triggered compare and clear not enabled. */\r
+ tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED,\r
+ \r
+ /** Compare and clear performed on each (optionally prescaled) LFA clock cycle. */\r
+ tccModeLFA = _PCNT_CTRL_TCCMODE_LFA,\r
+ \r
+ /** Compare and clear performed on PRS edges. Polarity defined by prsPolarity. */\r
+ tccModePRS = _PCNT_CTRL_TCCMODE_PRS\r
+} PCNT_TCCMode_TypeDef;\r
+\r
+/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */\r
+typedef enum \r
+{\r
+ /** Compare and clear event each LFA cycle. */\r
+ tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1,\r
+ \r
+ /** Compare and clear event every other LFA cycle. */\r
+ tccPrescDiv2 = _PCNT_CTRL_TCCPRESC_DIV2,\r
+ \r
+ /** Compare and clear event every 4th LFA cycle. */\r
+ tccPrescDiv4 = _PCNT_CTRL_TCCPRESC_DIV4,\r
+ \r
+ /** Compare and clear event every 8th LFA cycle. */\r
+ tccPrescDiv8 = _PCNT_CTRL_TCCPRESC_DIV8\r
+} PCNT_TCCPresc_Typedef;\r
+\r
+/** Compare modes for TCC module */\r
+typedef enum \r
+{\r
+ /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */\r
+ tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE,\r
+ \r
+ /** Compare match if PCNT_CNT is greater than or equal to PCNT_TOP. */\r
+ tccCompGTOE = _PCNT_CTRL_TCCCOMP_GTOE,\r
+ \r
+ /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater\r
+ * than, or equal to PCNT_TOP[7:0]. */\r
+ tccCompRange = _PCNT_CTRL_TCCCOMP_RANGE\r
+} PCNT_TCCComp_Typedef;\r
+\r
+/** TCC initialization structure */\r
+typedef struct \r
+{\r
+ /** Mode to operate in. */\r
+ PCNT_TCCMode_TypeDef mode;\r
+ \r
+ /** Prescaler value for LFACLK in LFA mode */\r
+ PCNT_TCCPresc_Typedef prescaler;\r
+ \r
+ /** Choose the event that will trigger a clear */\r
+ PCNT_TCCComp_Typedef compare;\r
+ \r
+ /** PRS input to TCC module, either for gating the PCNT clock, triggering the TCC comparison, or both. */\r
+ PCNT_PRSSel_TypeDef tccPRS;\r
+\r
+ /** TCC PRS input polarity. @n\r
+ * False = Rising edge for comparison trigger, and PCNT clock gated when the PRS signal is high. @n\r
+ * True = Falling edge for comparison trigger, and PCNT clock gated when the PRS signal is low. */\r
+ bool prsPolarity;\r
+ \r
+ /** Enable gating PCNT input clock through TCC PRS signal. \r
+ * Polarity selection is done through prsPolarity. */\r
+ bool prsGateEnable;\r
+} PCNT_TCC_TypeDef;\r
+\r
+#define PCNT_TCC_DEFAULT \\r
+{ \\r
+ tccModeDisabled, /* Disabled by default */ \\r
+ tccPrescDiv1, /* Do not prescale LFA clock in LFA mode */ \\r
+ tccCompLTOE, /* Clear when CNT <= TOP */ \\r
+ pcntPRSCh0, /* Select PRS channel 0 as input to TCC */ \\r
+ false, /* PRS polarity is rising edge, and gate when 1 */ \\r
+ false /* Do not gate the PCNT counter input */ \\r
+}\r
+\r
+#endif \r
+/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
return pcnt->CNT;\r
}\r
\r
-\r
-#if defined( _PCNT_AUXCNT_MASK )\r
+#if defined(_PCNT_AUXCNT_MASK)\r
/***************************************************************************//**\r
* @brief\r
* Get auxiliary counter value.\r
}\r
#endif\r
\r
-\r
void PCNT_CounterReset(PCNT_TypeDef *pcnt);\r
void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top);\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Set counter value.\r
PCNT_CounterTopSet(pcnt, count, pcnt->TOP);\r
}\r
\r
-\r
void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode);\r
void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable);\r
void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init);\r
\r
-#if defined( _PCNT_INPUT_MASK )\r
+#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)\r
+void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable);\r
+#endif\r
+\r
+#if defined(_PCNT_INPUT_MASK)\r
void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,\r
PCNT_PRSInput_TypeDef prsInput,\r
bool enable);\r
#endif\r
\r
-\r
+#if defined(PCNT_CTRL_TCCMODE_DEFAULT)\r
+void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config);\r
+#endif\r
/***************************************************************************//**\r
* @brief\r
* Clear one or more pending PCNT interrupts.\r
pcnt->IFC = flags;\r
}\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Disable one or more PCNT interrupts.\r
******************************************************************************/\r
__STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags)\r
{\r
- pcnt->IEN &= ~(flags);\r
+ pcnt->IEN &= ~flags;\r
}\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Enable one or more PCNT interrupts.\r
pcnt->IEN |= flags;\r
}\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Get pending PCNT interrupt flags.\r
return pcnt->IF;\r
}\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Get enabled and pending PCNT interrupt flags.\r
******************************************************************************/\r
__STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt)\r
{\r
- uint32_t tmp = 0U;\r
+ uint32_t ien;\r
\r
\r
/* Store pcnt->IEN in temporary variable in order to define explicit order\r
* of volatile accesses. */\r
- tmp = pcnt->IEN;\r
+ ien = pcnt->IEN;\r
\r
/* Bitwise AND of pending and enabled interrupts */\r
- return pcnt->IF & tmp;\r
+ return pcnt->IF & ien;\r
}\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Set one or more pending PCNT interrupts from SW.\r
\r
void PCNT_Reset(PCNT_TypeDef *pcnt);\r
\r
-\r
/***************************************************************************//**\r
* @brief\r
* Get pulse counter top buffer value.\r
\r
void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val);\r
\r
-\r
/** @} (end addtogroup PCNT) */\r
/** @} (end addtogroup EM_Library) */\r
\r
#endif\r
\r
#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_PCNT_H_ */\r
+#endif /* __SILICON_LABS_EM_PCNT_H__ */\r
/***************************************************************************//**\r
* @file em_prs.h\r
* @brief Peripheral Reflex System (PRS) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_PRS_H_\r
-#define __SILICON_LABS_EM_PRS_H_\r
+#ifndef __SILICON_LABS_EM_PRS_H__\r
+#define __SILICON_LABS_EM_PRS_H__\r
\r
#include "em_device.h"\r
#if defined(PRS_COUNT) && (PRS_COUNT > 0)\r
#endif\r
\r
#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_PRS_H_ */\r
+#endif /* __SILICON_LABS_EM_PRS_H__ */\r
/***************************************************************************//**\r
* @file em_rmu.h\r
* @brief Reset Management Unit (RMU) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_RMU_H_\r
-#define __SILICON_LABS_EM_RMU_H_\r
+#ifndef __SILICON_LABS_EM_RMU_H__\r
+#define __SILICON_LABS_EM_RMU_H__\r
\r
#include "em_device.h"\r
#if defined(RMU_COUNT) && (RMU_COUNT > 0)\r
+#include "em_assert.h"\r
\r
#include <stdbool.h>\r
\r
******************************** ENUMS ************************************\r
******************************************************************************/\r
\r
+/** RMU reset modes */\r
+typedef enum\r
+{\r
+#if defined(_RMU_CTRL_PINRMODE_MASK)\r
+ rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED,\r
+ rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED,\r
+ rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED,\r
+ rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL,\r
+#else\r
+ rmuResetModeClear = 0,\r
+ rmuResetModeSet = 1,\r
+#endif\r
+} RMU_ResetMode_TypeDef;\r
+\r
/** RMU controlled peripheral reset control and reset source control */\r
typedef enum\r
{\r
-#if defined( RMU_CTRL_BURSTEN )\r
- /** Reset control over Backup Power Domain */\r
- rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,\r
+#if defined(RMU_CTRL_BURSTEN)\r
+ rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select */\r
+#endif\r
+#if defined(RMU_CTRL_LOCKUPRDIS)\r
+ rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select */\r
+#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK)\r
+ rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */\r
+#endif\r
+#if defined(_RMU_CTRL_WDOGRMODE_MASK)\r
+ rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select */\r
+#endif\r
+#if defined(_RMU_CTRL_LOCKUPRMODE_MASK)\r
+ rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */\r
+#endif\r
+#if defined(_RMU_CTRL_SYSRMODE_MASK)\r
+ rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select */\r
+#endif\r
+#if defined(_RMU_CTRL_PINRMODE_MASK)\r
+ rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select */\r
#endif\r
- /** Allow Cortex-M3 lock up signal */\r
- rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT\r
} RMU_Reset_TypeDef;\r
\r
/*******************************************************************************\r
/** RMU_LockupResetDisable kept for backwards compatibility */\r
#define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A)\r
\r
-void RMU_ResetControl(RMU_Reset_TypeDef reset, bool enable);\r
+void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode);\r
void RMU_ResetCauseClear(void);\r
uint32_t RMU_ResetCauseGet(void);\r
\r
+#if defined(_RMU_CTRL_RESETSTATE_MASK)\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set user reset state. This state is reset only by a Power-on-reset and a\r
+ * pin reset.\r
+ *\r
+ * @param[in] userState User state to set\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState)\r
+{\r
+ EFM_ASSERT(!(userState\r
+ & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT)));\r
+ RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK)\r
+ | (userState << _RMU_CTRL_RESETSTATE_SHIFT);\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get user reset state. This state is reset only by a Power-on-reset and a\r
+ * pin reset.\r
+ *\r
+ * @return\r
+ * Reset surviving user state\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RMU_UserResetStateGet(void)\r
+{\r
+ uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK)\r
+ >> _RMU_CTRL_RESETSTATE_SHIFT;\r
+ return userState;\r
+}\r
+#endif\r
+\r
/** @} (end addtogroup RMU) */\r
/** @} (end addtogroup EM_Library) */\r
\r
#endif\r
\r
#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_RMU_H_ */\r
+#endif /* __SILICON_LABS_EM_RMU_H__ */\r
/***************************************************************************//**\r
* @file em_rtc.h\r
* @brief Real Time Counter (RTC) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_RTC_H_\r
-#define __SILICON_LABS_EM_RTC_H_\r
+#ifndef __SILICON_LABS_EM_RTC_H__\r
+#define __SILICON_LABS_EM_RTC_H__\r
\r
#include "em_device.h"\r
#if defined(RTC_COUNT) && (RTC_COUNT > 0)\r
} RTC_Init_TypeDef;\r
\r
/** Suggested default config for RTC init structure. */\r
-#define RTC_INIT_DEFAULT \\r
- { true, /* Start counting when init done */ \\r
- false, /* Disable updating during debug halt */ \\r
- true /* Restart counting from 0 when reaching COMP0 */ \\r
- }\r
+#define RTC_INIT_DEFAULT \\r
+{ \\r
+ true, /* Start counting when init done */ \\r
+ false, /* Disable updating during debug halt */ \\r
+ true /* Restart counting from 0 when reaching COMP0 */ \\r
+}\r
\r
\r
/*******************************************************************************\r
******************************************************************************/\r
__STATIC_INLINE uint32_t RTC_CounterGet(void)\r
{\r
- return(RTC->CNT);\r
+ return RTC->CNT;\r
}\r
\r
void RTC_CounterReset(void);\r
******************************************************************************/\r
__STATIC_INLINE void RTC_IntDisable(uint32_t flags)\r
{\r
- RTC->IEN &= ~(flags);\r
+ RTC->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t RTC_IntGet(void)\r
{\r
- return(RTC->IF);\r
+ return RTC->IF;\r
+}\r
+\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending RTC interrupt flags.\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @note\r
+ * Interrupt flags are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending and enabled RTC interrupt sources\r
+ * The return value is the bitwise AND of\r
+ * - the enabled interrupt sources in RTC_IEN and\r
+ * - the pending interrupt flags RTC_IF\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTC_IntGetEnabled(void)\r
+{\r
+ uint32_t ien;\r
+\r
+ ien = RTC->IEN;\r
+ return RTC->IF & ien;\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(RTC_COUNT) && (RTC_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_RTC_H_ */\r
+#endif /* __SILICON_LABS_EM_RTC_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief Real Time Counter (RTCC) peripheral API.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * Permission is granted to anyone to use this software for any purpose,\r
+ * including commercial applications, and to alter it and redistribute it\r
+ * freely, subject to the following restrictions:\r
+ *\r
+ * 1. The origin of this software must not be misrepresented; you must not\r
+ * claim that you wrote the original software.\r
+ * 2. Altered source versions must be plainly marked as such, and must not be\r
+ * misrepresented as being the original software.\r
+ * 3. This notice may not be removed or altered from any source distribution.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no\r
+ * obligation to support this Software. Silicon Labs is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Silicon Labs will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_EM_RTCC_H__\r
+#define __SILICON_LABS_EM_RTCC_H__\r
+\r
+#include "em_device.h"\r
+#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )\r
+\r
+#include <stdbool.h>\r
+#include "em_assert.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup EM_Library\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup RTCC\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ ********************************* ENUM ************************************\r
+ ******************************************************************************/\r
+\r
+/** Operational mode of the counter. */\r
+typedef enum\r
+{\r
+ /** Normal counter mode. The counter is incremented by 1 for each tick. */\r
+ rtccCntModeNormal = _RTCC_CTRL_CNTTICK_PRESC,\r
+\r
+ /** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more\r
+ * details on the calendar mode. */\r
+ rtccCntModeCalendar = _RTCC_CTRL_CNTTICK_CCV0MATCH\r
+} RTCC_CntMode_TypeDef;\r
+\r
+/** Counter prescaler selection. */\r
+typedef enum\r
+{\r
+ rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */\r
+ rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */\r
+ rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */\r
+ rtccCntPresc_8 = _RTCC_CTRL_CNTPRESC_DIV8, /**< Divide clock by 8. */\r
+ rtccCntPresc_16 = _RTCC_CTRL_CNTPRESC_DIV16, /**< Divide clock by 16. */\r
+ rtccCntPresc_32 = _RTCC_CTRL_CNTPRESC_DIV32, /**< Divide clock by 32. */\r
+ rtccCntPresc_64 = _RTCC_CTRL_CNTPRESC_DIV64, /**< Divide clock by 64. */\r
+ rtccCntPresc_128 = _RTCC_CTRL_CNTPRESC_DIV128, /**< Divide clock by 128. */\r
+ rtccCntPresc_256 = _RTCC_CTRL_CNTPRESC_DIV256, /**< Divide clock by 256. */\r
+ rtccCntPresc_512 = _RTCC_CTRL_CNTPRESC_DIV512, /**< Divide clock by 512. */\r
+ rtccCntPresc_1024 = _RTCC_CTRL_CNTPRESC_DIV1024, /**< Divide clock by 1024. */\r
+ rtccCntPresc_2048 = _RTCC_CTRL_CNTPRESC_DIV2048, /**< Divide clock by 2048. */\r
+ rtccCntPresc_4096 = _RTCC_CTRL_CNTPRESC_DIV4096, /**< Divide clock by 4096. */\r
+ rtccCntPresc_8192 = _RTCC_CTRL_CNTPRESC_DIV8192, /**< Divide clock by 8192. */\r
+ rtccCntPresc_16384 = _RTCC_CTRL_CNTPRESC_DIV16384, /**< Divide clock by 16384. */\r
+ rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */\r
+} RTCC_CntPresc_TypeDef;\r
+\r
+\r
+/** Prescaler mode of the RTCC counter. */\r
+typedef enum\r
+{\r
+ /** CNT register ticks according to the prescaler value. */\r
+ rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC,\r
+\r
+ /** CNT register ticks when PRECNT matches the 15 least significant bits of\r
+ * ch. 0 CCV register. */\r
+ rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH\r
+} RTCC_PrescMode_TypeDef;\r
+\r
+\r
+/** Capture/Compare channel mode. */\r
+typedef enum\r
+{\r
+ rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */\r
+ rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */\r
+ rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */\r
+} RTCC_CapComChMode_TypeDef;\r
+\r
+/** Compare match output action mode. */\r
+typedef enum\r
+{\r
+ rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */\r
+ rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */\r
+ rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */\r
+ rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */\r
+} RTCC_CompMatchOutAction_TypeDef;\r
+\r
+\r
+/** PRS input sources. */\r
+typedef enum\r
+{\r
+ rtccPRSCh0 = _RTCC_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */\r
+ rtccPRSCh1 = _RTCC_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
+ rtccPRSCh2 = _RTCC_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
+ rtccPRSCh3 = _RTCC_CC_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */\r
+ rtccPRSCh4 = _RTCC_CC_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */\r
+ rtccPRSCh5 = _RTCC_CC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */\r
+ rtccPRSCh6 = _RTCC_CC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */\r
+ rtccPRSCh7 = _RTCC_CC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */\r
+ rtccPRSCh8 = _RTCC_CC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */\r
+ rtccPRSCh9 = _RTCC_CC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */\r
+ rtccPRSCh10 = _RTCC_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */\r
+ rtccPRSCh11 = _RTCC_CC_CTRL_PRSSEL_PRSCH11 /**< PRS channel 11. */\r
+} RTCC_PRSSel_TypeDef;\r
+\r
+\r
+/** Input edge select. */\r
+typedef enum\r
+{\r
+ rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */\r
+ rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */\r
+ rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */\r
+ rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */\r
+} RTCC_InEdgeSel_TypeDef;\r
+\r
+\r
+/** Capture/Compare channel compare mode. */\r
+typedef enum\r
+{\r
+ /** CCVx is compared with the CNT register. */\r
+ rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT,\r
+\r
+ /** CCVx is compared with a CNT[16:0] and PRECNT[14:0]. */\r
+ rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT\r
+} RTCC_CompBase_TypeDef;\r
+\r
+ /** Day compare mode. */\r
+typedef enum\r
+{\r
+ rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */\r
+ rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */\r
+} RTCC_DayCompareMode_TypeDef;\r
+\r
+/*******************************************************************************\r
+ ******************************* STRUCTS ***********************************\r
+ ******************************************************************************/\r
+\r
+/** RTCC initialization structure. */\r
+typedef struct\r
+{\r
+ /** Enable/disable counting when initialization is completed. */\r
+ bool enable;\r
+\r
+ /** Enable/disable timer counting during debug halt. */\r
+ bool debugRun;\r
+\r
+ /** Enable/disable precounter wrap on ch. 0 CCV value. */\r
+ bool precntWrapOnCCV0;\r
+\r
+ /** Enable/disable counter wrap on ch. 1 CCV value. */\r
+ bool cntWrapOnCCV1;\r
+\r
+ /** Counter prescaler. */\r
+ RTCC_CntPresc_TypeDef presc;\r
+\r
+ /** Prescaler mode. */\r
+ RTCC_PrescMode_TypeDef prescMode;\r
+\r
+#if defined(_RTCC_CTRL_BUMODETSEN_MASK)\r
+ /** Enable/disable storing RTCC counter value in RTCC_CCV2 upon backup mode\r
+ * entry. */\r
+ bool enaBackupModeSet;\r
+#endif\r
+\r
+ /** Enable/disable the check that sets the OSCFFAIL interrupt flag if no\r
+ * LFCLK-RTCC ticks are detected within one ULFRCO cycles. */\r
+ bool enaOSCFailDetect;\r
+\r
+ /** Select the operational mode of the counter. */\r
+ RTCC_CntMode_TypeDef cntMode;\r
+\r
+ /** Disable leap year correction for the calendar mode. When this parameter is\r
+ * set to false, February has 29 days if (year % 4 == 0). If true, February\r
+ * always has 28 days. */\r
+ bool disLeapYearCorr;\r
+} RTCC_Init_TypeDef;\r
+\r
+\r
+/** RTCC capture/compare channel configuration structure. */\r
+typedef struct\r
+{\r
+ /** Select the mode of the Capture/Compare channel. */\r
+ RTCC_CapComChMode_TypeDef chMode;\r
+\r
+ /** Compare mode channel match output action. */\r
+ RTCC_CompMatchOutAction_TypeDef compMatchOutAction;\r
+\r
+ /** Capture mode channel PRS input channel selection. */\r
+ RTCC_PRSSel_TypeDef prsSel;\r
+\r
+ /** Capture mode channel input edge selection. */\r
+ RTCC_InEdgeSel_TypeDef inputEdgeSel;\r
+\r
+ /** Comparison base of the channel in compare mode. */\r
+ RTCC_CompBase_TypeDef compBase;\r
+\r
+ /** The COMPMASK (5 bit) most significant bits of the compare value will not\r
+ * be subject to comparison. */\r
+ uint8_t compMask;\r
+\r
+ /** Day compare mode. */\r
+ RTCC_DayCompareMode_TypeDef dayCompMode;\r
+} RTCC_CCChConf_TypeDef;\r
+\r
+\r
+/*******************************************************************************\r
+ ******************************* DEFINES ***********************************\r
+ ******************************************************************************/\r
+\r
+/** Default RTCC init structure. */\r
+#if defined(_RTCC_CTRL_BUMODETSEN_MASK)\r
+#define RTCC_INIT_DEFAULT \\r
+{ \\r
+ true, /* Start counting when init done. */ \\r
+ false, /* Disable RTCC during debug halt. */ \\r
+ false, /* Disable precounter wrap on ch. 0 CCV value. */ \\r
+ false, /* Disable counter wrap on ch. 1 CCV value. */ \\r
+ rtccCntPresc_32, /* 977 us per tick. */ \\r
+ rtccCntTickPresc, /* Counter increments according to prescaler value. */ \\r
+ false, /* No RTCC storage on backup mode entry. */ \\r
+ false, /* No RTCC oscillator failure detection. */ \\r
+ rtccCntModeNormal, /* Normal RTCC mode. */ \\r
+ false, /* No leap year correction. */ \\r
+}\r
+#else\r
+#define RTCC_INIT_DEFAULT \\r
+{ \\r
+ true, /* Start counting when init done. */ \\r
+ false, /* Disable RTCC during debug halt. */ \\r
+ false, /* Disable precounter wrap on ch. 0 CCV value. */ \\r
+ false, /* Disable counter wrap on ch. 1 CCV value. */ \\r
+ rtccCntPresc_32, /* 977 us per tick. */ \\r
+ rtccCntTickPresc, /* Counter increments according to prescaler value. */ \\r
+ false, /* No RTCC oscillator failure detection. */ \\r
+ rtccCntModeNormal, /* Normal RTCC mode. */ \\r
+ false, /* No leap year correction. */ \\r
+}\r
+#endif\r
+\r
+/** Default RTCC channel output compare init structure. */\r
+#define RTCC_CH_INIT_COMPARE_DEFAULT \\r
+{ \\r
+ rtccCapComChModeCompare, /* Select output compare mode. */ \\r
+ rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \\r
+ rtccPRSCh0, /* PRS channel 0 (not used). */ \\r
+ rtccInEdgeNone, /* No edge detection. */ \\r
+ rtccCompBaseCnt, /* Counter comparison base. */ \\r
+ 0, /* No compare mask bits set. */ \\r
+ rtccDayCompareModeMonth /* Don't care */ \\r
+}\r
+\r
+/** Default RTCC channel input capture init structure. */\r
+#define RTCC_CH_INIT_CAPTURE_DEFAULT \\r
+{ \\r
+ rtccCapComChModeCapture, /* Select input capture mode. */ \\r
+ rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \\r
+ rtccPRSCh0, /* PRS channel 0. */ \\r
+ rtccInEdgeRising, /* Rising edge detection. */ \\r
+ rtccCompBaseCnt, /* Don't care. */ \\r
+ 0, /* Don't care. */ \\r
+ rtccDayCompareModeMonth /* Don't care */ \\r
+}\r
+\r
+/** Validation of valid RTCC channel for assert statements. */\r
+#define RTCC_CH_VALID( ch ) ( ( ch ) < 3 )\r
+\r
+/*******************************************************************************\r
+ ***************************** PROTOTYPES **********************************\r
+ ******************************************************************************/\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get RTCC capture/compare register value (CCV) for selected channel.\r
+ *\r
+ * @param[in] ch\r
+ * Channel selector.\r
+ *\r
+ * @return\r
+ * Capture/compare register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_ChannelCCVGet( int ch )\r
+{\r
+ EFM_ASSERT( RTCC_CH_VALID( ch ) );\r
+ return RTCC->CC[ ch ].CCV;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set RTCC capture/compare register value (CCV) for selected channel.\r
+ *\r
+ * @param[in] ch\r
+ * Channel selector.\r
+ *\r
+ * @param[in] value\r
+ * CCV value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_ChannelCCVSet( int ch, uint32_t value )\r
+{\r
+ EFM_ASSERT( RTCC_CH_VALID( ch ) );\r
+ RTCC->CC[ ch ].CCV = value;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the calendar DATE register content for selected channel.\r
+ *\r
+ * @param[in] ch\r
+ * Channel selector.\r
+ *\r
+ * @return\r
+ * DATE register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_ChannelDateGet( int ch )\r
+{\r
+ EFM_ASSERT( RTCC_CH_VALID( ch ) );\r
+ return RTCC->CC[ ch ].DATE;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the calendar DATE register for selected channel.\r
+ *\r
+ * @param[in] ch\r
+ * Channel selector.\r
+ *\r
+ * @param[in] date\r
+ * DATE value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_ChannelDateSet( int ch, uint32_t date )\r
+{\r
+ EFM_ASSERT( RTCC_CH_VALID( ch ) );\r
+ RTCC->CC[ ch ].DATE = date;\r
+}\r
+\r
+void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr );\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the calendar TIME register content for selected channel.\r
+ *\r
+ * @param[in] ch\r
+ * Channel selector.\r
+ *\r
+ * @return\r
+ * TIME register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_ChannelTimeGet( int ch )\r
+{\r
+ EFM_ASSERT( RTCC_CH_VALID( ch ) );\r
+ return RTCC->CC[ ch ].TIME;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set the calendar TIME register for selected channel.\r
+ *\r
+ * @param[in] ch\r
+ * Channel selector.\r
+ *\r
+ * @param[in] time\r
+ * TIME value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_ChannelTimeSet( int ch, uint32_t time )\r
+{\r
+ EFM_ASSERT( RTCC_CH_VALID( ch ) );\r
+ RTCC->CC[ ch ].TIME = time;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get the combined CNT/PRECNT register content.\r
+ *\r
+ * @return\r
+ * CNT/PRECNT register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_CombinedCounterGet( void )\r
+{\r
+ return RTCC->COMBCNT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get RTCC counter value.\r
+ *\r
+ * @return\r
+ * Current RTCC counter value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_CounterGet( void )\r
+{\r
+ return RTCC->CNT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set RTCC CNT counter.\r
+ *\r
+ * @param[in] value\r
+ * CNT value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_CounterSet( uint32_t value )\r
+{\r
+ RTCC->CNT = value;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get DATE register value.\r
+ *\r
+ * @return\r
+ * Current DATE register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_DateGet( void )\r
+{\r
+ return RTCC->DATE;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set RTCC DATE register.\r
+ *\r
+ * @param[in] date\r
+ * DATE value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_DateSet( uint32_t date )\r
+{\r
+ RTCC->DATE = date;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable/disable EM4 wakeup capability.\r
+ *\r
+ * @param[in] enable\r
+ * True to enable EM4 wakeup, false to disable.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_EM4WakeupEnable( bool enable )\r
+{\r
+ if ( enable )\r
+ {\r
+ RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU;\r
+ }\r
+ else\r
+ {\r
+ RTCC->EM4WUEN = 0;\r
+ }\r
+}\r
+\r
+void RTCC_Enable( bool enable );\r
+\r
+void RTCC_Init( const RTCC_Init_TypeDef *init );\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Clear one or more pending RTCC interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed\r
+ * together to clear multiple interrupt sources.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_IntClear( uint32_t flags )\r
+{\r
+ RTCC->IFC = flags;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Disable one or more RTCC interrupts.\r
+ *\r
+ * @param[in] flags\r
+ * RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed\r
+ * together to disable multiple interrupt.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_IntDisable( uint32_t flags )\r
+{\r
+ RTCC->IEN &= ~flags;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Enable one or more RTCC interrupts.\r
+ *\r
+ * @note\r
+ * Depending on the use, a pending interrupt may already be set prior to\r
+ * enabling the interrupt. Consider using RTCC_IntClear() prior to enabling\r
+ * if such a pending interrupt should be ignored.\r
+ *\r
+ * @param[in] flags\r
+ * RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed\r
+ * together to set multiple interrupt.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_IntEnable( uint32_t flags )\r
+{\r
+ RTCC->IEN |= flags;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get pending RTCC interrupt flags.\r
+ *\r
+ * @note\r
+ * The event bits are not cleared by the use of this function.\r
+ *\r
+ * @return\r
+ * Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed\r
+ * together for the interrupt sources set.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_IntGet( void )\r
+{\r
+ return RTCC->IF;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get enabled and pending RTCC interrupt flags.\r
+ *\r
+ * @details\r
+ * Useful for handling more interrupt sources in the same interrupt handler.\r
+ *\r
+ * @return\r
+ * Pending and enabled RTCC interrupt sources. Returns a set of interrupt\r
+ * flags OR-ed together for the interrupt sources set.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_IntGetEnabled( void )\r
+{\r
+ uint32_t tmp;\r
+\r
+ tmp = RTCC->IEN;\r
+\r
+ /* Bitwise AND of pending and enabled interrupt flags. */\r
+ return RTCC->IF & tmp;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set one or more pending RTCC interrupts from SW.\r
+ *\r
+ * @param[in] flags\r
+ * RTCC interrupt sources to set to pending. Use a set of interrupt flags\r
+ * (RTCC_IFS_nnn).\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_IntSet( uint32_t flags )\r
+{\r
+ RTCC->IFS = flags;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Lock RTCC registers.\r
+ *\r
+ * @note\r
+ * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT,\r
+ * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers\r
+ * can not be written to.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_Lock( void )\r
+{\r
+ RTCC->LOCK = RTCC_LOCK_LOCKKEY_LOCK;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get RTCC pre-counter value.\r
+ *\r
+ * @return\r
+ * Current RTCC pre-counter value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_PreCounterGet( void )\r
+{\r
+ return RTCC->PRECNT;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set RTCC pre-counter value.\r
+ *\r
+ * @param[in] preCntVal\r
+ * RTCC pre-counter value to be set.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_PreCounterSet( uint32_t preCntVal )\r
+{\r
+ RTCC->PRECNT = preCntVal;\r
+}\r
+\r
+void RTCC_Reset( void );\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Power down the retention ram.\r
+ *\r
+ * @note\r
+ * Once retention ram is powered down, it cannot be powered up again.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_RetentionRamPowerDown( void )\r
+{\r
+ RTCC->POWERDOWN = RTCC_POWERDOWN_RAM;\r
+}\r
+\r
+void RTCC_StatusClear( void );\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get STATUS register value.\r
+ *\r
+ * @return\r
+ * Current STATUS register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_StatusGet( void )\r
+{\r
+ while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )\r
+ {\r
+ // Wait for syncronization.\r
+ }\r
+ return RTCC->STATUS;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get TIME register value.\r
+ *\r
+ * @return\r
+ * Current TIME register value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint32_t RTCC_TimeGet( void )\r
+{\r
+ return RTCC->TIME;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Set RTCC TIME register.\r
+ *\r
+ * @param[in] time\r
+ * TIME value.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_TimeSet( uint32_t time )\r
+{\r
+ RTCC->TIME = time;\r
+}\r
+\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Unlock RTCC registers.\r
+ *\r
+ * @note\r
+ * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT,\r
+ * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers\r
+ * can not be written to.\r
+ ******************************************************************************/\r
+__STATIC_INLINE void RTCC_Unlock( void )\r
+{\r
+ RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK;\r
+}\r
+\r
+/** @} (end addtogroup RTCC) */\r
+/** @} (end addtogroup EM_Library) */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* defined( RTCC_COUNT ) && ( RTC_COUNT == 1 ) */\r
+#endif /* __SILICON_LABS_EM_RTCC_H__ */\r
/***************************************************************************//**\r
* @file em_system.h\r
* @brief System API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_SYSTEM_H_\r
-#define __SILICON_LABS_EM_SYSTEM_H_\r
+#ifndef __SILICON_LABS_EM_SYSTEM_H__\r
+#define __SILICON_LABS_EM_SYSTEM_H__\r
\r
#include <stdbool.h>\r
#include "em_device.h"\r
******************************** ENUMS ************************************\r
******************************************************************************/\r
\r
-/** EFM32 part family identifiers. */\r
+/** Family identifiers. */\r
typedef enum\r
{\r
/* New style family #defines */\r
-#if defined ( _DEVINFO_PART_DEVICE_FAMILY_EFM32G )\r
- systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G)\r
+ systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG)\r
+ systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG)\r
+ systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG)\r
+ systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG)\r
+ systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG)\r
+ systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG)\r
+ systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B)\r
+ systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Gen1 Basic Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B)\r
+ systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Gen1 Basic Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG)\r
+ systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG)\r
+ systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG)\r
+ systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P)\r
+ systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Gen1 Premium Device Family */\r
#endif\r
-#if defined ( _DEVINFO_PART_DEVICE_FAMILY_EFM32GG )\r
- systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B)\r
+ systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Gen1 Basic Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EFM32TG )\r
- systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V)\r
+ systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Gen1 Value Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EFM32LG )\r
- systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P)\r
+ systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Gen1 Premium Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EFM32WG )\r
- systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B)\r
+ systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Gen1 Basic Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG )\r
- systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V)\r
+ systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Gen1 Value Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EFM32HG )\r
- systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32SG1P)\r
+ systemPartFamilySnappy1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32SG1P, /**< EFR32 Snappy Gecko Gen1 Premium Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EZR32WG )\r
- systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32SG1B)\r
+ systemPartFamilySnappy1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32SG1B, /**< EFR32 Snappy Gecko Gen1 Basic Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EZR32LG )\r
- systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32SG1V)\r
+ systemPartFamilySnappy1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32SG1V, /**< EFR32 Snappy Gecko Gen1 Value Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_EZR32HG )\r
- systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family */\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P)\r
+ systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Gen1 Premium Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B)\r
+ systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Gen1 Basic Device Family */\r
+#endif\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V)\r
+ systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Gen1 Value Device Family */\r
#endif\r
/* Legacy family #defines */\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_G )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_G)\r
systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_GG )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG)\r
systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_TG )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG)\r
systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_LG )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG)\r
systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_WG )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG)\r
systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_ZG )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG)\r
systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family */\r
#endif\r
-#if defined( _DEVINFO_PART_DEVICE_FAMILY_HG )\r
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG)\r
systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family */\r
#endif\r
systemPartFamilyUnknown = 0xFF /**< Unknown Device Family.\r
uint8_t family;/**< Device family number */\r
} SYSTEM_ChipRevision_TypeDef;\r
\r
-#if defined( __FPU_PRESENT ) && ( __FPU_PRESENT == 1 )\r
+#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)\r
/** Floating point coprocessor access modes. */\r
typedef enum\r
{\r
void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev);\r
uint32_t SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress);\r
\r
-#if defined( __FPU_PRESENT ) && ( __FPU_PRESENT == 1 )\r
+#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)\r
/***************************************************************************//**\r
* @brief\r
* Set floating point coprocessor (FPU) access mode.\r
******************************************************************************/\r
__STATIC_INLINE uint64_t SYSTEM_GetUnique(void)\r
{\r
- return ((uint64_t) ((uint64_t) DEVINFO->UNIQUEH << 32) | (uint64_t) DEVINFO->UNIQUEL);\r
+ return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | (uint64_t)DEVINFO->UNIQUEL;\r
}\r
\r
/***************************************************************************//**\r
******************************************************************************/\r
__STATIC_INLINE uint8_t SYSTEM_GetProdRev(void)\r
{\r
- return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)\r
- >> _DEVINFO_PART_PROD_REV_SHIFT);\r
+ return (DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)\r
+ >> _DEVINFO_PART_PROD_REV_SHIFT;\r
}\r
\r
/***************************************************************************//**\r
if (SYSTEM_GetProdRev() < 5)\r
{\r
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)\r
- >> _DEVINFO_MSIZE_FLASH_SHIFT;\r
+ >> _DEVINFO_MSIZE_FLASH_SHIFT;\r
}\r
#endif\r
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)\r
- >> _DEVINFO_MSIZE_SRAM_SHIFT;\r
+ >> _DEVINFO_MSIZE_SRAM_SHIFT;\r
}\r
\r
/***************************************************************************//**\r
if (SYSTEM_GetProdRev() < 5)\r
{\r
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)\r
- >> _DEVINFO_MSIZE_SRAM_SHIFT;\r
+ >> _DEVINFO_MSIZE_SRAM_SHIFT;\r
}\r
#endif\r
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)\r
- >> _DEVINFO_MSIZE_FLASH_SHIFT;\r
+ >> _DEVINFO_MSIZE_FLASH_SHIFT;\r
}\r
\r
\r
{\r
uint32_t tmp;\r
\r
-#if defined( _EFM32_GIANT_FAMILY )\r
- tmp = SYSTEM_GetProdRev();\r
- if (tmp < 18)\r
+#if defined(_EFM32_GIANT_FAMILY)\r
+ if (SYSTEM_GetProdRev() < 18)\r
{\r
/* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */\r
return FLASH_PAGE_SIZE;\r
}\r
-#elif defined( _EFM32_ZERO_FAMILY )\r
- tmp = SYSTEM_GetProdRev();\r
- if (tmp < 24)\r
+#elif defined(_EFM32_ZERO_FAMILY)\r
+ if (SYSTEM_GetProdRev() < 24)\r
{\r
/* Early Zero devices have an incorrect DEVINFO flash page size */\r
return FLASH_PAGE_SIZE;\r
}\r
#endif\r
+\r
tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK)\r
- >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT;\r
+ >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT;\r
\r
return 1 << ((tmp + 10) & 0xFF);\r
}\r
\r
\r
+#if defined( _DEVINFO_DEVINFOREV_DEVINFOREV_MASK )\r
+/***************************************************************************//**\r
+ * @brief\r
+ * Get DEVINFO revision.\r
+ *\r
+ * @return\r
+ * Revision of the DEVINFO contents.\r
+ ******************************************************************************/\r
+__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void)\r
+{\r
+ return (DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK)\r
+ >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT;\r
+}\r
+#endif\r
+\r
+\r
/***************************************************************************//**\r
* @brief\r
* Get part number of the MCU.\r
__STATIC_INLINE uint16_t SYSTEM_GetPartNumber(void)\r
{\r
return (DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK)\r
- >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT;\r
+ >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT;\r
}\r
\r
/***************************************************************************//**\r
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)\r
{\r
return (SYSTEM_PartFamily_TypeDef)\r
- ((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK)\r
- >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);\r
+ ((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK)\r
+ >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);\r
}\r
\r
\r
__STATIC_INLINE uint8_t SYSTEM_GetCalibrationTemperature(void)\r
{\r
return (DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK)\r
- >> _DEVINFO_CAL_TEMP_SHIFT;\r
+ >> _DEVINFO_CAL_TEMP_SHIFT;\r
}\r
\r
/** @} (end addtogroup SYSTEM) */\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_SYSTEM_H_ */\r
+#endif /* __SILICON_LABS_EM_SYSTEM_H__ */\r
/***************************************************************************//**\r
* @file em_timer.h\r
* @brief Timer/counter (TIMER) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_TIMER_H_\r
-#define __SILICON_LABS_EM_TIMER_H_\r
+#ifndef __SILICON_LABS_EM_TIMER_H__\r
+#define __SILICON_LABS_EM_TIMER_H__\r
\r
#include "em_device.h"\r
#if defined(TIMER_COUNT) && (TIMER_COUNT > 0)\r
#elif (TIMER_COUNT == 2)\r
#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || ((ref) == TIMER1))\r
#elif (TIMER_COUNT == 3)\r
-#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || \\r
- ((ref) == TIMER1) || \\r
- ((ref) == TIMER2))\r
+#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \\r
+ || ((ref) == TIMER1) \\r
+ || ((ref) == TIMER2))\r
#elif (TIMER_COUNT == 4)\r
-#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || \\r
- ((ref) == TIMER1) || \\r
- ((ref) == TIMER2) || \\r
- ((ref) == TIMER3))\r
+#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \\r
+ || ((ref) == TIMER1) \\r
+ || ((ref) == TIMER2) \\r
+ || ((ref) == TIMER3))\r
#else\r
-#error Undefined number of timers.\r
+#error "Undefined number of timers."\r
#endif\r
\r
/** Validation of TIMER compare/capture channel number */\r
+#if defined(_SILICON_LABS_32B_PLATFORM_1)\r
#define TIMER_CH_VALID(ch) ((ch) < 3)\r
+#elif defined(_SILICON_LABS_32B_PLATFORM_2)\r
+#define TIMER_CH_VALID(ch) ((ch) < 4)\r
+#else\r
+#error "Unknown platform. Undefined number of channels."\r
+#endif\r
\r
/** @endcond */\r
\r
timerPRSSELCh1 = _TIMER_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */\r
timerPRSSELCh2 = _TIMER_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */\r
timerPRSSELCh3 = _TIMER_CC_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH4 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH4)\r
timerPRSSELCh4 = _TIMER_CC_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH5 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH5)\r
timerPRSSELCh5 = _TIMER_CC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH6 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH6)\r
timerPRSSELCh6 = _TIMER_CC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH7 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH7)\r
timerPRSSELCh7 = _TIMER_CC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH8 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH8)\r
timerPRSSELCh8 = _TIMER_CC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH9 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH9)\r
timerPRSSELCh9 = _TIMER_CC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH10 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH10)\r
timerPRSSELCh10 = _TIMER_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */\r
#endif\r
-#if defined( _TIMER_CC_CTRL_PRSSEL_PRSCH11 )\r
+#if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH11)\r
timerPRSSELCh11 = _TIMER_CC_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */\r
#endif\r
} TIMER_PRSSEL_TypeDef;\r
\r
-#ifdef _TIMER_DTFC_DTFA_NONE\r
+#if defined(_TIMER_DTFC_DTFA_NONE)\r
/** DT (Dead Time) Fault Actions. */\r
typedef enum\r
{\r
/** Clock selection. */\r
TIMER_ClkSel_TypeDef clkSel;\r
\r
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )\r
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)\r
/** 2x Count mode, counter increments/decrements by 2, meant for PWN mode. */\r
bool count2x;\r
\r
} TIMER_Init_TypeDef;\r
\r
/** Default config for TIMER init structure. */\r
-#if defined( TIMER_CTRL_X2CNT ) && defined( TIMER_CTRL_ATI )\r
-#define TIMER_INIT_DEFAULT \\r
- { true, /* Enable timer when init complete. */ \\r
- false, /* Stop counter during debug halt. */ \\r
- timerPrescale1, /* No prescaling. */ \\r
- timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
- false, /* Not 2x count mode. */ \\r
- false, /* No ATI. */ \\r
- timerInputActionNone, /* No action on falling input edge. */ \\r
- timerInputActionNone, /* No action on rising input edge. */ \\r
- timerModeUp, /* Up-counting. */ \\r
- false, /* Do not clear DMA requests when DMA channel is active. */ \\r
- false, /* Select X2 quadrature decode mode (if used). */ \\r
- false, /* Disable one shot. */ \\r
- false /* Not started/stopped/reloaded by other timers. */ \\r
- }\r
+#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)\r
+#define TIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable timer when init complete. */ \\r
+ false, /* Stop counter during debug halt. */ \\r
+ timerPrescale1, /* No prescaling. */ \\r
+ timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
+ false, /* Not 2x count mode. */ \\r
+ false, /* No ATI. */ \\r
+ timerInputActionNone, /* No action on falling input edge. */ \\r
+ timerInputActionNone, /* No action on rising input edge. */ \\r
+ timerModeUp, /* Up-counting. */ \\r
+ false, /* Do not clear DMA requests when DMA channel is active. */ \\r
+ false, /* Select X2 quadrature decode mode (if used). */ \\r
+ false, /* Disable one shot. */ \\r
+ false /* Not started/stopped/reloaded by other timers. */ \\r
+}\r
#else\r
-#define TIMER_INIT_DEFAULT \\r
- { true, /* Enable timer when init complete. */ \\r
- false, /* Stop counter during debug halt. */ \\r
- timerPrescale1, /* No prescaling. */ \\r
- timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
- timerInputActionNone, /* No action on falling input edge. */ \\r
- timerInputActionNone, /* No action on rising input edge. */ \\r
- timerModeUp, /* Up-counting. */ \\r
- false, /* Do not clear DMA requests when DMA channel is active. */ \\r
- false, /* Select X2 quadrature decode mode (if used). */ \\r
- false, /* Disable one shot. */ \\r
- false /* Not started/stopped/reloaded by other timers. */ \\r
- }\r
+#define TIMER_INIT_DEFAULT \\r
+{ \\r
+ true, /* Enable timer when init complete. */ \\r
+ false, /* Stop counter during debug halt. */ \\r
+ timerPrescale1, /* No prescaling. */ \\r
+ timerClkSelHFPerClk, /* Select HFPER clock. */ \\r
+ timerInputActionNone, /* No action on falling input edge. */ \\r
+ timerInputActionNone, /* No action on rising input edge. */ \\r
+ timerModeUp, /* Up-counting. */ \\r
+ false, /* Do not clear DMA requests when DMA channel is active. */ \\r
+ false, /* Select X2 quadrature decode mode (if used). */ \\r
+ false, /* Disable one shot. */ \\r
+ false /* Not started/stopped/reloaded by other timers. */ \\r
+}\r
#endif\r
\r
/** TIMER compare/capture initialization structure. */\r
} TIMER_InitCC_TypeDef;\r
\r
/** Default config for TIMER compare/capture init structure. */\r
-#define TIMER_INITCC_DEFAULT \\r
- { timerEventEveryEdge, /* Event on every capture. */ \\r
- timerEdgeRising, /* Input capture edge on rising edge. */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- timerOutputActionNone, /* No action on underflow. */ \\r
- timerOutputActionNone, /* No action on overflow. */ \\r
- timerOutputActionNone, /* No action on match. */ \\r
- timerCCModeOff, /* Disable compare/capture channel. */ \\r
- false, /* Disable filter. */ \\r
- false, /* Select TIMERnCCx input. */ \\r
- false, /* Clear output when counter disabled. */ \\r
- false /* Do not invert output. */ \\r
- }\r
+#define TIMER_INITCC_DEFAULT \\r
+{ \\r
+ timerEventEveryEdge, /* Event on every capture. */ \\r
+ timerEdgeRising, /* Input capture edge on rising edge. */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ timerOutputActionNone, /* No action on underflow. */ \\r
+ timerOutputActionNone, /* No action on overflow. */ \\r
+ timerOutputActionNone, /* No action on match. */ \\r
+ timerCCModeOff, /* Disable compare/capture channel. */ \\r
+ false, /* Disable filter. */ \\r
+ false, /* Select TIMERnCCx input. */ \\r
+ false, /* Clear output when counter disabled. */ \\r
+ false /* Do not invert output. */ \\r
+}\r
\r
-#ifdef _TIMER_DTCTRL_MASK\r
+#if defined(_TIMER_DTCTRL_MASK)\r
/** TIMER Dead Time Insertion (DTI) initialization structure. */\r
typedef struct\r
{\r
\r
\r
/** Default config for TIMER DTI init structure. */\r
-#define TIMER_INITDTI_DEFAULT \\r
- { true, /* Enable the DTI. */ \\r
- false, /* CC[0|1|2] outputs are active high. */ \\r
- false, /* CDTI[0|1|2] outputs are not inverted. */ \\r
- false, /* No auto restart when debugger exits. */ \\r
- false, /* No PRS source selected. */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- timerPrescale1, /* No prescaling. */ \\r
- 0, /* No rise time. */ \\r
- 0, /* No fall time. */ \\r
- TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\\r
- true, /* Enable core lockup as fault source */ \\r
- true, /* Enable debugger as fault source */ \\r
- false, /* Disable PRS fault source 0 */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- false, /* Disable PRS fault source 1 */ \\r
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
- timerDtiFaultActionInactive, /* No fault action. */ \\r
- }\r
+#define TIMER_INITDTI_DEFAULT \\r
+{ \\r
+ true, /* Enable the DTI. */ \\r
+ false, /* CC[0|1|2] outputs are active high. */ \\r
+ false, /* CDTI[0|1|2] outputs are not inverted. */ \\r
+ false, /* No auto restart when debugger exits. */ \\r
+ false, /* No PRS source selected. */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ timerPrescale1, /* No prescaling. */ \\r
+ 0, /* No rise time. */ \\r
+ 0, /* No fall time. */ \\r
+ TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\\r
+ true, /* Enable core lockup as fault source */ \\r
+ true, /* Enable debugger as fault source */ \\r
+ false, /* Disable PRS fault source 0 */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ false, /* Disable PRS fault source 1 */ \\r
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \\r
+ timerDtiFaultActionInactive, /* No fault action. */ \\r
+}\r
#endif /* _TIMER_DTCTRL_MASK */\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)\r
{\r
- return(timer->CC[ch].CCV);\r
+ return timer->CC[ch].CCV;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)\r
{\r
- return(timer->CNT);\r
+ return timer->CNT;\r
}\r
\r
\r
unsigned int ch,\r
const TIMER_InitCC_TypeDef *init);\r
\r
-#ifdef _TIMER_DTCTRL_MASK\r
+#if defined(_TIMER_DTCTRL_MASK)\r
void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init);\r
\r
/***************************************************************************//**\r
__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)\r
{\r
EFM_ASSERT(TIMER0 == timer);\r
- return(timer->DTFAULT);\r
+ return timer->DTFAULT;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)\r
{\r
- timer->IEN &= ~(flags);\r
+ timer->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)\r
{\r
- return(timer->IF);\r
+ return timer->IF;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)\r
{\r
- uint32_t tmp;\r
+ uint32_t ien;\r
\r
/* Store TIMER->IEN in temporary variable in order to define explicit order\r
* of volatile accesses. */\r
- tmp = timer->IEN;\r
+ ien = timer->IEN;\r
\r
/* Bitwise AND of pending and enabled interrupts */\r
- return timer->IF & tmp;\r
+ return timer->IF & ien;\r
}\r
\r
\r
timer->IFS = flags;\r
}\r
\r
-#ifdef TIMER_DTLOCK_LOCKKEY_LOCK\r
+#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK)\r
/***************************************************************************//**\r
* @brief\r
* Lock some of the TIMER registers in order to protect them from being\r
******************************************************************************/\r
__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)\r
{\r
- return(timer->TOP);\r
+ return timer->TOP;\r
}\r
\r
\r
}\r
\r
\r
-#ifdef TIMER_DTLOCK_LOCKKEY_UNLOCK\r
+#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)\r
/***************************************************************************//**\r
* @brief\r
* Unlock the TIMER so that writing to locked registers again is possible.\r
#endif\r
\r
#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_TIMER_H_ */\r
+#endif /* __SILICON_LABS_EM_TIMER_H__ */\r
* @file em_usart.h\r
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)\r
* peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
******************************************************************************/\r
\r
\r
-#ifndef __SILICON_LABS_EM_USART_H_\r
-#define __SILICON_LABS_EM_USART_H_\r
+#ifndef __SILICON_LABS_EM_USART_H__\r
+#define __SILICON_LABS_EM_USART_H__\r
\r
#include "em_device.h"\r
#if defined(USART_COUNT) && (USART_COUNT > 0)\r
usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */\r
usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */\r
usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3, /**< PRS channel 3 */\r
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH4 )\r
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH4)\r
usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4, /**< PRS channel 4 */\r
#endif\r
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH5 )\r
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH5)\r
usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5, /**< PRS channel 5 */\r
#endif\r
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH6 )\r
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH6)\r
usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6, /**< PRS channel 6 */\r
#endif\r
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH7 )\r
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH7)\r
usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7, /**< PRS channel 7 */\r
#endif\r
} USART_IrDAPrsSel_Typedef;\r
\r
-#if defined( _USART_I2SCTRL_MASK )\r
+#if defined(_USART_I2SCTRL_MASK)\r
/** I2S format selection. */\r
typedef enum\r
{\r
} USART_I2sJustify_TypeDef;\r
#endif\r
\r
-#if defined( _USART_INPUT_MASK )\r
+#if defined(_USART_INPUT_MASK)\r
/** USART Rx input PRS selection. */\r
typedef enum\r
{\r
usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */\r
usartPrsRxCh3 = USART_INPUT_RXPRSSEL_PRSCH3, /**< PRSCH3 selected as USART_INPUT */\r
\r
-#if defined( USART_INPUT_RXPRSSEL_PRSCH7 )\r
+#if defined(USART_INPUT_RXPRSSEL_PRSCH7)\r
usartPrsRxCh4 = USART_INPUT_RXPRSSEL_PRSCH4, /**< PRSCH4 selected as USART_INPUT */\r
usartPrsRxCh5 = USART_INPUT_RXPRSSEL_PRSCH5, /**< PRSCH5 selected as USART_INPUT */\r
usartPrsRxCh6 = USART_INPUT_RXPRSSEL_PRSCH6, /**< PRSCH6 selected as USART_INPUT */\r
usartPrsRxCh7 = USART_INPUT_RXPRSSEL_PRSCH7, /**< PRSCH7 selected as USART_INPUT */\r
#endif\r
\r
-#if defined( USART_INPUT_RXPRSSEL_PRSCH11 )\r
+#if defined(USART_INPUT_RXPRSSEL_PRSCH11)\r
usartPrsRxCh8 = USART_INPUT_RXPRSSEL_PRSCH8, /**< PRSCH8 selected as USART_INPUT */\r
usartPrsRxCh9 = USART_INPUT_RXPRSSEL_PRSCH9, /**< PRSCH9 selected as USART_INPUT */\r
usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10, /**< PRSCH10 selected as USART_INPUT */\r
usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */\r
usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, /**< PRSCH0 selected as USART Trigger */\r
\r
-#if defined( USART_TRIGCTRL_TSEL_PRSCH7 )\r
+#if defined(USART_TRIGCTRL_TSEL_PRSCH7)\r
usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, /**< PRSCH0 selected as USART Trigger */\r
usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, /**< PRSCH0 selected as USART Trigger */\r
usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, /**< PRSCH0 selected as USART Trigger */\r
/** Number of stopbits to use. */\r
USART_Stopbits_TypeDef stopbits;\r
\r
-#if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )\r
+#if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)\r
/** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */\r
bool mvdis;\r
\r
/** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */\r
USART_PrsRxCh_TypeDef prsRxCh;\r
#endif\r
+#if defined(_USART_TIMING_CSHOLD_MASK)\r
+ /** Auto CS enabling */\r
+ bool autoCsEnable;\r
+ /** Auto CS hold time in baud cycles */\r
+ uint8_t autoCsHold;\r
+ /** Auto CS setup time in baud cycles */\r
+ uint8_t autoCsSetup;\r
+#endif\r
} USART_InitAsync_TypeDef;\r
\r
/** USART PRS trigger enable */\r
typedef struct\r
{\r
-#if defined( USART_TRIGCTRL_AUTOTXTEN )\r
+#if defined(USART_TRIGCTRL_AUTOTXTEN)\r
/** Enable AUTOTX */\r
bool autoTxTriggerEnable;\r
#endif\r
} USART_PrsTriggerInit_TypeDef;\r
\r
/** Default config for USART async init structure. */\r
-#if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )\r
-#define USART_INITASYNC_DEFAULT \\r
- { usartEnable, /* Enable RX/TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 115200, /* 115200 bits/s. */ \\r
- usartOVS16, /* 16x oversampling. */ \\r
- usartDatabits8, /* 8 databits. */ \\r
- usartNoParity, /* No parity. */ \\r
- usartStopbits1, /* 1 stopbit. */ \\r
- false, /* Do not disable majority vote. */ \\r
- false, /* Not USART PRS input mode. */ \\r
- usartPrsRxCh0 /* PRS channel 0. */ \\r
- }\r
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)\r
+#define USART_INITASYNC_DEFAULT \\r
+{ \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 115200, /* 115200 bits/s. */ \\r
+ usartOVS16, /* 16x oversampling. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ usartNoParity, /* No parity. */ \\r
+ usartStopbits1, /* 1 stopbit. */ \\r
+ false, /* Do not disable majority vote. */ \\r
+ false, /* Not USART PRS input mode. */ \\r
+ usartPrsRxCh0, /* PRS channel 0. */ \\r
+ false, /* Auto CS functionality enable/disable switch */ \\r
+ 0, /* Auto CS Hold cycles */ \\r
+ 0 /* Auto CS Setup cycles */ \\r
+}\r
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)\r
+#define USART_INITASYNC_DEFAULT \\r
+{ \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 115200, /* 115200 bits/s. */ \\r
+ usartOVS16, /* 16x oversampling. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ usartNoParity, /* No parity. */ \\r
+ usartStopbits1, /* 1 stopbit. */ \\r
+ false, /* Do not disable majority vote. */ \\r
+ false, /* Not USART PRS input mode. */ \\r
+ usartPrsRxCh0 /* PRS channel 0. */ \\r
+}\r
#else\r
-#define USART_INITASYNC_DEFAULT \\r
- { usartEnable, /* Enable RX/TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 115200, /* 115200 bits/s. */ \\r
- usartOVS16, /* 16x oversampling. */ \\r
- usartDatabits8, /* 8 databits. */ \\r
- usartNoParity, /* No parity. */ \\r
- usartStopbits1 /* 1 stopbit. */ \\r
- }\r
+#define USART_INITASYNC_DEFAULT \\r
+{ \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 115200, /* 115200 bits/s. */ \\r
+ usartOVS16, /* 16x oversampling. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ usartNoParity, /* No parity. */ \\r
+ usartStopbits1 /* 1 stopbit. */ \\r
+}\r
#endif\r
\r
/** Default config for USART PRS triggering structure. */\r
-#if defined ( USART_TRIGCTRL_AUTOTXTEN )\r
-#define USART_INITPRSTRIGGER_DEFAULT \\r
- { false, /* Do not enable autoTX triggering. */ \\r
- false, /* Do not enable receive triggering. */ \\r
- false, /* Do not enable transmit triggering. */ \\r
- usartPrsTriggerCh0 /* Set default channel to zero. */ \\r
- }\r
+#if defined(USART_TRIGCTRL_AUTOTXTEN)\r
+#define USART_INITPRSTRIGGER_DEFAULT \\r
+{ \\r
+ false, /* Do not enable autoTX triggering. */ \\r
+ false, /* Do not enable receive triggering. */ \\r
+ false, /* Do not enable transmit triggering. */ \\r
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \\r
+}\r
#else\r
-#define USART_INITPRSTRIGGER_DEFAULT \\r
- { false, /* Do not enable receive triggering. */ \\r
- false, /* Do not enable transmit triggering. */ \\r
- usartPrsTriggerCh0 /* Set default channel to zero. */ \\r
- }\r
+#define USART_INITPRSTRIGGER_DEFAULT \\r
+{ \\r
+ false, /* Do not enable receive triggering. */ \\r
+ false, /* Do not enable transmit triggering. */ \\r
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \\r
+}\r
#endif\r
\r
/** Synchronous mode init structure. */\r
/** Clock polarity/phase mode. */\r
USART_ClockMode_TypeDef clockMode;\r
\r
-#if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )\r
+#if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)\r
/** Enable USART Rx via PRS. */\r
bool prsRxEnable;\r
\r
* If TX is empty, underflows are generated. */\r
bool autoTx;\r
#endif\r
+#if defined(_USART_TIMING_CSHOLD_MASK)\r
+ /** Auto CS enabling */\r
+ bool autoCsEnable;\r
+ /** Auto CS hold time in baud cycles */\r
+ uint8_t autoCsHold;\r
+ /** Auto CS setup time in baud cycles */\r
+ uint8_t autoCsSetup;\r
+#endif\r
} USART_InitSync_TypeDef;\r
\r
/** Default config for USART sync init structure. */\r
-#if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )\r
-#define USART_INITSYNC_DEFAULT \\r
- { usartEnable, /* Enable RX/TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 1000000, /* 1 Mbits/s. */ \\r
- usartDatabits8, /* 8 databits. */ \\r
- true, /* Master mode. */ \\r
- false, /* Send least significant bit first. */ \\r
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \\r
- false, /* Not USART PRS input mode. */ \\r
- usartPrsRxCh0, /* PRS channel 0. */ \\r
- false /* No AUTOTX mode. */ \\r
- }\r
+#if defined(_USART_TIMING_CSHOLD_MASK)\r
+#define USART_INITSYNC_DEFAULT \\r
+{ \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 1000000, /* 1 Mbits/s. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ true, /* Master mode. */ \\r
+ false, /* Send least significant bit first. */ \\r
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \\r
+ false, /* Not USART PRS input mode. */ \\r
+ usartPrsRxCh0, /* PRS channel 0. */ \\r
+ false, /* No AUTOTX mode. */ \\r
+ false, /* No AUTOCS mode */ \\r
+ 0, /* Auto CS Hold cycles */ \\r
+ 0 /* Auto CS Setup cycles */ \\r
+}\r
+#elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)\r
+#define USART_INITSYNC_DEFAULT \\r
+{ \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 1000000, /* 1 Mbits/s. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ true, /* Master mode. */ \\r
+ false, /* Send least significant bit first. */ \\r
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \\r
+ false, /* Not USART PRS input mode. */ \\r
+ usartPrsRxCh0, /* PRS channel 0. */ \\r
+ false /* No AUTOTX mode. */ \\r
+}\r
#else\r
-#define USART_INITSYNC_DEFAULT \\r
- { usartEnable, /* Enable RX/TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 1000000, /* 1 Mbits/s. */ \\r
- usartDatabits8, /* 8 databits. */ \\r
- true, /* Master mode. */ \\r
- false, /* Send least significant bit first. */ \\r
- usartClockMode0 /* Clock idle low, sample on rising edge. */ \\r
- }\r
+#define USART_INITSYNC_DEFAULT \\r
+{ \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 1000000, /* 1 Mbits/s. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ true, /* Master mode. */ \\r
+ false, /* Send least significant bit first. */ \\r
+ usartClockMode0 /* Clock idle low, sample on rising edge. */ \\r
+}\r
#endif\r
\r
\r
\r
\r
/** Default config for IrDA mode init structure. */\r
-#define USART_INITIRDA_DEFAULT \\r
- { \\r
- { usartEnable, /* Enable RX/TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 115200, /* 115200 bits/s. */ \\r
- usartOVS16, /* 16x oversampling. */ \\r
- usartDatabits8, /* 8 databits. */ \\r
- usartEvenParity, /* Even parity. */ \\r
- usartStopbits1 /* 1 stopbit. */ \\r
- }, \\r
- false, /* Rx invert disabled. */ \\r
- false, /* Filtering disabled. */ \\r
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \\r
- false, /* Routing to PRS is disabled. */ \\r
- usartIrDAPrsCh0 /* PRS channel 0. */ \\r
- }\r
-\r
-\r
-#if defined( _USART_I2SCTRL_MASK )\r
+#define USART_INITIRDA_DEFAULT \\r
+{ \\r
+ { \\r
+ usartEnable, /* Enable RX/TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 115200, /* 115200 bits/s. */ \\r
+ usartOVS16, /* 16x oversampling. */ \\r
+ usartDatabits8, /* 8 databits. */ \\r
+ usartEvenParity, /* Even parity. */ \\r
+ usartStopbits1 /* 1 stopbit. */ \\r
+ }, \\r
+ false, /* Rx invert disabled. */ \\r
+ false, /* Filtering disabled. */ \\r
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \\r
+ false, /* Routing to PRS is disabled. */ \\r
+ usartIrDAPrsCh0 /* PRS channel 0. */ \\r
+}\r
+\r
+\r
+#if defined(_USART_I2SCTRL_MASK)\r
/** I2S mode init structure. Inherited from synchronous mode init structure */\r
typedef struct\r
{\r
\r
\r
/** Default config for I2S mode init structure. */\r
-#define USART_INITI2S_DEFAULT \\r
- { \\r
- { usartEnableTx, /* Enable TX when init completed. */ \\r
- 0, /* Use current configured reference clock for configuring baudrate. */ \\r
- 1000000, /* Baudrate 1M bits/s. */ \\r
- usartDatabits16, /* 16 databits. */ \\r
- true, /* Operate as I2S master. */ \\r
- true, /* Most significant bit first. */ \\r
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \\r
- false, /* Don't enable USARTRx via PRS. */ \\r
- usartPrsRxCh0, /* PRS channel selection (dummy). */ \\r
- false /* Disable AUTOTX mode. */ \\r
- }, \\r
- usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \\r
- true, /* Delay on I2S data. */ \\r
- false, /* No DMA split. */ \\r
- usartI2sJustifyLeft, /* Data is left-justified within the frame */ \\r
- false /* Stereo mode. */ \\r
- }\r
+#define USART_INITI2S_DEFAULT \\r
+{ \\r
+ { \\r
+ usartEnableTx, /* Enable TX when init completed. */ \\r
+ 0, /* Use current configured reference clock for configuring baudrate. */ \\r
+ 1000000, /* Baudrate 1M bits/s. */ \\r
+ usartDatabits16, /* 16 databits. */ \\r
+ true, /* Operate as I2S master. */ \\r
+ true, /* Most significant bit first. */ \\r
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \\r
+ false, /* Don't enable USARTRx via PRS. */ \\r
+ usartPrsRxCh0, /* PRS channel selection (dummy). */ \\r
+ false /* Disable AUTOTX mode. */ \\r
+ }, \\r
+ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \\r
+ true, /* Delay on I2S data. */ \\r
+ false, /* No DMA split. */ \\r
+ usartI2sJustifyLeft, /* Data is left-justified within the frame */ \\r
+ false /* Stereo mode. */ \\r
+}\r
#endif\r
\r
/*******************************************************************************\r
\r
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);\r
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);\r
-#if defined(USART0) || ( (USART_COUNT == 1) && defined( USART1 ) )\r
+#if defined(USART0) || ((USART_COUNT == 1) && defined(USART1))\r
void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);\r
#endif\r
\r
-#if defined( _USART_I2SCTRL_MASK )\r
+#if defined(_USART_I2SCTRL_MASK)\r
void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);\r
#endif\r
void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);\r
******************************************************************************/\r
__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)\r
{\r
- usart->IEN &= ~(flags);\r
+ usart->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)\r
{\r
- uint32_t tmp;\r
+ uint32_t ien;\r
\r
/* Store USARTx->IEN in temporary variable in order to define explicit order\r
* of volatile accesses. */\r
- tmp = usart->IEN;\r
+ ien = usart->IEN;\r
\r
/* Bitwise AND of pending and enabled interrupts */\r
- return usart->IF & tmp;\r
+ return usart->IF & ien;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)\r
{\r
- return (uint8_t) (usart->RXDATA);\r
+ return (uint8_t)usart->RXDATA;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)\r
{\r
- return (uint16_t) (usart->RXDOUBLE);\r
+ return (uint16_t)usart->RXDOUBLE;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)\r
{\r
- return (uint16_t) (usart->RXDATAX);\r
+ return (uint16_t)usart->RXDATAX;\r
}\r
\r
uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);\r
#endif\r
\r
#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_USART_H_ */\r
+#endif /* __SILICON_LABS_EM_USART_H__ */\r
/***************************************************************************//**\r
* @file em_vcmp.h\r
* @brief Voltage Comparator (VCMP) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_VCMP_H_\r
-#define __SILICON_LABS_EM_VCMP_H_\r
+#ifndef __SILICON_LABS_EM_VCMP_H__\r
+#define __SILICON_LABS_EM_VCMP_H__\r
\r
#include "em_device.h"\r
#if defined(VCMP_COUNT) && (VCMP_COUNT > 0)\r
} VCMP_Init_TypeDef;\r
\r
/** Default VCMP initialization structure */\r
-#define VCMP_INIT_DEFAULT \\r
- { true, /** Half Bias enabled */ \\r
- 0x7, /** Bias curernt 0.7 uA when half bias enabled */ \\r
- false, /** Falling edge sense not enabled */ \\r
- false, /** Rising edge sense not enabled */ \\r
- vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */ \\r
- vcmpHystNone, /** No hysteresis */ \\r
- 0, /** 0 in digital ouput when inactive */ \\r
- true, /** Do not use low power reference */ \\r
- 39, /** Trigger level just below 3V */ \\r
- true, /** Enable after init */ \\r
- }\r
+#define VCMP_INIT_DEFAULT \\r
+{ \\r
+ true, /** Half Bias enabled */ \\r
+ 0x7, /** Bias curernt 0.7 uA when half bias enabled */ \\r
+ false, /** Falling edge sense not enabled */ \\r
+ false, /** Rising edge sense not enabled */ \\r
+ vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */ \\r
+ vcmpHystNone, /** No hysteresis */ \\r
+ 0, /** 0 in digital ouput when inactive */ \\r
+ true, /** Do not use low power reference */ \\r
+ 39, /** Trigger level just below 3V */ \\r
+ true, /** Enable after init */ \\r
+}\r
\r
/*******************************************************************************\r
***************************** PROTOTYPES **********************************\r
******************************************************************************/\r
+\r
void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit);\r
void VCMP_LowPowerRefSet(bool enable);\r
void VCMP_TriggerSet(int level);\r
\r
-__STATIC_INLINE void VCMP_Enable(void);\r
-__STATIC_INLINE void VCMP_Disable(void);\r
-__STATIC_INLINE uint32_t VCMP_VoltageToLevel(float v);\r
-__STATIC_INLINE bool VCMP_VDDLower(void);\r
-__STATIC_INLINE bool VCMP_VDDHigher(void);\r
-__STATIC_INLINE bool VCMP_Ready(void);\r
-__STATIC_INLINE void VCMP_IntClear(uint32_t flags);\r
-__STATIC_INLINE void VCMP_IntSet(uint32_t flags);\r
-__STATIC_INLINE void VCMP_IntDisable(uint32_t flags);\r
-__STATIC_INLINE void VCMP_IntEnable(uint32_t flags);\r
-__STATIC_INLINE uint32_t VCMP_IntGet(void);\r
-__STATIC_INLINE uint32_t VCMP_IntGetEnabled(void);\r
-\r
/***************************************************************************//**\r
* @brief\r
* Enable Voltage Comparator\r
******************************************************************************/\r
__STATIC_INLINE void VCMP_Disable(void)\r
{\r
- VCMP->CTRL &= ~(VCMP_CTRL_EN);\r
+ VCMP->CTRL &= ~VCMP_CTRL_EN;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE void VCMP_IntDisable(uint32_t flags)\r
{\r
- VCMP->IEN &= ~(flags);\r
+ VCMP->IEN &= ~flags;\r
}\r
\r
\r
******************************************************************************/\r
__STATIC_INLINE uint32_t VCMP_IntGet(void)\r
{\r
- return(VCMP->IF);\r
+ return VCMP->IF;\r
}\r
\r
\r
#endif\r
\r
#endif /* defined(VCMP_COUNT) && (VCMP_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_VCMP_H_ */\r
+#endif /* __SILICON_LABS_EM_VCMP_H__ */\r
/***************************************************************************//**\r
* @file em_version.h\r
* @brief Assign correct part number for include file\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
*\r
******************************************************************************/\r
\r
-\r
-#ifndef __SILICON_LABS_EM_VERSION_H_\r
-#define __SILICON_LABS_EM_VERSION_H_\r
+#ifndef __SILICON_LABS_EM_VERSION_H__\r
+#define __SILICON_LABS_EM_VERSION_H__\r
\r
#include "em_device.h"\r
\r
******************************************************************************/\r
\r
/***************************************************************************//**\r
- * @addtogroup Version\r
+ * @addtogroup VERSION\r
* @{\r
******************************************************************************/\r
\r
/** Version number of emlib peripheral API. */\r
-#define _EMLIB_VERSION 4.0.0\r
+#define _EMLIB_VERSION 4.2.1\r
\r
/** Major version of emlib. Bumped when incompatible API changes introduced. */\r
#define _EMLIB_VERSION_MAJOR 4\r
\r
/** Minor version of emlib. Bumped when functionality is added in a backwards-\r
compatible manner. */\r
-#define _EMLIB_VERSION_MINOR 0\r
+#define _EMLIB_VERSION_MINOR 2\r
\r
/** Patch revision of emlib. Bumped when adding backwards-compatible bug\r
fixes.*/\r
-#define _EMLIB_VERSION_PATCH 0\r
+#define _EMLIB_VERSION_PATCH 1\r
\r
\r
/** Version number of targeted CMSIS package. */\r
}\r
#endif\r
\r
-#endif /* __SILICON_LABS_EM_VERSION_H_ */\r
+#endif /* __SILICON_LABS_EM_VERSION_H__ */\r
/***************************************************************************//**\r
* @file em_wdog.h\r
* @brief Watchdog (WDOG) peripheral API\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
*******************************************************************************\r
* @section License\r
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
*******************************************************************************\r
*\r
* Permission is granted to anyone to use this software for any purpose,\r
******************************************************************************/\r
\r
\r
-#ifndef __SILICON_LABS_EM_WDOG_H_\r
-#define __SILICON_LABS_EM_WDOG_H_\r
+#ifndef __SILICON_LABS_EM_WDOG_H__\r
+#define __SILICON_LABS_EM_WDOG_H__\r
\r
#include "em_device.h"\r
#if defined(WDOG_COUNT) && (WDOG_COUNT > 0)\r
} WDOG_Init_TypeDef;\r
\r
/** Suggested default config for WDOG init structure. */\r
-#define WDOG_INIT_DEFAULT \\r
- { true, /* Start watchdog when init done */ \\r
- false, /* WDOG not counting during debug halt */ \\r
- false, /* WDOG not counting when in EM2 */ \\r
- false, /* WDOG not counting when in EM3 */ \\r
- false, /* EM4 can be entered */ \\r
- false, /* Do not block disabling LFRCO/LFXO in CMU */ \\r
- false, /* Do not lock WDOG configuration (if locked, reset needed to unlock) */ \\r
- wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \\r
- wdogPeriod_256k /* Set longest possible timeout period */ \\r
- }\r
+#define WDOG_INIT_DEFAULT \\r
+{ \\r
+ true, /* Start watchdog when init done */ \\r
+ false, /* WDOG not counting during debug halt */ \\r
+ false, /* WDOG not counting when in EM2 */ \\r
+ false, /* WDOG not counting when in EM3 */ \\r
+ false, /* EM4 can be entered */ \\r
+ false, /* Do not block disabling LFRCO/LFXO in CMU */ \\r
+ false, /* Do not lock WDOG configuration (if locked, reset needed to unlock) */ \\r
+ wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \\r
+ wdogPeriod_256k /* Set longest possible timeout period */ \\r
+}\r
\r
\r
/*******************************************************************************\r
#endif\r
\r
#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */\r
-#endif /* __SILICON_LABS_EM_WDOG_H_ */\r
+#endif /* __SILICON_LABS_EM_WDOG_H__ */\r
--- /dev/null
+================ Revision history ============================================\r
+4.2.1:\r
+ - Fixed armgcc makefiles for mbedtls examples.\r
+\r
+4.2.0:\r
+ - Added prs example.\r
+ - Added examples for mbedtls on Pearl, namely mbedtls_aescrypt and\r
+ mbedtls_ecdsa.\r
+\r
+4.1.1:\r
+ - No changes.\r
+\r
+4.1.0:\r
+ - Initial version.\r
--- /dev/null
+====== Kit Examples ======\r
+\r
+This package include examples for the SLSTK3401A development\r
+kit from Silicon Labs.\r
+\r
+====== Dependencies ======\r
+\r
+This package _requires_ the EM_BSP_COMMON and EFM32 CMSIS packages to be\r
+installed at the same level as this package. If you did not get this as part\r
+of the Simplicity Studio application, you should also download and install the\r
+EFM32 CMSIS package. See the Changes file for required version.\r
+\r
+The CMSIS package requires C99 support, and so does this package.\r
+\r
+====== File structure ======\r
+\r
+kits/SLSTK3401A/config\r
+ Configuration data for BSP and Drivers in EM_BSP_COMMON.\r
+\r
+kits/SLSTK3401A/examples\r
+ Several example projects demonstrating various capabilities of the\r
+ mcu.\r
+ Project files for various IDEs/compilers are in subdirectories of\r
+ each example. Use these as a starting point for your own development\r
+ and prototyping of SLSTK3401A software.\r
+\r
+====== Updates ======\r
+\r
+Silicon Labs continually works to provide updated and improved example code,\r
+header files and other software of use for our customers. Please check\r
+\r
+http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit\r
+\r
+for the latest releases.\r
+\r
+====== License ======\r
+\r
+License information for use of the source code is given at the top of\r
+all C files.\r
+\r
+(C) Copyright Silicon Laboratories Inc. 2014. All rights reserved.\r
--- /dev/null
+END-USER LICENSE AGREEMENT\r
+IMPORTANT: READ CAREFULLY\r
+BEFORE AGREEING TO TERMS\r
+\r
+THIS PRODUCT CONTAINS CERTAIN COMPUTER PROGRAMS AND OTHER THIRD PARTY\r
+PROPRIETARY MATERIAL ("LICENSED PRODUCT"), THE USE OF WHICH IS SUBJECT TO THIS\r
+END-USER LICENSE AGREEMENT. INDICATING YOUR AGREEMENT CONSTITUTES YOUR AND\r
+(IF APPLICABLE) YOUR COMPANY'S ASSENT TO AND ACCEPTANCE OF THIS END-USER LICENSE\r
+AGREEMENT (THE "LICENSE" OR "AGREEMENT"). IF YOU DO NOT AGREE WITH ALL OF THE\r
+TERMS, YOU MUST NOT USE THIS PRODUCT. WRITTEN APPROVAL IS NOT A PREREQUISITE TO\r
+THE VALIDITY OR ENFORCEABILITY OF THIS AGREEMENT, AND NO SOLICITATION OF SUCH\r
+WRITTEN APPROVAL BY OR ON BEHALF OF SILICON LABORATORIES, INC. ("SILICON LABS")\r
+SHALL BE CONSTRUED AS AN INFERENCE TO THE CONTRARY. IF THESE TERMS ARE\r
+CONSIDERED AN OFFER BY SILICON LABS, ACCEPTANCE IS EXPRESSLY LIMITED TO THESE\r
+TERMS.\r
+\r
+LICENSE AND WARRANTY: The Licensed Product and the embedded Software which is\r
+made the subject of this License is either the property of SILICON LABS or a\r
+third party from whom SILICON LABS has the authorization to distribute to you\r
+subject to the terms of this Agreement. This Licensed Product is protected by\r
+state, federal, and international copyright law. Although SILICON LABS continues\r
+to own the Licensed Product and the right to distribute the embedded third party\r
+Software, you will have certain rights to use the Licensed Product and the\r
+embedded Software after your acceptance of this License. Except as may be\r
+modified by a license addendum which accompanies this License, your rights and\r
+obligations with respect to the use of this Product and the embedded software\r
+are as follows:\r
+\r
+1. AS APPROPRIATE WITH RESPECT TO THE LICENSED PRODUCT, YOU MAY: Use, copy,\r
+ distribute and make derivative works of the Software for any purpose,\r
+ including commercial applications, subject to the following restrictions:\r
+ (i) The origin of this software must not be misrepresented; (ii) you must\r
+ not claim that you wrote the original software; (iii) altered source\r
+ versions must be plainly marked as such, and must not be misrepresented as\r
+ being the original software; and (iv) any notices contained in the Software\r
+ may not be removed or altered, including notices in source code versions.\r
+\r
+2. YOU MAY NOT: (A) Sublicense, assign, rent or lease any portion of the\r
+ Licensed Product or the embedded Software; or (B) Remove any product\r
+ identification, copyright or other notices that appear on the Licensed\r
+ Product or embedded Software.\r
+\r
+3. Limited Use: Use of any of the Software is strictly limited to use in\r
+ systems containing one or more SILICON LABS products when the Software is\r
+ enabled to be functional. Any unauthorized use is expressly prohibited and\r
+ will constitute a breach of this Agreement.\r
+\r
+4. Warranty: SILICON LABS does not warrant that the Licensed Product or\r
+ embedded Software will meet your requirements or that operation of the\r
+ Licensed Product will be uninterrupted or that the embedded Software will be\r
+ error-free. You agree that the Licensed Product is provided "AS IS" and\r
+ that SILICON LABS makes no warranty as to the Licensed Product or embedded\r
+ Software. SILICON LABS DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,\r
+ INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY,\r
+ FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, RELATED TO THE\r
+ SOFTWARE, ITS USE OR ANY INABILITY TO USE IT, THE RESULTS OF ITS USE AND\r
+ THIS AGREEMENT.\r
+\r
+ YOU MAY HAVE OTHER RIGHTS, WHICH VARY FROM STATE TO STATE.\r
+\r
+5. Disclaimer of Damages: IN NO EVENT WILL SILICON LABS BE LIABLE TO YOU FOR\r
+ ANY SPECIAL, CONSEQUENTIAL, INDIRECT, OR SIMILAR DAMAGES, INCLUDING ANY LOST\r
+ PROFITS OR LOST DATA ARISING OUT OF THE USE OR INABILITY TO USE THE LICENSED\r
+ PRODUCT EVEN IF SILICON LABS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH\r
+ DAMAGES.\r
+\r
+ SOME STATES DO NOT ALLOW THE LIMITATION OR EXCLUSION OF LIABILITY FOR\r
+ INCIDENTAL OR CONSEQUENTIAL DAMAGES. SO THE ABOVE LIMITATION OR EXCLUSION\r
+ MAY NOT APPLY TO YOU.\r
+\r
+ IN NO CASE SHALL SILICON LABS' LIABILITY EXCEED THE PURCHASE PRICE FOR THE\r
+ LICENSED PRODUCT. The disclaimers and limitations set forth above will\r
+ apply regardless of whether you accept the Licensed Software.\r
+\r
+6. Term and Termination: The term of this Agreement and the License granted\r
+ herein shall begin upon use of the Licensed Product and continue in\r
+ perpetuity unless you breach any of the obligations set out under this\r
+ Agreement. Upon your breach of this Agreement by you, the license granted\r
+ hereunder shall terminate immediately and you shall cease all use of the\r
+ Licensed Products and return same as well as any copies of the Licensed\r
+ Product and/or embedded Software to SILICON LABS immediately. Termination\r
+ of this License upon your breach is only one remedy available to SILICON\r
+ LABS. In addition to termination of this Agreement upon your breach,\r
+ SILICON LABS shall be entitled to seek any and all other available remedies,\r
+ at law or at equity, arising from your breach.\r
+\r
+7. Export: You shall comply with all applicable federal, provincial, state and\r
+ local laws, regulations and ordinances including but not limited to\r
+ applicable U.S. Export Administration Laws and Regulations. You shall not\r
+ export or re-export, or allow the export or re-export of the Licensed\r
+ Product, any component of the Licensed Product, or any copy of the embedded\r
+ Software in violation of any such restrictions, laws or regulations, or to\r
+ Cuba, Libya, North Korea, Iran, Iraq, or Rwanda or to any Group D:1 or E:2\r
+ country (or any national of such country) specified in the then current\r
+ Supplement No. 1 to Part 740, or, in violation of the embargo provisions in\r
+ Part 746, of the U.S. Export Administration Regulations (or any successor\r
+ regulations or supplement), except in compliance with and with all licenses\r
+ and approvals required under applicable export laws and regulations,\r
+ including without limitation, those of the U.S. Department of Commerce.\r
+\r
+8. General: This Agreement will be governed by the laws of the State of Texas\r
+ and any applicable federal laws or regulations. The waiver by either Party\r
+ of any default or breach of this Agreement shall not constitute a waiver of\r
+ any other or subsequent default or breach. This Agreement constitutes the\r
+ complete and exclusive statement of the mutual understanding between you and\r
+ SILICON LABS with respect to this subject matter herein. This Agreement may\r
+ only be modified by a written addendum, which has been signed by both you\r
+ and SILICON LABS. Should you have any questions concerning this Agreement,\r
+ or if you desire to contact SILICON LABS for any reason, please write:\r
+\r
+Silicon Laboratories, Inc.\r
+400 West Cesar Chavez\r
+Austin, Texas 78701, U.S.A.\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief Provide BSP (board support package) configuration parameters.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_BSPCONFIG_H__\r
+#define __SILICON_LABS_BSPCONFIG_H__\r
+\r
+#define BSP_STK\r
+#define BSP_STK_BRD2500\r
+\r
+#define BSP_BCC_USART USART0\r
+#define BSP_BCC_CLK cmuClock_USART0\r
+#define BSP_BCC_TX_LOCATION USART_ROUTELOC0_TXLOC_LOC0\r
+#define BSP_BCC_RX_LOCATION USART_ROUTELOC0_RXLOC_LOC0\r
+#define BSP_BCC_TXPORT gpioPortA\r
+#define BSP_BCC_TXPIN 0\r
+#define BSP_BCC_RXPORT gpioPortA\r
+#define BSP_BCC_RXPIN 1\r
+#define BSP_BCC_ENABLE_PORT gpioPortA\r
+#define BSP_BCC_ENABLE_PIN 5 /* VCOM_ENABLE */\r
+\r
+#define BSP_DISP_ENABLE_PORT gpioPortD\r
+#define BSP_DISP_ENABLE_PIN 15 /* MemLCD display enable */\r
+\r
+#define BSP_GPIO_LEDS\r
+#define BSP_NO_OF_LEDS 2\r
+#define BSP_GPIO_LEDARRAY_INIT {{gpioPortF,4},{gpioPortF,5}}\r
+\r
+#define BSP_GPIO_BUTTONS\r
+#define BSP_NO_OF_BUTTONS 2\r
+#define BSP_GPIO_PB0_PORT gpioPortF\r
+#define BSP_GPIO_PB0_PIN 6\r
+#define BSP_GPIO_PB1_PORT gpioPortF\r
+#define BSP_GPIO_PB1_PIN 7\r
+\r
+#define BSP_GPIO_BUTTONARRAY_INIT {{BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN}, {BSP_GPIO_PB1_PORT, BSP_GPIO_PB1_PIN}}\r
+\r
+#define BSP_INIT_DEFAULT 0\r
+\r
+#if !defined( EMU_DCDCINIT_STK_DEFAULT )\r
+/* Use emlib defaults */\r
+#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT\r
+#endif\r
+\r
+#if !defined(CMU_HFXOINIT_STK_DEFAULT)\r
+#define CMU_HFXOINIT_STK_DEFAULT \\r
+{ \\r
+ true, /* Low-power mode for EFM32 */ \\r
+ false, /* Disable auto-start on EM0/1 entry */ \\r
+ false, /* Disable auto-select on EM0/1 entry */ \\r
+ false, /* Disable auto-start and select on RAC wakeup */ \\r
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \\r
+ 0x142, /* Steady-state CTUNE for STK boards without load caps */ \\r
+ _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT, \\r
+ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \\r
+ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \\r
+ 0x7, /* Recommended steady-state osc core bias current */ \\r
+ 0x6, /* Recommended peak detection threshold */ \\r
+ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \\r
+ 0xA, /* Recommended peak detection timeout */ \\r
+ _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT, \\r
+ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \\r
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \\r
+}\r
+#endif\r
+\r
+#define BSP_BCP_VERSION 2\r
+#include "bsp_bcp.h"\r
+\r
+#endif /* __SILICON_LABS_BSPCONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief capsense configuration parameters.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_CAPSENSCONFIG_H__\r
+#define __SILICON_LABS_CAPSENSCONFIG_H__\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Use ACMP0 module for capsense */\r
+#define ACMP_CAPSENSE ACMP0\r
+#define ACMP_CAPSENSE_CMUCLOCK cmuClock_ACMP0\r
+#define PRS_CH_CTRL_SOURCESEL_ACMP_CAPSENSE PRS_CH_CTRL_SOURCESEL_ACMP0\r
+#define PRS_CH_CTRL_SIGSEL_ACMPOUT_CAPSENSE PRS_CH_CTRL_SIGSEL_ACMP0OUT\r
+\r
+/* On the SLSTK3401A the touch buttons are connected to PB11 and PB12.\r
+ *\r
+ * Pin | APORT Channel (for ACMP0)\r
+ * -------------------------\r
+ * PB11 | APORT4XCH27\r
+ * PB12 | APORT3XCH28\r
+ *\r
+ */\r
+#define CAPSENSE_CHANNELS { acmpInputAPORT4XCH27, acmpInputAPORT3XCH28 }\r
+#define BUTTON0_CHANNEL 0 /**< Button 0 channel */\r
+#define BUTTON1_CHANNEL 1 /**< Button 1 channel */\r
+#define ACMP_CHANNELS 2 /**< Number of channels in use for capsense */\r
+#define NUM_SLIDER_CHANNELS 0 /**< The kit does not have a slider */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* __SILICON_LABS_CAPSENSCONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file displayconfig.h\r
+ * @brief Configuration file for DISPLAY device driver interface.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_DISPLAYCONFIG_H__\r
+#define __SILICON_LABS_DISPLAYCONFIG_H__\r
+\r
+/* Include the application specific configuration file. */\r
+#include "displayconfigapp.h"\r
+\r
+/* Include support for the SHARP Memory LCD model LS013B7DH03 */\r
+#define INCLUDE_DISPLAY_SHARP_LS013B7DH03\r
+\r
+#include "displayls013b7dh03config.h"\r
+#include "displayls013b7dh03.h"\r
+\r
+/**\r
+ * Maximum number of display devices the display module is configured\r
+ * to support. This number may be increased if the system includes more than\r
+ * one display device. However, the number should be kept low in order to\r
+ * save memory.\r
+ */\r
+#define DISPLAY_DEVICES_MAX (1)\r
+\r
+/**\r
+ * Geometry of display device #0 in the system. Display device #0 on this kit\r
+ * is the SHARP Memory LCD LS013B7DH03 which has 128x128 pixels.\r
+ * These defines can be used to declare static framebuffers in order to save\r
+ * extra memory consumed by malloc.\r
+ */\r
+#define DISPLAY0_WIDTH (LS013B7DH03_WIDTH)\r
+#define DISPLAY0_HEIGHT (LS013B7DH03_HEIGHT)\r
+\r
+\r
+/**\r
+ * Define all display device driver initialization functions here.\r
+ */\r
+#define DISPLAY_DEVICE_DRIVER_INIT_FUNCTIONS \\r
+ { \\r
+ DISPLAY_Ls013b7dh03Init, \\r
+ NULL \\r
+ }\r
+\r
+#endif /* __SILICON_LABS_DISPLAYCONFIG_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file displayls013b7dh03config.h\r
+ * @brief SLWSTK6100A_EFR32MG specific configuration for the display driver for\r
+ * the Sharp Memory LCD model LS013B7DH03.\r
+ * @version 4.2.1\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SILICON_LABS_DISPLAYLS013B7DH03CONFIG_H__\r
+#define __SILICON_LABS_DISPLAYLS013B7DH03CONFIG_H__\r
+\r
+#include "displayconfigapp.h"\r
+\r
+/* Display device name. */\r
+#define SHARP_MEMLCD_DEVICE_NAME "Sharp LS013B7DH03 #1"\r
+\r
+\r
+/* LCD and SPI GPIO pin connections on the SLSTK3401A kit. */\r
+#define LCD_PORT_SCLK (gpioPortC) /* EFM_DISP_SCLK on PC8 */\r
+#define LCD_PIN_SCLK (8)\r
+#define LCD_PORT_SI (gpioPortC) /* EFM_DISP_MOSI on PC6 */\r
+#define LCD_PIN_SI (6)\r
+#define LCD_PORT_SCS (gpioPortD) /* EFM_DISP_CS on PD14 */\r
+#define LCD_PIN_SCS (14)\r
+#define LCD_PORT_EXTCOMIN (gpioPortD) /* EFM_DISP_COM on PD13 */\r
+#define LCD_PIN_EXTCOMIN (13)\r
+#define LCD_PORT_DISP_PWR (gpioPortD) /* EFM_DISP_ENABLE on PD15 */\r
+#define LCD_PIN_DISP_PWR (15)\r
+\r
+/* PRS settings for polarity inversion extcomin auto toggle. */\r
+#define LCD_AUTO_TOGGLE_PRS_CH (4) /* PRS channel 4. */\r
+#define LCD_AUTO_TOGGLE_PRS_ROUTELOC() PRS->ROUTELOC1 = \\r
+ ((PRS->ROUTELOC1 & ~_PRS_ROUTELOC1_CH4LOC_MASK) | PRS_ROUTELOC1_CH4LOC_LOC4)\r
+#define LCD_AUTO_TOGGLE_PRS_ROUTEPEN PRS_ROUTEPEN_CH4PEN\r
+\r
+/*\r
+ * Select how LCD polarity inversion should be handled:\r
+ *\r
+ * If POLARITY_INVERSION_EXTCOMIN is defined, the EXTMODE pin is set to HIGH,\r
+ * and the polarity inversion is armed for every rising edge of the EXTCOMIN\r
+ * pin. The actual polarity inversion is triggered at the next transision of\r
+ * SCS. This mode is recommended because it causes less CPU and SPI load than\r
+ * the alternative mode, see below.\r
+ * If POLARITY_INVERSION_EXTCOMIN is undefined, the EXTMODE pin is set to LOW,\r
+ * and the polarity inversion is toggled by sending an SPI command. This mode\r
+ * causes more CPU and SPI load than using the EXTCOMIN pin mode.\r
+ */\r
+#define POLARITY_INVERSION_EXTCOMIN\r
+\r
+/* Define POLARITY_INVERSION_EXTCOMIN_PAL_AUTO_TOGGLE if you want the PAL\r
+ * (Platform Abstraction Layer interface) to automatically toggle the EXTCOMIN\r
+ * pin.\r
+ * If the PAL_TIMER_REPEAT function is defined the EXTCOMIN toggling is handled\r
+ * by a timer repeat system, therefore we must undefine\r
+ * POLARITY_INVERSION_EXTCOMIN_PAL_AUTO_TOGGLE;\r
+ */\r
+#ifndef PAL_TIMER_REPEAT_FUNCTION\r
+ #define POLARITY_INVERSION_EXTCOMIN_PAL_AUTO_TOGGLE\r
+#endif\r
+\r
+#endif /* __SILICON_LABS_DISPLAYLS013B7DH03CONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file displaypalconfig.h\r
+ * @brief Configuration file for PAL (Platform Abstraction Layer)\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_DISPLAYPALCONFIG_H__\r
+#define __SILICON_LABS_DISPLAYPALCONFIG_H__\r
+\r
+/*\r
+ * Select which oscillator should source the RTC clock.\r
+ */\r
+#undef PAL_RTCC_CLOCK_LFXO\r
+#define PAL_RTCC_CLOCK_LFRCO\r
+#undef PAL_RTCC_CLOCK_ULFRCO\r
+\r
+/*\r
+ * PAL SPI / USART configuration for the SLSTK3401A.\r
+ * Select which USART and location is connected to the device via SPI.\r
+ */\r
+#define PAL_SPI_USART_UNIT (USART1)\r
+#define PAL_SPI_USART_CLOCK (cmuClock_USART1)\r
+#define PAL_SPI_USART_LOCATION_TX (11)\r
+#define PAL_SPI_USART_LOCATION_SCLK (11)\r
+\r
+/*\r
+ * Specify the SPI baud rate:\r
+ */\r
+#define PAL_SPI_BAUDRATE (3500000) /* Max baudrate on EFM32PG. */\r
+\r
+/*\r
+ * On the SLSTK3401A, we can toggle some GPIO pins with hw only,\r
+ * especially the GPIO port D pin 13 signal which is connected to the\r
+ * polarity inversion (EXTCOMIN) pin on the Sharp Memory LCD. By defining\r
+ * INCLUDE_PAL_GPIO_PIN_AUTO_TOGGLE_HW_ONLY the toggling of EXTCOMIN will\r
+ * be handled by hardware, without software intervention, which saves power.\r
+ */\r
+#define INCLUDE_PAL_GPIO_PIN_AUTO_TOGGLE_HW_ONLY\r
+\r
+\r
+#endif /* __SILICON_LABS_DISPLAYPALCONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief Provide configuration parameters for EM4 wakeup button.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_EM4CONFIG_H__\r
+#define __SILICON_LABS_EM4CONFIG_H__\r
+\r
+#include "bspconfig.h"\r
+\r
+#define EM4_WU_PB PB1\r
+#define EM4_WU_PB_EN (1 << 17) /* GPIO_EM4WU1 = PF7 = pushbutton 1 */\r
+#define EM4_WU_PB_PIN BSP_GPIO_PB1_PIN\r
+#define EM4_WU_PB_PORT BSP_GPIO_PB1_PORT\r
+#define EM4_WU_PB_STR "PB1"\r
+\r
+#define EM4_NON_WU_PB PB0\r
+#define EM4_NON_WU_PB_PIN BSP_GPIO_PB0_PIN\r
+#define EM4_NON_WU_PB_PORT BSP_GPIO_PB0_PORT\r
+#define EM4_NON_WU_PB_STR "PB0"\r
+\r
+#endif /* __SILICON_LABS_EM4CONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file i2cspmconfig.h\r
+ * @brief I2CSPM driver configuration file\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_I2CSPMCONFIG_H__\r
+#define __SILICON_LABS_I2CSPMCONFIG_H__\r
+\r
+/***************************************************************************//**\r
+ * @addtogroup Drivers\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+ /***************************************************************************//**\r
+ * @addtogroup I2CSPM\r
+ * @{\r
+ ******************************************************************************/\r
+\r
+/* I2C SPM driver config. This default override only works if one I2C interface\r
+ is in use. If multiple interfaces are in use, define the peripheral setup\r
+ inside the application in a I2CSPM_Init_TypeDef and then pass the initialization\r
+ struct to I2CSPM_Init(). */\r
+#define I2CSPM_INIT_DEFAULT \\r
+ { I2C0, /* Use I2C instance 0 */ \\r
+ gpioPortC, /* SCL port */ \\r
+ 11, /* SCL pin */ \\r
+ gpioPortC, /* SDA port */ \\r
+ 10, /* SDA pin */ \\r
+ 15, /* Location of SCL */ \\r
+ 15, /* Location of SDA */ \\r
+ 0, /* Use currently configured reference clock */ \\r
+ I2C_FREQ_STANDARD_MAX, /* Set to standard rate */ \\r
+ i2cClockHLRStandard, /* Set to use 4:4 low/high duty cycle */ \\r
+ }\r
+\r
+#define I2CSPM_TRANSFER_TIMEOUT 300000\r
+\r
+/** @} (end addtogroup I2CSPM) */\r
+/** @} (end addtogroup Drivers) */\r
+\r
+#endif /* __SILICON_LABS_I2CSPMCONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief Provide stdio retargeting configuration parameters.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_RETARGETSERIALCONFIG_H__\r
+#define __SILICON_LABS_RETARGETSERIALCONFIG_H__\r
+\r
+#include "bsp.h"\r
+\r
+/***************************************************************************//**\r
+ *\r
+ * When retargeting serial output the user can choose which peripheral\r
+ * to use as the serial output device. This choice is made by configuring\r
+ * one or more of the following defines: RETARGET_USART0, RETARGET_LEUART0, \r
+ * RETARGET_VCOM.\r
+ *\r
+ * This table shows the supported configurations and the resulting serial\r
+ * output device.\r
+ *\r
+ * +----------------------------------------------------------------------+\r
+ * | Defines | Serial Output (Locations) |\r
+ * |----------------------------------------------------------------------+\r
+ * | None | USART0 (Rx #0, Tx #0) |\r
+ * | RETARGET_USART0 | USART0 (Rx #0, Tx #0) |\r
+ * | RETARGET_VCOM | VCOM using USART0 |\r
+ * | RETARGET_LEUART0 | LEUART0 (Rx #0, Tx #0) |\r
+ * | RETARGET_LEUART0 and RETARGET_VCOM | VCOM using LEUART0 |\r
+ * +----------------------------------------------------------------------+\r
+ *\r
+ * Note that the default configuration is the same as RETARGET_USART0.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#if !defined(RETARGET_USART0) && \\r
+ !defined(RETARGET_LEUART0)\r
+#define RETARGET_USART0 /* Use USART0 by default. */\r
+#endif\r
+\r
+#if defined(RETARGET_USART0)\r
+ #define RETARGET_IRQ_NAME USART0_RX_IRQHandler /* UART IRQ Handler */\r
+ #define RETARGET_CLK cmuClock_USART0 /* HFPER Clock */\r
+ #define RETARGET_IRQn USART0_RX_IRQn /* IRQ number */\r
+ #define RETARGET_UART USART0 /* UART instance */\r
+ #define RETARGET_TX USART_Tx /* Set TX to USART_Tx */\r
+ #define RETARGET_RX USART_Rx /* Set RX to USART_Rx */\r
+ #define RETARGET_TX_LOCATION _USART_ROUTELOC0_TXLOC_LOC0 /* Location of of USART TX pin */\r
+ #define RETARGET_RX_LOCATION _USART_ROUTELOC0_RXLOC_LOC0 /* Location of of USART RX pin */\r
+ #define RETARGET_TXPORT gpioPortA /* UART transmission port */\r
+ #define RETARGET_TXPIN 0 /* UART transmission pin */\r
+ #define RETARGET_RXPORT gpioPortA /* UART reception port */\r
+ #define RETARGET_RXPIN 1 /* UART reception pin */\r
+ #define RETARGET_USART 1 /* Includes em_usart.h */\r
+\r
+#elif defined(RETARGET_LEUART0)\r
+ #define RETARGET_IRQ_NAME LEUART0_IRQHandler /* LEUART IRQ Handler */\r
+ #define RETARGET_CLK cmuClock_LEUART0 /* HFPER Clock */\r
+ #define RETARGET_IRQn LEUART0_IRQn /* IRQ number */\r
+ #define RETARGET_UART LEUART0 /* LEUART instance */\r
+ #define RETARGET_TX LEUART_Tx /* Set TX to LEUART_Tx */\r
+ #define RETARGET_RX LEUART_Rx /* Set RX to LEUART_Rx */\r
+ #define RETARGET_TX_LOCATION _LEUART_ROUTELOC0_TXLOC_LOC0 /* Location of of LEUART TX pin */\r
+ #define RETARGET_RX_LOCATION _LEUART_ROUTELOC0_RXLOC_LOC0 /* Location of of LEUART RX pin */\r
+ #define RETARGET_TXPORT gpioPortA /* LEUART transmission port */\r
+ #define RETARGET_TXPIN 0 /* LEUART transmission pin */\r
+ #define RETARGET_RXPORT gpioPortA /* LEUART reception port */\r
+ #define RETARGET_RXPIN 1 /* LEUART reception pin */\r
+ #define RETARGET_LEUART 1 /* Includes em_leuart.h */\r
+\r
+#else\r
+#error "Illegal USART selection."\r
+#endif\r
+ \r
+#if defined(RETARGET_VCOM)\r
+ #define RETARGET_PERIPHERAL_ENABLE() \\r
+ GPIO_PinModeSet(BSP_BCC_ENABLE_PORT, \\r
+ BSP_BCC_ENABLE_PIN, \\r
+ gpioModePushPull, \\r
+ 1);\r
+#else\r
+ #define RETARGET_PERIPHERAL_ENABLE()\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file retargettextdisplayconfig.h\r
+ * @brief Configuration file for stdio text display retarget module.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_RETARGETTEXTDISPLAYCONFIG_H__\r
+#define __SILICON_LABS_RETARGETTEXTDISPLAYCONFIG_H__\r
+\r
+/* Display number to retarget stdout to. */\r
+#define RETARGETTEXTDISPLAY_DISPLAY_NO (0)\r
+\r
+#endif /* __SILICON_LABS_RETARGETTEXTDISPLAYCONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file textdisplayconfig.h\r
+ * @brief Configuration file for textdisplay module.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_TEXTDISPLAYCONFIG_H__\r
+#define __SILICON_LABS_TEXTDISPLAYCONFIG_H__\r
+\r
+/* Include display configuration files here because the textdisplay\r
+ configuration depends on the display configuration. */\r
+#include "displayconfig.h"\r
+#include "displayconfigapp.h"\r
+\r
+/**\r
+ * Maximum number of text display devices the display module is configured\r
+ * to support. This number may be increased if the system includes more than\r
+ * one display device. However, the number should be kept low in order to\r
+ * save memory.\r
+ */\r
+#define TEXTDISPLAY_DEVICES_MAX (1)\r
+\r
+\r
+/* Font definitions depending on which font is selected. */\r
+#ifdef TEXTDISPLAY_FONT_8x8\r
+ #define FONT_WIDTH (8)\r
+ #define FONT_HEIGHT (8)\r
+#endif\r
+#ifdef TEXTDISPLAY_FONT_6x8\r
+ #define FONT_WIDTH (6)\r
+ #define FONT_HEIGHT (8)\r
+#endif\r
+#ifdef TEXTDISPLAY_NUMBER_FONT_16x20\r
+ #define FONT_WIDTH (16)\r
+ #define FONT_HEIGHT (20)\r
+#endif\r
+\r
+\r
+/**\r
+ * Determine the number of lines and columns of the text display devices.\r
+ * These constants are used for static memory allocation in the textdisplay\r
+ * device driver.\r
+ *\r
+ * Please make sure that the combined selection of font, lines and columns fits\r
+ * inside the DISPLAY geometry.\r
+ */\r
+#ifndef TEXTDISPLAY_DEVICE_0_LINES\r
+#define TEXTDISPLAY_DEVICE_0_LINES (DISPLAY0_HEIGHT / FONT_HEIGHT)\r
+#endif\r
+#define TEXTDISPLAY_DEVICE_0_COLUMNS (DISPLAY0_WIDTH / FONT_WIDTH)\r
+\r
+\r
+/* Enable PixelMatrix allocation support in the display device driver.\r
+ The textdisplay module allocates a pixel matrix corresponding to one line of\r
+ text on the display. Therefore we need support for pixel matrix allocation.\r
+*/\r
+#define PIXEL_MATRIX_ALLOC_SUPPORT\r
+\r
+/* Enable allocation of pixel matrices from the static pixel matrix pool.\r
+ NOTE:\r
+ The allocator does not support free'ing pixel matrices. It allocates\r
+ continuosly from the static pool without keeping track of the sizes of\r
+ old allocations. I.e. this is a one-shot allocator, and the user should\r
+ allocate buffers once at the beginning of the program.\r
+*/\r
+#define USE_STATIC_PIXEL_MATRIX_POOL\r
+\r
+/* Specify the size of the static pixel matrix pool. For the textdisplay\r
+ we need one line of text, that is, the font height (8) times the\r
+ display width (128 pixels divided by 8 bits per byte). */\r
+#ifndef PIXEL_MATRIX_POOL_SIZE\r
+#define PIXEL_MATRIX_POOL_SIZE (FONT_HEIGHT * DISPLAY0_WIDTH/8)\r
+#endif\r
+/* The alignment of the pixel matrices must depend on the font width\r
+ in order to be handled correctly.*/\r
+#define PIXEL_MATRIX_ALIGNMENT (FONT_WIDTH/8 + ((FONT_WIDTH%8)?1:0))\r
+\r
+#endif /* __SILICON_LABS_TEXTDISPLAYCONFIG_H__ */\r
--- /dev/null
+/***************************************************************************//**\r
+ * @file\r
+ * @brief Provide SWO/ETM TRACE configuration parameters.\r
+ * @version 4.2.1\r
+ *******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
+ *******************************************************************************\r
+ *\r
+ * This file is licensed under the Silabs License Agreement. See the file\r
+ * "Silabs_License_Agreement.txt" for details. Before using this software for\r
+ * any purpose, you must agree to the terms of that agreement.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __SILICON_LABS_TRACECONFIG_H__\r
+#define __SILICON_LABS_TRACECONFIG_H__\r
+\r
+#define BSP_TRACE_SWO_LOCATION GPIO_ROUTELOC0_SWVLOC_LOC0\r
+\r
+/* Enable output on pin - GPIO Port F, Pin 2. */\r
+#define TRACE_ENABLE_PINS() \\r
+ GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK); \\r
+ GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL\r
+\r
+/* No ETM trace support on this WSTK. */\r
+\r
+#endif\r
/**************************************************************************//**\r
* @file\r
* @brief EFM32 Segment LCD Display driver\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
/**************************************************************************//**\r
* @file\r
* @brief EFM32 Segment LCD Display driver, header file\r
- * @version 4.0.0\r
+ * @version 4.2.1\r
******************************************************************************\r
* @section License\r
* <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>\r
projects / freertos / commitdiff