1 /***************************************************************************//**
\r
3 * @brief Reset Management Unit (RMU) peripheral module peripheral API
\r
6 *******************************************************************************
\r
8 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
\r
9 *******************************************************************************
\r
11 * Permission is granted to anyone to use this software for any purpose,
\r
12 * including commercial applications, and to alter it and redistribute it
\r
13 * freely, subject to the following restrictions:
\r
15 * 1. The origin of this software must not be misrepresented; you must not
\r
16 * claim that you wrote the original software.
\r
17 * 2. Altered source versions must be plainly marked as such, and must not be
\r
18 * misrepresented as being the original software.
\r
19 * 3. This notice may not be removed or altered from any source distribution.
\r
21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
\r
22 * obligation to support this Software. Silicon Labs is providing the
\r
23 * Software "AS IS", with no express or implied warranties of any kind,
\r
24 * including, but not limited to, any implied warranties of merchantability
\r
25 * or fitness for any particular purpose or warranties against infringement
\r
26 * of any proprietary rights of a third party.
\r
28 * Silicon Labs will not be liable for any consequential, incidental, or
\r
29 * special damages, or any other relief, or for any claim by any third party,
\r
30 * arising from your use of this Software.
\r
32 ******************************************************************************/
\r
35 #if defined(RMU_COUNT) && (RMU_COUNT > 0)
\r
37 #include "em_common.h"
\r
41 /***************************************************************************//**
\r
42 * @addtogroup EM_Library
\r
44 ******************************************************************************/
\r
46 /***************************************************************************//**
\r
48 * @brief Reset Management Unit (RMU) Peripheral API
\r
50 ******************************************************************************/
\r
52 /*******************************************************************************
\r
53 ***************************** DEFINES *********************************
\r
54 ******************************************************************************/
\r
56 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
\r
58 /* Reset cause "don't care" definitions.
\r
59 1's mark the bits that must be zero, zeros are "don't cares". */
\r
60 #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL)
\r
61 #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */
\r
62 #define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */
\r
63 #define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */
\r
64 #define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */
\r
65 #define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */
\r
66 #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */
\r
67 #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */
\r
68 #define NUM_RSTCAUSES (7)
\r
70 #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL)
\r
71 #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */
\r
72 #define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */
\r
73 #define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */
\r
74 #define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */
\r
75 #define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */
\r
76 #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */
\r
77 #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */
\r
78 #define RMU_RSTCAUSE_EM4RST_XMASK (0x00000719) /**0b0000011100011001 < EM4 Reset */
\r
79 #define RMU_RSTCAUSE_EM4WURST_XMASK (0x00000619) /**0b0000011000011001 < EM4 Wake-up Reset */
\r
80 #define RMU_RSTCAUSE_BODAVDD0_XMASK (0x0000041F) /**0b0000010000011111 < AVDD0 Bod Reset. */
\r
81 #define RMU_RSTCAUSE_BODAVDD1_XMASK (0x0000021F) /**0b0000001000011111 < AVDD1 Bod Reset. */
\r
82 #define NUM_RSTCAUSES (11)
\r
84 #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL)
\r
85 #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */
\r
86 #define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */
\r
87 #define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */
\r
88 #define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */
\r
89 #define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */
\r
90 #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */
\r
91 #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */
\r
92 #define RMU_RSTCAUSE_EM4RST_XMASK (0x00000719) /**0b0000011100011001 < EM4 Reset */
\r
93 #define RMU_RSTCAUSE_EM4WURST_XMASK (0x00000619) /**0b0000011000011001 < EM4 Wake-up Reset */
\r
94 #define RMU_RSTCAUSE_BODAVDD0_XMASK (0x0000041F) /**0b0000010000011111 < AVDD0 Bod Reset */
\r
95 #define RMU_RSTCAUSE_BODAVDD1_XMASK (0x0000021F) /**0b0000001000011111 < AVDD1 Bod Reset */
\r
96 #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector, VDD_DREG */
\r
97 #define RMU_RSTCAUSE_BUBODBUVIN_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector, BU_VIN */
\r
98 #define RMU_RSTCAUSE_BUBODUNREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector Unregulated Domain */
\r
99 #define RMU_RSTCAUSE_BUBODREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector Regulated Domain */
\r
100 #define RMU_RSTCAUSE_BUMODERST_XMASK (0x00000001) /**0b0000000000000001 < Backup mode reset */
\r
101 #define NUM_RSTCAUSES (16)
\r
103 #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL)
\r
104 #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */
\r
105 #define RMU_RSTCAUSE_BODAVDD_XMASK (0x00000001) /**0b0000000000000001 < AVDD Bod Reset */
\r
106 #define RMU_RSTCAUSE_BODDVDD_XMASK (0x00000003) /**0b0000000000000011 < DVDD Bod Reset */
\r
107 #define RMU_RSTCAUSE_BODREGRST_XMASK (0x0000000F) /**0b0000000000001111 < Brown Out Detector Regulated Domain Reset */
\r
108 #define RMU_RSTCAUSE_EXTRST_XMASK (0x0000000F) /**0b0000000000001111 < External Pin Reset */
\r
109 #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000001F) /**0b0000000000011111 < LOCKUP Reset */
\r
110 #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000001F) /**0b0000000000011111 < System Request Reset */
\r
111 #define RMU_RSTCAUSE_WDOGRST_XMASK (0x0000001F) /**0b0000000000011111 < Watchdog Reset */
\r
112 #define RMU_RSTCAUSE_EM4RST_XMASK (0x00000003) /**0b0000000000000011 < EM4H/S Reset */
\r
113 #define NUM_RSTCAUSES (9)
\r
116 #warning "RMU_RSTCAUSE XMASKs are not defined for this family."
\r
119 /*******************************************************************************
\r
120 ******************************* STRUCTS ***********************************
\r
121 ******************************************************************************/
\r
123 /** Reset cause mask type. */
\r
126 uint32_t resetCauseMask;
\r
127 uint32_t dontCareMask;
\r
128 } RMU_ResetCauseMasks_Typedef;
\r
131 /*******************************************************************************
\r
132 ******************************* TYPEDEFS **********************************
\r
133 ******************************************************************************/
\r
135 /** Reset cause mask table. */
\r
136 static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =
\r
138 { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
\r
139 #if defined(RMU_RSTCAUSE_BODUNREGRST)
\r
140 { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
\r
142 #if defined(RMU_RSTCAUSE_BODREGRST)
\r
143 { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
\r
145 #if defined(RMU_RSTCAUSE_AVDDBOD)
\r
146 { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
\r
148 #if defined(RMU_RSTCAUSE_DVDDBOD)
\r
149 { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
\r
151 #if defined(RMU_RSTCAUSE_DECBOD)
\r
152 { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
\r
154 { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
\r
155 { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
\r
156 { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
\r
157 { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
\r
158 #if defined(RMU_RSTCAUSE_EM4RST)
\r
159 { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
\r
161 #if defined(RMU_RSTCAUSE_EM4WURST)
\r
162 { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
\r
164 #if defined(RMU_RSTCAUSE_BODAVDD0)
\r
165 { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
\r
167 #if defined(RMU_RSTCAUSE_BODAVDD1)
\r
168 { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
\r
170 #if defined(BU_PRESENT)
\r
171 { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
\r
172 { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
\r
173 { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
\r
174 { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
\r
175 { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
\r
180 /*******************************************************************************
\r
181 ******************************** TEST ********************************
\r
182 ******************************************************************************/
\r
183 #if defined(EMLIB_REGRESSION_TEST)
\r
184 /* Test variable that replaces the RSTCAUSE cause register when testing
\r
185 the RMU_ResetCauseGet function. */
\r
186 extern uint32_t rstCause;
\r
192 /*******************************************************************************
\r
193 ************************** GLOBAL FUNCTIONS *******************************
\r
194 ******************************************************************************/
\r
196 /***************************************************************************//**
\r
198 * Disable/enable reset for various peripherals and signal sources
\r
200 * @param[in] reset Reset types to enable/disable
\r
202 * @param[in] mode Reset mode
\r
203 ******************************************************************************/
\r
204 void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
\r
206 /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */
\r
207 #if defined(_RMU_CTRL_PINRMODE_MASK)
\r
212 shift = EFM32_CTZ((uint32_t)reset);
\r
213 #if defined(_RMU_CTRL_PINRMODE_MASK)
\r
214 val = (uint32_t)mode << shift;
\r
215 RMU->CTRL = (RMU->CTRL & ~reset) | val;
\r
217 BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0);
\r
222 /***************************************************************************//**
\r
224 * Clear the reset cause register.
\r
227 * This function clears all the reset cause bits of the RSTCAUSE register.
\r
228 * The reset cause bits must be cleared by SW before a new reset occurs,
\r
229 * otherwise reset causes may accumulate. See @ref RMU_ResetCauseGet().
\r
230 ******************************************************************************/
\r
231 void RMU_ResetCauseClear(void)
\r
233 RMU->CMD = RMU_CMD_RCCLR;
\r
235 #if defined(EMU_AUXCTRL_HRCCLR)
\r
239 /* Clear some reset causes not cleared with RMU CMD register */
\r
240 /* (If EMU registers locked, they must be unlocked first) */
\r
241 locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
\r
247 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);
\r
248 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);
\r
259 /***************************************************************************//**
\r
261 * Get the cause of the last reset.
\r
264 * In order to be useful, the reset cause must be cleared by software before a new
\r
265 * reset occurs, otherwise reset causes may accumulate. See @ref
\r
266 * RMU_ResetCauseClear(). This function call will return the main cause for
\r
267 * reset, which can be a bit mask (several causes), and clear away "noise".
\r
270 * Reset cause mask. Please consult the reference manual for description
\r
271 * of the reset cause mask.
\r
272 ******************************************************************************/
\r
273 uint32_t RMU_ResetCauseGet(void)
\r
275 #if !defined(EMLIB_REGRESSION_TEST)
\r
276 uint32_t rstCause = RMU->RSTCAUSE;
\r
278 uint32_t validRstCause = 0;
\r
281 for (i = 0; i < NUM_RSTCAUSES; i++)
\r
283 /* Checks to see if rstCause matches a RSTCAUSE and is not excluded by the X-mask */
\r
284 if ((rstCause & resetCauseMasks[i].resetCauseMask)
\r
285 && !(rstCause & resetCauseMasks[i].dontCareMask))
\r
287 /* Adds the reset-cause to list of real reset-causes */
\r
288 validRstCause |= resetCauseMasks[i].resetCauseMask;
\r
291 return validRstCause;
\r
295 /** @} (end addtogroup RMU) */
\r
296 /** @} (end addtogroup EM_Library) */
\r
297 #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */
\r