ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c

The new boardspecific DDR2 controller configuration is used for the Yucca
board. Now the Yucca board with 440SPe Rev. A chips is also supported.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 7316c34b4a7d8adc1a5de0e853579d7d464d6a38..d08fcf3565ffc618eb0e3b2ce0fdc1e70b75d62d 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -562,6 +562,40 @@ int checkboard (void)
        return 0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+       if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+               return 1;
+       else
+               return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+       /*
+        * Yucca boards with 440SPe rev. A need a slightly different setup
+        * for the MCIF0_WRDTR register.
+        */
+       if (ppc440spe_rev_a())
+               return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+       return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+       /*
+        * Yucca boards with 440SPe rev. A need a slightly different setup
+        * for the MCIF0_CLKTR register.
+        */
+       if (ppc440spe_rev_a())
+               return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+       return default_val;
+}
+
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
 {