ARMv8: Add secure sections for PSCI text and data

This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to
hold PSCI text and data, and it is based on the legacy implementation of ARMv7.

ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and
ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here
in Kconfig too.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 008da39a6c02d11b5b8aa02a34363d9cc3b187e0..3a81f131e2c7c3f5ac7faf9e257c0af96e09af35 100644 (file)
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -121,7 +121,8 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+               -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
                -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 965a8d129c1d0055a1decde4f38d898c1905452e..edae43de07dbd2f82b10d2d28a9c38c4d532e85c 100644 (file)
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -40,4 +40,35 @@ config PSCI_RESET
 
          Select Y here to make use of PSCI calls for system reset
 
+config ARMV8_PSCI
+       bool "Enable PSCI support" if EXPERT
+       default n
+       help
+         PSCI is Power State Coordination Interface defined by ARM.
+         The PSCI in U-boot provides a general framework and each platform
+         can implement their own specific PSCI functions.
+         Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+       int "Maximum supported CPUs for PSCI"
+       depends on ARMV8_PSCI
+       default 4
+       help
+         The maximum number of CPUs supported in the PSCI firmware.
+         It is no problem to set a larger value than the number of CPUs in
+         the actual hardware implementation.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+       hex "Secure address for PSCI image"
+       depends on ARMV8_PSCI
+       help
+         Address for placing the PSCI text, data and stack sections.
+         If not defined, the PSCI sections are placed together with the u-boot
+         but platform can choose to place PSCI code image separately in other
+         places such as some secure RAM built-in SOC etc.
+
+endif
+
 endif

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index d28a4229194467e450d25ed2cd630096392ca666..cc0dc889ae9ffb1d8197211bf829979dcde19f9d 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -47,6 +47,7 @@ menu "Layerscape architecture"
 menu "Layerscape PPA"
 config FSL_LS_PPA
        bool "FSL Layerscape PPA firmware support"
+       depends on !ARMV8_PSCI
        depends on ARCH_LS1043A || ARCH_LS1046A
        select FSL_PPA_ARMV8_PSCI
        help

diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad59637dabe86f3a1334570c76b951a0426f..22195b8834b52c063f3f94406dffba221c3a04d7 100644 (file)
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <config.h>
+#include <asm/psci.h>
+
 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
 OUTPUT_ARCH(aarch64)
 ENTRY(_start)
 SECTIONS
 {
+#ifdef CONFIG_ARMV8_SECURE_BASE
+       /DISCARD/ : { *(.rela._secure*) }
+#endif
        . = 0x00000000;
 
        . = ALIGN(8);
@@ -23,6 +29,57 @@ SECTIONS
                *(.text*)
        }
 
+#ifdef CONFIG_ARMV8_PSCI
+       .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+               ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+       {
+               KEEP(*(.__secure_start))
+       }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+       .secure_text CONFIG_ARMV8_SECURE_BASE :
+               AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+       {
+               *(._secure.text)
+       }
+
+       .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+       {
+               *(._secure.data)
+       }
+
+       .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+                           CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+               AT(ADDR(.secure_stack))
+#else
+               AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+       {
+               KEEP(*(.__secure_stack_start))
+
+               . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+               . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+               KEEP(*(.__secure_stack_end))
+       }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+       . = LOADADDR(.secure_stack);
+#endif
+
+       .__secure_end : AT(ADDR(.__secure_end)) {
+               KEEP(*(.__secure_end))
+               LONG(0x1d1071c);        /* Must output something to reset LMA */
+       }
+#endif
+
        . = ALIGN(8);
        .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }