#include <common.h>
#include <rtc.h>
#include <spi.h>
-
-static struct spi_slave *slave;
+#include <fsl_pmic.h>
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
- u32 reg;
- int err, tim, i = 0;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 1000000,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
-
- if (spi_claim_bus(slave))
- return -1;
+ int tim, i = 0;
do {
- reg = 0x2c000000;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (err)
- return err;
-
- reg = 0x28000000;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day1 = pmic_reg_read(REG_RTC_DAY);
+ if (day1 < 0)
+ return -1;
- if (err)
- return err;
+ time = pmic_reg_read(REG_RTC_TIME);
+ if (time < 0)
+ return -1;
- reg = 0x2c000000;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day2 = pmic_reg_read(REG_RTC_DAY);
+ if (day2 < 0)
+ return -1;
- if (err)
- return err;
} while (day1 != day2 && i++ < 3);
- spi_release_bus(slave);
-
tim = day1 * 86400 + time;
+
to_tm(tim, rtc);
rtc->tm_yday = 0;
int rtc_set(struct rtc_time *rtc)
{
- u32 time, day, reg;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 1000000,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
+ u32 time, day;
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
- if (spi_claim_bus(slave))
- return -1;
-
- reg = 0x2c000000 | day | 0x80000000;
- spi_xfer(slave, 32, (uchar *)®, (uchar *)&day,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- reg = 0x28000000 | time | 0x80000000;
- spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- spi_release_bus(slave);
+ pmic_reg_write(REG_RTC_DAY, day);
+ pmic_reg_write(REG_RTC_TIME, time);
return 0;
}
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS0 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS0 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS 1
+#define CONFIG_FSL_PMIC_CS 2
+#define CONFIG_FSL_PMIC_CLK 1000000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS2 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 2
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1