]> git.sur5r.net Git - u-boot/commitdiff
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)
authorKumar Gala <galak@kernel.crashing.org>
Wed, 9 Feb 2011 02:00:08 +0000 (02:00 +0000)
committerKumar Gala <galak@kernel.crashing.org>
Thu, 28 Apr 2011 03:29:04 +0000 (22:29 -0500)
The P3041DS & P5020DS boards are almost identical (except for the
processor in them).  Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.

Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS.  We utilize some of these for SERDES clock
configuration.

Additionally, the P3041DS/P5020DS support NAND.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 files changed:
arch/powerpc/include/asm/immap_85xx.h
board/freescale/common/Makefile
board/freescale/common/ngpixis.h
board/freescale/corenet_ds/Makefile
board/freescale/corenet_ds/corenet_ds.c
board/freescale/corenet_ds/law.c
board/freescale/corenet_ds/p3041ds_ddr.c [new file with mode: 0644]
board/freescale/corenet_ds/p5020ds_ddr.c [new file with mode: 0644]
board/freescale/corenet_ds/tlb.c
boards.cfg
include/configs/P3041DS.h [new file with mode: 0644]
include/configs/P5020DS.h [new file with mode: 0644]
include/configs/corenet_ds.h

index 286ecb9a5caff922f8815dcfd8b43f43faadf33a..4c7105722b8df03ebff8feb56a342f39b8078eb1 100644 (file)
@@ -2101,6 +2101,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_100       0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125       0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25    0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150       0x30000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK     0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25     0x00010000
index 8ea5acb5de47197c0bbb0d152a83a88f8aef8795..dbf1da81bd04655013fa031d5ea432defcbb40ab 100644 (file)
@@ -46,7 +46,9 @@ COBJS-$(CONFIG_MPC8536DS)     += ics307_clk.o
 COBJS-$(CONFIG_MPC8572DS)      += ics307_clk.o
 COBJS-$(CONFIG_P1022DS)                += ics307_clk.o
 COBJS-$(CONFIG_P2020DS)                += ics307_clk.o
+COBJS-$(CONFIG_P3041DS)                += ics307_clk.o
 COBJS-$(CONFIG_P4080DS)                += ics307_clk.o
+COBJS-$(CONFIG_P5020DS)                += ics307_clk.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
index 681b0d0b9126833cf770892f3b17d21eac43d41b..1d4483d8b9d21cce33b01a48476538dbbf457154 100644 (file)
@@ -20,16 +20,17 @@ typedef struct ngpixis {
        u8 scver;
        u8 csr;
        u8 rst;
-       u8 res1;
+       u8 serclk;
        u8 aux;
        u8 spd;
        u8 brdcfg0;
        u8 brdcfg1;     /* On some boards, this register is called 'dma' */
        u8 addr;
-       u8 res2[2];
+       u8 brdcfg2;
+       u8 gpiodir;
        u8 data;
        u8 led;
-       u8 res3;
+       u8 tag;
        u8 vctl;
        u8 vstat;
        u8 vcfgen0;
index 1047d783f498dfcc48fa9faf4962128193bf5d08..69e81a4d362ad031ea30c6a0b797634633cbaa6c 100644 (file)
@@ -28,7 +28,9 @@ LIB   = $(obj)lib$(BOARD).o
 
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
+COBJS-$(CONFIG_P3041DS)        += p3041ds_ddr.o
 COBJS-$(CONFIG_P4080DS)        += p4080ds_ddr.o
+COBJS-$(CONFIG_P5020DS)        += p5020ds_ddr.o
 COBJS-$(CONFIG_PCI)    += pci.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
index 3db93c364466f1578a534cf1bae695f6c03b29fc..93241251b8e003af471eb63ce9efbb8c0197a475 100644 (file)
@@ -87,10 +87,21 @@ int checkboard (void)
         * don't match.
         */
        puts("SERDES Reference Clocks: ");
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+       sw = in_8(&PIXIS_SW(5));
+       for (i = 0; i < 3; i++) {
+               static const char *freq[] = {"100", "125", "156.25", "212.5" };
+               unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+
+               printf("Bank%u=%sMhz ", i+1, freq[clock]);
+       }
+       puts("\n");
+#else
        sw = in_8(&PIXIS_SW(3));
        printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
        printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
        printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
+#endif
 
        return 0;
 }
@@ -146,7 +157,7 @@ static const char *serdes_clock_to_string(u32 clock)
        case SRDS_PLLCR0_RFCK_SEL_156_25:
                return "156.25";
        default:
-               return "???";
+               return "150";
        }
 }
 
@@ -157,19 +168,41 @@ int misc_init_r(void)
        serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
        u32 actual[NUM_SRDS_BANKS];
        unsigned int i;
-       u8 sw3;
+       u8 sw;
 
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+       sw = in_8(&PIXIS_SW(5));
+       for (i = 0; i < 3; i++) {
+               unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+               switch (clock) {
+               case 0:
+                       actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+                       break;
+               case 1:
+                       actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+                       break;
+               case 2:
+                       actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+                       break;
+               default:
+                       printf("Warning: SDREFCLK%u switch setting of '11' is "
+                              "unsupported\n", i + 1);
+                       break;
+               }
+       }
+#else
        /* Warn if the expected SERDES reference clocks don't match the
         * actual reference clocks.  This needs to be done after calling
         * p4080_erratum_serdes8(), since that function may modify the clocks.
         */
-       sw3 = in_8(&PIXIS_SW(3));
-       actual[0] = (sw3 & 0x40) ?
+       sw = in_8(&PIXIS_SW(3));
+       actual[0] = (sw & 0x40) ?
                SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
-       actual[1] = (sw3 & 0x20) ?
+       actual[1] = (sw & 0x20) ?
                SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
-       actual[2] = (sw3 & 0x10) ?
+       actual[2] = (sw & 0x10) ?
                SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+#endif
 
        for (i = 0; i < NUM_SRDS_BANKS; i++) {
                u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
index 43b4b97de184972381debfe51444c3d04ea1622f..d2ba556b636095cf6c269992cd259c10f5e89588 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -35,6 +35,9 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
new file mode 100644 (file)
index 0000000..5a8ed94
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+       {0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
new file mode 100644 (file)
index 0000000..e65de36
--- /dev/null
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+       {0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+       {0, 0, NULL}
+};
index fe77e798a8c311ff8deb20ff91316b2502e0fbfd..38736b449687b1c750689da61a7e530d32ff57f8 100644 (file)
@@ -117,6 +117,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 13, BOOKE_PAGESZ_4M, 1),
 #endif
+#ifdef CONFIG_SYS_NAND_BASE
+       /*
+        * *I*G - NAND
+        * entry 14 and 15 has been used hard coded, they will be disabled
+        * in cpu_init_f, so we use entry 16 for nand.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 16, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index ac83a6e119506a08f14afff2a697f24c4bbab891..a71b1bbe5555708ea38b3efe050387ba334a69a2 100644 (file)
@@ -558,8 +558,10 @@ P2020RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,NAND
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
+P3041DS                      powerpc     mpc85xx     corenet_ds          freescale
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
 P4080DS_RAMBOOT_PBL          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000
+P5020DS                      powerpc     mpc85xx     corenet_ds          freescale
 mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
new file mode 100644 (file)
index 0000000..46f91cc
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P3041 DS board configuration file
+ *
+ */
+#define CONFIG_P3041DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P3041
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ                25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
+
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
new file mode 100644 (file)
index 0000000..6d279b3
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P5020 DS board configuration file
+ *
+ */
+#define CONFIG_P5020DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P5020
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ                25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
+
index 9be7f1f3fc47035b72a1e707c0ec2d3134a0461b..b1ca537d2b0cd7182f5f2041fc6ee9569ed3789d 100644 (file)
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
+#define SPD_EEPROM_ADDRESS     SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 #define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */
 
 /*
 #define CONFIG_SYS_RAMBOOT
 #endif
 
+/* Nand Flash */
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
+#define CONFIG_NAND_FSL_ELBC
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS      0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                              | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                              | BR_PS_8               /* Port Size = 8 bit */ \
+                              | BR_MS_FCM             /* MSEL = FCM */ \
+                              | BR_V)                 /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000       /* length 256K */ \
+                              | OR_FCM_PGS            /* Large Page*/ \
+                              | OR_FCM_CSCT \
+                              | OR_FCM_CST \
+                              | OR_FCM_CHT \
+                              | OR_FCM_SCY_1 \
+                              | OR_FCM_TRLX \
+                              | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+#endif
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}