85xx: Ensure timebase is zero on secondary cores

The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 75676b5b9e8bd9d88d2e3ce0b139cb070b29298e..ec5e4daf88f1b09838f4a425f4742fe7acb1024e 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -37,6 +37,11 @@ __secondary_start_page:
        li      r3,0x201
        mtspr   SPRN_BUCSR,r3
 
+       /* Ensure TB is 0 */
+       li      r3,0
+       mttbl   r3
+       mttbu   r3
+
        /* Enable/invalidate the I-Cache */
        mfspr   r0,SPRN_L1CSR1
        ori     r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)