32bit BUg fix for DDR2 on 8572

This errata fix is required for 32 bit DDR2 controller on 8572.
May  also be required for P10XX20XX platforms

Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index a2b45c5719ebde1c1345a232785d2fc965bbe251..8dc2b3ac528bd66894778224c4c531c3c05903bd 100644 (file)
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -19,6 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 {
        unsigned int i;
        volatile ccsr_ddr_t *ddr;
+       u32 temp_sdram_cfg;
 
        switch (ctrl_num) {
        case 0:
@@ -78,6 +79,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
+       /* Do not enable the memory */
+       temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+       temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+       out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
        /*
         * For 8572 DDR1 erratum - DDR controller may enter illegal state
         * when operatiing in 32-bit bus mode with 4-beat bursts,
@@ -99,7 +104,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        udelay(200);
        asm volatile("sync;isync");
 
-       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+       /* Let the controller go */
+       temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+       out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 
        /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
        while (in_be32(&ddr->sdram_cfg_2) & 0x10) {

diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index b213af35ef362f5dc894ea4ef46bb84e4dda6ea4..6e3b2559c9fcef5a805d164b902624c315fed45d 100644 (file)
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -51,6 +51,23 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define FSL_DDR_BANK_INTERLEAVING      0x2
 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
 
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN               0x80000000
+#define SDRAM_CFG_SREN                 0x40000000
+#define SDRAM_CFG_ECC_EN               0x20000000
+#define SDRAM_CFG_RD_EN                        0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1      0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2      0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK      0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
+#define SDRAM_CFG_DYN_PWR              0x00200000
+#define SDRAM_CFG_32_BE                        0x00080000
+#define SDRAM_CFG_8_BE                 0x00040000
+#define SDRAM_CFG_NCAP                 0x00020000
+#define SDRAM_CFG_2T_EN                        0x00008000
+#define SDRAM_CFG_BI                   0x00000001
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
        struct {