dm: spi: Correct status register access width

The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 6b6cfbf37512eb23942e40b66cfd53e29d8012da..66a5cbaaa18a2a099d5ea0b1146ae46b052db9bc 100644 (file)
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -411,6 +411,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
                        const void *dout, void *din, unsigned long flags)
 {
        struct udevice *bus = dev_get_parent(dev);
+       struct ich_spi_platdata *plat = dev_get_platdata(bus);
        struct ich_spi_priv *ctlr = dev_get_priv(bus);
        uint16_t control;
        int16_t opcode_index;
@@ -477,7 +478,10 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
        if (ret < 0)
                return ret;
 
-       ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+       if (plat->ich_version == 7)
+               ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+       else
+               ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 
        spi_setup_type(trans, using_cmd ? bytes : 0);
        opcode_index = spi_setup_opcode(ctlr, trans);