Merge git://git.denx.de/u-boot-sunxi

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/.travis.yml b/.travis.yml
index 6cad65fd378d3457422683b15fd836335cba57ff..d83a5e63329a43f247ee70944d48f4c12a984222 100644 (file)
--- a/.travis.yml
+++ b/.travis.yml
@@ -38,7 +38,7 @@ install:
  - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
  - echo -e "aarch64 = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu" >> ~/.buildman
  - echo -e "arm = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf" >> ~/.buildman
- - echo -e "arc = /tmp/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+ - echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
  - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
@@ -70,8 +70,8 @@ before_script:
       echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
     fi
   - if [[ "${TOOLCHAIN}" == arc ]]; then
-       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2016.09-release/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
-       tar -C /tmp -xf arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
+       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
+       tar -C /tmp -xf arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
     fi
   - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
        wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&

diff --git a/MAINTAINERS b/MAINTAINERS
index f251cf71e8ad2bf6119931979122430e9c4f7c28..fde77b2b61161e40cb1006c27dedbab81a39f8fe 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -159,6 +159,8 @@ F:  board/rockchip/
 F:     drivers/clk/rockchip/
 F:     drivers/gpio/rk_gpio.c
 F:     drivers/misc/rockchip-efuse.c
+F:     drivers/mmc/rockchip_sdhci.c
+F:     drivers/mmc/rockchip_dw_mmc.c
 F:     drivers/pinctrl/rockchip/
 F:     drivers/ram/rockchip/
 F:     drivers/sysreset/sysreset_rockchip.c
@@ -195,6 +197,13 @@ T: git git://git.denx.de/u-boot-stm.git
 F:     arch/arm/cpu/arm926ejs/spear/
 F:     arch/arm/include/asm/arch-spear/
 
+ARM STM STM32MP
+M:     Patrick Delaunay <patrick.delaunay@st.com>
+S:     Maintained
+F:     arch/arm/mach-stm32mp
+F:     clk/clk_stm32mp1.c
+F:     ram/stm32mp1
+
 ARM STM STV0991
 M:     Vikas Manocha <vikas.manocha@st.com>
 S:     Maintained
@@ -238,14 +247,50 @@ N:        uniphier
 ARM ZYNQ
 M:     Michal Simek <monstr@monstr.eu>
 S:     Maintained
-F:     arch/arm/cpu/armv7/zynq/
-F:     arch/arm/include/asm/arch-zynq/
+T:     git git://git.denx.de/u-boot-microblaze.git
+F:     arch/arm/mach-zynq/
+F:     drivers/clk/clk_zynq.c
+F:     drivers/fpga/zynqpl.c
+F:     drivers/gpio/zynq_gpio.c
+F:     drivers/i2c/i2c-cdns.c
+F:     drivers/i2c/muxes/pca954x.c
+F:     drivers/i2c/zynq_i2c.c
+F:     drivers/mmc/zynq_sdhci.c
+F:     drivers/mtd/nand/zynq_nand.c
+F:     drivers/net/phy/xilinx_phy.c
+F:     drivers/net/zynq_gem.c
+F:     drivers/serial/serial_zynq.c
+F:     drivers/spi/zynq_qspi.c
+F:     drivers/spi/zynq_spi.c
+F:     drivers/usb/host/ehci-zynq.c
+F:     drivers/watchdog/cdns_wdt.c
+F:     include/zynqmp.h
+F:     tools/zynqimage.c
+N:     zynq
 
 ARM ZYNQMP
 M:     Michal Simek <michal.simek@xilinx.com>
 S:     Maintained
-F:     arch/arm/cpu/armv8/zynqmp/
-F:     arch/arm/include/asm/arch-zynqmp/
+T:     git git://git.denx.de/u-boot-microblaze.git
+F:     arch/arm/mach-zynq/
+F:     drivers/clk/clk_zynq.c
+F:     drivers/fpga/zynqpl.c
+F:     drivers/gpio/zynq_gpio.c
+F:     drivers/i2c/i2c-cdns.c
+F:     drivers/i2c/muxes/pca954x.c
+F:     drivers/i2c/zynq_i2c.c
+F:     drivers/mmc/zynq_sdhci.c
+F:     drivers/mtd/nand/zynq_nand.c
+F:     drivers/net/phy/xilinx_phy.c
+F:     drivers/net/zynq_gem.c
+F:     drivers/serial/serial_zynq.c
+F:     drivers/spi/zynq_qspi.c
+F:     drivers/spi/zynq_spi.c
+F:     drivers/usb/host/ehci-zynq.c
+F:     drivers/watchdog/cdns_wdt.c
+F:     include/zynqmp.h
+F:     tools/zynqimage.c
+N:     zynqmp
 
 BUILDMAN
 M:     Simon Glass <sjg@chromium.org>
@@ -336,6 +381,14 @@ M: Michal Simek <monstr@monstr.eu>
 S:     Maintained
 T:     git git://git.denx.de/u-boot-microblaze.git
 F:     arch/microblaze/
+F:     cmd/mfsl.c
+F:     drivers/gpio/xilinx_gpio.c
+F:     drivers/net/xilinx_axi_emac.c
+F:     drivers/net/xilinx_emaclite.c
+F:     drivers/serial/serial_xuartlite.c
+F:     drivers/spi/xilinx_spi.c
+F:     drivers/watchdog/xilinx_tb_wdt.c
+N:     xilinx
 
 MIPS
 M:     Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
@@ -421,12 +474,6 @@ S: Maintained
 T:     git git://git.denx.de/u-boot-mpc86xx.git
 F:     arch/powerpc/cpu/mpc86xx/
 
-POWERPC PPC4XX
-M:     Stefan Roese <sr@denx.de>
-S:     Maintained
-T:     git git://git.denx.de/u-boot-ppc4xx.git
-F:     arch/powerpc/cpu/ppc4xx/
-
 RISC-V
 M:     Rick Chen <rick@andestech.com>
 S:     Maintained

diff --git a/Makefile b/Makefile
index 5fa14789d99f7f265385029fa55954a9157e05ae..034e5aadce5c5296ceb8265f2a45ac8ed808972b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
 #
 
 VERSION = 2018
-PATCHLEVEL = 03
+PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -600,9 +600,13 @@ KBUILD_CFLAGS      += -g
 KBUILD_AFLAGS  += -g
 
 # Report stack usage if supported
+# ARC tools based on GCC 7.1 has an issue with stack usage
+# with naked functions, see commit message for more details
+ifndef CONFIG_ARC
 ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y)
        KBUILD_CFLAGS += -fstack-usage
 endif
+endif
 
 KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
 

diff --git a/README b/README
index 5fd6428c5cdc462d0f8d5b9c7c370b4e337a746a..ed79298fd4ea9f09911ac5bbc7860da870d9055a 100644 (file)
--- a/README
+++ b/README
@@ -2482,12 +2482,6 @@ FIT uImage format:
                kernel. Needed for UBI support.
 
 - UBI support
-               CONFIG_UBI_SILENCE_MSG
-
-               Make the verbose messages from UBI stop printing.  This leaves
-               warnings and errors enabled.
-
-
                CONFIG_MTD_UBI_WL_THRESHOLD
                This parameter defines the maximum difference between the highest
                erase counter value and the lowest erase counter value of eraseblocks
@@ -2549,12 +2543,6 @@ FIT uImage format:
                Enable UBI fastmap debug
                default: 0
 
-- UBIFS support
-               CONFIG_UBIFS_SILENCE_MSG
-
-               Make the verbose messages from UBIFS stop printing.  This leaves
-               warnings and errors enabled.
-
 - SPL framework
                CONFIG_SPL
                Enable building of SPL globally.

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index e3f9db7b2972bc3d6bb5f8a7e19396952588bc12..aee15d5353d4cc8816b614d7aa947e71fdfaa483 100644 (file)
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -116,6 +116,24 @@ config SYS_DCACHE_OFF
        bool "Do not use Data Cache"
        default n
 
+menuconfig ARC_DBG
+       bool "ARC debugging"
+       default n
+
+if ARC_DBG
+
+config ARC_DBG_IOC_ENABLE
+       bool "Enable IO coherency unit"
+       depends on CPU_ARCHS38
+       default n
+       help
+         Enable IO coherency unit to debug problems with caches and
+         DMA peripherals.
+         NOTE: as of today linux will not work properly if this option
+         is enabled in u-boot!
+
+endif
+
 choice
        prompt "Target select"
        default TARGET_AXS103

diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 3ed0c282bae0b42689d5baf9c1ae9c26981f0681..d040454d1aa96fb229efab339757b7b266b6a544 100644 (file)
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -51,9 +51,10 @@ PLATFORM_CPPFLAGS += -mcpu=archs
 endif
 
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
 
 # Needed for relocation
-LDFLAGS_FINAL += -pie
+LDFLAGS_FINAL += -pie --gc-sections
 
 # Load address for standalone apps
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000

diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index b74d3c85459f072f5afd639fb15537fcb3b0e4d9..17ef656483cc1ee84ef18096b0fe6f5a1e28381d 100644 (file)
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -31,11 +31,8 @@
                };
 
                ethernet@18000 {
-                       #interrupt-cells = <1>;
                        compatible = "altr,socfpga-stmmac";
                        reg = < 0x18000 0x2000 >;
-                       interrupts = < 25 >;
-                       interrupt-names = "macirq";
                        phy-mode = "gmii";
                        snps,pbl = < 32 >;
                        clocks = <&apbclk>;
@@ -46,13 +43,11 @@
                ehci@0x40000 {
                        compatible = "generic-ehci";
                        reg = < 0x40000 0x100 >;
-                       interrupts = < 8 >;
                };
 
                ohci@0x60000 {
                        compatible = "generic-ohci";
                        reg = < 0x60000 0x100 >;
-                       interrupts = < 8 >;
                };
 
                uart0: serial0@22000 {

diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 67dfb93ca8d08380caa182652e125235469f2c7f..80b864af7436876e0b4a5824708576b4dd692602 100644 (file)
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
 
 / {
        #address-cells = <1>;
@@ -13,6 +14,7 @@
 
        aliases {
                console = &uart0;
+               spi0 = &spi0;
        };
 
        cpu_card {
@@ -24,6 +26,35 @@
                };
        };
 
+       clk-fmeas {
+               clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+                        <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+                        <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+                        <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+                        <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+                        <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+                        <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+                        <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
+                        <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
+                        <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
+                        <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+                        <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
+                        <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
+               clock-names = "cpu-pll", "sys-pll",
+                             "tun-pll", "ddr-clk",
+                             "cpu-clk", "hdmi-pll",
+                             "tun-clk", "hdmi-clk",
+                             "apb-clk", "axi-clk",
+                             "eth-clk", "usb-clk",
+                             "sdio-clk", "hdmi-sys-clk",
+                             "gfx-core-clk", "gfx-dma-clk",
+                             "gfx-cfg-clk", "dmac-core-clk",
+                             "dmac-cfg-clk", "sdio-ref-clk",
+                             "spi-clk", "i2c-clk",
+                             "uart-clk", "ebi-clk",
+                             "rom-clk", "pwm-clk";
+       };
+
        cgu_clk: cgu-clk@f0000000 {
                compatible = "snps,hsdk-cgu-clock";
                reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
@@ -53,4 +84,29 @@
                compatible = "generic-ohci";
                reg = <0xf0060000 0x100>;
        };
+
+       spi0: spi@f0020000 {
+               compatible = "snps,dw-apb-ssi";
+               reg = <0xf0020000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               spi-max-frequency = <4000000>;
+               clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+               clock-names = "spi_clk";
+               cs-gpio = <&cs_gpio 0>;
+               spi_flash@0 {
+                       compatible = "spi-flash";
+                       reg = <0>;
+                       spi-max-frequency = <4000000>;
+               };
+       };
+
+       cs_gpio: gpio@f00014b0 {
+               compatible = "snps,hsdk-creg-gpio";
+               reg = <0xf00014b0 0x4>;
+               gpio-controller;
+               #gpio-cells = <1>;
+               gpio-bank-name = "hsdk-spi-cs";
+               gpio-count = <1>;
+       };
 };

diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h
new file mode 100644 (file)
index 0000000..823906d
--- /dev/null
+++ b/arch/arc/include/asm/arc-bcr.h
@@ -0,0 +1,77 @@
+/*
+ * ARC Build Configuration Registers, with encoded hardware config
+ *
+ * Copyright (C) 2018 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARC_BCR_H
+#define __ARC_BCR_H
+#ifndef __ASSEMBLY__
+
+#include <config.h>
+
+union bcr_di_cache {
+       struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+               unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+               unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+       } fields;
+       unsigned int word;
+};
+
+union bcr_slc_cfg {
+       struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+               unsigned int pad:24, way:2, lsz:2, sz:4;
+#else
+               unsigned int sz:4, lsz:2, way:2, pad:24;
+#endif
+       } fields;
+       unsigned int word;
+};
+
+union bcr_generic {
+       struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+               unsigned int pad:24, ver:8;
+#else
+               unsigned int ver:8, pad:24;
+#endif
+       } fields;
+       unsigned int word;
+};
+
+union bcr_clust_cfg {
+       struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+               unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
+#else
+               unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
+#endif
+       } fields;
+       unsigned int word;
+};
+
+union bcr_mmu_4 {
+       struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+       unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+                    n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+       /*           DTLB      ITLB      JES        JE         JA      */
+       unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+                    pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif
+       } fields;
+       unsigned int word;
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARC_BCR_H */

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 67f416305dfcd39f4960978d8aff78fabda9fc3a..3a513149f547376b5e2e88617cf281e2d9c9d126 100644 (file)
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -8,6 +8,7 @@
 #define _ASM_ARC_ARCREGS_H
 
 #include <asm/cache.h>
+#include <config.h>
 
 /*
  * ARC architecture has additional address space - auxiliary registers.
@@ -88,6 +89,16 @@
 
 /* ARCNUM [15:8] - field to identify each core in a multi-core system */
 #define CPU_ID_GET()   ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
+
+static const inline int is_isa_arcv2(void)
+{
+       return IS_ENABLED(CONFIG_ISA_ARCV2);
+}
+
+static const inline int is_isa_arcompact(void)
+{
+       return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
+}
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_ARC_ARCREGS_H */

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index d26d9fb18d0e1b6573b2d8a8c3019ba7c59565ee..2269183615fb1e8843de517ddb50d2c1a118ae90 100644 (file)
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -30,6 +30,13 @@
 #ifndef __ASSEMBLY__
 
 void cache_init(void);
+void flush_n_invalidate_dcache_all(void);
+void sync_n_cleanup_cache_all(void);
+
+static const inline int is_ioc_enabled(void)
+{
+       return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
+}
 
 #endif /* __ASSEMBLY__ */
 

diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
index f0242f1ad6e340d8196fc0bec3a195221016381e..43e13430959d60d648c481329072ed48c631c5d5 100644 (file)
--- a/arch/arc/include/asm/global_data.h
+++ b/arch/arc/include/asm/global_data.h
@@ -7,9 +7,15 @@
 #ifndef        __ASM_ARC_GLOBAL_DATA_H
 #define __ASM_ARC_GLOBAL_DATA_H
 
+#include <config.h>
+
 #ifndef __ASSEMBLY__
 /* Architecture-specific global data */
 struct arch_global_data {
+       int l1_line_sz;
+#if defined(CONFIG_ISA_ARCV2)
+       int slc_line_sz;
+#endif
 };
 #endif /* __ASSEMBLY__ */
 

diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index a12303bc7367cd1b709357ca402a57443b0e5363..060cdf637bc0e8d7dcd3ae0133e6c3d37ff6c7f7 100644 (file)
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -10,7 +10,7 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
-#ifdef CONFIG_ISA_ARCV2
+#ifdef __ARCHS__
 
 /*
  * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
@@ -42,12 +42,12 @@
 #define mb()   asm volatile("sync\n" : : : "memory")
 #endif
 
-#ifdef CONFIG_ISA_ARCV2
+#ifdef __ARCHS__
 #define __iormb()              rmb()
 #define __iowmb()              wmb()
 #else
-#define __iormb()              do { } while (0)
-#define __iowmb()              do { } while (0)
+#define __iormb()              asm volatile("" : : : "memory")
+#define __iowmb()              asm volatile("" : : : "memory")
 #endif
 
 static inline void sync(void)

diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
index 909129c333188e12b5f9de8a7f37e1fb2381d50d..8b137891791fe96927ad78e64b0aad7bded08bdc 100644 (file)
--- a/arch/arc/include/asm/string.h
+++ b/arch/arc/include/asm/string.h
@@ -1,27 +1 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
 
-#ifndef __ASM_ARC_STRING_H
-#define __ASM_ARC_STRING_H
-
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_STRCHR
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRLEN
-
-extern void *memset(void *ptr, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-extern void memzero(void *ptr, __kernel_size_t n);
-extern int memcmp(const void *, const void *, __kernel_size_t);
-extern char *strchr(const char *s, int c);
-extern char *strcpy(char *dest, const char *src);
-extern int strcmp(const char *cs, const char *ct);
-extern __kernel_size_t strlen(const char *);
-
-#endif /* __ASM_ARC_STRING_H */

diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index 12097bf3bee79e0b4588b22de35d799d5ce04aed..6b7fb0fdff9c0025124b05d73cf470ae97a92432 100644 (file)
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -10,13 +10,6 @@ obj-y += cache.o
 obj-y += cpu.o
 obj-y += interrupts.o
 obj-y += relocate.o
-obj-y += strchr-700.o
-obj-y += strcmp.o
-obj-y += strcpy-700.o
-obj-y += strlen.o
-obj-y += memcmp.o
-obj-y += memcpy-700.o
-obj-y += memset.o
 obj-y += reset.o
 obj-y += ints_low.o
 obj-y += init_helpers.o

diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
index 4d4acff239d41ea5ceb77ae8e5a54f24f3146964..4f04aad34a7a01bef308f8f6a81efa6ca2c356d1 100644 (file)
--- a/arch/arc/lib/bootm.c
+++ b/arch/arc/lib/bootm.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <asm/cache.h>
 #include <common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,41 +41,52 @@ void arch_lmb_reserve(struct lmb *lmb)
 static int cleanup_before_linux(void)
 {
        disable_interrupts();
-       flush_dcache_all();
-       invalidate_icache_all();
+       sync_n_cleanup_cache_all();
 
        return 0;
 }
 
+__weak int board_prep_linux(bootm_headers_t *images) { return 0; }
+
 /* Subcommand: PREP */
-static void boot_prep_linux(bootm_headers_t *images)
+static int boot_prep_linux(bootm_headers_t *images)
 {
-       if (image_setup_linux(images))
-               hang();
+       int ret;
+
+       ret = image_setup_linux(images);
+       if (ret)
+               return ret;
+
+       return board_prep_linux(images);
 }
 
-__weak void smp_set_core_boot_addr(unsigned long addr, int corenr) {}
-__weak void smp_kick_all_cpus(void) {}
+/* Generic implementation for single core CPU */
+__weak void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+       void (*kernel_entry)(int zero, int arch, uint params);
+
+       kernel_entry = (void (*)(int, int, uint))entry;
+
+       kernel_entry(zero, arch, params);
+}
 
 /* Subcommand: GO */
 static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
-       void (*kernel_entry)(int zero, int arch, uint params);
+       ulong kernel_entry;
        unsigned int r0, r2;
        int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
 
-       kernel_entry = (void (*)(int, int, uint))images->ep;
+       kernel_entry = images->ep;
 
        debug("## Transferring control to Linux (at address %08lx)...\n",
-             (ulong) kernel_entry);
+             kernel_entry);
        bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
        printf("\nStarting kernel ...%s\n\n", fake ?
               "(fake run for tracing)" : "");
        bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 
-       cleanup_before_linux();
-
        if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
                r0 = 2;
                r2 = (unsigned int)images->ft_addr;
@@ -83,11 +95,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
                r2 = (unsigned int)env_get("bootargs");
        }
 
-       if (!fake) {
-               smp_set_core_boot_addr((unsigned long)kernel_entry, -1);
-               smp_kick_all_cpus();
-               kernel_entry(r0, 0, r2);
-       }
+       cleanup_before_linux();
+
+       if (!fake)
+               board_jump_and_run(kernel_entry, r0, 0, r2);
 }
 
 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
@@ -96,17 +107,13 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
        if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
                return -1;
 
-       if (flag & BOOTM_STATE_OS_PREP) {
-               boot_prep_linux(images);
-               return 0;
-       }
+       if (flag & BOOTM_STATE_OS_PREP)
+               return boot_prep_linux(images);
 
        if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
                boot_jump_linux(images, flag);
                return 0;
        }
 
-       boot_prep_linux(images);
-       boot_jump_linux(images, flag);
-       return 0;
+       return -1;
 }

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 04f1d9d59b5471f7b96ec214e70d17e93a4d5737..8203fae14502c96cca95c605db89a403d2c6ba48 100644 (file)
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -10,8 +10,145 @@
 #include <linux/kernel.h>
 #include <linux/log2.h>
 #include <asm/arcregs.h>
+#include <asm/arc-bcr.h>
 #include <asm/cache.h>
 
+/*
+ * [ NOTE 1 ]:
+ * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
+ * operation may result in unexpected behavior and data loss even if we flush
+ * data cache right before invalidation. That may happens if we store any context
+ * on stack (like we store BLINK register on stack before function call).
+ * BLINK register is the register where return address is automatically saved
+ * when we do function call with instructions like 'bl'.
+ *
+ * There is the real example:
+ * We may hang in the next code as we store any BLINK register on stack in
+ * invalidate_dcache_all() function.
+ *
+ * void flush_dcache_all() {
+ *     __dc_entire_op(OP_FLUSH);
+ *     // Other code //
+ * }
+ *
+ * void invalidate_dcache_all() {
+ *     __dc_entire_op(OP_INV);
+ *     // Other code //
+ * }
+ *
+ * void foo(void) {
+ *     flush_dcache_all();
+ *     invalidate_dcache_all();
+ * }
+ *
+ * Now let's see what really happens during that code execution:
+ *
+ * foo()
+ *   |->> call flush_dcache_all
+ *     [return address is saved to BLINK register]
+ *     [push BLINK] (save to stack)              ![point 1]
+ *     |->> call __dc_entire_op(OP_FLUSH)
+ *         [return address is saved to BLINK register]
+ *         [flush L1 D$]
+ *         return [jump to BLINK]
+ *     <<------
+ *     [other flush_dcache_all code]
+ *     [pop BLINK] (get from stack)
+ *     return [jump to BLINK]
+ *   <<------
+ *   |->> call invalidate_dcache_all
+ *     [return address is saved to BLINK register]
+ *     [push BLINK] (save to stack)               ![point 2]
+ *     |->> call __dc_entire_op(OP_FLUSH)
+ *         [return address is saved to BLINK register]
+ *         [invalidate L1 D$]                 ![point 3]
+ *         // Oops!!!
+ *         // We lose return address from invalidate_dcache_all function:
+ *         // we save it to stack and invalidate L1 D$ after that!
+ *         return [jump to BLINK]
+ *     <<------
+ *     [other invalidate_dcache_all code]
+ *     [pop BLINK] (get from stack)
+ *     // we don't have this data in L1 dcache as we invalidated it in [point 3]
+ *     // so we get it from next memory level (for example DDR memory)
+ *     // but in the memory we have value which we save in [point 1], which
+ *     // is return address from flush_dcache_all function (instead of
+ *     // address from current invalidate_dcache_all function which we
+ *     // saved in [point 2] !)
+ *     return [jump to BLINK]
+ *   <<------
+ *   // As BLINK points to invalidate_dcache_all, we call it again and
+ *   // loop forever.
+ *
+ * Fortunately we may fix that by using flush & invalidation of D$ with a single
+ * one instruction (instead of flush and invalidation instructions pair) and
+ * enabling force function inline with '__attribute__((always_inline))' gcc
+ * attribute to avoid any function call (and BLINK store) between cache flush
+ * and disable.
+ *
+ *
+ * [ NOTE 2 ]:
+ * As of today we only support the following cache configurations on ARC.
+ * Other configurations may exist in HW (for example, since version 3.0 HS
+ * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
+ * Configuration 1:
+ *        ______________________
+ *       |                      |
+ *       |   ARC CPU            |
+ *       |______________________|
+ *        ___|___        ___|___
+ *       |       |      |       |
+ *       | L1 I$ |      | L1 D$ |
+ *       |_______|      |_______|
+ *        on/off         on/off
+ *        ___|______________|____
+ *       |                      |
+ *       |   main memory        |
+ *       |______________________|
+ *
+ * Configuration 2:
+ *        ______________________
+ *       |                      |
+ *       |   ARC CPU            |
+ *       |______________________|
+ *        ___|___        ___|___
+ *       |       |      |       |
+ *       | L1 I$ |      | L1 D$ |
+ *       |_______|      |_______|
+ *        on/off         on/off
+ *        ___|______________|____
+ *       |                      |
+ *       |   L2 (SL$)           |
+ *       |______________________|
+ *          always must be on
+ *        ___|______________|____
+ *       |                      |
+ *       |   main memory        |
+ *       |______________________|
+ *
+ * Configuration 3:
+ *        ______________________
+ *       |                      |
+ *       |   ARC CPU            |
+ *       |______________________|
+ *        ___|___        ___|___
+ *       |       |      |       |
+ *       | L1 I$ |      | L1 D$ |
+ *       |_______|      |_______|
+ *        on/off        must be on
+ *        ___|______________|____      _______
+ *       |                      |     |       |
+ *       |   L2 (SL$)           |-----|  IOC  |
+ *       |______________________|     |_______|
+ *          always must be on          on/off
+ *        ___|______________|____
+ *       |                      |
+ *       |   main memory        |
+ *       |______________________|
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Bit values in IC_CTRL */
 #define IC_CTRL_CACHE_DISABLE  BIT(0)
 
@@ -19,11 +156,10 @@
 #define DC_CTRL_CACHE_DISABLE  BIT(0)
 #define DC_CTRL_INV_MODE_FLUSH BIT(6)
 #define DC_CTRL_FLUSH_STATUS   BIT(8)
-#define CACHE_VER_NUM_MASK     0xF
 
-#define OP_INV         0x1
-#define OP_FLUSH       0x2
-#define OP_INV_IC      0x3
+#define OP_INV                 BIT(0)
+#define OP_FLUSH               BIT(1)
+#define OP_FLUSH_N_INV         (OP_FLUSH | OP_INV)
 
 /* Bit val in SLC_CONTROL */
 #define SLC_CTRL_DIS           0x001
@@ -31,55 +167,117 @@
 #define SLC_CTRL_BUSY          0x100
 #define SLC_CTRL_RGN_OP_INV    0x200
 
+#define CACHE_LINE_MASK                (~(gd->arch.l1_line_sz - 1))
+
 /*
- * By default that variable will fall into .bss section.
- * But .bss section is not relocated and so it will be initilized before
- * relocation but will be used after being zeroed.
+ * We don't want to use '__always_inline' macro here as it can be redefined
+ * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
+ * details about the reasons we need to use always_inline functions.
  */
-int l1_line_sz __section(".data");
-bool dcache_exists __section(".data") = false;
-bool icache_exists __section(".data") = false;
-
-#define CACHE_LINE_MASK                (~(l1_line_sz - 1))
-
-#ifdef CONFIG_ISA_ARCV2
-int slc_line_sz __section(".data");
-bool slc_exists __section(".data") = false;
-bool ioc_exists __section(".data") = false;
-bool pae_exists __section(".data") = false;
+#define inlined_cachefunc       inline __attribute__((always_inline))
 
-/* To force enable IOC set ioc_enable to 'true' */
-bool ioc_enable __section(".data") = false;
+static inlined_cachefunc void __ic_entire_invalidate(void);
+static inlined_cachefunc void __dc_entire_op(const int cacheop);
 
-void read_decode_mmu_bcr(void)
+static inline bool pae_exists(void)
 {
        /* TODO: should we compare mmu version from BCR and from CONFIG? */
 #if (CONFIG_ARC_MMU_VER >= 4)
-       u32 tmp;
+       union bcr_mmu_4 mmu4;
 
-       tmp = read_aux_reg(ARC_AUX_MMU_BCR);
+       mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
 
-       struct bcr_mmu_4 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-       unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
-                    n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
-#else
-       /*           DTLB      ITLB      JES        JE         JA      */
-       unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
-                    pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
-#endif /* CONFIG_CPU_BIG_ENDIAN */
-       } *mmu4;
+       if (mmu4.fields.pae)
+               return true;
+#endif /* (CONFIG_ARC_MMU_VER >= 4) */
 
-       mmu4 = (struct bcr_mmu_4 *)&tmp;
+       return false;
+}
 
-       pae_exists = !!mmu4->pae;
-#endif /* (CONFIG_ARC_MMU_VER >= 4) */
+static inlined_cachefunc bool icache_exists(void)
+{
+       union bcr_di_cache ibcr;
+
+       ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
+       return !!ibcr.fields.ver;
 }
 
-static void __slc_entire_op(const int op)
+static inlined_cachefunc bool icache_enabled(void)
+{
+       if (!icache_exists())
+               return false;
+
+       return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
+}
+
+static inlined_cachefunc bool dcache_exists(void)
+{
+       union bcr_di_cache dbcr;
+
+       dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
+       return !!dbcr.fields.ver;
+}
+
+static inlined_cachefunc bool dcache_enabled(void)
+{
+       if (!dcache_exists())
+               return false;
+
+       return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
+}
+
+static inlined_cachefunc bool slc_exists(void)
+{
+       if (is_isa_arcv2()) {
+               union bcr_generic sbcr;
+
+               sbcr.word = read_aux_reg(ARC_BCR_SLC);
+               return !!sbcr.fields.ver;
+       }
+
+       return false;
+}
+
+static inlined_cachefunc bool slc_data_bypass(void)
+{
+       /*
+        * If L1 data cache is disabled SL$ is bypassed and all load/store
+        * requests are sent directly to main memory.
+        */
+       return !dcache_enabled();
+}
+
+static inline bool ioc_exists(void)
+{
+       if (is_isa_arcv2()) {
+               union bcr_clust_cfg cbcr;
+
+               cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
+               return cbcr.fields.c;
+       }
+
+       return false;
+}
+
+static inline bool ioc_enabled(void)
+{
+       /*
+        * We check only CONFIG option instead of IOC HW state check as IOC
+        * must be disabled by default.
+        */
+       if (is_ioc_enabled())
+               return ioc_exists();
+
+       return false;
+}
+
+static inlined_cachefunc void __slc_entire_op(const int op)
 {
        unsigned int ctrl;
 
+       if (!slc_exists())
+               return;
+
        ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
 
        if (!(op & OP_FLUSH))           /* i.e. OP_INV */
@@ -103,6 +301,14 @@ static void __slc_entire_op(const int op)
 
 static void slc_upper_region_init(void)
 {
+       /*
+        * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
+        * only if PAE exists in current HW. So we had to check pae_exist
+        * before using them.
+        */
+       if (!pae_exists())
+               return;
+
        /*
         * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
         * as we don't use PAE40.
@@ -113,9 +319,14 @@ static void slc_upper_region_init(void)
 
 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
 {
+#ifdef CONFIG_ISA_ARCV2
+
        unsigned int ctrl;
        unsigned long end;
 
+       if (!slc_exists())
+               return;
+
        /*
         * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
         *  - b'000 (default) is Flush,
@@ -142,7 +353,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
         * END needs to be setup before START (latter triggers the operation)
         * END can't be same as START, so add (l2_line_sz - 1) to sz
         */
-       end = paddr + sz + slc_line_sz - 1;
+       end = paddr + sz + gd->arch.slc_line_sz - 1;
 
        /*
         * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
@@ -156,85 +367,82 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
        read_aux_reg(ARC_AUX_SLC_CTRL);
 
        while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
-}
+
 #endif /* CONFIG_ISA_ARCV2 */
+}
+
+static void arc_ioc_setup(void)
+{
+       /* IOC Aperture start is equal to DDR start */
+       unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+       /* IOC Aperture size is equal to DDR size */
+       long ap_size = CONFIG_SYS_SDRAM_SIZE;
+
+       /* Unsupported configuration. See [ NOTE 2 ] for more details. */
+       if (!slc_exists())
+               panic("Try to enable IOC but SLC is not present");
+
+       /* Unsupported configuration. See [ NOTE 2 ] for more details. */
+       if (!dcache_enabled())
+               panic("Try to enable IOC but L1 D$ is disabled");
+
+       if (!is_power_of_2(ap_size) || ap_size < 4096)
+               panic("IOC Aperture size must be power of 2 and bigger 4Kib");
+
+       /* IOC Aperture start must be aligned to the size of the aperture */
+       if (ap_base % ap_size != 0)
+               panic("IOC Aperture start must be aligned to the size of the aperture");
+
+       flush_n_invalidate_dcache_all();
+
+       /*
+        * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
+        * so setting 0x11 implies 512M, 0x12 implies 1G...
+        */
+       write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
+                     order_base_2(ap_size / 1024) - 2);
+
+       write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
+       write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
+       write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
+}
 
-#ifdef CONFIG_ISA_ARCV2
 static void read_decode_cache_bcr_arcv2(void)
 {
-       union {
-               struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-                       unsigned int pad:24, way:2, lsz:2, sz:4;
-#else
-                       unsigned int sz:4, lsz:2, way:2, pad:24;
-#endif
-               } fields;
-               unsigned int word;
-       } slc_cfg;
-
-       union {
-               struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-                       unsigned int pad:24, ver:8;
-#else
-                       unsigned int ver:8, pad:24;
-#endif
-               } fields;
-               unsigned int word;
-       } sbcr;
+#ifdef CONFIG_ISA_ARCV2
 
-       sbcr.word = read_aux_reg(ARC_BCR_SLC);
-       if (sbcr.fields.ver) {
+       union bcr_slc_cfg slc_cfg;
+
+       if (slc_exists()) {
                slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
-               slc_exists = true;
-               slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
-       }
+               gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
 
-       union {
-               struct bcr_clust_cfg {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-                       unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
-#else
-                       unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
-#endif
-               } fields;
-               unsigned int word;
-       } cbcr;
+               /*
+                * We don't support configuration where L1 I$ or L1 D$ is
+                * absent but SL$ exists. See [ NOTE 2 ] for more details.
+                */
+               if (!icache_exists() || !dcache_exists())
+                       panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
+       }
 
-       cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
-       if (cbcr.fields.c && ioc_enable)
-               ioc_exists = true;
+#endif /* CONFIG_ISA_ARCV2 */
 }
-#endif
 
 void read_decode_cache_bcr(void)
 {
        int dc_line_sz = 0, ic_line_sz = 0;
-
-       union {
-               struct {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-                       unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
-#else
-                       unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
-#endif
-               } fields;
-               unsigned int word;
-       } ibcr, dbcr;
+       union bcr_di_cache ibcr, dbcr;
 
        ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
        if (ibcr.fields.ver) {
-               icache_exists = true;
-               l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
+               gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
                if (!ic_line_sz)
                        panic("Instruction exists but line length is 0\n");
        }
 
        dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
        if (dbcr.fields.ver) {
-               dcache_exists = true;
-               l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
+               gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
                if (!dc_line_sz)
                        panic("Data cache exists but line length is 0\n");
        }
@@ -247,109 +455,79 @@ void cache_init(void)
 {
        read_decode_cache_bcr();
 
-#ifdef CONFIG_ISA_ARCV2
-       read_decode_cache_bcr_arcv2();
-
-       if (ioc_exists) {
-               /* IOC Aperture start is equal to DDR start */
-               unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
-               /* IOC Aperture size is equal to DDR size */
-               long ap_size = CONFIG_SYS_SDRAM_SIZE;
-
-               flush_dcache_all();
-               invalidate_dcache_all();
+       if (is_isa_arcv2())
+               read_decode_cache_bcr_arcv2();
 
-               if (!is_power_of_2(ap_size) || ap_size < 4096)
-                       panic("IOC Aperture size must be power of 2 and bigger 4Kib");
-
-               /*
-                * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
-                * so setting 0x11 implies 512M, 0x12 implies 1G...
-                */
-               write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
-                             order_base_2(ap_size / 1024) - 2);
-
-               /* IOC Aperture start must be aligned to the size of the aperture */
-               if (ap_base % ap_size != 0)
-                       panic("IOC Aperture start must be aligned to the size of the aperture");
-
-               write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
-               write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
-               write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
-       }
+       if (is_isa_arcv2() && ioc_enabled())
+               arc_ioc_setup();
 
-       read_decode_mmu_bcr();
-
-       /*
-        * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
-        * only if PAE exists in current HW. So we had to check pae_exist
-        * before using them.
-        */
-       if (slc_exists && pae_exists)
+       if (is_isa_arcv2() && slc_exists())
                slc_upper_region_init();
-#endif /* CONFIG_ISA_ARCV2 */
 }
 
 int icache_status(void)
 {
-       if (!icache_exists)
-               return 0;
-
-       if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
-               return 0;
-       else
-               return 1;
+       return icache_enabled();
 }
 
 void icache_enable(void)
 {
-       if (icache_exists)
+       if (icache_exists())
                write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
                              ~IC_CTRL_CACHE_DISABLE);
 }
 
 void icache_disable(void)
 {
-       if (icache_exists)
-               write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
-                             IC_CTRL_CACHE_DISABLE);
+       if (!icache_exists())
+               return;
+
+       __ic_entire_invalidate();
+
+       write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+                     IC_CTRL_CACHE_DISABLE);
 }
 
-void invalidate_icache_all(void)
+/* IC supports only invalidation */
+static inlined_cachefunc void __ic_entire_invalidate(void)
 {
+       if (!icache_enabled())
+               return;
+
        /* Any write to IC_IVIC register triggers invalidation of entire I$ */
-       if (icache_status()) {
-               write_aux_reg(ARC_AUX_IC_IVIC, 1);
-               /*
-                * As per ARC HS databook (see chapter 5.3.3.2)
-                * it is required to add 3 NOPs after each write to IC_IVIC.
-                */
-               __builtin_arc_nop();
-               __builtin_arc_nop();
-               __builtin_arc_nop();
-               read_aux_reg(ARC_AUX_IC_CTRL);  /* blocks */
-       }
+       write_aux_reg(ARC_AUX_IC_IVIC, 1);
+       /*
+        * As per ARC HS databook (see chapter 5.3.3.2)
+        * it is required to add 3 NOPs after each write to IC_IVIC.
+        */
+       __builtin_arc_nop();
+       __builtin_arc_nop();
+       __builtin_arc_nop();
+       read_aux_reg(ARC_AUX_IC_CTRL);  /* blocks */
+}
 
-#ifdef CONFIG_ISA_ARCV2
-       if (slc_exists)
+void invalidate_icache_all(void)
+{
+       __ic_entire_invalidate();
+
+       /*
+        * If SL$ is bypassed for data it is used only for instructions,
+        * so we need to invalidate it too.
+        * TODO: HS 3.0 supports SLC disable so we need to check slc
+        * enable/disable status here.
+        */
+       if (is_isa_arcv2() && slc_data_bypass())
                __slc_entire_op(OP_INV);
-#endif
 }
 
 int dcache_status(void)
 {
-       if (!dcache_exists)
-               return 0;
-
-       if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
-               return 0;
-       else
-               return 1;
+       return dcache_enabled();
 }
 
 void dcache_enable(void)
 {
-       if (!dcache_exists)
+       if (!dcache_exists())
                return;
 
        write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
@@ -358,83 +536,77 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-       if (!dcache_exists)
+       if (!dcache_exists())
                return;
 
+       __dc_entire_op(OP_FLUSH_N_INV);
+
+       /*
+        * As SLC will be bypassed for data after L1 D$ disable we need to
+        * flush it first before L1 D$ disable. Also we invalidate SLC to
+        * avoid any inconsistent data problems after enabling L1 D$ again with
+        * dcache_enable function.
+        */
+       if (is_isa_arcv2())
+               __slc_entire_op(OP_FLUSH_N_INV);
+
        write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
                      DC_CTRL_CACHE_DISABLE);
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-/*
- * Common Helper for Line Operations on {I,D}-Cache
- */
-static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
-                                    const int cacheop)
+/* Common Helper for Line Operations on D-cache */
+static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
+                                     const int cacheop)
 {
        unsigned int aux_cmd;
-#if (CONFIG_ARC_MMU_VER == 3)
-       unsigned int aux_tag;
-#endif
        int num_lines;
 
-       if (cacheop == OP_INV_IC) {
-               aux_cmd = ARC_AUX_IC_IVIL;
-#if (CONFIG_ARC_MMU_VER == 3)
-               aux_tag = ARC_AUX_IC_PTAG;
-#endif
-       } else {
-               /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
-               aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
-#if (CONFIG_ARC_MMU_VER == 3)
-               aux_tag = ARC_AUX_DC_PTAG;
-#endif
-       }
+       /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
+       aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
 
        sz += paddr & ~CACHE_LINE_MASK;
        paddr &= CACHE_LINE_MASK;
 
-       num_lines = DIV_ROUND_UP(sz, l1_line_sz);
+       num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
 
        while (num_lines-- > 0) {
 #if (CONFIG_ARC_MMU_VER == 3)
-               write_aux_reg(aux_tag, paddr);
+               write_aux_reg(ARC_AUX_DC_PTAG, paddr);
 #endif
                write_aux_reg(aux_cmd, paddr);
-               paddr += l1_line_sz;
+               paddr += gd->arch.l1_line_sz;
        }
 }
 
-static unsigned int __before_dc_op(const int op)
+static inlined_cachefunc void __before_dc_op(const int op)
 {
-       unsigned int reg;
+       unsigned int ctrl;
 
-       if (op == OP_INV) {
-               /*
-                * IM is set by default and implies Flush-n-inv
-                * Clear it here for vanilla inv
-                */
-               reg = read_aux_reg(ARC_AUX_DC_CTRL);
-               write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
-       }
+       ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
 
-       return reg;
+       /* IM bit implies flush-n-inv, instead of vanilla inv */
+       if (op == OP_INV)
+               ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
+       else
+               ctrl |= DC_CTRL_INV_MODE_FLUSH;
+
+       write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
 }
 
-static void __after_dc_op(const int op, unsigned int reg)
+static inlined_cachefunc void __after_dc_op(const int op)
 {
        if (op & OP_FLUSH)      /* flush / flush-n-inv both wait */
                while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-
-       /* Switch back to default Invalidate mode */
-       if (op == OP_INV)
-               write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
 }
 
-static inline void __dc_entire_op(const int cacheop)
+static inlined_cachefunc void __dc_entire_op(const int cacheop)
 {
        int aux;
-       unsigned int ctrl_reg = __before_dc_op(cacheop);
+
+       if (!dcache_enabled())
+               return;
+
+       __before_dc_op(cacheop);
 
        if (cacheop & OP_INV)   /* Inv or flush-n-inv use same cmd reg */
                aux = ARC_AUX_DC_IVDC;
@@ -443,36 +615,36 @@ static inline void __dc_entire_op(const int cacheop)
 
        write_aux_reg(aux, 0x1);
 
-       __after_dc_op(cacheop, ctrl_reg);
+       __after_dc_op(cacheop);
 }
 
 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
                                const int cacheop)
 {
-       unsigned int ctrl_reg = __before_dc_op(cacheop);
+       if (!dcache_enabled())
+               return;
 
-       __cache_line_loop(paddr, sz, cacheop);
-       __after_dc_op(cacheop, ctrl_reg);
+       __before_dc_op(cacheop);
+       __dcache_line_loop(paddr, sz, cacheop);
+       __after_dc_op(cacheop);
 }
-#else
-#define __dc_entire_op(cacheop)
-#define __dc_line_op(paddr, sz, cacheop)
-#endif /* !CONFIG_SYS_DCACHE_OFF */
 
 void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
        if (start >= end)
                return;
 
-#ifdef CONFIG_ISA_ARCV2
-       if (!ioc_exists)
-#endif
+       /*
+        * ARCv1                                 -> call __dc_line_op
+        * ARCv2 && L1 D$ disabled               -> nothing
+        * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
+        * ARCv2 && L1 D$ enabled && no IOC      -> call __dc_line_op; call __slc_rgn_op
+        */
+       if (!is_isa_arcv2() || !ioc_enabled())
                __dc_line_op(start, end - start, OP_INV);
 
-#ifdef CONFIG_ISA_ARCV2
-       if (slc_exists && !ioc_exists)
+       if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
                __slc_rgn_op(start, end - start, OP_INV);
-#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -480,15 +652,17 @@ void flush_dcache_range(unsigned long start, unsigned long end)
        if (start >= end)
                return;
 
-#ifdef CONFIG_ISA_ARCV2
-       if (!ioc_exists)
-#endif
+       /*
+        * ARCv1                                 -> call __dc_line_op
+        * ARCv2 && L1 D$ disabled               -> nothing
+        * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
+        * ARCv2 && L1 D$ enabled && no IOC      -> call __dc_line_op; call __slc_rgn_op
+        */
+       if (!is_isa_arcv2() || !ioc_enabled())
                __dc_line_op(start, end - start, OP_FLUSH);
 
-#ifdef CONFIG_ISA_ARCV2
-       if (slc_exists && !ioc_exists)
+       if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
                __slc_rgn_op(start, end - start, OP_FLUSH);
-#endif
 }
 
 void flush_cache(unsigned long start, unsigned long size)
@@ -496,22 +670,47 @@ void flush_cache(unsigned long start, unsigned long size)
        flush_dcache_range(start, start + size);
 }
 
-void invalidate_dcache_all(void)
+/*
+ * As invalidate_dcache_all() is not used in generic U-Boot code and as we
+ * don't need it in arch/arc code alone (invalidate without flush) we implement
+ * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
+ * it's much safer. See [ NOTE 1 ] for more details.
+ */
+void flush_n_invalidate_dcache_all(void)
 {
-       __dc_entire_op(OP_INV);
+       __dc_entire_op(OP_FLUSH_N_INV);
 
-#ifdef CONFIG_ISA_ARCV2
-       if (slc_exists)
-               __slc_entire_op(OP_INV);
-#endif
+       if (is_isa_arcv2() && !slc_data_bypass())
+               __slc_entire_op(OP_FLUSH_N_INV);
 }
 
 void flush_dcache_all(void)
 {
        __dc_entire_op(OP_FLUSH);
 
-#ifdef CONFIG_ISA_ARCV2
-       if (slc_exists)
+       if (is_isa_arcv2() && !slc_data_bypass())
                __slc_entire_op(OP_FLUSH);
-#endif
+}
+
+/*
+ * This is function to cleanup all caches (and therefore sync I/D caches) which
+ * can be used for cleanup before linux launch or to sync caches during
+ * relocation.
+ */
+void sync_n_cleanup_cache_all(void)
+{
+       __dc_entire_op(OP_FLUSH_N_INV);
+
+       /*
+        * If SL$ is bypassed for data it is used only for instructions,
+        * and we shouldn't flush it. So invalidate it instead of flush_n_inv.
+        */
+       if (is_isa_arcv2()) {
+               if (slc_data_bypass())
+                       __slc_entire_op(OP_INV);
+               else
+                       __slc_entire_op(OP_FLUSH_N_INV);
+       }
+
+       __ic_entire_invalidate();
 }

diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
index dbc8d68ffb240c692eac6c3dda76404f8451a439..435fe96ef447aa0e0779cb00de34d91b93e1cbaf 100644 (file)
--- a/arch/arc/lib/init_helpers.c
+++ b/arch/arc/lib/init_helpers.c
@@ -4,14 +4,14 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <asm/cache.h>
 #include <common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int init_cache_f_r(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
-       flush_dcache_all();
-#endif
+       sync_n_cleanup_cache_all();
+
        return 0;
 }

diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
deleted file mode 100644 (file)
index 87bccab..0000000
--- a/arch/arc/lib/memcmp.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifdef __LITTLE_ENDIAN__
-#define WORD2 r2
-#define SHIFT r3
-#else /* __BIG_ENDIAN__ */
-#define WORD2 r3
-#define SHIFT r2
-#endif /* _ENDIAN__ */
-
-.global memcmp
-.align 4
-memcmp:
-       or      %r12, %r0, %r1
-       asl_s   %r12, %r12, 30
-       sub     %r3, %r2, 1
-       brls    %r2, %r12, .Lbytewise
-       ld      %r4, [%r0, 0]
-       ld      %r5, [%r1, 0]
-       lsr.f   %lp_count, %r3, 3
-       lpne    .Loop_end
-       ld_s    WORD2, [%r0, 4]
-       ld_s    %r12, [%r1, 4]
-       brne    %r4, %r5, .Leven
-       ld.a    %r4, [%r0, 8]
-       ld.a    %r5, [%r1, 8]
-       brne    WORD2, %r12, .Lodd
-       nop
-.Loop_end:
-       asl_s   SHIFT, SHIFT, 3
-       bhs_s   .Last_cmp
-       brne    %r4, %r5, .Leven
-       ld      %r4, [%r0, 4]
-       ld      %r5, [%r1, 4]
-#ifdef __LITTLE_ENDIAN__
-       nop_s
-       /* one more load latency cycle */
-.Last_cmp:
-       xor     %r0, %r4, %r5
-       bset    %r0, %r0, SHIFT
-       sub_s   %r1, %r0, 1
-       bic_s   %r1, %r1, %r0
-       norm    %r1, %r1
-       b.d     .Leven_cmp
-       and     %r1, %r1, 24
-.Leven:
-       xor     %r0, %r4, %r5
-       sub_s   %r1, %r0, 1
-       bic_s   %r1, %r1, %r0
-       norm    %r1, %r1
-       /* slow track insn */
-       and     %r1, %r1, 24
-.Leven_cmp:
-       asl     %r2, %r4, %r1
-       asl     %r12, %r5, %r1
-       lsr_s   %r2, %r2, 1
-       lsr_s   %r12, %r12, 1
-       j_s.d   [%blink]
-       sub     %r0, %r2, %r12
-       .balign 4
-.Lodd:
-       xor     %r0, WORD2, %r12
-       sub_s   %r1, %r0, 1
-       bic_s   %r1, %r1, %r0
-       norm    %r1, %r1
-       /* slow track insn */
-       and     %r1, %r1, 24
-       asl_s   %r2, %r2, %r1
-       asl_s   %r12, %r12, %r1
-       lsr_s   %r2, %r2, 1
-       lsr_s   %r12, %r12, 1
-       j_s.d   [%blink]
-       sub     %r0, %r2, %r12
-#else /* __BIG_ENDIAN__ */
-.Last_cmp:
-       neg_s   SHIFT, SHIFT
-       lsr     %r4, %r4, SHIFT
-       lsr     %r5, %r5, SHIFT
-       /* slow track insn */
-.Leven:
-       sub.f   %r0, %r4, %r5
-       mov.ne  %r0, 1
-       j_s.d   [%blink]
-       bset.cs %r0, %r0, 31
-.Lodd:
-       cmp_s   WORD2, %r12
-
-       mov_s   %r0, 1
-       j_s.d   [%blink]
-       bset.cs %r0, %r0, 31
-#endif /* _ENDIAN__ */
-       .balign 4
-.Lbytewise:
-       breq    %r2, 0, .Lnil
-       ldb     %r4, [%r0, 0]
-       ldb     %r5, [%r1, 0]
-       lsr.f   %lp_count, %r3
-       lpne    .Lbyte_end
-       ldb_s   %r3, [%r0, 1]
-       ldb     %r12, [%r1, 1]
-       brne    %r4, %r5, .Lbyte_even
-       ldb.a   %r4, [%r0, 2]
-       ldb.a   %r5, [%r1, 2]
-       brne    %r3, %r12, .Lbyte_odd
-       nop
-.Lbyte_end:
-       bcc     .Lbyte_even
-       brne    %r4, %r5, .Lbyte_even
-       ldb_s   %r3, [%r0, 1]
-       ldb_s   %r12, [%r1, 1]
-.Lbyte_odd:
-       j_s.d   [%blink]
-       sub     %r0, %r3, %r12
-.Lbyte_even:
-       j_s.d   [%blink]
-       sub     %r0, %r4, %r5
-.Lnil:
-       j_s.d   [%blink]
-       mov     %r0, 0

diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
deleted file mode 100644 (file)
index 51dd73a..0000000
--- a/arch/arc/lib/memcpy-700.S
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-.global memcpy
-.align 4
-memcpy:
-       or      %r3, %r0, %r1
-       asl_s   %r3, %r3, 30
-       mov_s   %r5, %r0
-       brls.d  %r2, %r3, .Lcopy_bytewise
-       sub.f   %r3, %r2, 1
-       ld_s    %r12, [%r1, 0]
-       asr.f   %lp_count, %r3, 3
-       bbit0.d %r3, 2, .Lnox4
-       bmsk_s  %r2, %r2, 1
-       st.ab   %r12, [%r5, 4]
-       ld.a    %r12, [%r1, 4]
-.Lnox4:
-       lppnz   .Lendloop
-       ld_s    %r3, [%r1, 4]
-       st.ab   %r12, [%r5, 4]
-       ld.a    %r12, [%r1, 8]
-       st.ab   %r3, [%r5, 4]
-.Lendloop:
-       breq    %r2, 0, .Last_store
-       ld      %r3, [%r5, 0]
-#ifdef __LITTLE_ENDIAN__
-       add3    %r2, -1, %r2
-       /* uses long immediate */
-       xor_s   %r12, %r12, %r3
-       bmsk    %r12, %r12, %r2
-       xor_s   %r12, %r12, %r3
-#else /* __BIG_ENDIAN__ */
-       sub3    %r2, 31, %r2
-       /* uses long immediate */
-       xor_s   %r3, %r3, %r12
-       bmsk    %r3, %r3, %r2
-       xor_s   %r12, %r12, %r3
-#endif /* _ENDIAN__ */
-.Last_store:
-       j_s.d   [%blink]
-       st      %r12, [%r5, 0]
-
-       .balign 4
-.Lcopy_bytewise:
-       jcs     [%blink]
-       ldb_s   %r12, [%r1, 0]
-       lsr.f   %lp_count, %r3
-       bhs_s   .Lnox1
-       stb.ab  %r12, [%r5, 1]
-       ldb.a   %r12, [%r1, 1]
-.Lnox1:
-       lppnz   .Lendbloop
-       ldb_s   %r3, [%r1, 1]
-       stb.ab  %r12, [%r5, 1]
-       ldb.a   %r12, [%r1, 2]
-       stb.ab  %r3, [%r5, 1]
-.Lendbloop:
-       j_s.d   [%blink]
-       stb     %r12, [%r5, 0]

diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
deleted file mode 100644 (file)
index 017e8af..0000000
--- a/arch/arc/lib/memset.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#define SMALL  7 /* Must be at least 6 to deal with alignment/loop issues.  */
-
-.global memset
-.align 4
-memset:
-       mov_s   %r4, %r0
-       or      %r12, %r0, %r2
-       bmsk.f  %r12, %r12, 1
-       extb_s  %r1, %r1
-       asl     %r3, %r1, 8
-       beq.d   .Laligned
-       or_s    %r1, %r1, %r3
-       brls    %r2, SMALL, .Ltiny
-       add     %r3, %r2, %r0
-       stb     %r1, [%r3, -1]
-       bclr_s  %r3, %r3, 0
-       stw     %r1, [%r3, -2]
-       bmsk.f  %r12, %r0, 1
-       add_s   %r2, %r2, %r12
-       sub.ne  %r2, %r2, 4
-       stb.ab  %r1, [%r4, 1]
-       and     %r4, %r4, -2
-       stw.ab  %r1, [%r4, 2]
-       and     %r4, %r4, -4
-
-       .balign 4
-.Laligned:
-       asl     %r3, %r1, 16
-       lsr.f   %lp_count, %r2, 2
-       or_s    %r1, %r1, %r3
-       lpne    .Loop_end
-       st.ab   %r1, [%r4, 4]
-.Loop_end:
-       j_s     [%blink]
-
-       .balign 4
-.Ltiny:
-       mov.f   %lp_count, %r2
-       lpne    .Ltiny_end
-       stb.ab  %r1, [%r4, 1]
-.Ltiny_end:
-       j_s     [%blink]
-
-/*
- * memzero: @r0 = mem, @r1 = size_t
- * memset:  @r0 = mem, @r1 = char, @r2 = size_t
- */
-
-.global memzero
-.align 4
-memzero:
-       /* adjust bzero args to memset args */
-       mov     %r2, %r1
-       mov     %r1, 0
-       /* tail call so need to tinker with blink */
-       b       memset

diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
index 7802f4054594fcfa311225c542eef9256d27c4f0..96b4bd3d8fa6d1a2c83646b0ee7d67a695e821e8 100644 (file)
--- a/arch/arc/lib/relocate.c
+++ b/arch/arc/lib/relocate.c
@@ -17,6 +17,9 @@ int copy_uboot_to_ram(void)
 {
        size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
 
+       if (gd->flags & GD_FLG_SKIP_RELOC)
+               return 0;
+
        memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
 
        return 0;
@@ -40,6 +43,9 @@ int do_elf_reloc_fixups(void)
        Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
        Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
 
+       if (gd->flags & GD_FLG_SKIP_RELOC)
+               return 0;
+
        debug("Section .rela.dyn is located at %08x-%08x\n",
              (unsigned int)re_src, (unsigned int)re_end);
 

diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 0d72fe71d42bbdf1f304150e2a1d27d2a07d7fc7..c78dd001d81d2996cb99ffe6fbc4baae9be2e500 100644 (file)
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -10,26 +10,6 @@
 #include <asm/arcregs.h>
 
 ENTRY(_start)
-; ARCompact devices are not supposed to be SMP so master/slave check
-; makes no sense.
-#ifdef CONFIG_ISA_ARCV2
-       ; Non-masters will be halted immediately, they might be kicked later
-       ; by platform code right before passing control to the Linux kernel
-       ; in bootm.c:boot_jump_linux().
-       lr      r5, [identity]
-       lsr     r5, r5, 8
-       bmsk    r5, r5, 7
-       cmp     r5, 0
-       mov.nz  r0, r5
-       bz      .Lmaster_proceed
-       flag    1
-       nop
-       nop
-       nop
-
-.Lmaster_proceed:
-#endif
-
        /* Setup interrupt vector base that matches "__text_start" */
        sr      __ivt_start, [ARC_AUX_INTR_VEC_BASE]
 
@@ -98,7 +78,13 @@ ENTRY(_start)
 
        /* Zero the one and only argument of "board_init_f" */
        mov_s   %r0, 0
-       j       board_init_f
+       bl      board_init_f
+
+       /* We only get here if relocation is disabled by GD_FLG_SKIP_RELOC */
+       /* Make sure we don't lose GD overwritten by zero new GD */
+       mov     %r0, %r25
+       mov     %r1, 0
+       bl      board_init_r
 ENDPROC(_start)
 
 /*

diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
deleted file mode 100644 (file)
index 55fcc9f..0000000
--- a/arch/arc/lib/strchr-700.S
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * ARC700 has a relatively long pipeline and branch prediction, so we want
- * to avoid branches that are hard to predict.  On the other hand, the
- * presence of the norm instruction makes it easier to operate on whole
- * words branch-free.
- */
-
-.global strchr
-.align 4
-strchr:
-       extb_s  %r1, %r1
-       asl     %r5, %r1, 8
-       bmsk    %r2, %r0, 1
-       or      %r5, %r5, %r1
-       mov_s   %r3, 0x01010101
-       breq.d  %r2, %r0, .Laligned
-       asl     %r4, %r5, 16
-       sub_s   %r0, %r0, %r2
-       asl     %r7, %r2, 3
-       ld_s    %r2, [%r0]
-#ifdef __LITTLE_ENDIAN__
-       asl     %r7, %r3, %r7
-#else /* __BIG_ENDIAN__ */
-       lsr     %r7, %r3, %r7
-#endif /* _ENDIAN__ */
-       or      %r5, %r5, %r4
-       ror     %r4, %r3
-       sub     %r12, %r2, %r7
-       bic_s   %r12, %r12, %r2
-       and     %r12, %r12, %r4
-       brne.d  %r12, 0, .Lfound0_ua
-       xor     %r6, %r2, %r5
-       ld.a    %r2, [%r0, 4]
-       sub     %r12, %r6, %r7
-       bic     %r12, %r12, %r6
-#ifdef __LITTLE_ENDIAN__
-       and     %r7, %r12, %r4
-       /* For speed, we want this branch to be unaligned. */
-       breq    %r7, 0, .Loop
-       /* Likewise this one */
-       b       .Lfound_char
-#else /* __BIG_ENDIAN__ */
-       and     %r12, %r12, %r4
-       /* For speed, we want this branch to be unaligned. */
-       breq    %r12, 0, .Loop
-       lsr_s   %r12, %r12, 7
-       bic     %r2, %r7, %r6
-       b.d     .Lfound_char_b
-       and_s   %r2, %r2, %r12
-#endif /* _ENDIAN__ */
-       /* We require this code address to be unaligned for speed...  */
-.Laligned:
-       ld_s    %r2, [%r0]
-       or      %r5, %r5, %r4
-       ror     %r4, %r3
-       /* ... so that this code address is aligned, for itself and ...  */
-.Loop:
-       sub     %r12, %r2, %r3
-       bic_s   %r12, %r12, %r2
-       and     %r12, %r12, %r4
-       brne.d  %r12, 0, .Lfound0
-       xor     %r6, %r2, %r5
-       ld.a    %r2, [%r0, 4]
-       sub     %r12, %r6, %r3
-       bic     %r12, %r12, %r6
-       and     %r7, %r12, %r4
-       breq    %r7, 0, .Loop
-       /*
-        *... so that this branch is unaligned.
-        * Found searched-for character.
-        * r0 has already advanced to next word.
-        */
-#ifdef __LITTLE_ENDIAN__
-       /*
-        * We only need the information about the first matching byte
-        * (i.e. the least significant matching byte) to be exact,
-        * hence there is no problem with carry effects.
-        */
-.Lfound_char:
-       sub     %r3, %r7, 1
-       bic     %r3, %r3, %r7
-       norm    %r2, %r3
-       sub_s   %r0, %r0, 1
-       asr_s   %r2, %r2, 3
-       j.d     [%blink]
-       sub_s   %r0, %r0, %r2
-
-       .balign 4
-.Lfound0_ua:
-       mov     %r3, %r7
-.Lfound0:
-       sub     %r3, %r6, %r3
-       bic     %r3, %r3, %r6
-       and     %r2, %r3, %r4
-       or_s    %r12, %r12, %r2
-       sub_s   %r3, %r12, 1
-       bic_s   %r3, %r3, %r12
-       norm    %r3, %r3
-       add_s   %r0, %r0, 3
-       asr_s   %r12, %r3, 3
-       asl.f   0, %r2, %r3
-       sub_s   %r0, %r0, %r12
-       j_s.d   [%blink]
-       mov.pl  %r0, 0
-#else /* __BIG_ENDIAN__ */
-.Lfound_char:
-       lsr     %r7, %r7, 7
-
-       bic     %r2, %r7, %r6
-.Lfound_char_b:
-       norm    %r2, %r2
-       sub_s   %r0, %r0, 4
-       asr_s   %r2, %r2, 3
-       j.d     [%blink]
-       add_s   %r0, %r0, %r2
-
-.Lfound0_ua:
-       mov_s   %r3, %r7
-.Lfound0:
-       asl_s   %r2, %r2, 7
-       or      %r7, %r6, %r4
-       bic_s   %r12, %r12, %r2
-       sub     %r2, %r7, %r3
-       or      %r2, %r2, %r6
-       bic     %r12, %r2, %r12
-       bic.f   %r3, %r4, %r12
-       norm    %r3, %r3
-
-       add.pl  %r3, %r3, 1
-       asr_s   %r12, %r3, 3
-       asl.f   0, %r2, %r3
-       add_s   %r0, %r0, %r12
-       j_s.d   [%blink]
-       mov.mi  %r0, 0
-#endif /* _ENDIAN__ */

diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
deleted file mode 100644 (file)
index 8cb7d2f..0000000
--- a/arch/arc/lib/strcmp.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * This is optimized primarily for the ARC700.
- * It would be possible to speed up the loops by one cycle / word
- * respective one cycle / byte by forcing double source 1 alignment, unrolling
- * by a factor of two, and speculatively loading the second word / byte of
- * source 1; however, that would increase the overhead for loop setup / finish,
- * and strcmp might often terminate early.
- */
-
-.global strcmp
-.align 4
-strcmp:
-       or      %r2, %r0, %r1
-       bmsk_s  %r2, %r2, 1
-       brne    %r2, 0, .Lcharloop
-       mov_s   %r12, 0x01010101
-       ror     %r5, %r12
-.Lwordloop:
-       ld.ab   %r2, [%r0, 4]
-       ld.ab   %r3, [%r1, 4]
-       nop_s
-       sub     %r4, %r2, %r12
-       bic     %r4, %r4, %r2
-       and     %r4, %r4, %r5
-       brne    %r4, 0, .Lfound0
-       breq    %r2 ,%r3, .Lwordloop
-#ifdef __LITTLE_ENDIAN__
-       xor     %r0, %r2, %r3   /* mask for difference */
-       sub_s   %r1, %r0, 1
-       bic_s   %r0, %r0, %r1   /* mask for least significant difference bit */
-       sub     %r1, %r5, %r0
-       xor     %r0, %r5, %r1   /* mask for least significant difference byte */
-       and_s   %r2, %r2, %r0
-       and_s   %r3, %r3, %r0
-#endif /* _ENDIAN__ */
-       cmp_s   %r2, %r3
-       mov_s   %r0, 1
-       j_s.d   [%blink]
-       bset.lo %r0, %r0, 31
-
-       .balign 4
-#ifdef __LITTLE_ENDIAN__
-.Lfound0:
-       xor     %r0, %r2, %r3   /* mask for difference */
-       or      %r0, %r0, %r4   /* or in zero indicator */
-       sub_s   %r1, %r0, 1
-       bic_s   %r0, %r0, %r1   /* mask for least significant difference bit */
-       sub     %r1, %r5, %r0
-       xor     %r0, %r5, %r1   /* mask for least significant difference byte */
-       and_s   %r2, %r2, %r0
-       and_s   %r3, %r3, %r0
-       sub.f   %r0, %r2, %r3
-       mov.hi  %r0, 1
-       j_s.d   [%blink]
-       bset.lo %r0, %r0, 31
-#else /* __BIG_ENDIAN__ */
-       /*
-        * The zero-detection above can mis-detect 0x01 bytes as zeroes
-        * because of carry-propagateion from a lower significant zero byte.
-        * We can compensate for this by checking that bit0 is zero.
-        * This compensation is not necessary in the step where we
-        * get a low estimate for r2, because in any affected bytes
-        * we already have 0x00 or 0x01, which will remain unchanged
-        * when bit 7 is cleared.
-        */
-       .balign 4
-.Lfound0:
-       lsr     %r0, %r4, 8
-       lsr_s   %r1, %r2
-       bic_s   %r2, %r2, %r0   /* get low estimate for r2 and get ... */
-       bic_s   %r0, %r0, %r1   /* <this is the adjusted mask for zeros> */
-       or_s    %r3, %r3, %r0   /* ... high estimate r3 so that r2 > r3 will */
-       cmp_s   %r3, %r2        /* ... be independent of trailing garbage */
-       or_s    %r2, %r2, %r0   /* likewise for r3 > r2 */
-       bic_s   %r3, %r3, %r0
-       rlc     %r0, 0          /* r0 := r2 > r3 ? 1 : 0 */
-       cmp_s   %r2, %r3
-       j_s.d   [%blink]
-       bset.lo %r0, %r0, 31
-#endif /* _ENDIAN__ */
-
-       .balign 4
-.Lcharloop:
-       ldb.ab  %r2,[%r0,1]
-       ldb.ab  %r3,[%r1,1]
-       nop_s
-       breq    %r2, 0, .Lcmpend
-       breq    %r2, %r3, .Lcharloop
-.Lcmpend:
-       j_s.d   [%blink]
-       sub     %r0, %r2, %r3

diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
deleted file mode 100644 (file)
index 41bb53e..0000000
--- a/arch/arc/lib/strcpy-700.S
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * If dst and src are 4 byte aligned, copy 8 bytes at a time.
- * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
- * it 8 byte aligned.  Thus, we can do a little read-ahead, without
- * dereferencing a cache line that we should not touch.
- * Note that short and long instructions have been scheduled to avoid
- * branch stalls.
- * The beq_s to r3z could be made unaligned & long to avoid a stall
- * there, but it is not likely to be taken often, and it would also be likely
- * to cost an unaligned mispredict at the next call.
- */
-
-.global strcpy
-.align 4
-strcpy:
-       or      %r2, %r0, %r1
-       bmsk_s  %r2, %r2, 1
-       brne.d  %r2, 0, charloop
-       mov_s   %r10, %r0
-       ld_s    %r3, [%r1, 0]
-       mov     %r8, 0x01010101
-       bbit0.d %r1, 2, loop_start
-       ror     %r12, %r8
-       sub     %r2, %r3, %r8
-       bic_s   %r2, %r2, %r3
-       tst_s   %r2,%r12
-       bne     r3z
-       mov_s   %r4,%r3
-       .balign 4
-loop:
-       ld.a    %r3, [%r1, 4]
-       st.ab   %r4, [%r10, 4]
-loop_start:
-       ld.a    %r4, [%r1, 4]
-       sub     %r2, %r3, %r8
-       bic_s   %r2, %r2, %r3
-       tst_s   %r2, %r12
-       bne_s   r3z
-       st.ab   %r3, [%r10, 4]
-       sub     %r2, %r4, %r8
-       bic     %r2, %r2, %r4
-       tst     %r2, %r12
-       beq     loop
-       mov_s   %r3, %r4
-#ifdef __LITTLE_ENDIAN__
-r3z:   bmsk.f  %r1, %r3, 7
-       lsr_s   %r3, %r3, 8
-#else /* __BIG_ENDIAN__ */
-r3z:   lsr.f   %r1, %r3, 24
-       asl_s   %r3, %r3, 8
-#endif /* _ENDIAN__ */
-       bne.d   r3z
-       stb.ab  %r1, [%r10, 1]
-       j_s     [%blink]
-
-       .balign 4
-charloop:
-       ldb.ab  %r3, [%r1, 1]
-       brne.d  %r3, 0, charloop
-       stb.ab  %r3, [%r10, 1]
-       j       [%blink]

diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
deleted file mode 100644 (file)
index 666e22c..0000000
--- a/arch/arc/lib/strlen.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-.global strlen
-.align 4
-strlen:
-       or      %r3, %r0, 7
-       ld      %r2, [%r3, -7]
-       ld.a    %r6, [%r3, -3]
-       mov     %r4, 0x01010101
-       /* uses long immediate */
-#ifdef __LITTLE_ENDIAN__
-       asl_s   %r1, %r0, 3
-       btst_s  %r0, 2
-       asl     %r7, %r4, %r1
-       ror     %r5, %r4
-       sub     %r1, %r2, %r7
-       bic_s   %r1, %r1, %r2
-       mov.eq  %r7, %r4
-       sub     %r12, %r6, %r7
-       bic     %r12, %r12, %r6
-       or.eq   %r12, %r12, %r1
-       and     %r12, %r12, %r5
-       brne    %r12, 0, .Learly_end
-#else /* __BIG_ENDIAN__ */
-       ror     %r5, %r4
-       btst_s  %r0, 2
-       mov_s   %r1, 31
-       sub3    %r7, %r1, %r0
-       sub     %r1, %r2, %r4
-       bic_s   %r1, %r1, %r2
-       bmsk    %r1, %r1, %r7
-       sub     %r12, %r6, %r4
-       bic     %r12, %r12, %r6
-       bmsk.ne %r12, %r12, %r7
-       or.eq   %r12, %r12, %r1
-       and     %r12, %r12, %r5
-       brne    %r12, 0, .Learly_end
-#endif /* _ENDIAN__ */
-
-.Loop:
-       ld_s    %r2, [%r3, 4]
-       ld.a    %r6, [%r3, 8]
-       /* stall for load result */
-       sub     %r1, %r2, %r4
-       bic_s   %r1, %r1, %r2
-       sub     %r12, %r6, %r4
-       bic     %r12, %r12, %r6
-       or      %r12, %r12, %r1
-       and     %r12, %r12, %r5
-       breq    %r12, 0, .Loop
-.Lend:
-       and.f   %r1, %r1, %r5
-       sub.ne  %r3, %r3, 4
-       mov.eq  %r1, %r12
-#ifdef __LITTLE_ENDIAN__
-       sub_s   %r2, %r1, 1
-       bic_s   %r2, %r2, %r1
-       norm    %r1, %r2
-       sub_s   %r0, %r0, 3
-       lsr_s   %r1, %r1, 3
-       sub     %r0, %r3, %r0
-       j_s.d   [%blink]
-       sub     %r0, %r0, %r1
-#else /* __BIG_ENDIAN__ */
-       lsr_s   %r1, %r1, 7
-       mov.eq  %r2, %r6
-       bic_s   %r1, %r1, %r2
-       norm    %r1, %r1
-       sub     %r0, %r3, %r0
-       lsr_s   %r1, %r1, 3
-       j_s.d   [%blink]
-       add     %r0, %r0, %r1
-#endif /* _ENDIAN */
-.Learly_end:
-       b.d     .Lend
-       sub_s.ne %r1, %r1, %r1

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 95553bee9df3895b68332a43ff9ad35d40bd602b..068ea1e8776f881623f33202a9e7793560b1a5a2 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -762,6 +762,7 @@ config ARCH_ZYNQ
        select SUPPORT_SPL
        select OF_CONTROL
        select SPL_BOARD_INIT if SPL
+       select BOARD_EARLY_INIT_F if WDT
        select SPL_OF_CONTROL if SPL
        select DM
        select DM_ETH if NET
@@ -1132,7 +1133,7 @@ config ARCH_UNIPHIER
          (formerly, System LSI Business Division of Panasonic Corporation)
 
 config STM32
-       bool "Support STM32"
+       bool "Support STMicroelectronics STM32 MCU with cortex M"
        select CPU_V7M
        select DM
        select DM_SERIAL
@@ -1150,6 +1151,27 @@ config ARCH_STI
          Support for STMicroelectronics STiH407/10 SoC family.
          This SoC is used on Linaro 96Board STiH410-B2260
 
+config ARCH_STM32MP
+       bool "Support STMicroelectronics STM32MP Socs with cortex A"
+       select BOARD_LATE_INIT
+       select CLK
+       select DM
+       select DM_GPIO
+       select DM_RESET
+       select DM_SERIAL
+       select OF_CONTROL
+       select OF_LIBFDT
+       select PINCTRL
+       select REGMAP
+       select SUPPORT_SPL
+       select SYSCON
+       select SYS_THUMB_BUILD
+       help
+         Support for STM32MP SoC family developed by STMicroelectronics,
+         MPUs based on ARM cortex A core
+         U-BOOT is running in DDR and SPL support is the unsecure First Stage
+         BootLoader (FSBL)
+
 config ARCH_ROCKCHIP
        bool "Support Rockchip SoCs"
        select OF_CONTROL
@@ -1262,6 +1284,8 @@ source "arch/arm/mach-sti/Kconfig"
 
 source "arch/arm/mach-stm32/Kconfig"
 
+source "arch/arm/mach-stm32mp/Kconfig"
+
 source "arch/arm/mach-sunxi/Kconfig"
 
 source "arch/arm/mach-tegra/Kconfig"
@@ -1336,6 +1360,7 @@ source "board/toradex/colibri_pxa270/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
 source "board/zipitz2/Kconfig"
 
 source "arch/arm/Kconfig.debug"

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5881fdc8e28409b33b01b722efe60eac1655a496..4fa8b38397d960688234a8ac534d41ef376bacc8 100644 (file)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_SOCFPGA)                += socfpga
 machine-$(CONFIG_ARCH_RMOBILE)         += rmobile
 machine-$(CONFIG_ARCH_ROCKCHIP)                += rockchip
 machine-$(CONFIG_STM32)                        += stm32
+machine-$(CONFIG_ARCH_STM32MP)         += stm32mp
 machine-$(CONFIG_TEGRA)                        += tegra
 machine-$(CONFIG_ARCH_UNIPHIER)                += uniphier
 machine-$(CONFIG_ARCH_ZYNQ)            += zynq

diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 30915d28aa9cc09b86f23d4f4b6679996a458b40..545c5185066bd4b90033be7097a311cf7db0badc 100644 (file)
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -17,7 +17,7 @@ int timer_init(void)
        gd->arch.tbl = 0;
        gd->arch.tbu = 0;
 
-       gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+       gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
        return 0;
 }
 
@@ -34,27 +34,9 @@ unsigned long long get_ticks(void)
 }
 
 
-ulong get_timer(ulong base)
-{
-       return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
-}
-
 ulong timer_get_boot_us(void)
 {
-       return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
-void __udelay(unsigned long usec)
-{
-       unsigned long long endtime;
-
-       endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
-                       1000UL);
-
-       endtime += get_ticks();
-
-       while (get_ticks() < endtime)
-               ;
+       return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000);
 }
 
 ulong get_tbclk(void)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9f837d58d3247a796e19b166fad035a1adb9e1e..18fb937a3a4cb091e756d8d80e0a5162d1942434 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -612,6 +612,29 @@ int setup_chip_volt(void)
        return 0;
 }
 
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       u32 ecccr2;
+
+       out_be32(&scfg->pfeasbcr,
+                in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+       out_be32(&scfg->pfebsbcr,
+                in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+       /* CCI-400 QoS settings for PFE */
+       out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+                | SCFG_WR_QOS1_PFE2_QOS));
+       out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+                | SCFG_RD_QOS1_PFE2_QOS));
+
+       ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+       out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+                ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index bc77dd03c361a86e14ae57763b25782a907a7b70..14e7d40064944bc796e1c9cafe590f06b2d94841 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -185,7 +185,7 @@ void zynqmp_pmufw_version(void)
               pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
               pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 
-       if (pm_api_version != ZYNQMP_PM_VERSION)
+       if (pm_api_version < ZYNQMP_PM_VERSION)
                panic("PMUFW version error. Expected: v%d.%d\n",
                      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 }

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83e13ec9155e791a3783fe22b98e3034f449c428..e983622fea5bef32a320fb0d8efb588e53f46485 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -146,7 +146,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
        zynq-zturn-myir.dtb \
        zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
-       zynqmp-ep108.dtb                        \
        zynqmp-mini-emmc.dtb                    \
        zynqmp-mini-nand.dtb                    \
        zynqmp-zcu102-revA.dtb                  \
@@ -500,6 +499,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
 
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 
+dtb-$(CONFIG_TARGET_STM32MP1) += \
+       stm32mp157c-ed1.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here

diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 5f06252e4e24a55207b0801bc3c6d9e643362675..770c08aa7dd4178fc814cb3cf0264f6bf3843e46 100644 (file)
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -82,7 +82,7 @@
 
 &eth0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&rgmii_pins>;
+       pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
        status = "okay";
        phy-mode = "rgmii";
 };
@@ -100,6 +100,8 @@
 
 &sdhci0 {
        bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdio_pins>;
        status = "okay";
 };
 
@@ -109,6 +111,8 @@
        mmc-ddr-1_8v;
        mmc-hs400-1_8v;
        marvell,pad-type = "fixed-1-8v";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc_pins>;
        status = "okay";
 
        #address-cells = <1>;
@@ -150,3 +154,11 @@
 &usb3 {
        status = "okay";
 };
+
+/* CON17 */
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_pins>;
+       reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};

diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index aa6587af667d1dc091f84e12845afeca97df2128..7bfccb0435afe359b0221481383b0dee5566e3bd 100644 (file)
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -89,6 +89,8 @@
 
 &eth0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
        phy-mode = "rgmii";
        phy_addr = <0x1>;
        fixed-link {
@@ -98,6 +100,8 @@
 };
 
 &i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
        status = "okay";
 };
 
@@ -108,6 +112,8 @@
 
 &spi0 {
        status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi_quad_pins>;
 
        spi-flash@0 {
                #address-cells = <1>;
@@ -121,6 +127,8 @@
 
 /* Exported on the micro USB connector CON32 through an FTDI */
 &uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_pins>;
        status = "okay";
 };
 
@@ -133,3 +141,10 @@
 &usb3 {
        status = "okay";
 };
+
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_pins>;
+       reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};

diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 690234234b5e3e47ab5173e2bd744131d727a8c0..54007428ed3b83e98c2ec7704870bd2023dd1cc3 100644 (file)
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -46,6 +46,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/comphy/comphy_data.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
        model = "Marvell Armada 37xx SoC";
@@ -154,6 +155,11 @@
                                        groups = "uart2";
                                        function = "uart";
                                };
+
+                               mmc_pins: mmc-pins {
+                                       groups = "emmc_nb";
+                                       function = "emmc";
+                               };
                        };
 
                        pinctrl_sb: pinctrl-sb@18800 {
@@ -162,7 +168,7 @@
                                reg = <0x18800 0x100>, <0x18C00 0x20>;
                                gpiosb: gpiosb {
                                        #gpio-cells = <2>;
-                                       gpio-ranges = <&pinctrl_sb 0 0 29>;
+                                       gpio-ranges = <&pinctrl_sb 0 0 30>;
                                        gpio-controller;
                                        interrupts =
                                        <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
@@ -177,6 +183,20 @@
                                        function = "mii";
                                };
 
+                               smi_pins: smi-pins {
+                                       groups = "smi";
+                                       function = "smi";
+                               };
+
+                               sdio_pins: sdio-pins {
+                                       groups = "sdio_sb";
+                                       function = "sdio";
+                               };
+
+                               pcie_pins: pcie-pins {
+                                       groups = "pcie1";
+                                       function = "gpio";
+                               };
                        };
 
                        usb3: usb@58000 {
@@ -266,20 +286,6 @@
                                status = "disabled";
                        };
 
-                       pinctl0: pinctl@13830 { /* north bridge */
-                               compatible = "marvell,armada-3700-pinctl";
-                               bank-name = "armada-3700-nb";
-                               reg = <0x13830 0x4>;
-                               pin-count = <36>;
-                       };
-
-                       pinctl1: pinctl@18830 { /* south bridge */
-                               compatible = "marvell,armada-3700-pinctl";
-                               bank-name = "armada-3700-sb";
-                               reg = <0x18830 0x4>;
-                               pin-count = <30>;
-                       };
-
                        comphy: comphy@18300 {
                                compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
                                reg = <0x18300 0x28>,
@@ -288,5 +294,21 @@
                                max-lanes = <2>;
                        };
                };
+
+               pcie0: pcie@d0070000 {
+                       compatible = "marvell,armada-37xx-pcie";
+                       reg = <0 0xd0070000 0 0x20000>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <1>;
+                       status = "disabled";
+
+                       bus-range = <0 0xff>;
+                       ranges = <0x82000000 0 0xe8000000
+                                0 0xe8000000 0 0x1000000 /* Port 0 MEM */
+                                0x81000000 0 0xe9000000
+                                0 0xe9000000 0 0x10000>; /* Port 0 IO*/
+               };
        };
 };

diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi
new file mode 100644 (file)
index 0000000..c67c3dd
--- /dev/null
+++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi
@@ -0,0 +1,13 @@
+/*
+ * da850-lcdk U-Boot Additions
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/ {
+       aliases {
+               i2c0 = &i2c0;
+       };
+};

diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts
new file mode 100644 (file)
index 0000000..a1f4d6d
--- /dev/null
+++ b/arch/arm/dts/da850-lcdk.dts
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "da850.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "DA850/AM1808/OMAP-L138 LCDK";
+       compatible = "ti,da850-lcdk", "ti,da850";
+
+       aliases {
+               serial2 = &serial2;
+               ethernet0 = &eth0;
+       };
+
+       chosen {
+               stdout-path = "serial2:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0xc0000000 0x08000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               dsp_memory_region: dsp-memory@c3000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0xc3000000 0x1000000>;
+                       reusable;
+                       status = "okay";
+               };
+       };
+
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "DA850/OMAP-L138 LCDK";
+               simple-audio-card,widgets =
+                       "Line", "Line In",
+                       "Line", "Line Out";
+               simple-audio-card,routing =
+                       "LINE1L", "Line In",
+                       "LINE1R", "Line In",
+                       "Line Out", "LLOUT",
+                       "Line Out", "RLOUT";
+               simple-audio-card,format = "dsp_b";
+               simple-audio-card,bitclock-master = <&link0_codec>;
+               simple-audio-card,frame-master = <&link0_codec>;
+               simple-audio-card,bitclock-inversion;
+
+               simple-audio-card,cpu {
+                       sound-dai = <&mcasp0>;
+                       system-clock-frequency = <24576000>;
+               };
+
+               link0_codec: simple-audio-card,codec {
+                       sound-dai = <&tlv320aic3106>;
+                       system-clock-frequency = <24576000>;
+               };
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               autorepeat;
+
+               user1 {
+                       label = "GPIO Key USER1";
+                       linux,code = <BTN_0>;
+                       gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
+               };
+
+               user2 {
+                       label = "GPIO Key USER2";
+                       linux,code = <BTN_1>;
+                       gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       vga-bridge {
+               compatible = "ti,ths8135";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               vga_bridge_in: endpoint {
+                                       remote-endpoint = <&lcdc_out_vga>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               vga_bridge_out: endpoint {
+                                       remote-endpoint = <&vga_con_in>;
+                               };
+                       };
+               };
+       };
+
+       vga {
+               compatible = "vga-connector";
+
+               ddc-i2c-bus = <&i2c0>;
+
+               port {
+                       vga_con_in: endpoint {
+                               remote-endpoint = <&vga_bridge_out>;
+                       };
+               };
+       };
+};
+
+&pmx_core {
+       status = "okay";
+
+       mcasp0_pins: pinmux_mcasp0_pins {
+               pinctrl-single,bits = <
+                       /* AHCLKX AFSX ACLKX */
+                       0x00 0x00101010 0x00f0f0f0
+                       /* ARX13 ARX14 */
+                       0x04 0x00000110 0x00000ff0
+               >;
+       };
+
+       nand_pins: nand_pins {
+               pinctrl-single,bits = <
+                       /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
+                       0x1c 0x10110010  0xf0ff00f0
+                       /*
+                        * EMA_D[0], EMA_D[1], EMA_D[2],
+                        * EMA_D[3], EMA_D[4], EMA_D[5],
+                        * EMA_D[6], EMA_D[7]
+                        */
+                       0x24 0x11111111  0xffffffff
+                       /*
+                        * EMA_D[8],  EMA_D[9],  EMA_D[10],
+                        * EMA_D[11], EMA_D[12], EMA_D[13],
+                        * EMA_D[14], EMA_D[15]
+                        */
+                       0x20 0x11111111  0xffffffff
+                       /* EMA_A[1], EMA_A[2] */
+                       0x30 0x01100000  0x0ff00000
+               >;
+       };
+};
+
+&serial2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&serial2_rxtx_pins>;
+       status = "okay";
+};
+
+&wdt {
+       status = "okay";
+};
+
+&rtc0 {
+       status = "okay";
+};
+
+&gpio {
+       status = "okay";
+};
+
+&sata {
+       status = "okay";
+};
+
+&mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mdio_pins>;
+       bus_freq = <2200000>;
+       status = "okay";
+};
+
+&eth0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mii_pins>;
+       status = "okay";
+};
+
+&mmc0 {
+       max-frequency = <50000000>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc0_pins>;
+       cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       clock-frequency = <100000>;
+       status = "okay";
+
+       tlv320aic3106: tlv320aic3106@18 {
+               #sound-dai-cells = <0>;
+               compatible = "ti,tlv320aic3106";
+               reg = <0x18>;
+               status = "okay";
+       };
+};
+
+&mcasp0 {
+       #sound-dai-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcasp0_pins>;
+       status = "okay";
+
+       op-mode = <0>;   /* DAVINCI_MCASP_IIS_MODE */
+       tdm-slots = <2>;
+       serial-dir = <   /* 0: INACTIVE, 1: TX, 2: RX */
+               0 0 0 0
+               0 0 0 0
+               0 0 0 0
+               0 1 2 0
+       >;
+       tx-num-evt = <32>;
+       rx-num-evt = <32>;
+};
+
+&usb_phy {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+};
+
+&usb1 {
+       status = "okay";
+};
+
+&aemif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&nand_pins>;
+       status = "okay";
+       cs3 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               clock-ranges;
+               ranges;
+
+               ti,cs-chipselect = <3>;
+
+               nand@2000000,0 {
+                       compatible = "ti,davinci-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0 0x02000000 0x02000000
+                              1 0x00000000 0x00008000>;
+
+                       ti,davinci-chipselect = <1>;
+                       ti,davinci-mask-ale = <0>;
+                       ti,davinci-mask-cle = <0>;
+                       ti,davinci-mask-chipsel = <0>;
+
+                       ti,davinci-nand-buswidth = <16>;
+                       ti,davinci-ecc-mode = "hw";
+                       ti,davinci-ecc-bits = <4>;
+                       ti,davinci-nand-use-bbt;
+
+                       /*
+                        * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
+                        * "To boot from NAND Flash, the AIS should be written
+                        * to NAND block 1 (NAND block 0 is not used by default)".
+                        * The same doc mentions that for ROM "Silicon Revision 2.1",
+                        * "Updated NAND boot mode to offer boot from block 0 or block 1".
+                        * However the limitaion is left here by default for compatibility
+                        * with older silicon and because it needs new boot pin settings
+                        * not possible in stock LCDK.
+                        */
+                       partitions {
+                               compatible = "fixed-partitions";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               partition@0 {
+                                       label = "u-boot env";
+                                       reg = <0 0x020000>;
+                               };
+                               partition@20000 {
+                                       /* The LCDK defaults to booting from this partition */
+                                       label = "u-boot";
+                                       reg = <0x020000 0x080000>;
+                               };
+                               partition@a0000 {
+                                       label = "free space";
+                                       reg = <0x0a0000 0>;
+                               };
+                       };
+               };
+       };
+};
+
+&prictrl {
+       status = "okay";
+};
+
+&memctrl {
+       status = "okay";
+};
+
+&lcdc {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&lcd_pins>;
+
+       port {
+               lcdc_out_vga: endpoint {
+                       remote-endpoint = <&vga_bridge_in>;
+               };
+       };
+};
+
+&vpif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&vpif_capture_pins>;
+       status = "okay";
+};
+
+&dsp {
+       memory-region = <&dsp_memory_region>;
+       status = "okay";
+};

diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi
index 02e2f8f2586a76a92342e06afb7612c05887d3a1..c66cf78953639db3ed025e4997beb6ef77719064 100644 (file)
--- a/arch/arm/dts/da850.dtsi
+++ b/arch/arm/dts/da850.dtsi
@@ -23,11 +23,18 @@
                        reg = <0xfffee000 0x2000>;
                };
        };
-
-       aliases {
-               spi0 = &spi0;
+       dsp: dsp@11800000 {
+               compatible = "ti,da850-dsp";
+               reg = <0x11800000 0x40000>,
+                     <0x11e00000 0x8000>,
+                     <0x11f00000 0x8000>,
+                     <0x01c14044 0x4>,
+                     <0x01c14174 0x8>;
+               reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
+               interrupt-parent = <&intc>;
+               interrupts = <28>;
+               status = "disabled";
        };
-
        soc@1c00000 {
                compatible = "simple-bus";
                model = "da850";

diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts
index 225c7c53c752997ac0c18568863fe0da9008bd15..02000fcba820881a559c1cf3f9d80662077b6fbe 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a-qds.dts
+++ b/arch/arm/dts/fsl-ls1088a-qds.dts
@@ -19,6 +19,43 @@
        };
 };
 
+&ifc {
+       #address-cells = <2>;
+       #size-cells = <1>;
+       /* NOR, NAND Flashes and FPGA on board */
+       ranges = <0 0 0x5 0x80000000 0x08000000
+                       2 0 0x5 0x30000000 0x00010000
+                       3 0 0x5 0x20000000 0x00010000>;
+       status = "okay";
+
+       nor@0,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0x0 0x0 0x8000000>;
+               bank-width = <2>;
+               device-width = <1>;
+       };
+
+       nand@2,0 {
+               compatible = "fsl,ifc-nand";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x1 0x0 0x10000>;
+       };
+
+       fpga: board-control@3,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus", "fsl,ls1088aqds-fpga",
+                               "fsl,fpga-qixis";
+               reg = <0x2 0x0 0x0000100>;
+               bank-width = <1>;
+               device-width = <1>;
+               ranges = <0 2 0 0x100>;
+       };
+};
+
 &dspi {
        bus-num = <0>;
        status = "okay";

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f8f8654e151a403264c9fd48a571ca622e6d7fc5..b4a42cf5d0cda91b570b359d86303df8dba11088 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -75,6 +75,11 @@
                reg-names = "QuadSPI", "QuadSPI-memory";
                num-cs = <4>;
        };
+       ifc: ifc@1530000 {
+               compatible = "fsl,ifc", "simple-bus";
+               reg = <0x0 0x2240000 0x0 0x20000>;
+               interrupts = <0 21 0x4>; /* Level high type */
+       };
 
        usb0: usb3@3100000 {
                compatible = "fsl,layerscape-dwc3";

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a045c327f1ecb8910a791b2592018c19bbc..e47f762e54dce20adca8f7f077e11ff61998e0fb 100644 (file)
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
                compatible = "st,button1";
                button-gpio = <&gpioi 11 0>;
        };
+
+       backlight: backlight {
+               compatible = "gpio-backlight";
+               gpios = <&gpiok 3 0>;
+               status = "okay";
+       };
+
+       panel-rgb@0 {
+               compatible = "simple-panel";
+               backlight = <&backlight>;
+               enable-gpios = <&gpioi 12 0>;
+               status = "okay";
+
+               display-timings {
+                       timing@0 {
+                               clock-frequency = <9000000>;
+                               hactive = <480>;
+                               vactive = <272>;
+                               hfront-porch = <2>;
+                               hback-porch = <2>;
+                               hsync-len = <41>;
+                               vfront-porch = <2>;
+                               vback-porch = <2>;
+                               vsync-len = <10>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <0>;
+                               pixelclk-active = <1>;
+                       };
+               };
+       };
 };
 
 &clk_hse {
@@ -183,6 +214,40 @@
                          slew-rate = <2>;
                };
        };
+
+       ltdc_pins: ltdc@0 {
+               pins {
+                       pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
+                              <STM32F746_PG12_FUNC_LCD_B4>,
+                              <STM32F746_PI9_FUNC_LCD_VSYNC>,
+                              <STM32F746_PI10_FUNC_LCD_HSYNC>,
+                              <STM32F746_PI14_FUNC_LCD_CLK>,
+                              <STM32F746_PI15_FUNC_LCD_R0>,
+                              <STM32F746_PJ0_FUNC_LCD_R1>,
+                              <STM32F746_PJ1_FUNC_LCD_R2>,
+                              <STM32F746_PJ2_FUNC_LCD_R3>,
+                              <STM32F746_PJ3_FUNC_LCD_R4>,
+                              <STM32F746_PJ4_FUNC_LCD_R5>,
+                              <STM32F746_PJ5_FUNC_LCD_R6>,
+                              <STM32F746_PJ6_FUNC_LCD_R7>,
+                              <STM32F746_PJ7_FUNC_LCD_G0>,
+                              <STM32F746_PJ8_FUNC_LCD_G1>,
+                              <STM32F746_PJ9_FUNC_LCD_G2>,
+                              <STM32F746_PJ10_FUNC_LCD_G3>,
+                              <STM32F746_PJ11_FUNC_LCD_G4>,
+                              <STM32F746_PJ13_FUNC_LCD_B1>,
+                              <STM32F746_PJ14_FUNC_LCD_B2>,
+                              <STM32F746_PJ15_FUNC_LCD_B3>,
+                              <STM32F746_PK0_FUNC_LCD_G5>,
+                              <STM32F746_PK1_FUNC_LCD_G6>,
+                              <STM32F746_PK2_FUNC_LCD_G7>,
+                              <STM32F746_PK4_FUNC_LCD_B5>,
+                              <STM32F746_PK5_FUNC_LCD_B6>,
+                              <STM32F746_PK6_FUNC_LCD_B7>,
+                              <STM32F746_PK7_FUNC_LCD_DE>;
+                       slew-rate = <2>;
+               };
+       };
 };
 
 &usart1 {
@@ -250,3 +315,8 @@
        bus-width = <4>;
        max-frequency = <25000000>;
 };
+
+&ltdc {
+       status = "okay";
+       pinctrl-0 = <&ltdc_pins>;
+};

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8c6fa133e0ab5807153951873391e350a33ec3cb..8581df9a2778e85187ffa43242810db328af781c 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -330,6 +330,15 @@
                        interrupts = <50>;
                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
                };
+
+               ltdc: display-controller@40016800 {
+                       compatible = "st,stm32-ltdc";
+                       reg = <0x40016800 0x200>;
+                       resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+                       clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+                       u-boot,dm-pre-reloc;
+                       status = "disabled";
+               };
        };
 };
 

diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
new file mode 100644 (file)
index 0000000..ddfa079
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+/ {
+       soc {
+               ddr: ddr@0x5A003000{
+                       u-boot,dm-pre-reloc;
+
+                       compatible = "st,stm32mp1-ddr";
+
+                       reg = <0x5A003000 0x550
+                              0x5A004000 0x234>;
+
+                       clocks = <&rcc_clk AXIDCG>,
+                                <&rcc_clk DDRC1>,
+                                <&rcc_clk DDRC2>,
+                                <&rcc_clk DDRPHYC>,
+                                <&rcc_clk DDRCAPB>,
+                                <&rcc_clk DDRPHYCAPB>;
+
+                       clock-names = "axidcg",
+                                     "ddrc1",
+                                     "ddrc2",
+                                     "ddrphyc",
+                                     "ddrcapb",
+                                     "ddrphycapb";
+
+                       st,mem-name = DDR_MEM_NAME;
+                       st,mem-speed = <DDR_MEM_SPEED>;
+                       st,mem-size = <DDR_MEM_SIZE>;
+
+                       st,ctl-reg = <
+                               DDR_MSTR
+                               DDR_MRCTRL0
+                               DDR_MRCTRL1
+                               DDR_DERATEEN
+                               DDR_DERATEINT
+                               DDR_PWRCTL
+                               DDR_PWRTMG
+                               DDR_HWLPCTL
+                               DDR_RFSHCTL0
+                               DDR_RFSHCTL3
+                               DDR_CRCPARCTL0
+                               DDR_ZQCTL0
+                               DDR_DFITMG0
+                               DDR_DFITMG1
+                               DDR_DFILPCFG0
+                               DDR_DFIUPD0
+                               DDR_DFIUPD1
+                               DDR_DFIUPD2
+                               DDR_DFIPHYMSTR
+                               DDR_ODTMAP
+                               DDR_DBG0
+                               DDR_DBG1
+                               DDR_DBGCMD
+                               DDR_POISONCFG
+                               DDR_PCCFG
+                       >;
+
+                       st,ctl-timing = <
+                               DDR_RFSHTMG
+                               DDR_DRAMTMG0
+                               DDR_DRAMTMG1
+                               DDR_DRAMTMG2
+                               DDR_DRAMTMG3
+                               DDR_DRAMTMG4
+                               DDR_DRAMTMG5
+                               DDR_DRAMTMG6
+                               DDR_DRAMTMG7
+                               DDR_DRAMTMG8
+                               DDR_DRAMTMG14
+                               DDR_ODTCFG
+                       >;
+
+                       st,ctl-map = <
+                               DDR_ADDRMAP1
+                               DDR_ADDRMAP2
+                               DDR_ADDRMAP3
+                               DDR_ADDRMAP4
+                               DDR_ADDRMAP5
+                               DDR_ADDRMAP6
+                               DDR_ADDRMAP9
+                               DDR_ADDRMAP10
+                               DDR_ADDRMAP11
+                       >;
+
+                       st,ctl-perf = <
+                               DDR_SCHED
+                               DDR_SCHED1
+                               DDR_PERFHPR1
+                               DDR_PERFLPR1
+                               DDR_PERFWR1
+                               DDR_PCFGR_0
+                               DDR_PCFGW_0
+                               DDR_PCFGQOS0_0
+                               DDR_PCFGQOS1_0
+                               DDR_PCFGWQOS0_0
+                               DDR_PCFGWQOS1_0
+                               DDR_PCFGR_1
+                               DDR_PCFGW_1
+                               DDR_PCFGQOS0_1
+                               DDR_PCFGQOS1_1
+                               DDR_PCFGWQOS0_1
+                               DDR_PCFGWQOS1_1
+                       >;
+
+                       st,phy-reg = <
+                               DDR_PGCR
+                               DDR_ACIOCR
+                               DDR_DXCCR
+                               DDR_DSGCR
+                               DDR_DCR
+                               DDR_ODTCR
+                               DDR_ZQ0CR1
+                               DDR_DX0GCR
+                               DDR_DX1GCR
+                               DDR_DX2GCR
+                               DDR_DX3GCR
+                       >;
+
+                       st,phy-timing = <
+                               DDR_PTR0
+                               DDR_PTR1
+                               DDR_PTR2
+                               DDR_DTPR0
+                               DDR_DTPR1
+                               DDR_DTPR2
+                               DDR_MR0
+                               DDR_MR1
+                               DDR_MR2
+                               DDR_MR3
+                       >;
+
+                       st,phy-cal = <
+                               DDR_DX0DLLCR
+                               DDR_DX0DQTR
+                               DDR_DX0DQSTR
+                               DDR_DX1DLLCR
+                               DDR_DX1DQTR
+                               DDR_DX1DQSTR
+                               DDR_DX2DLLCR
+                               DDR_DX2DQTR
+                               DDR_DX2DQSTR
+                               DDR_DX3DLLCR
+                               DDR_DX3DQTR
+                               DDR_DX3DQSTR
+                       >;
+
+                       status = "okay";
+               };
+       };
+};

diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
new file mode 100644 (file)
index 0000000..352e470
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+/* STM32MP157C ED1 and ED2 BOARD configuration
+ * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used NT5CC256M16DP-DI from NANYA
+ *
+ * DDR type / Platform DDR3/3L
+ * freq                533MHz
+ * width       32
+ * datasheet   0  = MT41J256M16-187 / DDR3-1066 bin G
+ * DDR density 8
+ * timing mode optimized
+ * Scheduling/QoS options : type = 2
+ * address mapping : RBC
+ */
+
+#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
+#define DDR_MEM_SPEED 533
+#define DDR_MEM_SIZE 0x40000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0081008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B2414
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F070707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00001201
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100B03
+#define DDR_PCFGQOS1_1 0x00800100
+#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200001F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000208
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x0000005B
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"

diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
new file mode 100644 (file)
index 0000000..d374b2b
--- /dev/null
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+/ {
+       aliases {
+               gpio0 = &gpioa;
+               gpio1 = &gpiob;
+               gpio2 = &gpioc;
+               gpio3 = &gpiod;
+               gpio4 = &gpioe;
+               gpio5 = &gpiof;
+               gpio6 = &gpiog;
+               gpio7 = &gpioh;
+               gpio8 = &gpioi;
+               gpio9 = &gpioj;
+               gpio10 = &gpiok;
+               gpio25 = &gpioz;
+       };
+
+       config {
+               u-boot,dm-pre-reloc;
+       };
+
+       clocks {
+               u-boot,dm-pre-reloc;
+       };
+
+       soc {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&clk_hsi {
+       u-boot,dm-pre-reloc;
+};
+
+&clk_hse {
+       u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+       u-boot,dm-pre-reloc;
+};
+
+&clk_lsi {
+       u-boot,dm-pre-reloc;
+};
+
+&clk_csi {
+       u-boot,dm-pre-reloc;
+};
+
+&rcc {
+       u-boot,dm-pre-reloc;
+};
+
+&rcc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&rcc_rst {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl_z {
+       u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};
+
+&gpioz {
+       compatible = "st,stm32-gpio";
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
new file mode 100644 (file)
index 0000000..32d3984
--- /dev/null
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset-controller/stm32mp1-resets.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0>;
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <1>;
+               };
+       };
+
+       aliases {
+               serial3 = &uart4;
+       };
+
+       intc: interrupt-controller@a0021000 {
+               compatible = "arm,cortex-a7-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0xa0021000 0x1000>,
+                     <0xa0022000 0x2000>;
+       };
+
+       clocks {
+               clk_hse: clk-hse {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+
+               clk_hsi: clk-hsi {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <64000000>;
+               };
+
+               clk_lse: clk-lse {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <32768>;
+               };
+
+               clk_lsi: clk-lsi {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <32000>;
+               };
+
+               clk_csi: clk-csi {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <4000000>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&intc>;
+               ranges;
+
+               uart4: serial@40010000 {
+                       compatible = "st,stm32h7-uart";
+                       reg = <0x40010000 0x400>;
+                       clocks = <&rcc_clk UART4_K>;
+                       status = "disabled";
+               };
+
+               rcc: rcc@50000000 {
+                       compatible = "syscon", "simple-mfd";
+
+                       reg = <0x50000000 0x1000>;
+
+                       rcc_clk: rcc-clk@50000000 {
+                               #clock-cells = <1>;
+                               compatible = "st,stm32mp1-rcc-clk";
+                       };
+
+                       rcc_rst: rcc-reset@50000000 {
+                               #reset-cells = <1>;
+                               compatible = "st,stm32mp1-rcc-rst";
+                       };
+               };
+
+               pinctrl: pin-controller {
+                       compatible = "st,stm32mp157-pinctrl";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x50002000 0xa400>;
+                       pins-are-numbered;
+
+                       gpioa: gpio@50002000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x0 0x400>;
+                               clocks = <&rcc_clk GPIOA>;
+                               st,bank-name = "GPIOA";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 0 16>;
+                               status = "disabled";
+                       };
+
+                       gpiob: gpio@50003000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x1000 0x400>;
+                               clocks = <&rcc_clk GPIOB>;
+                               st,bank-name = "GPIOB";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 16 16>;
+                               status = "disabled";
+                       };
+
+                       gpioc: gpio@50004000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x2000 0x400>;
+                               clocks = <&rcc_clk GPIOC>;
+                               st,bank-name = "GPIOC";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 32 16>;
+                               status = "disabled";
+                       };
+
+                       gpiod: gpio@50005000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x3000 0x400>;
+                               clocks = <&rcc_clk GPIOD>;
+                               st,bank-name = "GPIOD";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 48 16>;
+                               status = "disabled";
+                       };
+
+                       gpioe: gpio@50006000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x4000 0x400>;
+                               clocks = <&rcc_clk GPIOE>;
+                               st,bank-name = "GPIOE";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 64 16>;
+                               status = "disabled";
+                       };
+
+                       gpiof: gpio@50007000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x5000 0x400>;
+                               clocks = <&rcc_clk GPIOF>;
+                               st,bank-name = "GPIOF";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 80 16>;
+                               status = "disabled";
+                       };
+
+                       gpiog: gpio@50008000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x6000 0x400>;
+                               clocks = <&rcc_clk GPIOG>;
+                               st,bank-name = "GPIOG";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 96 16>;
+                               status = "disabled";
+                       };
+
+                       gpioh: gpio@50009000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x7000 0x400>;
+                               clocks = <&rcc_clk GPIOH>;
+                               st,bank-name = "GPIOH";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 112 16>;
+                               status = "disabled";
+                       };
+
+                       gpioi: gpio@5000a000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x8000 0x400>;
+                               clocks = <&rcc_clk GPIOI>;
+                               st,bank-name = "GPIOI";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 128 16>;
+                               status = "disabled";
+                       };
+
+                       gpioj: gpio@5000b000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x9000 0x400>;
+                               clocks = <&rcc_clk GPIOJ>;
+                               st,bank-name = "GPIOJ";
+                               ngpios = <16>;
+                               gpio-ranges = <&pinctrl 0 144 16>;
+                               status = "disabled";
+                       };
+
+                       gpiok: gpio@5000c000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0xa000 0x400>;
+                               clocks = <&rcc_clk GPIOK>;
+                               st,bank-name = "GPIOK";
+                               ngpios = <8>;
+                               gpio-ranges = <&pinctrl 0 160 8>;
+                               status = "disabled";
+                       };
+               };
+
+               pinctrl_z: pin-controller-z {
+                       compatible = "st,stm32mp157-z-pinctrl";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x54004000 0x400>;
+                       pins-are-numbered;
+
+                       gpioz: gpio@54004000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0 0x400>;
+                               clocks = <&rcc_clk GPIOZ>;
+                               st,bank-name = "GPIOZ";
+                               st,bank-ioport = <11>;
+                               ngpios = <8>;
+                               gpio-ranges = <&pinctrl_z 0 400 8>;
+                               status = "disabled";
+                       };
+               };
+
+               sdmmc1: sdmmc@58005000 {
+                       compatible = "st,stm32-sdmmc2";
+                       reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+                       reg-names = "sdmmc", "delay";
+                       clocks = <&rcc_clk SDMMC1_K>;
+                       resets = <&rcc_rst SDMMC1_R>;
+                       st,idma = <1>;
+                       cap-sd-highspeed;
+                       cap-mmc-highspeed;
+                       max-frequency = <120000000>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@5c002000 {
+                       compatible = "st,stm32f7-i2c";
+                       reg = <0x5c002000 0x400>;
+                       interrupt-names = "event", "error", "wakeup";
+                       clocks = <&rcc_clk I2C4_K>;
+                       resets = <&rcc_rst I2C4_R>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       wakeup-source;
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
new file mode 100644 (file)
index 0000000..94d27fb
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -0,0 +1,133 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+       aliases {
+               mmc0 = &sdmmc1;
+               i2c3 = &i2c4;
+       };
+};
+
+&uart4_pins_a {
+       u-boot,dm-pre-reloc;
+       pins1 {
+               u-boot,dm-pre-reloc;
+       };
+       pins2 {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&i2c4_pins_a {
+       u-boot,dm-pre-reloc;
+       pins {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&uart4 {
+       u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+       u-boot,dm-pre-reloc;
+};
+
+&pmic {
+       u-boot,dm-pre-reloc;
+};
+
+/* CLOCK init */
+&rcc_clk {
+       st,clksrc = <
+               CLK_MPU_PLL1P
+               CLK_AXI_PLL2P
+               CLK_MCU_PLL3P
+               CLK_PLL12_HSE
+               CLK_PLL3_HSE
+               CLK_PLL4_HSE
+               CLK_RTC_LSE
+               CLK_MCO1_DISABLED
+               CLK_MCO2_DISABLED
+       >;
+
+       st,clkdiv = <
+               1 /*MPU*/
+               0 /*AXI*/
+               0 /*MCU*/
+               1 /*APB1*/
+               1 /*APB2*/
+               1 /*APB3*/
+               1 /*APB4*/
+               2 /*APB5*/
+               23 /*RTC*/
+               0 /*MCO1*/
+               0 /*MCO2*/
+       >;
+
+       st,pkcs = <
+               CLK_CKPER_DISABLED
+               CLK_SDMMC12_PLL3R
+               CLK_I2C46_PCLK5
+               CLK_I2C12_PCLK1
+               CLK_I2C35_PCLK1
+               CLK_UART1_PCLK5
+               CLK_UART24_PCLK1
+               CLK_UART35_PCLK1
+               CLK_UART6_PCLK2
+               CLK_UART78_PCLK1
+       >;
+
+       /* VCO = 1300.0 MHz => P = 650 (CPU) */
+       pll1: st,pll@0 {
+               cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+               frac = < 0x800 >;
+               u-boot,dm-pre-reloc;
+       };
+
+       /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+       pll2: st,pll@1 {
+               cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+               frac = < 0x1400 >;
+               u-boot,dm-pre-reloc;
+       };
+
+       /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
+       pll3: st,pll@2 {
+               cfg = < 3 128 3 20 7 PQR(1,1,1) >;
+               u-boot,dm-pre-reloc;
+       };
+
+       /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+       pll4: st,pll@3 {
+               cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+               u-boot,dm-pre-reloc;
+       };
+};
+
+/* SPL part **************************************/
+/* MMC1 boot */
+&sdmmc1_b4_pins_a {
+       u-boot,dm-spl;
+       pins {
+               u-boot,dm-spl;
+       };
+};
+
+&sdmmc1_dir_pins_a {
+       u-boot,dm-spl;
+       pins {
+               u-boot,dm-spl;
+       };
+};
+
+&sdmmc1 {
+       u-boot,dm-spl;
+};

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
new file mode 100644 (file)
index 0000000..4b20fab
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+       model = "STMicroelectronics STM32MP157C pmic eval daughter";
+       compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+       chosen {
+               bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
+               stdout-path = "serial3:115200n8";
+       };
+
+       memory {
+               reg = <0xC0000000 0x40000000>;
+       };
+};
+
+&gpioa {
+       status = "okay";
+};
+
+&gpiob {
+       status = "okay";
+};
+
+&gpioc {
+       status = "okay";
+};
+
+&gpiod {
+       status = "okay";
+};
+
+&gpioe {
+       status = "okay";
+};
+
+&gpiof {
+       status = "okay";
+};
+
+&gpiog {
+       status = "okay";
+};
+
+&gpioh {
+       status = "okay";
+};
+
+&gpioi {
+       status = "okay";
+};
+
+&gpioj {
+       status = "okay";
+};
+
+&gpiok {
+       status = "okay";
+};
+
+&gpioz {
+       status = "okay";
+};
+
+&pinctrl {
+       uart4_pins_a: uart4@0 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <0>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+                       bias-disable;
+               };
+       };
+
+       sdmmc1_b4_pins_a: sdmmc1-b4@0 {
+               pins {
+                       pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+                                <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+                                <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+                                <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+                                <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+                                <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+                       slew-rate = <3>;
+                       drive-push-pull;
+                       bias-disable;
+               };
+       };
+
+       sdmmc1_dir_pins_a: sdmmc1-dir@0 {
+               pins {
+                       pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+                                <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+                                <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
+                                <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+                       slew-rate = <3>;
+                       drive-push-pull;
+                       bias-pull-up;
+               };
+       };
+};
+
+&pinctrl_z {
+       i2c4_pins_a: i2c4@0 {
+               pins {
+                       pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+                                <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+                       bias-disable;
+                       drive-open-drain;
+                       slew-rate = <0>;
+               };
+       };
+};
+
+&i2c4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c4_pins_a>;
+       i2c-scl-rising-time-ns = <185>;
+       i2c-scl-falling-time-ns = <20>;
+       status = "okay";
+
+       pmic: stpmu1@33 {
+               compatible = "st,stpmu1";
+               reg = <0x33>;
+               interrupts = <0 2>;
+               interrupt-parent = <&gpioa>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               status = "okay";
+       };
+};
+
+&sdmmc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+       broken-cd;
+       st,dirpol;
+       st,negedge;
+       st,pin-ckin;
+       bus-width = <4>;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-ddr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart4_pins_a>;
+       status = "okay";
+};

diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index d342306293b42626e310946bb49701ca938ad1b2..a88a83c16650f361d9a2ebcfafe18148c0bfea61 100644 (file)
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -333,3 +333,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usb0_default>;
 };
+
+&watchdog0 {
+       reset-on-timeout;
+};

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
new file mode 100644 (file)
index 0000000..4449d5b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -0,0 +1,290 @@
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+       fclk0: fclk0 {
+               status = "disabled";
+               compatible = "xlnx,fclk";
+               clocks = <&clkc 71>;
+       };
+
+       fclk1: fclk1 {
+               status = "disabled";
+               compatible = "xlnx,fclk";
+               clocks = <&clkc 72>;
+       };
+
+       fclk2: fclk2 {
+               status = "disabled";
+               compatible = "xlnx,fclk";
+               clocks = <&clkc 73>;
+       };
+
+       fclk3: fclk3 {
+               status = "disabled";
+               compatible = "xlnx,fclk";
+               clocks = <&clkc 74>;
+       };
+
+       pss_ref_clk: pss_ref_clk {
+               u-boot,dm-pre-reloc;
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <33333333>;
+       };
+
+       video_clk: video_clk {
+               u-boot,dm-pre-reloc;
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <27000000>;
+       };
+
+       pss_alt_ref_clk: pss_alt_ref_clk {
+               u-boot,dm-pre-reloc;
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       gt_crx_ref_clk: gt_crx_ref_clk {
+               u-boot,dm-pre-reloc;
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <108000000>;
+       };
+
+       aux_ref_clk: aux_ref_clk {
+               u-boot,dm-pre-reloc;
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <27000000>;
+       };
+
+       clkc: clkc {
+               u-boot,dm-pre-reloc;
+               #clock-cells = <1>;
+               compatible = "xlnx,zynqmp-clkc";
+               clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
+               clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
+               clock-output-names = "iopll", "rpll", "apll", "dpll",
+                               "vpll", "iopll_to_fpd", "rpll_to_fpd",
+                               "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
+                               "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
+                               "dbg_trace", "dbg_tstmp", "dp_video_ref",
+                               "dp_audio_ref", "dp_stc_ref", "gdma_ref",
+                               "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
+                               "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
+                               "topsw_main", "topsw_lsbus", "gtgref0_ref",
+                               "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
+                               "usb1_bus_ref", "usb3_dual_ref", "usb0",
+                               "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
+                               "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
+                               "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
+                               "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
+                               "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
+                               "uart0_ref", "uart1_ref", "spi0_ref",
+                               "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
+                               "can0_ref", "can1_ref", "can0", "can1",
+                               "dll_ref", "adma_ref", "timestamp_ref",
+                               "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
+       };
+
+       dp_aclk: dp_aclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+               clock-accuracy = <100>;
+       };
+};
+
+&can0 {
+       clocks = <&clkc 63>, <&clkc 31>;
+};
+
+&can1 {
+       clocks = <&clkc 64>, <&clkc 31>;
+};
+
+&cpu0 {
+       clocks = <&clkc 10>;
+};
+
+&fpd_dma_chan1 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan2 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan3 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan4 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan5 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan6 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan7 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan8 {
+       clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&gpu {
+       clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
+};
+
+&lpd_dma_chan1 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan2 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan3 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan4 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan5 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan6 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan7 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan8 {
+       clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&nand0 {
+       clocks = <&clkc 60>, <&clkc 31>;
+};
+
+&gem0 {
+       clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem1 {
+       clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem2 {
+       clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem3 {
+       clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gpio {
+       clocks = <&clkc 31>;
+};
+
+&i2c0 {
+       clocks = <&clkc 61>;
+};
+
+&i2c1 {
+       clocks = <&clkc 62>;
+};
+
+&pcie {
+       clocks = <&clkc 23>;
+};
+
+&qspi {
+       clocks = <&clkc 53>, <&clkc 31>;
+};
+
+&sata {
+       clocks = <&clkc 22>;
+};
+
+&sdhci0 {
+       clocks = <&clkc 54>, <&clkc 31>;
+};
+
+&sdhci1 {
+       clocks = <&clkc 55>, <&clkc 31>;
+};
+
+&spi0 {
+       clocks = <&clkc 58>, <&clkc 31>;
+};
+
+&spi1 {
+       clocks = <&clkc 59>, <&clkc 31>;
+};
+
+&uart0 {
+       clocks = <&clkc 56>,  <&clkc 31>;
+};
+
+&uart1 {
+       clocks = <&clkc 57>,  <&clkc 31>;
+};
+
+&usb0 {
+       clocks = <&clkc 32>,  <&clkc 34>;
+};
+
+&usb1 {
+       clocks = <&clkc 33>,  <&clkc 34>;
+};
+
+&watchdog0 {
+       clocks = <&clkc 75>;
+};
+
+&xilinx_ams {
+       clocks = <&clkc 70>;
+};
+
+&xilinx_drm {
+       clocks = <&clkc 16>;
+};
+
+&xlnx_dp {
+       clocks = <&dp_aclk>, <&clkc 17>;
+};
+
+&xlnx_dpdma {
+       clocks = <&clkc 20>;
+};
+
+&xlnx_dp_snd_codec0 {
+       clocks = <&clkc 17>;
+};

diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
deleted file mode 100644 (file)
index 12d9fe1..0000000
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * clock specification for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/ {
-       misc_clk: misc_clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <25000000>;
-               u-boot,dm-pre-reloc;
-       };
-
-       i2c_clk: i2c_clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0x0>;
-               clock-frequency = <111111111>;
-       };
-
-       sata_clk: sata_clk {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <75000000>;
-       };
-
-       dp_aclk: clock0 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <50000000>;
-               clock-accuracy = <100>;
-       };
-
-       clk100: clk100 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <100000000>;
-       };
-
-       clk600: clk600 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <600000000>;
-       };
-
-       dp_aud_clk: clock1 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <22579200>;
-               clock-accuracy = <100>;
-       };
-};
-
-&can0 {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&can1 {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&fpd_dma_chan1 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan2 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan3 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan4 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan5 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan6 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan7 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan8 {
-       clocks = <&clk600>, <&clk100>;
-};
-
-&gem0 {
-       clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
-};
-
-&gpio {
-       clocks = <&misc_clk>;
-};
-
-&i2c0 {
-       clocks = <&i2c_clk>;
-};
-
-&i2c1 {
-       clocks = <&i2c_clk>;
-};
-
-&nand0 {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&qspi {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&sata {
-       clocks = <&sata_clk>;
-};
-
-&sdhci0 {
-       clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&sdhci1 {
-       clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&spi0 {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&spi1 {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&uart0 {
-       clocks = <&misc_clk &misc_clk>;
-};
-
-&usb0 {
-       clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&usb1 {
-       clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&watchdog0 {
-       clocks= <&misc_clk>;
-};
-
-&xilinx_drm {
-       clocks = <&misc_clk>;
-};
-
-&xlnx_dp {
-       clocks = <&dp_aclk>, <&dp_aud_clk>;
-};
-
-&xlnx_dp_snd_codec0 {
-       clocks = <&dp_aud_clk>;
-};
-
-&xlnx_dpdma {
-       clocks = <&misc_clk>;
-};

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
deleted file mode 100644 (file)
index a16ffdc..0000000
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * dts file for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-ep108-clk.dtsi"
-
-/ {
-       model = "ZynqMP EP108";
-
-       aliases {
-               ethernet0 = &gem0;
-               mmc0 = &sdhci0;
-               mmc1 = &sdhci1;
-               serial0 = &uart0;
-               spi0 = &qspi;
-               spi1 = &spi0;
-               spi2 = &spi1;
-               usb0 = &usb0;
-               usb1 = &usb1;
-       };
-
-       chosen {
-               bootargs = "earlycon";
-               stdout-path = "serial0:115200n8";
-       };
-
-       memory@0 {
-               device_type = "memory";
-               reg = <0x0 0x0 0x0 0x40000000>;
-       };
-};
-
-&can0 {
-       status = "okay";
-};
-
-&can1 {
-       status = "okay";
-};
-
-&gem0 {
-       status = "okay";
-       phy-handle = <&phy0>;
-       phy-mode = "rgmii-id";
-       phy0: phy@0 {
-               reg = <0>;
-               max-speed = <100>;
-       };
-};
-
-&gpio {
-       status = "okay";
-};
-
-&i2c0 {
-       status = "okay";
-       clock-frequency = <400000>;
-       eeprom@54 {
-               compatible = "atmel,24c64";
-               reg = <0x54>;
-       };
-};
-
-&i2c1 {
-       status = "okay";
-       clock-frequency = <400000>;
-       eeprom@55 {
-               compatible = "atmel,24c64";
-               reg = <0x55>;
-       };
-};
-
-&nand0 {
-       status = "okay";
-       arasan,has-mdma;
-       num-cs = <1>;
-
-       partition@0 {   /* for testing purpose */
-               label = "nand-fsbl-uboot";
-               reg = <0x0 0x0 0x400000>;
-       };
-       partition@1 {   /* for testing purpose */
-               label = "nand-linux";
-               reg = <0x0 0x400000 0x1400000>;
-       };
-       partition@2 {   /* for testing purpose */
-               label = "nand-device-tree";
-               reg = <0x0 0x1800000 0x400000>;
-       };
-       partition@3 {   /* for testing purpose */
-               label = "nand-rootfs";
-               reg = <0x0 0x1C00000 0x1400000>;
-       };
-       partition@4 {   /* for testing purpose */
-               label = "nand-bitstream";
-               reg = <0x0 0x3000000 0x400000>;
-       };
-       partition@5 {   /* for testing purpose */
-               label = "nand-misc";
-               reg = <0x0 0x3400000 0xFCC00000>;
-       };
-};
-
-&qspi {
-       status = "okay";
-       flash@0 {
-               compatible = "m25p80";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               reg = <0x0>;
-               spi-tx-bus-width = <1>;
-               spi-rx-bus-width = <4>;
-               spi-max-frequency = <10000000>;
-               partition@qspi-fsbl-uboot { /* for testing purpose */
-                       label = "qspi-fsbl-uboot";
-                       reg = <0x0 0x100000>;
-               };
-               partition@qspi-linux { /* for testing purpose */
-                       label = "qspi-linux";
-                       reg = <0x100000 0x500000>;
-               };
-               partition@qspi-device-tree { /* for testing purpose */
-                       label = "qspi-device-tree";
-                       reg = <0x600000 0x20000>;
-               };
-               partition@qspi-rootfs { /* for testing purpose */
-                       label = "qspi-rootfs";
-                       reg = <0x620000 0x5E0000>;
-               };
-       };
-};
-
-&sata {
-       status = "okay";
-       ceva,broken-gen2;
-       /* SATA Phy OOB timing settings */
-       ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
-       ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
-       ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
-       ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
-       ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
-       ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
-       ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
-       ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
-};
-
-&sdhci0 {
-       status = "okay";
-       bus-width = <8>;
-       xlnx,mio_bank = <2>;
-};
-
-&sdhci1 {
-       status = "okay";
-       xlnx,mio_bank = <1>;
-};
-
-&spi0 {
-       status = "okay";
-       num-cs = <1>;
-       spi0_flash0: spi0_flash0@0 {
-               compatible = "m25p80";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               spi-max-frequency = <50000000>;
-               reg = <0>;
-
-               spi0_flash0@0 {
-                       label = "spi0_flash0";
-                       reg = <0x0 0x100000>;
-               };
-       };
-};
-
-&spi1 {
-       status = "okay";
-       num-cs = <1>;
-       spi1_flash0: spi1_flash0@0 {
-               compatible = "m25p80";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               spi-max-frequency = <50000000>;
-               reg = <0>;
-
-               spi1_flash0@0 {
-                       label = "spi1_flash0";
-                       reg = <0x0 0x100000>;
-               };
-       };
-};
-
-&uart0 {
-       status = "okay";
-};
-
-&usb0 {
-       status = "okay";
-};
-
-&dwc3_0 {
-       status = "okay";
-       dr_mode = "peripheral";
-       maximum-speed = "high-speed";
-};
-
-&usb1 {
-       status = "okay";
-};
-
-&dwc3_1 {
-       status = "okay";
-       dr_mode = "host";
-       maximum-speed = "high-speed";
-};
-
-&watchdog0 {
-       status = "okay";
-};
-
-&xlnx_dp {
-       xlnx,max-pclock-frequency = <200000>;
-};
-
-&xlnx_dpdma {
-       xlnx,axi-clock-freq = <200000000>;
-};

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 04d82c4d2ec96160548a01824153d6f3d822d5a4..9062ffe919e155ffeae14c7ca8246d7fcf9b4750 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm015-dc1 RevA";

diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 7dfe960135a5d0d54590f04bb05b18ff098537c6..bf43bf8748855601f62fb11b82ce95de353ea31f 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm016-dc2 RevA";

diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 648e3ba79939540b37120d4ed6b068d3917eb70b..39c82c592f73d60fe7746deade475126c8922389 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm018-dc4";

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index f3020a57600a26ea6e398157f479827e56b8b872..c774b866fb146730929f75ef637839e0d603541d 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 / {
        model = "ZynqMP zc1751-xm019-dc5 RevA";
        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 64a883b96e3a182fa028052dac737024b09ef5a9..2be6eb0eb5ebacc06d91617155b5f2dbd66814bf 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 #include <dt-bindings/phy/phy.h>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac344ad76a65bcc6a27751d643e0b9f77c4..af68af471e19d59b3f7bb1311cdef893b07af2a5 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
 #define QSPI0_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x00550000)
 #define DSPI1_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x01100000)
 
+#define GPIO1_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x1330000)
+
 #define LPUART_BASE                            (CONFIG_SYS_IMMR + 0x01950000)
 
 #define AHCI_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x02200000)
@@ -200,6 +205,8 @@ struct sys_info {
 
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1               0x0
+#define DCFG_DCSR_ECCCR2               0x524
+#define DISABLE_PFE_ECC                        BIT(13)
 
 struct ccsr_gur {
        u32     porsr1;         /* POR status 1 */
@@ -390,6 +397,29 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
 
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO          BIT(3)
+#define SCFG_RGMIIPCR_SETSP_1000M      BIT(2)
+#define SCFG_RGMIIPCR_SETSP_100M       0
+#define SCFG_RGMIIPCR_SETSP_10M                BIT(1)
+#define SCFG_RGMIIPCR_SETFD            BIT(0)
+
+/* PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0         BIT(31)
+#define SCFG_PFEASBCR_AWCACHE0         BIT(30)
+#define SCFG_PFEASBCR_ARCACHE1         BIT(29)
+#define SCFG_PFEASBCR_AWCACHE1         BIT(28)
+#define SCFG_PFEASBCR_ARSNP            BIT(27)
+#define SCFG_PFEASBCR_AWSNP            BIT(26)
+
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS          GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS          GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS          GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS          GENMASK(23, 20)
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
        u8 res_000[0x100-0x000];
@@ -407,7 +437,12 @@ struct ccsr_scfg {
        u8 res_140[0x158-0x140];
        u32 altcbar;
        u32 qspi_cfg;
-       u8 res_160[0x180-0x160];
+       u8 res_160[0x164 - 0x160];
+       u32 wr_qos1;
+       u32 wr_qos2;
+       u32 rd_qos1;
+       u32 rd_qos2;
+       u8 res_174[0x180 - 0x174];
        u32 dmamcr;
        u8 res_184[0x188-0x184];
        u32 gic_align;
@@ -438,7 +473,21 @@ struct ccsr_scfg {
        u32 usb_refclk_selcr1;
        u32 usb_refclk_selcr2;
        u32 usb_refclk_selcr3;
-       u8 res_424[0x600-0x424];
+       u8 res_424[0x434 - 0x424];
+       u32 rgmiipcr;
+       u32 res_438;
+       u32 rgmiipsr;
+       u32 pfepfcssr1;
+       u32 pfeintencr1;
+       u32 pfepfcssr2;
+       u32 pfeintencr2;
+       u32 pfeerrcr;
+       u32 pfeeerrintencr;
+       u32 pfeasbcr;
+       u32 pfebsbcr;
+       u8 res_460[0x484 - 0x460];
+       u32 mdioselcr;
+       u8 res_468[0x600 - 0x488];
        u32 scratchrw[4];
        u8 res_610[0x680-0x610];
        u32 corebcr;
@@ -591,6 +640,16 @@ struct ccsr_serdes {
        u8      res_19a0[0x2000-0x19a0];        /* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+       u32     gpdir;
+       u32     gpodr;
+       u32     gpdat;
+       u32     gpier;
+       u32     gpimr;
+       u32     gpicr;
+       u32     gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0                      (SMMU_BASE + 0x0)
 #define SMMU_SCR1                      (SMMU_BASE + 0x4)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d866abf0974bf541fb3acd10e4f317a5aa7..fe97a930e5f39347d16e61f126583fbe6dcfd3c8 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
        CSU_CSLX_PCIE3_IO,
        CSU_CSLX_USB3 = 20,
        CSU_CSLX_USB2,
+       CSU_CSLX_PFE = 23,
        CSU_CSLX_SERDES = 32,
        CSU_CSLX_QDMA,
        CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
         {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
         {CSU_CSLX_USB3, CSU_ALL_RW},
         {CSU_CSLX_USB2, CSU_ALL_RW},
+        {CSU_CSLX_PFE, CSU_ALL_RW},
         {CSU_CSLX_SERDES, CSU_ALL_RW},
         {CSU_CSLX_QDMA, CSU_ALL_RW},
         {CSU_CSLX_LPUART2, CSU_ALL_RW},

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5b38afc1500c1225bda737a0b02a927ab5..d9bfddb23b1ab488404f29bab3c6d0d348d86cc6 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
 #endif
 
 void cpu_name(char *name);

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
index d995b7db14cfba72f1b09d091a19bad76442cd6d..eaae10bdebc2ea12a979b2ab5a5de0ea33621300 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
@@ -80,413 +80,4 @@ struct rk3036_grf {
 };
 check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
 
-/* GRF_GPIO0A_IOMUX */
-enum {
-       GPIO0A3_SHIFT           = 6,
-       GPIO0A3_MASK            = 1 << GPIO0A3_SHIFT,
-       GPIO0A3_GPIO            = 0,
-       GPIO0A3_I2C1_SDA,
-
-       GPIO0A2_SHIFT           = 4,
-       GPIO0A2_MASK            = 1 << GPIO0A2_SHIFT,
-       GPIO0A2_GPIO            = 0,
-       GPIO0A2_I2C1_SCL,
-
-       GPIO0A1_SHIFT           = 2,
-       GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
-       GPIO0A1_GPIO            = 0,
-       GPIO0A1_I2C0_SDA,
-       GPIO0A1_PWM2,
-
-       GPIO0A0_SHIFT           = 0,
-       GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
-       GPIO0A0_GPIO            = 0,
-       GPIO0A0_I2C0_SCL,
-       GPIO0A0_PWM1,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
-       GPIO0B6_SHIFT           = 12,
-       GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
-       GPIO0B6_GPIO            = 0,
-       GPIO0B6_MMC1_D3,
-       GPIO0B6_I2S1_SCLK,
-
-       GPIO0B5_SHIFT           = 10,
-       GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
-       GPIO0B5_GPIO            = 0,
-       GPIO0B5_MMC1_D2,
-       GPIO0B5_I2S1_SDI,
-
-       GPIO0B4_SHIFT           = 8,
-       GPIO0B4_MASK            = 3 << GPIO0B4_SHIFT,
-       GPIO0B4_GPIO            = 0,
-       GPIO0B4_MMC1_D1,
-       GPIO0B4_I2S1_LRCKTX,
-
-       GPIO0B3_SHIFT           = 6,
-       GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
-       GPIO0B3_GPIO            = 0,
-       GPIO0B3_MMC1_D0,
-       GPIO0B3_I2S1_LRCKRX,
-
-       GPIO0B1_SHIFT           = 2,
-       GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
-       GPIO0B1_GPIO            = 0,
-       GPIO0B1_MMC1_CLKOUT,
-       GPIO0B1_I2S1_MCLK,
-
-       GPIO0B0_SHIFT           = 0,
-       GPIO0B0_MASK            = 3,
-       GPIO0B0_GPIO            = 0,
-       GPIO0B0_MMC1_CMD,
-       GPIO0B0_I2S1_SDO,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
-       GPIO0C4_SHIFT           = 8,
-       GPIO0C4_MASK            = 1 << GPIO0C4_SHIFT,
-       GPIO0C4_GPIO            = 0,
-       GPIO0C4_DRIVE_VBUS,
-
-       GPIO0C3_SHIFT           = 6,
-       GPIO0C3_MASK            = 1 << GPIO0C3_SHIFT,
-       GPIO0C3_GPIO            = 0,
-       GPIO0C3_UART0_CTSN,
-
-       GPIO0C2_SHIFT           = 4,
-       GPIO0C2_MASK            = 1 << GPIO0C2_SHIFT,
-       GPIO0C2_GPIO            = 0,
-       GPIO0C2_UART0_RTSN,
-
-       GPIO0C1_SHIFT           = 2,
-       GPIO0C1_MASK            = 1 << GPIO0C1_SHIFT,
-       GPIO0C1_GPIO            = 0,
-       GPIO0C1_UART0_SIN,
-
-
-       GPIO0C0_SHIFT           = 0,
-       GPIO0C0_MASK            = 1 << GPIO0C0_SHIFT,
-       GPIO0C0_GPIO            = 0,
-       GPIO0C0_UART0_SOUT,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
-       GPIO0D4_SHIFT           = 8,
-       GPIO0D4_MASK            = 1 << GPIO0D4_SHIFT,
-       GPIO0D4_GPIO            = 0,
-       GPIO0D4_SPDIF,
-
-       GPIO0D3_SHIFT           = 6,
-       GPIO0D3_MASK            = 1 << GPIO0D3_SHIFT,
-       GPIO0D3_GPIO            = 0,
-       GPIO0D3_PWM3,
-
-       GPIO0D2_SHIFT           = 4,
-       GPIO0D2_MASK            = 1 << GPIO0D2_SHIFT,
-       GPIO0D2_GPIO            = 0,
-       GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
-       GPIO1A5_SHIFT           = 10,
-       GPIO1A5_MASK            = 1 << GPIO1A5_SHIFT,
-       GPIO1A5_GPIO            = 0,
-       GPIO1A5_I2S_SDI,
-
-       GPIO1A4_SHIFT           = 8,
-       GPIO1A4_MASK            = 1 << GPIO1A4_SHIFT,
-       GPIO1A4_GPIO            = 0,
-       GPIO1A4_I2S_SD0,
-
-       GPIO1A3_SHIFT           = 6,
-       GPIO1A3_MASK            = 1 << GPIO1A3_SHIFT,
-       GPIO1A3_GPIO            = 0,
-       GPIO1A3_I2S_LRCKTX,
-
-       GPIO1A2_SHIFT           = 4,
-       GPIO1A2_MASK            = 3 << GPIO1A2_SHIFT,
-       GPIO1A2_GPIO            = 0,
-       GPIO1A2_I2S_LRCKRX,
-       GPIO1A2_PWM1_0,
-
-       GPIO1A1_SHIFT           = 2,
-       GPIO1A1_MASK            = 1 << GPIO1A1_SHIFT,
-       GPIO1A1_GPIO            = 0,
-       GPIO1A1_I2S_SCLK,
-
-       GPIO1A0_SHIFT           = 0,
-       GPIO1A0_MASK            = 1 << GPIO1A0_SHIFT,
-       GPIO1A0_GPIO            = 0,
-       GPIO1A0_I2S_MCLK,
-
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
-       GPIO1B7_SHIFT           = 14,
-       GPIO1B7_MASK            = 1 << GPIO1B7_SHIFT,
-       GPIO1B7_GPIO            = 0,
-       GPIO1B7_MMC0_CMD,
-
-       GPIO1B3_SHIFT           = 6,
-       GPIO1B3_MASK            = 1 << GPIO1B3_SHIFT,
-       GPIO1B3_GPIO            = 0,
-       GPIO1B3_HDMI_HPD,
-
-       GPIO1B2_SHIFT           = 4,
-       GPIO1B2_MASK            = 1 << GPIO1B2_SHIFT,
-       GPIO1B2_GPIO            = 0,
-       GPIO1B2_HDMI_SCL,
-
-       GPIO1B1_SHIFT           = 2,
-       GPIO1B1_MASK            = 1 << GPIO1B1_SHIFT,
-       GPIO1B1_GPIO            = 0,
-       GPIO1B1_HDMI_SDA,
-
-       GPIO1B0_SHIFT           = 0,
-       GPIO1B0_MASK            = 1 << GPIO1B0_SHIFT,
-       GPIO1B0_GPIO            = 0,
-       GPIO1B0_HDMI_CEC,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
-       GPIO1C5_SHIFT           = 10,
-       GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
-       GPIO1C5_GPIO            = 0,
-       GPIO1C5_MMC0_D3,
-       GPIO1C5_JTAG_TMS,
-
-       GPIO1C4_SHIFT           = 8,
-       GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
-       GPIO1C4_GPIO            = 0,
-       GPIO1C4_MMC0_D2,
-       GPIO1C4_JTAG_TCK,
-
-       GPIO1C3_SHIFT           = 6,
-       GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
-       GPIO1C3_GPIO            = 0,
-       GPIO1C3_MMC0_D1,
-       GPIO1C3_UART2_SOUT,
-
-       GPIO1C2_SHIFT           = 4,
-       GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT ,
-       GPIO1C2_GPIO            = 0,
-       GPIO1C2_MMC0_D0,
-       GPIO1C2_UART2_SIN,
-
-       GPIO1C1_SHIFT           = 2,
-       GPIO1C1_MASK            = 1 << GPIO1C1_SHIFT,
-       GPIO1C1_GPIO            = 0,
-       GPIO1C1_MMC0_DETN,
-
-       GPIO1C0_SHIFT           = 0,
-       GPIO1C0_MASK            = 1 << GPIO1C0_SHIFT,
-       GPIO1C0_GPIO            = 0,
-       GPIO1C0_MMC0_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
-       GPIO1D7_SHIFT           = 14,
-       GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
-       GPIO1D7_GPIO            = 0,
-       GPIO1D7_NAND_D7,
-       GPIO1D7_EMMC_D7,
-       GPIO1D7_SPI_CSN1,
-
-       GPIO1D6_SHIFT           = 12,
-       GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
-       GPIO1D6_GPIO            = 0,
-       GPIO1D6_NAND_D6,
-       GPIO1D6_EMMC_D6,
-       GPIO1D6_SPI_CSN0,
-
-       GPIO1D5_SHIFT           = 10,
-       GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
-       GPIO1D5_GPIO            = 0,
-       GPIO1D5_NAND_D5,
-       GPIO1D5_EMMC_D5,
-       GPIO1D5_SPI_TXD,
-
-       GPIO1D4_SHIFT           = 8,
-       GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
-       GPIO1D4_GPIO            = 0,
-       GPIO1D4_NAND_D4,
-       GPIO1D4_EMMC_D4,
-       GPIO1D4_SPI_RXD,
-
-       GPIO1D3_SHIFT           = 6,
-       GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
-       GPIO1D3_GPIO            = 0,
-       GPIO1D3_NAND_D3,
-       GPIO1D3_EMMC_D3,
-       GPIO1D3_SFC_SIO3,
-
-       GPIO1D2_SHIFT           = 4,
-       GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
-       GPIO1D2_GPIO            = 0,
-       GPIO1D2_NAND_D2,
-       GPIO1D2_EMMC_D2,
-       GPIO1D2_SFC_SIO2,
-
-       GPIO1D1_SHIFT           = 2,
-       GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
-       GPIO1D1_GPIO            = 0,
-       GPIO1D1_NAND_D1,
-       GPIO1D1_EMMC_D1,
-       GPIO1D1_SFC_SIO1,
-
-       GPIO1D0_SHIFT           = 0,
-       GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
-       GPIO1D0_GPIO            = 0,
-       GPIO1D0_NAND_D0,
-       GPIO1D0_EMMC_D0,
-       GPIO1D0_SFC_SIO0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
-       GPIO2A7_SHIFT           = 14,
-       GPIO2A7_MASK            = 1 << GPIO2A7_SHIFT,
-       GPIO2A7_GPIO            = 0,
-       GPIO2A7_TESTCLK_OUT,
-
-       GPIO2A6_SHIFT           = 12,
-       GPIO2A6_MASK            = 1 << GPIO2A6_SHIFT,
-       GPIO2A6_GPIO            = 0,
-       GPIO2A6_NAND_CS0,
-
-       GPIO2A4_SHIFT           = 8,
-       GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
-       GPIO2A4_GPIO            = 0,
-       GPIO2A4_NAND_RDY,
-       GPIO2A4_EMMC_CMD,
-       GPIO2A3_SFC_CLK,
-
-       GPIO2A3_SHIFT           = 6,
-       GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
-       GPIO2A3_GPIO            = 0,
-       GPIO2A3_NAND_RDN,
-       GPIO2A4_SFC_CSN1,
-
-       GPIO2A2_SHIFT           = 4,
-       GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
-       GPIO2A2_GPIO            = 0,
-       GPIO2A2_NAND_WRN,
-       GPIO2A4_SFC_CSN0,
-
-       GPIO2A1_SHIFT           = 2,
-       GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
-       GPIO2A1_GPIO            = 0,
-       GPIO2A1_NAND_CLE,
-       GPIO2A1_EMMC_CLKOUT,
-
-       GPIO2A0_SHIFT           = 0,
-       GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
-       GPIO2A0_GPIO            = 0,
-       GPIO2A0_NAND_ALE,
-       GPIO2A0_SPI_CLK,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
-       GPIO2B7_SHIFT           = 14,
-       GPIO2B7_MASK            = 1 << GPIO2B7_SHIFT,
-       GPIO2B7_GPIO            = 0,
-       GPIO2B7_MAC_RXER,
-
-       GPIO2B6_SHIFT           = 12,
-       GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
-       GPIO2B6_GPIO            = 0,
-       GPIO2B6_MAC_CLKOUT,
-       GPIO2B6_MAC_CLKIN,
-
-       GPIO2B5_SHIFT           = 10,
-       GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
-       GPIO2B5_GPIO            = 0,
-       GPIO2B5_MAC_TXEN,
-
-       GPIO2B4_SHIFT           = 8,
-       GPIO2B4_MASK            = 1 << GPIO2B4_SHIFT,
-       GPIO2B4_GPIO            = 0,
-       GPIO2B4_MAC_MDIO,
-
-       GPIO2B2_SHIFT           = 4,
-       GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
-       GPIO2B2_GPIO            = 0,
-       GPIO2B2_MAC_CRS,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
-       GPIO2C7_SHIFT           = 14,
-       GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
-       GPIO2C7_GPIO            = 0,
-       GPIO2C7_UART1_SOUT,
-       GPIO2C7_TESTCLK_OUT1,
-
-       GPIO2C6_SHIFT           = 12,
-       GPIO2C6_MASK            = 1 << GPIO2C6_SHIFT,
-       GPIO2C6_GPIO            = 0,
-       GPIO2C6_UART1_SIN,
-
-       GPIO2C5_SHIFT           = 10,
-       GPIO2C5_MASK            = 1 << GPIO2C5_SHIFT,
-       GPIO2C5_GPIO            = 0,
-       GPIO2C5_I2C2_SCL,
-
-       GPIO2C4_SHIFT           = 8,
-       GPIO2C4_MASK            = 1 << GPIO2C4_SHIFT,
-       GPIO2C4_GPIO            = 0,
-       GPIO2C4_I2C2_SDA,
-
-       GPIO2C3_SHIFT           = 6,
-       GPIO2C3_MASK            = 1 << GPIO2C3_SHIFT,
-       GPIO2C3_GPIO            = 0,
-       GPIO2C3_MAC_TXD0,
-
-       GPIO2C2_SHIFT           = 4,
-       GPIO2C2_MASK            = 1 << GPIO2C2_SHIFT,
-       GPIO2C2_GPIO            = 0,
-       GPIO2C2_MAC_TXD1,
-
-       GPIO2C1_SHIFT           = 2,
-       GPIO2C1_MASK            = 1 << GPIO2C1_SHIFT,
-       GPIO2C1_GPIO            = 0,
-       GPIO2C1_MAC_RXD0,
-
-       GPIO2C0_SHIFT           = 0,
-       GPIO2C0_MASK            = 1 << GPIO2C0_SHIFT,
-       GPIO2C0_GPIO            = 0,
-       GPIO2C0_MAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
-       GPIO2D6_SHIFT           = 12,
-       GPIO2D6_MASK            = 1 << GPIO2D6_SHIFT,
-       GPIO2D6_GPIO            = 0,
-       GPIO2D6_I2S_SDO1,
-
-       GPIO2D5_SHIFT           = 10,
-       GPIO2D5_MASK            = 1 << GPIO2D5_SHIFT,
-       GPIO2D5_GPIO            = 0,
-       GPIO2D5_I2S_SDO2,
-
-       GPIO2D4_SHIFT           = 8,
-       GPIO2D4_MASK            = 1 << GPIO2D4_SHIFT,
-       GPIO2D4_GPIO            = 0,
-       GPIO2D4_I2S_SDO3,
-
-       GPIO2D1_SHIFT           = 2,
-       GPIO2D1_MASK            = 1 << GPIO2D1_SHIFT,
-       GPIO2D1_GPIO            = 0,
-       GPIO2D1_MAC_MDC,
-};
 #endif

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
index ce7bac5338063f8f4f07088e062b4726adb17532..905288e0d5f5a0dd66b36a0c65618038bb63bb65 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
@@ -69,386 +69,6 @@ struct rk3188_grf {
 };
 check_member(rk3188_grf, flash_cmd_p, 0x01a4);
 
-/* GRF_GPIO0D_IOMUX */
-enum {
-       GPIO0D7_SHIFT           = 14,
-       GPIO0D7_MASK            = 1,
-       GPIO0D7_GPIO            = 0,
-       GPIO0D7_SPI1_CSN0,
-
-       GPIO0D6_SHIFT           = 12,
-       GPIO0D6_MASK            = 1,
-       GPIO0D6_GPIO            = 0,
-       GPIO0D6_SPI1_CLK,
-
-       GPIO0D5_SHIFT           = 10,
-       GPIO0D5_MASK            = 1,
-       GPIO0D5_GPIO            = 0,
-       GPIO0D5_SPI1_TXD,
-
-       GPIO0D4_SHIFT           = 8,
-       GPIO0D4_MASK            = 1,
-       GPIO0D4_GPIO            = 0,
-       GPIO0D4_SPI0_RXD,
-
-       GPIO0D3_SHIFT           = 6,
-       GPIO0D3_MASK            = 3,
-       GPIO0D3_GPIO            = 0,
-       GPIO0D3_FLASH_CSN3,
-       GPIO0D3_EMMC_RSTN_OUT,
-
-       GPIO0D2_SHIFT           = 4,
-       GPIO0D2_MASK            = 3,
-       GPIO0D2_GPIO            = 0,
-       GPIO0D2_FLASH_CSN2,
-       GPIO0D2_EMMC_CMD,
-
-       GPIO0D1_SHIFT           = 2,
-       GPIO0D1_MASK            = 1,
-       GPIO0D1_GPIO            = 0,
-       GPIO0D1_FLASH_CSN1,
-
-       GPIO0D0_SHIFT           = 0,
-       GPIO0D0_MASK            = 3,
-       GPIO0D0_GPIO            = 0,
-       GPIO0D0_FLASH_DQS,
-       GPIO0D0_EMMC_CLKOUT
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
-       GPIO1A7_SHIFT           = 14,
-       GPIO1A7_MASK            = 3,
-       GPIO1A7_GPIO            = 0,
-       GPIO1A7_UART1_RTS_N,
-       GPIO1A7_SPI0_CSN0,
-
-       GPIO1A6_SHIFT           = 12,
-       GPIO1A6_MASK            = 3,
-       GPIO1A6_GPIO            = 0,
-       GPIO1A6_UART1_CTS_N,
-       GPIO1A6_SPI0_CLK,
-
-       GPIO1A5_SHIFT           = 10,
-       GPIO1A5_MASK            = 3,
-       GPIO1A5_GPIO            = 0,
-       GPIO1A5_UART1_SOUT,
-       GPIO1A5_SPI0_TXD,
-
-       GPIO1A4_SHIFT           = 8,
-       GPIO1A4_MASK            = 3,
-       GPIO1A4_GPIO            = 0,
-       GPIO1A4_UART1_SIN,
-       GPIO1A4_SPI0_RXD,
-
-       GPIO1A3_SHIFT           = 6,
-       GPIO1A3_MASK            = 1,
-       GPIO1A3_GPIO            = 0,
-       GPIO1A3_UART0_RTS_N,
-
-       GPIO1A2_SHIFT           = 4,
-       GPIO1A2_MASK            = 1,
-       GPIO1A2_GPIO            = 0,
-       GPIO1A2_UART0_CTS_N,
-
-       GPIO1A1_SHIFT           = 2,
-       GPIO1A1_MASK            = 1,
-       GPIO1A1_GPIO            = 0,
-       GPIO1A1_UART0_SOUT,
-
-       GPIO1A0_SHIFT           = 0,
-       GPIO1A0_MASK            = 1,
-       GPIO1A0_GPIO            = 0,
-       GPIO1A0_UART0_SIN,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
-       GPIO1B7_SHIFT           = 14,
-       GPIO1B7_MASK            = 1,
-       GPIO1B7_GPIO            = 0,
-       GPIO1B7_SPI0_CSN1,
-
-       GPIO1B6_SHIFT           = 12,
-       GPIO1B6_MASK            = 3,
-       GPIO1B6_GPIO            = 0,
-       GPIO1B6_SPDIF_TX,
-       GPIO1B6_SPI1_CSN1,
-
-       GPIO1B5_SHIFT           = 10,
-       GPIO1B5_MASK            = 3,
-       GPIO1B5_GPIO            = 0,
-       GPIO1B5_UART3_RTS_N,
-       GPIO1B5_RESERVED,
-
-       GPIO1B4_SHIFT           = 8,
-       GPIO1B4_MASK            = 3,
-       GPIO1B4_GPIO            = 0,
-       GPIO1B4_UART3_CTS_N,
-       GPIO1B4_GPS_RFCLK,
-
-       GPIO1B3_SHIFT           = 6,
-       GPIO1B3_MASK            = 3,
-       GPIO1B3_GPIO            = 0,
-       GPIO1B3_UART3_SOUT,
-       GPIO1B3_GPS_SIG,
-
-       GPIO1B2_SHIFT           = 4,
-       GPIO1B2_MASK            = 3,
-       GPIO1B2_GPIO            = 0,
-       GPIO1B2_UART3_SIN,
-       GPIO1B2_GPS_MAG,
-
-       GPIO1B1_SHIFT           = 2,
-       GPIO1B1_MASK            = 3,
-       GPIO1B1_GPIO            = 0,
-       GPIO1B1_UART2_SOUT,
-       GPIO1B1_JTAG_TDO,
-
-       GPIO1B0_SHIFT           = 0,
-       GPIO1B0_MASK            = 3,
-       GPIO1B0_GPIO            = 0,
-       GPIO1B0_UART2_SIN,
-       GPIO1B0_JTAG_TDI,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
-       GPIO1D7_SHIFT           = 14,
-       GPIO1D7_MASK            = 1,
-       GPIO1D7_GPIO            = 0,
-       GPIO1D7_I2C4_SCL,
-
-       GPIO1D6_SHIFT           = 12,
-       GPIO1D6_MASK            = 1,
-       GPIO1D6_GPIO            = 0,
-       GPIO1D6_I2C4_SDA,
-
-       GPIO1D5_SHIFT           = 10,
-       GPIO1D5_MASK            = 1,
-       GPIO1D5_GPIO            = 0,
-       GPIO1D5_I2C2_SCL,
-
-       GPIO1D4_SHIFT           = 8,
-       GPIO1D4_MASK            = 1,
-       GPIO1D4_GPIO            = 0,
-       GPIO1D4_I2C2_SDA,
-
-       GPIO1D3_SHIFT           = 6,
-       GPIO1D3_MASK            = 1,
-       GPIO1D3_GPIO            = 0,
-       GPIO1D3_I2C1_SCL,
-
-       GPIO1D2_SHIFT           = 4,
-       GPIO1D2_MASK            = 1,
-       GPIO1D2_GPIO            = 0,
-       GPIO1D2_I2C1_SDA,
-
-       GPIO1D1_SHIFT           = 2,
-       GPIO1D1_MASK            = 1,
-       GPIO1D1_GPIO            = 0,
-       GPIO1D1_I2C0_SCL,
-
-       GPIO1D0_SHIFT           = 0,
-       GPIO1D0_MASK            = 1,
-       GPIO1D0_GPIO            = 0,
-       GPIO1D0_I2C0_SDA,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
-       GPIO3A7_SHIFT           = 14,
-       GPIO3A7_MASK            = 1,
-       GPIO3A7_GPIO            = 0,
-       GPIO3A7_SDMMC0_DATA3,
-
-       GPIO3A6_SHIFT           = 12,
-       GPIO3A6_MASK            = 1,
-       GPIO3A6_GPIO            = 0,
-       GPIO3A6_SDMMC0_DATA2,
-
-       GPIO3A5_SHIFT           = 10,
-       GPIO3A5_MASK            = 1,
-       GPIO3A5_GPIO            = 0,
-       GPIO3A5_SDMMC0_DATA1,
-
-       GPIO3A4_SHIFT           = 8,
-       GPIO3A4_MASK            = 1,
-       GPIO3A4_GPIO            = 0,
-       GPIO3A4_SDMMC0_DATA0,
-
-       GPIO3A3_SHIFT           = 6,
-       GPIO3A3_MASK            = 1,
-       GPIO3A3_GPIO            = 0,
-       GPIO3A3_SDMMC0_CMD,
-
-       GPIO3A2_SHIFT           = 4,
-       GPIO3A2_MASK            = 1,
-       GPIO3A2_GPIO            = 0,
-       GPIO3A2_SDMMC0_CLKOUT,
-
-       GPIO3A1_SHIFT           = 2,
-       GPIO3A1_MASK            = 1,
-       GPIO3A1_GPIO            = 0,
-       GPIO3A1_SDMMC0_PWREN,
-
-       GPIO3A0_SHIFT           = 0,
-       GPIO3A0_MASK            = 1,
-       GPIO3A0_GPIO            = 0,
-       GPIO3A0_SDMMC0_RSTN,
-};
-
-/* GRF_GPIO3B_IOMUX */
-enum {
-       GPIO3B7_SHIFT           = 14,
-       GPIO3B7_MASK            = 3,
-       GPIO3B7_GPIO            = 0,
-       GPIO3B7_CIF_DATA11,
-       GPIO3B7_I2C3_SCL,
-
-       GPIO3B6_SHIFT           = 12,
-       GPIO3B6_MASK            = 3,
-       GPIO3B6_GPIO            = 0,
-       GPIO3B6_CIF_DATA10,
-       GPIO3B6_I2C3_SDA,
-
-       GPIO3B5_SHIFT           = 10,
-       GPIO3B5_MASK            = 3,
-       GPIO3B5_GPIO            = 0,
-       GPIO3B5_CIF_DATA1,
-       GPIO3B5_HSADC_DATA9,
-
-       GPIO3B4_SHIFT           = 8,
-       GPIO3B4_MASK            = 3,
-       GPIO3B4_GPIO            = 0,
-       GPIO3B4_CIF_DATA0,
-       GPIO3B4_HSADC_DATA8,
-
-       GPIO3B3_SHIFT           = 6,
-       GPIO3B3_MASK            = 1,
-       GPIO3B3_GPIO            = 0,
-       GPIO3B3_CIF_CLKOUT,
-
-       GPIO3B2_SHIFT           = 4,
-       GPIO3B2_MASK            = 1,
-       GPIO3B2_GPIO            = 0,
-       /* no muxes */
-
-       GPIO3B1_SHIFT           = 2,
-       GPIO3B1_MASK            = 1,
-       GPIO3B1_GPIO            = 0,
-       GPIO3B1_SDMMC0_WRITE_PRT,
-
-       GPIO3B0_SHIFT           = 0,
-       GPIO3B0_MASK            = 1,
-       GPIO3B0_GPIO            = 0,
-       GPIO3B0_SDMMC_DETECT_N,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
-       GPIO3C7_SHIFT           = 14,
-       GPIO3C7_MASK            = 3,
-       GPIO3C7_GPIO            = 0,
-       GPIO3C7_SDMMC1_WRITE_PRT,
-       GPIO3C7_RMII_CRS_DVALID,
-       GPIO3C7_RESERVED,
-
-       GPIO3C6_SHIFT           = 12,
-       GPIO3C6_MASK            = 3,
-       GPIO3C6_GPIO            = 0,
-       GPIO3C6_SDMMC1_DECTN,
-       GPIO3C6_RMII_RX_ERR,
-       GPIO3C6_RESERVED,
-
-       GPIO3C5_SHIFT           = 10,
-       GPIO3C5_MASK            = 3,
-       GPIO3C5_GPIO            = 0,
-       GPIO3C5_SDMMC1_CLKOUT,
-       GPIO3C5_RMII_CLKOUT,
-       GPIO3C5_RMII_CLKIN,
-
-       GPIO3C4_SHIFT           = 8,
-       GPIO3C4_MASK            = 3,
-       GPIO3C4_GPIO            = 0,
-       GPIO3C4_SDMMC1_DATA3,
-       GPIO3C4_RMII_RXD1,
-       GPIO3C4_RESERVED,
-
-       GPIO3C3_SHIFT           = 6,
-       GPIO3C3_MASK            = 3,
-       GPIO3C3_GPIO            = 0,
-       GPIO3C3_SDMMC1_DATA2,
-       GPIO3C3_RMII_RXD0,
-       GPIO3C3_RESERVED,
-
-       GPIO3C2_SHIFT           = 4,
-       GPIO3C2_MASK            = 3,
-       GPIO3C2_GPIO            = 0,
-       GPIO3C2_SDMMC1_DATA1,
-       GPIO3C2_RMII_TXD0,
-       GPIO3C2_RESERVED,
-
-       GPIO3C1_SHIFT           = 2,
-       GPIO3C1_MASK            = 3,
-       GPIO3C1_GPIO            = 0,
-       GPIO3C1_SDMMC1_DATA0,
-       GPIO3C1_RMII_TXD1,
-       GPIO3C1_RESERVED,
-
-       GPIO3C0_SHIFT           = 0,
-       GPIO3C0_MASK            = 3,
-       GPIO3C0_GPIO            = 0,
-       GPIO3C0_SDMMC1_CMD,
-       GPIO3C0_RMII_TX_EN,
-       GPIO3C0_RESERVED,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
-       GPIO3D6_SHIFT           = 12,
-       GPIO3D6_MASK            = 3,
-       GPIO3D6_GPIO            = 0,
-       GPIO3D6_PWM_3,
-       GPIO3D6_JTAG_TMS,
-       GPIO3D6_HOST_DRV_VBUS,
-
-       GPIO3D5_SHIFT           = 10,
-       GPIO3D5_MASK            = 3,
-       GPIO3D5_GPIO            = 0,
-       GPIO3D5_PWM_2,
-       GPIO3D5_JTAG_TCK,
-       GPIO3D5_OTG_DRV_VBUS,
-
-       GPIO3D4_SHIFT           = 8,
-       GPIO3D4_MASK            = 3,
-       GPIO3D4_GPIO            = 0,
-       GPIO3D4_PWM_1,
-       GPIO3D4_JTAG_TRSTN,
-
-       GPIO3D3_SHIFT           = 6,
-       GPIO3D3_MASK            = 3,
-       GPIO3D3_GPIO            = 0,
-       GPIO3D3_PWM_0,
-
-       GPIO3D2_SHIFT           = 4,
-       GPIO3D2_MASK            = 3,
-       GPIO3D2_GPIO            = 0,
-       GPIO3D2_SDMMC1_INT_N,
-
-       GPIO3D1_SHIFT           = 2,
-       GPIO3D1_MASK            = 3,
-       GPIO3D1_GPIO            = 0,
-       GPIO3D1_SDMMC1_BACKEND_PWR,
-       GPIO3D1_MII_MDCLK,
-
-       GPIO3D0_SHIFT           = 0,
-       GPIO3D0_MASK            = 3,
-       GPIO3D0_GPIO            = 0,
-       GPIO3D0_SDMMC1_PWR_EN,
-       GPIO3D0_MII_MD,
-};
-
 /* GRF_SOC_CON0 */
 enum {
        HSADC_CLK_DIR_SHIFT     = 15,

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index b541e2caa1855bc6593bbbbdc557961da46b0b4f..91e8d2d216fca3c30f2832bae27cc63b0f63494b 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -324,13 +324,29 @@ struct rk3399_pmusgrf_regs {
 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
 
 enum {
+       /* GRF_GPIO2A_IOMUX */
+       GRF_GPIO2A0_SEL_SHIFT   = 0,
+       GRF_GPIO2A0_SEL_MASK    = 3 << GRF_GPIO2A0_SEL_SHIFT,
+       GRF_I2C2_SDA            = 2,
+       GRF_GPIO2A1_SEL_SHIFT   = 2,
+       GRF_GPIO2A1_SEL_MASK    = 3 << GRF_GPIO2A1_SEL_SHIFT,
+       GRF_I2C2_SCL            = 2,
+       GRF_GPIO2A7_SEL_SHIFT   = 14,
+       GRF_GPIO2A7_SEL_MASK    = 3 << GRF_GPIO2A7_SEL_SHIFT,
+       GRF_I2C7_SDA            = 2,
+
        /* GRF_GPIO2B_IOMUX */
-       GRF_GPIO2B1_SEL_SHIFT   = 0,
+       GRF_GPIO2B0_SEL_SHIFT   = 0,
+       GRF_GPIO2B0_SEL_MASK    = 3 << GRF_GPIO2B0_SEL_SHIFT,
+       GRF_I2C7_SCL            = 2,
+       GRF_GPIO2B1_SEL_SHIFT   = 2,
        GRF_GPIO2B1_SEL_MASK    = 3 << GRF_GPIO2B1_SEL_SHIFT,
        GRF_SPI2TPM_RXD         = 1,
-       GRF_GPIO2B2_SEL_SHIFT   = 2,
+       GRF_I2C6_SDA            = 2,
+       GRF_GPIO2B2_SEL_SHIFT   = 4,
        GRF_GPIO2B2_SEL_MASK    = 3 << GRF_GPIO2B2_SEL_SHIFT,
        GRF_SPI2TPM_TXD         = 1,
+       GRF_I2C6_SCL            = 2,
        GRF_GPIO2B3_SEL_SHIFT   = 6,
        GRF_GPIO2B3_SEL_MASK    = 3 << GRF_GPIO2B3_SEL_SHIFT,
        GRF_SPI2TPM_CLK         = 1,
@@ -414,6 +430,14 @@ enum {
        GRF_GPIO3C1_SEL_MASK    = 3 << GRF_GPIO3C1_SEL_SHIFT,
        GRF_MAC_TXCLK           = 1,
 
+       /* GRF_GPIO4A_IOMUX */
+       GRF_GPIO4A1_SEL_SHIFT   = 2,
+       GRF_GPIO4A1_SEL_MASK    = 3 << GRF_GPIO4A1_SEL_SHIFT,
+       GRF_I2C1_SDA            = 1,
+       GRF_GPIO4A2_SEL_SHIFT   = 4,
+       GRF_GPIO4A2_SEL_MASK    = 3 << GRF_GPIO4A2_SEL_SHIFT,
+       GRF_I2C1_SCL            = 1,
+
        /* GRF_GPIO4B_IOMUX */
        GRF_GPIO4B0_SEL_SHIFT   = 0,
        GRF_GPIO4B0_SEL_MASK    = 3 << GRF_GPIO4B0_SEL_SHIFT,
@@ -575,6 +599,12 @@ enum {
        PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
        PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
        PMUGRF_SPI1EC_CSN0      = 2,
+       PMUGRF_GPIO1B3_SEL_SHIFT        = 6,
+       PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
+       PMUGRF_I2C4_SDA         = 1,
+       PMUGRF_GPIO1B4_SEL_SHIFT        = 8,
+       PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
+       PMUGRF_I2C4_SCL         = 1,
        PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
        PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
        PMUGRF_PWM_3B           = 1,

diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 084d55a2b01f5ae5f64bf54cd5f60052ff2432af..ad3dc9aba50d0b956f575bb21dba9b4dbb74a47b 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -11,6 +11,8 @@
 #define PAYLOAD_ARG_CNT                5
 
 #define ZYNQMP_CSU_SILICON_VER_MASK    0xF
+#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD      0xC200002D
+#define KEY_PTR_LEN    32
 
 enum {
        IDCODE,

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 30752839a3152999e7fbcaa21736010b7353c836..5e7baba3fe49a540b7ad41b86ebeded45785f208 100644 (file)
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -58,6 +58,7 @@ config SOC_DA850
 config SOC_DA8XX
        bool
        select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+       select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
 
 config MACH_DAVINCI_DA850_EVM
        bool

diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c
index b9214f7bd9e1356e74e118271bae8a093588f1d0..ab4164cbe00d7f925478e4d787dbe2490fdb81c3 100644 (file)
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -45,6 +45,14 @@ static struct mm_region mvebu_mem_map[] = {
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE
        },
+       {
+               /* PCI regions */
+               .phys = 0xe8000000UL,
+               .virt = 0xe8000000UL,
+               .size = 0x02000000UL,   /* 32MiB master PCI space */
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE
+       },
        {
                /* List terminator */
                0,

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
new file mode 100644 (file)
index 0000000..8c755f8
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -0,0 +1,43 @@
+if ARCH_STM32MP
+
+config SPL
+       select SPL_BOARD_INIT
+       select SPL_CLK
+       select SPL_DM
+       select SPL_DM_SEQ_ALIAS
+       select SPL_FRAMEWORK
+       select SPL_GPIO_SUPPORT
+       select SPL_LIBCOMMON_SUPPORT
+       select SPL_LIBGENERIC_SUPPORT
+       select SPL_OF_CONTROL
+       select SPL_OF_TRANSLATE
+       select SPL_PINCTRL
+       select SPL_REGMAP
+       select SPL_RESET_SUPPORT
+       select SPL_SERIAL_SUPPORT
+       select SPL_SYSCON
+       imply SPL_LIBDISK_SUPPORT
+
+config SYS_SOC
+       default "stm32mp"
+
+config TARGET_STM32MP1
+       bool "Support stm32mp1xx"
+       select CPU_V7
+       select PINCTRL_STM32
+       select STM32_RESET
+       help
+               target STMicroelectronics SOC STM32MP1 family
+               STMicroelectronics MPU with core ARMv7
+
+config SYS_TEXT_BASE
+       prompt "U-Boot base address"
+       default 0xC0100000
+       help
+               configure the U-Boot base address
+               when DDR driver is used:
+                 DDR + 1MB (0xC0100000)
+
+source "board/st/stm32mp1/Kconfig"
+
+endif

diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
new file mode 100644 (file)
index 0000000..4620869
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
+#
+
+obj-y += cpu.o
+obj-y += dram_init.o
+
+obj-$(CONFIG_SPL_BUILD) += spl.o

diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk
new file mode 100644 (file)
index 0000000..34e59c6
--- /dev/null
+++ b/arch/arm/mach-stm32mp/config.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
+#
+
+ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32
+
+MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
+
+spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
+
+spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
+       $(call if_changed,mkimage)

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
new file mode 100644 (file)
index 0000000..7c43dc1
--- /dev/null
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+#include <common.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+/**********************************************
+ * Security init
+ *********************************************/
+#define ETZPC_TZMA1_SIZE       (STM32_ETZPC_BASE + 0x04)
+#define ETZPC_DECPROT0         (STM32_ETZPC_BASE + 0x10)
+
+#define TZC_GATE_KEEPER                (STM32_TZC_BASE + 0x008)
+#define TZC_REGION_ATTRIBUTE0  (STM32_TZC_BASE + 0x110)
+#define TZC_REGION_ID_ACCESS0  (STM32_TZC_BASE + 0x114)
+
+#define TAMP_CR1               (STM32_TAMP_BASE + 0x00)
+
+#define PWR_CR1                        (STM32_PWR_BASE + 0x00)
+#define PWR_CR1_DBP            BIT(8)
+
+#define RCC_TZCR               (STM32_RCC_BASE + 0x00)
+#define RCC_BDCR               (STM32_RCC_BASE + 0x0140)
+#define RCC_MP_APB5ENSETR      (STM32_RCC_BASE + 0x0208)
+
+#define RCC_BDCR_VSWRST                BIT(31)
+#define RCC_BDCR_RTCSRC                GENMASK(17, 16)
+
+static void security_init(void)
+{
+       /* Disable the backup domain write protection */
+       /* the protection is enable at each reset by hardware */
+       /* And must be disable by software */
+       setbits_le32(PWR_CR1, PWR_CR1_DBP);
+
+       while (!(readl(PWR_CR1) & PWR_CR1_DBP))
+               ;
+
+       /* If RTC clock isn't enable so this is a cold boot then we need
+        * to reset the backup domain
+        */
+       if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
+               setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+               while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
+                       ;
+               clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+       }
+
+       /* allow non secure access in Write/Read for all peripheral */
+       writel(GENMASK(25, 0), ETZPC_DECPROT0);
+
+       /* Open SYSRAM for no secure access */
+       writel(0x0, ETZPC_TZMA1_SIZE);
+
+       /* enable TZC1 TZC2 clock */
+       writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
+
+       /* Region 0 set to no access by default */
+       /* bit 0 / 16 => nsaid0 read/write Enable
+        * bit 1 / 17 => nsaid1 read/write Enable
+        * ...
+        * bit 15 / 31 => nsaid15 read/write Enable
+        */
+       writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
+       /* bit 30 / 31 => Secure Global Enable : write/read */
+       /* bit 0 / 1 => Region Enable for filter 0/1 */
+       writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
+
+       /* Enable Filter 0 and 1 */
+       setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
+
+       /* RCC trust zone deactivated */
+       writel(0x0, RCC_TZCR);
+
+       /* TAMP: deactivate the internal tamper
+        * Bit 23 ITAMP8E: monotonic counter overflow
+        * Bit 20 ITAMP5E: RTC calendar overflow
+        * Bit 19 ITAMP4E: HSE monitoring
+        * Bit 18 ITAMP3E: LSE monitoring
+        * Bit 16 ITAMP1E: RTC power domain supply monitoring
+        */
+       writel(0x0, TAMP_CR1);
+}
+
+/**********************************************
+ * Debug init
+ *********************************************/
+#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+
+#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
+
+static void dbgmcu_init(void)
+{
+       setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+
+       /* Freeze IWDG2 if Cortex-A7 is in debug mode */
+       setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+}
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+
+int arch_cpu_init(void)
+{
+       /* early armv7 timer init: needed for polling */
+       timer_init();
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       dbgmcu_init();
+
+       security_init();
+#endif
+
+       return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       printf("CPU: STM32MP15x\n");
+
+       return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+void reset_cpu(ulong addr)
+{
+}

diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
new file mode 100644 (file)
index 0000000..ecb4c98
--- /dev/null
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       struct ram_info ram;
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               debug("RAM init failed: %d\n", ret);
+               return ret;
+       }
+       ret = ram_get_info(dev, &ram);
+       if (ret) {
+               debug("Cannot get RAM size: %d\n", ret);
+               return ret;
+       }
+       debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+       gd->ram_size = ram.size;
+
+       return 0;
+}

diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
new file mode 100644 (file)
index 0000000..b635001
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef __MACH_STM32MP_DDR_H_
+#define __MACH_STM32MP_DDR_H_
+
+int board_ddr_power_init(void);
+
+#endif

diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h
new file mode 100644 (file)
index 0000000..5952557
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/gpio.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+#include <asm/gpio.h>
+
+enum stm32_gpio_port {
+       STM32_GPIO_PORT_A = 0,
+       STM32_GPIO_PORT_B,
+       STM32_GPIO_PORT_C,
+       STM32_GPIO_PORT_D,
+       STM32_GPIO_PORT_E,
+       STM32_GPIO_PORT_F,
+       STM32_GPIO_PORT_G,
+       STM32_GPIO_PORT_H,
+       STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+       STM32_GPIO_PIN_0 = 0,
+       STM32_GPIO_PIN_1,
+       STM32_GPIO_PIN_2,
+       STM32_GPIO_PIN_3,
+       STM32_GPIO_PIN_4,
+       STM32_GPIO_PIN_5,
+       STM32_GPIO_PIN_6,
+       STM32_GPIO_PIN_7,
+       STM32_GPIO_PIN_8,
+       STM32_GPIO_PIN_9,
+       STM32_GPIO_PIN_10,
+       STM32_GPIO_PIN_11,
+       STM32_GPIO_PIN_12,
+       STM32_GPIO_PIN_13,
+       STM32_GPIO_PIN_14,
+       STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+       STM32_GPIO_MODE_IN = 0,
+       STM32_GPIO_MODE_OUT,
+       STM32_GPIO_MODE_AF,
+       STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+       STM32_GPIO_OTYPE_PP = 0,
+       STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+       STM32_GPIO_SPEED_2M = 0,
+       STM32_GPIO_SPEED_25M,
+       STM32_GPIO_SPEED_50M,
+       STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+       STM32_GPIO_PUPD_NO = 0,
+       STM32_GPIO_PUPD_UP,
+       STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+       STM32_GPIO_AF0 = 0,
+       STM32_GPIO_AF1,
+       STM32_GPIO_AF2,
+       STM32_GPIO_AF3,
+       STM32_GPIO_AF4,
+       STM32_GPIO_AF5,
+       STM32_GPIO_AF6,
+       STM32_GPIO_AF7,
+       STM32_GPIO_AF8,
+       STM32_GPIO_AF9,
+       STM32_GPIO_AF10,
+       STM32_GPIO_AF11,
+       STM32_GPIO_AF12,
+       STM32_GPIO_AF13,
+       STM32_GPIO_AF14,
+       STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+       enum stm32_gpio_port    port;
+       enum stm32_gpio_pin     pin;
+};
+
+struct stm32_gpio_ctl {
+       enum stm32_gpio_mode    mode;
+       enum stm32_gpio_otype   otype;
+       enum stm32_gpio_speed   speed;
+       enum stm32_gpio_pupd    pupd;
+       enum stm32_gpio_af      af;
+};
+
+struct stm32_gpio_regs {
+       u32 moder;      /* GPIO port mode */
+       u32 otyper;     /* GPIO port output type */
+       u32 ospeedr;    /* GPIO port output speed */
+       u32 pupdr;      /* GPIO port pull-up/pull-down */
+       u32 idr;        /* GPIO port input data */
+       u32 odr;        /* GPIO port output data */
+       u32 bsrr;       /* GPIO port bit set/reset */
+       u32 lckr;       /* GPIO port configuration lock */
+       u32 afr[2];     /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+       struct stm32_gpio_regs *regs;
+};
+#endif /* _STM32_GPIO_H_ */

diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
new file mode 100644 (file)
index 0000000..ffbe0b1
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ * only address used before device tree parsing
+ */
+#define STM32_RCC_BASE                 0x50000000
+#define STM32_PWR_BASE                 0x50001000
+#define STM32_DBGMCU_BASE              0x50081000
+#define STM32_TZC_BASE                 0x5C006000
+#define STM32_ETZPC_BASE               0x5C007000
+#define STM32_TAMP_BASE                        0x5C00A000
+
+#define STM32_SYSRAM_BASE              0x2FFC0000
+#define STM32_SYSRAM_SIZE              SZ_256K
+
+#define STM32_DDR_BASE                 0xC0000000
+#define STM32_DDR_SIZE                 SZ_1G
+
+#endif /* _MACH_STM32_H_ */

diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
new file mode 100644 (file)
index 0000000..8f5962a
--- /dev/null
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+       return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+       return MMCSD_MODE_RAW;
+}
+
+void board_init_f(ulong dummy)
+{
+       struct udevice *dev;
+       int ret;
+
+       arch_cpu_init();
+
+       ret = spl_early_init();
+       if (ret) {
+               debug("spl_early_init() failed: %d\n", ret);
+               hang();
+       }
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               debug("Clock init failed: %d\n", ret);
+               return;
+       }
+
+       ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+       if (ret) {
+               debug("Reset init failed: %d\n", ret);
+               return;
+       }
+
+       ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
+       if (ret) {
+               debug("%s: Cannot find pinctrl device\n", __func__);
+               return;
+       }
+
+       /* enable console uart printing */
+       preloader_console_init();
+
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               debug("DRAM init failed: %d\n", ret);
+               return;
+       }
+}

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 840dbf170dc4681fb410c74959e74309e19f171a..e80905cf3a512807a871eb9091f807c31c685238 100644 (file)
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -15,6 +15,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
+dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 

diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi
index 54964a700989327285e4b7c85c64bf7c5b7c8ad9..015acc91735c6f39a2052973f2c0a3f97fc467dc 100644 (file)
--- a/arch/mips/dts/brcm,bcm6318.dtsi
+++ b/arch/mips/dts/brcm,bcm6318.dtsi
@@ -153,5 +153,35 @@
                        reg = <0x10004000 0x38>;
                        u-boot,dm-pre-reloc;
                };
+
+               ehci: usb-controller@10005000 {
+                       compatible = "brcm,bcm6318-ehci", "generic-ehci";
+                       reg = <0x10005000 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10005100 {
+                       compatible = "brcm,bcm6318-ohci", "generic-ohci";
+                       reg = <0x10005100 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10005200 {
+                       compatible = "brcm,bcm6318-usbh";
+                       reg = <0x10005200 0x30>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6318_CLK_USB>;
+                       clock-names = "usbh";
+                       power-domains = <&periph_pwr BCM6318_PWR_USB>;
+                       resets = <&periph_rst BCM6318_RST_USBH>;
+
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 4d4e36ccccf27a9f158c7e2c9ea941ef6bd85bc2..ade0b49e68ac35fa13873edd731f51111efd35bf 100644 (file)
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -183,6 +183,36 @@
                        status = "disabled";
                };
 
+               ehci: usb-controller@10002500 {
+                       compatible = "brcm,bcm63268-ehci", "generic-ehci";
+                       reg = <0x10002500 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10002600 {
+                       compatible = "brcm,bcm63268-ohci", "generic-ohci";
+                       reg = <0x10002600 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10002700 {
+                       compatible = "brcm,bcm63268-usbh";
+                       reg = <0x10002700 0x38>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
+                       clock-names = "usbh", "usb_ref";
+                       power-domains = <&periph_pwr BCM63268_PWR_USBH>;
+                       resets = <&periph_rst BCM63268_RST_USBH>;
+
+                       status = "disabled";
+               };
+
                memory-controller@10003000 {
                        compatible = "brcm,bcm6328-mc";
                        reg = <0x10003000 0x894>;

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index 67d9278be49b5d7fc8e73477b588a6b48a995955..4fbbcec1530dc7de5647831e5758b05b4170f85f 100644 (file)
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -153,6 +153,36 @@
                        #power-domain-cells = <1>;
                };
 
+               ehci: usb-controller@10002500 {
+                       compatible = "brcm,bcm6328-ehci", "generic-ehci";
+                       reg = <0x10002500 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10002600 {
+                       compatible = "brcm,bcm6328-ohci", "generic-ohci";
+                       reg = <0x10002600 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10002700 {
+                       compatible = "brcm,bcm6328-usbh";
+                       reg = <0x10002700 0x38>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6328_CLK_USBH>;
+                       clock-names = "usbh";
+                       power-domains = <&periph_pwr BCM6328_PWR_USBH>;
+                       resets = <&periph_rst BCM6328_RST_USBH>;
+
+                       status = "disabled";
+               };
+
                memory-controller@10003000 {
                        compatible = "brcm,bcm6328-mc";
                        reg = <0x10003000 0x864>;

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
index 540b9fea5ba9901f025ec87be5dbba513d3ec161..92fb91afc1bfd92875412f57d98a3a56c6f389ef 100644 (file)
--- a/arch/mips/dts/brcm,bcm6348.dtsi
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -135,6 +135,26 @@
                        status = "disabled";
                };
 
+               ohci: usb-controller@fffe1b00 {
+                       compatible = "brcm,bcm6348-ohci", "generic-ohci";
+                       reg = <0xfffe1b00 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@fffe1c00 {
+                       compatible = "brcm,bcm6348-usbh";
+                       reg = <0xfffe1c00 0x4>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6348_CLK_USBH>;
+                       clock-names = "usbh";
+                       resets = <&periph_rst BCM6348_RST_USBH>;
+
+                       status = "disabled";
+               };
+
                memory-controller@fffe2300 {
                        compatible = "brcm,bcm6338-mc";
                        reg = <0xfffe2300 0x38>;

diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index 1662783279f9e34b615b2eb7a4387824dc37506e..b63b53baee727319a88e9f59a7cedb65cded57d3 100644 (file)
--- a/arch/mips/dts/brcm,bcm6358.dtsi
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -164,5 +164,32 @@
                        reg = <0xfffe1200 0x4c>;
                        u-boot,dm-pre-reloc;
                };
+
+               ehci: usb-controller@fffe1300 {
+                       compatible = "brcm,bcm6358-ehci", "generic-ehci";
+                       reg = <0xfffe1300 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@fffe1400 {
+                       compatible = "brcm,bcm6358-ohci", "generic-ohci";
+                       reg = <0xfffe1400 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@fffe1500 {
+                       compatible = "brcm,bcm6358-usbh";
+                       reg = <0xfffe1500 0x28>;
+                       #phy-cells = <0>;
+                       resets = <&periph_rst BCM6358_RST_USBH>;
+
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi
new file mode 100644 (file)
index 0000000..f695ec3
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6362.dtsi
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6362-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power-domain/bcm6362-power-domain.h>
+#include <dt-bindings/reset/bcm6362-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,bcm6362";
+
+       aliases {
+               spi0 = &lsspi;
+               spi1 = &hsspi;
+       };
+
+       cpus {
+               reg = <0x10000000 0x4>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               u-boot,dm-pre-reloc;
+
+               cpu@0 {
+                       compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <0>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               cpu@1 {
+                       compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <1>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <133333333>;
+               };
+
+               periph_osc: periph-osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               periph_clk: periph-clk {
+                       compatible = "brcm,bcm6345-clk";
+                       reg = <0x10000004 0x4>;
+                       #clock-cells = <1>;
+               };
+       };
+
+       ubus {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               pll_cntl: syscon@10000008 {
+                       compatible = "syscon";
+                       reg = <0x10000008 0x4>;
+               };
+
+               syscon-reboot {
+                       compatible = "syscon-reboot";
+                       regmap = <&pll_cntl>;
+                       offset = <0x0>;
+                       mask = <0x1>;
+               };
+
+               periph_rst: reset-controller@10000010 {
+                       compatible = "brcm,bcm6345-reset";
+                       reg = <0x10000010 0x4>;
+                       #reset-cells = <1>;
+               };
+
+               wdt: watchdog@1000005c {
+                       compatible = "brcm,bcm6345-wdt";
+                       reg = <0x1000005c 0xc>;
+                       clocks = <&periph_osc>;
+               };
+
+               wdt-reboot {
+                       compatible = "wdt-reboot";
+                       wdt = <&wdt>;
+               };
+
+               gpio1: gpio-controller@10000080 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x10000080 0x4>, <0x10000088 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <16>;
+
+                       status = "disabled";
+               };
+
+               gpio0: gpio-controller@10000084 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               uart0: serial@10000100 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000100 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               uart1: serial@10000120 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000120 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               lsspi: spi@10000800 {
+                       compatible = "brcm,bcm6358-spi";
+                       reg = <0x10000800 0x70c>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&periph_clk BCM6362_CLK_SPI>;
+                       resets = <&periph_rst BCM6362_RST_SPI>;
+                       spi-max-frequency = <20000000>;
+                       num-cs = <8>;
+
+                       status = "disabled";
+               };
+
+               hsspi: spi@10001000 {
+                       compatible = "brcm,bcm6328-hsspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x10001000 0x600>;
+                       clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       resets = <&periph_rst BCM6362_RST_SPI>;
+                       spi-max-frequency = <50000000>;
+                       num-cs = <8>;
+
+                       status = "disabled";
+               };
+
+               leds: led-controller@10001900 {
+                       compatible = "brcm,bcm6328-leds";
+                       reg = <0x10001900 0x24>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               periph_pwr: power-controller@10001848 {
+                       compatible = "brcm,bcm6328-power-domain";
+                       reg = <0x10001848 0x4>;
+                       #power-domain-cells = <1>;
+               };
+
+               ehci: usb-controller@10002500 {
+                       compatible = "brcm,bcm6362-ehci", "generic-ehci";
+                       reg = <0x10002500 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10002600 {
+                       compatible = "brcm,bcm6362-ohci", "generic-ohci";
+                       reg = <0x10002600 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10002700 {
+                       compatible = "brcm,bcm6368-usbh";
+                       reg = <0x10002700 0x38>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6362_CLK_USBH>;
+                       clock-names = "usbh";
+                       power-domains = <&periph_pwr BCM6362_PWR_USBH>;
+                       resets = <&periph_rst BCM6362_RST_USBH>;
+
+                       status = "disabled";
+               };
+
+               memory-controller@10003000 {
+                       compatible = "brcm,bcm6328-mc";
+                       reg = <0x10003000 0x864>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};

diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi
index 1bb538a1f34f33bf332ca012dc78808fdb99c4a3..fc1c5a244f0b2cfe69f968d60a42f4a93540697e 100644 (file)
--- a/arch/mips/dts/brcm,bcm6368.dtsi
+++ b/arch/mips/dts/brcm,bcm6368.dtsi
@@ -164,5 +164,34 @@
                        reg = <0x10001200 0x4c>;
                        u-boot,dm-pre-reloc;
                };
+
+               ehci: usb-controller@10001500 {
+                       compatible = "brcm,bcm6368-ehci", "generic-ehci";
+                       reg = <0x10001500 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10001600 {
+                       compatible = "brcm,bcm6368-ohci", "generic-ohci";
+                       reg = <0x10001600 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10001700 {
+                       compatible = "brcm,bcm6368-usbh";
+                       reg = <0x10001700 0x38>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6368_CLK_USBH>;
+                       clock-names = "usbh";
+                       resets = <&periph_rst BCM6368_RST_USBH>;
+
+                       status = "disabled";
+               };
        };
 };

diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts
index 4e4d69b638468f48e105668d745862376711976f..af3159a03afe8c1624652e5fbe589acc1314cace 100644 (file)
--- a/arch/mips/dts/comtrend,ar-5315u.dts
+++ b/arch/mips/dts/comtrend,ar-5315u.dts
@@ -21,6 +21,10 @@
        };
 };
 
+&ehci {
+       status = "okay";
+};
+
 &leds {
        status = "okay";
 
@@ -67,6 +71,10 @@
        };
 };
 
+&ohci {
+       status = "okay";
+};
+
 &spi {
        status = "okay";
 
@@ -83,3 +91,7 @@
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts
index 6067881a78a0113b8194e973217064b1b044da04..3a97315b3fb41f874607d058993e532a6fa46833 100644 (file)
--- a/arch/mips/dts/comtrend,ar-5387un.dts
+++ b/arch/mips/dts/comtrend,ar-5387un.dts
@@ -21,6 +21,10 @@
        };
 };
 
+&ehci {
+       status = "okay";
+};
+
 &leds {
        status = "okay";
 
@@ -51,6 +55,10 @@
        };
 };
 
+&ohci {
+       status = "okay";
+};
+
 &spi {
        status = "okay";
 
@@ -67,3 +75,7 @@
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
index c909a528a976c2853e61b2160856f3a21a600e92..74dc09046ce432ec19de62d5436b651a1ec11e95 100644 (file)
--- a/arch/mips/dts/comtrend,ct-5361.dts
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -39,6 +39,10 @@
        status = "okay";
 };
 
+&ohci {
+       status = "okay";
+};
+
 &pflash {
        status = "okay";
 };
@@ -47,3 +51,7 @@
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts
index 54e738c8210fd469e79bc59517ee7eb1b8785d69..9bbecbcdff2d32fd9e4f8dffdd364c2aacee4fe5 100644 (file)
--- a/arch/mips/dts/comtrend,vr-3032u.dts
+++ b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -21,6 +21,10 @@
        };
 };
 
+&ehci {
+       status = "okay";
+};
+
 &leds {
        status = "okay";
        brcm,serial-leds;
@@ -64,7 +68,15 @@
        };
 };
 
+&ohci {
+       status = "okay";
+};
+
 &uart0 {
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts
index 29386e2662e5f02cb23061f28d98ff495bb9c625..f1f5430b42292b816ee32dde6f2169731e7b9190 100644 (file)
--- a/arch/mips/dts/comtrend,wap-5813n.dts
+++ b/arch/mips/dts/comtrend,wap-5813n.dts
@@ -51,10 +51,18 @@
        };
 };
 
+&ehci {
+       status = "okay";
+};
+
 &gpio0 {
        status = "okay";
 };
 
+&ohci {
+       status = "okay";
+};
+
 &pflash {
        status = "okay";
 };
@@ -63,3 +71,7 @@
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts
index 31c7d7ed5ce5c1c286a331b772db0cd169709212..a1e9c15ab90c88b98cdad0b0afe6e5cbe9613b94 100644 (file)
--- a/arch/mips/dts/huawei,hg556a.dts
+++ b/arch/mips/dts/huawei,hg556a.dts
@@ -90,10 +90,18 @@
        };
 };
 
+&ehci {
+       status = "okay";
+};
+
 &gpio0 {
        status = "okay";
 };
 
+&ohci {
+       status = "okay";
+};
+
 &pflash {
        status = "okay";
 };
@@ -102,3 +110,7 @@
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts
new file mode 100644 (file)
index 0000000..8dc7d7e
--- /dev/null
+++ b/arch/mips/dts/netgear,dgnd3700v2.dts
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6362.dtsi"
+
+/ {
+       model = "Netgear DGND3700v2";
+       compatible = "netgear,dgnd3700v2", "brcm,bcm6362";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               inet_green {
+                       label = "DGND3700v2:green:inet";
+                       gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+               };
+
+               dsl_green {
+                       label = "DGND3700v2:green:dsl";
+                       gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+               };
+
+               power_amber {
+                       label = "DGND3700v2:red:power";
+                       gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+&ehci {
+       status = "okay";
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&leds {
+       status = "okay";
+       brcm,serial-leds;
+       brcm,serial-dat-low;
+       brcm,serial-shift-inv;
+       brcm,serial-mux;
+
+       led@8 {
+               reg = <8>;
+               label = "DGND3700v2:green:power";
+       };
+
+       led@9 {
+               reg = <9>;
+               active-low;
+               label = "DGND3700v2:green:wps";
+       };
+
+       led@10 {
+               reg = <10>;
+               active-low;
+               label = "DGND3700v2:green:usb1";
+       };
+
+       led@11 {
+               reg = <11>;
+               active-low;
+               label = "DGND3700v2:green:usb2";
+       };
+
+       led@12 {
+               reg = <12>;
+               active-low;
+               label = "DGND3700v2:amber:inet";
+       };
+
+       led@13 {
+               reg = <13>;
+               active-low;
+               label = "DGND3700v2:green:ethernet";
+       };
+
+       led@14 {
+               reg = <14>;
+               active-low;
+               label = "DGND3700v2:amber:dsl";
+       };
+
+       led@16 {
+               reg = <16>;
+               active-low;
+               label = "DGND3700v2:amber:usb1";
+       };
+
+       led@17 {
+               reg = <17>;
+               active-low;
+               label = "DGND3700v2:amber:usb2";
+       };
+
+       led@18 {
+               reg = <18>;
+               active-low;
+               label = "DGND3700v2:amber:ethernet";
+       };
+};
+
+&ohci {
+       status = "okay";
+};
+
+&uart0 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts
index f2092e9f999f56480175227308b11dd95bf0dc13..473372faa186429fda3c22f4fe8c121d3531a368 100644 (file)
--- a/arch/mips/dts/sfr,nb4-ser.dts
+++ b/arch/mips/dts/sfr,nb4-ser.dts
@@ -50,6 +50,10 @@
        };
 };
 
+&ehci {
+       status = "okay";
+};
+
 &gpio0 {
        status = "okay";
 };
@@ -83,6 +87,10 @@
        };
 };
 
+&ohci {
+       status = "okay";
+};
+
 &pflash {
        status = "okay";
 };
@@ -91,3 +99,7 @@
        u-boot,dm-pre-reloc;
        status = "okay";
 };
+
+&usbh {
+       status = "okay";
+};

diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index e4a0118368d346eabf726d77ec90460f19cdee44..10900bf6045ae2c1bcb765422e120662c2ef0605 100644 (file)
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -12,6 +12,7 @@ config SYS_SOC
        default "bcm6348" if SOC_BMIPS_BCM6348
        default "bcm6358" if SOC_BMIPS_BCM6358
        default "bcm6368" if SOC_BMIPS_BCM6368
+       default "bcm6362" if SOC_BMIPS_BCM6362
        default "bcm63268" if SOC_BMIPS_BCM63268
 
 choice
@@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368
        help
          This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
 
+config SOC_BMIPS_BCM6362
+       bool "BMIPS BCM6362 family"
+       select SUPPORTS_BIG_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select MIPS_TUNE_4KC
+       select MIPS_L1_CACHE_SHIFT_4
+       select SWAP_IO_SPACE
+       select SYSRESET_SYSCON
+       help
+         This supports BMIPS BCM6362 family including BCM6361 and BCM6362.
+
 config SOC_BMIPS_BCM63268
        bool "BMIPS BCM63268 family"
        select SUPPORTS_BIG_ENDIAN
@@ -188,6 +200,17 @@ config BOARD_NETGEAR_CG3100D
          ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
          (miniPCIe).
 
+config BOARD_NETGEAR_DGND3700V2
+       bool "Netgear DGND3700v2"
+       depends on SOC_BMIPS_BCM6362
+       select BMIPS_SUPPORTS_BOOT_RAM
+       help
+         Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and
+         32 MB of flash (NAND).
+         Between its different peripherals there's a BCM53125 switch with 5
+         ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a
+         BCM43228 (miniPCIe).
+
 config BOARD_SAGEM_FAST1704
        bool "Sagem F@ST1704"
        depends on SOC_BMIPS_BCM6338
@@ -235,6 +258,7 @@ source "board/comtrend/vr3032u/Kconfig"
 source "board/comtrend/wap5813n/Kconfig"
 source "board/huawei/hg556a/Kconfig"
 source "board/netgear/cg3100d/Kconfig"
+source "board/netgear/dgnd3700v2/Kconfig"
 source "board/sagem/f@st1704/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
 

diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts
index 19dc36fa157e87fbdffe1de9960cb0c395ee998e..7832efb12fbea6e273c0858f8b906a00d8077b2f 100644 (file)
--- a/arch/nds32/dts/ag101p.dts
+++ b/arch/nds32/dts/ag101p.dts
@@ -67,5 +67,6 @@
                fifo-depth = <0x10>;
                reg = <0x98e00000 0x1000>;
                interrupts = <5 4>;
+               cap-sd-highspeed;
        };
 };

diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
index b074e8489a186ef1a658a2f76781810ee6e2f0b5..9d55c9784c58aae46e635cd7183729c2719b693d 100644 (file)
--- a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
+++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
@@ -44,8 +44,6 @@
 #define CONFIG_FTGPIO010_BASE          0xf0700000
 /* I2C */
 #define CONFIG_FTIIC010_BASE           0xf0a00000
-/* SD Controller */
-#define CONFIG_FTSDC010_BASE           0xf0e00000
 
 /* The following address was not defined in Linux */
 

diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
index 490f28b62d847c6c8f455a23fbc8fe2957e929fd..0f4c3efbd4dccdcfcc87de8ef84f07b7da8084d2 100644 (file)
--- a/arch/nds32/include/asm/arch-ag101/ag101.h
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -69,8 +69,6 @@
 #define CONFIG_RESERVED_04_BASE                0x98C00000
 /* Compat Flash Controller */
 #define CONFIG_FTCFC010_BASE           0x98D00000
-/* SD Controller */
-#define CONFIG_FTSDC010_BASE           0x98E00000
 
 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */
 #define CONFIG_FTSSP010_02_BASE                0x99400000

diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
index c5ee3d94985b9fbb5dcd21b336b711bbd8a6a5ec..a8aef9381f4ab099013302b130e0d11afd992c22 100644 (file)
--- a/arch/nds32/include/asm/arch-ag102/ag102.h
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -56,8 +56,6 @@
 #define CONFIG_FTSSP010_01_BASE                0x94100000
 /* UART1 - APB STUART Controller (UART0 in Linux) */
 #define CONFIG_FTUART010_01_BASE       0x94200000
-/* FTSDC010 SD Controller */
-#define CONFIG_FTSDC010_BASE           0x94400000
 /* APB - SSP with HDA/AC97 Controller */
 #define CONFIG_FTSSP010_02_BASE                0x94500000
 /* UART2 - APB STUART Controller (UART1 in Linux) */

diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S
index 6a076639d34191f9f423a66062c64b78c5551842..cd0a66360de3da6800036e38619abbd5ff81e99c 100644 (file)
--- a/arch/riscv/cpu/nx25/start.S
+++ b/arch/riscv/cpu/nx25/start.S
@@ -45,6 +45,8 @@ trap_vector:
 
 .global trap_entry
 handle_reset:
+       li t0, CONFIG_SYS_SDRAM_BASE
+       SREG a2, 0(t0)
        la t0, trap_entry
        csrw mtvec, t0
        csrwi mstatus, 0

diff --git a/arch/riscv/dts/ae250.dts b/arch/riscv/dts/ae250.dts
index 5dc4fb04be62a4c506bbd0b309f8c48a2a2ed8dd..9a38345e36058ae88687ec88108683c11d3e1d1c 100644 (file)
--- a/arch/riscv/dts/ae250.dts
+++ b/arch/riscv/dts/ae250.dts
@@ -74,6 +74,7 @@
                fifo-depth = <0x10>;
                reg = <0xf0e00000 0x1000>;
                interrupts = <17 4>;
+               cap-sd-highspeed;
        };
 
        spi: spi@f0b00000 {

diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h
index 0a644bb58bb62d138c68d24ddf3b4eaa6aba123b..9a90f23a22e49c5f99a83a19c5743af2519e12d5 100644 (file)
--- a/arch/riscv/include/asm/bootm.h
+++ b/arch/riscv/include/asm/bootm.h
@@ -13,53 +13,4 @@
 
 #include <asm/setup.h>
 
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-               defined(CONFIG_CMDLINE_TAG) || \
-               defined(CONFIG_INITRD_TAG) || \
-               defined(CONFIG_SERIAL_TAG) || \
-               defined(CONFIG_REVISION_TAG)
-# define BOOTM_ENABLE_TAGS             1
-#else
-# define BOOTM_ENABLE_TAGS             0
-#endif
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-# define BOOTM_ENABLE_MEMORY_TAGS      1
-#else
-# define BOOTM_ENABLE_MEMORY_TAGS      0
-#endif
-
-#ifdef CONFIG_CMDLINE_TAG
- #define BOOTM_ENABLE_CMDLINE_TAG      1
-#else
- #define BOOTM_ENABLE_CMDLINE_TAG      0
-#endif
-
-#ifdef CONFIG_INITRD_TAG
- #define BOOTM_ENABLE_INITRD_TAG       1
-#else
- #define BOOTM_ENABLE_INITRD_TAG       0
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
- #define BOOTM_ENABLE_SERIAL_TAG       1
-void get_board_serial(struct tag_serialnr *serialnr);
-#else
- #define BOOTM_ENABLE_SERIAL_TAG       0
-static inline void get_board_serial(struct tag_serialnr *serialnr)
-{
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
- #define BOOTM_ENABLE_REVISION_TAG     1
-u32 get_board_rev(void);
-#else
- #define BOOTM_ENABLE_REVISION_TAG     0
-static inline u32 get_board_rev(void)
-{
-       return 0;
-}
-#endif
-
 #endif

diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 5ff6d591499fd7497c3dd51d6d7573e7a18a76d1..dbf8d45fb72f3dc6a2a7d13f7a3d06369835fd81 100644 (file)
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -121,7 +121,9 @@
 #define PTE_SW(PTE)    ((0x88888880U >> ((PTE) & 0x1F)) & 1)
 #define PTE_SX(PTE)    ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
 
-#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
+#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
+       typeof(_PTE) (PTE) = (_PTE); \
+       typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
        ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
        (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
        ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
@@ -151,27 +153,31 @@
        asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
        __tmp; })
 
-#define write_csr(reg, val) ({ \
+#define write_csr(reg, _val) ({ \
+typeof(_val) (val) = (_val); \
 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
        asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
 else \
        asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
 
-#define swap_csr(reg, val) ({ unsigned long __tmp; \
+#define swap_csr(reg, _val) ({ unsigned long __tmp; \
+typeof(_val) (val) = (_val); \
 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
        asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
 else \
        asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
        __tmp; })
 
-#define set_csr(reg, bit) ({ unsigned long __tmp; \
+#define set_csr(reg, _bit) ({ unsigned long __tmp; \
+typeof(_bit) (bit) = (_bit); \
 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
        asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 else \
        asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
        __tmp; })
 
-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
+typeof(_bit) (bit) = (_bit); \
 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
        asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 else \

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 0cce98ab531a8ad2248a91a2093b00053b8cb144..bd352c2cda951531f19f441514c98f8b7fa883f5 100644 (file)
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -17,6 +17,6 @@ struct arch_global_data {
 
 #include <asm-generic/global_data.h>
 
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("gp")
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
 
 #endif /* __ASM_GBL_DATA_H */

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index e7f63ed8a9d6d9e12204d67838f503a76dd64b5d..1df6b1b2bf0ed2f9fce25ce99368690e683d4d48 100644 (file)
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -416,19 +416,17 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen)
 #define eth_io_copy_and_sum(s, c, l, b) \
        eth_copy_and_sum((s), __mem_pci(c), (l), (b))
 
-static inline int
-check_signature(unsigned long io_addr, const unsigned char *signature,
-                 int length)
+static inline int check_signature(ulong io_addr, const uchar *s, int len)
 {
        int retval = 0;
 
        do {
-               if (readb(io_addr) != *signature)
+               if (readb(io_addr) != *s)
                        goto out;
                io_addr++;
-               signature++;
-               length--;
-       } while (length);
+               s++;
+               len--;
+       } while (len);
        retval = 1;
 out:
        return retval;
@@ -455,18 +453,17 @@ out:
        eth_copy_and_sum((a), __mem_isa(b), (c), (d))
 
 static inline int
-isa_check_signature(unsigned long io_addr, const unsigned char *signature,
-                      int length)
+isa_check_signature(ulong io_addr, const uchar *s, int len)
 {
        int retval = 0;
 
        do {
-               if (isa_readb(io_addr) != *signature)
+               if (isa_readb(io_addr) != *s)
                        goto out;
                io_addr++;
-               signature++;
-               length--;
-       } while (length);
+               s++;
+               len--;
+       } while (len);
        retval = 1;
 out:
        return retval;

diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h
index 6892b6681430f445d08a121c5d1b323f3bc867fe..7438dbeb03f8ba8e1d50a83a9d5b426382a76584 100644 (file)
--- a/arch/riscv/include/asm/posix_types.h
+++ b/arch/riscv/include/asm/posix_types.h
@@ -69,19 +69,23 @@ typedef struct {
 #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
 
 #undef __FD_SET
-#define __FD_SET(fd, fdsetp) \
+#define __FD_SET(_fd, fdsetp) \
+       typeof(_fd) (fd) = (_fd); \
        (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31)))
 
 #undef __FD_CLR
-#define __FD_CLR(fd, fdsetp) \
+#define __FD_CLR(_fd, fdsetp) \
+       typeof(_fd) (fd) = (_fd); \
        (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31)))
 
 #undef __FD_ISSET
-#define __FD_ISSET(fd, fdsetp) \
+#define __FD_ISSET(_fd, fdsetp) \
+       typeof(_fd) (fd) = (_fd); \
        ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0)
 
 #undef __FD_ZERO
-#define __FD_ZERO(fdsetp) \
+#define __FD_ZERO(_fdsetp) \
+       typeof(_fdsetp) (fd) = (_fdsetp); \
        (memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
 
 #endif

diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
index 76d68698bb4e4a8ae93237edcf1c73ae59a4b34e..651078fcfda39ba012896c6761d5396a3d89fd4e 100644 (file)
--- a/arch/riscv/include/asm/ptrace.h
+++ b/arch/riscv/include/asm/ptrace.h
@@ -65,8 +65,7 @@ static inline unsigned long instruction_pointer(struct pt_regs *regs)
        return GET_IP(regs);
 }
 
-static inline void instruction_pointer_set(struct pt_regs *regs,
-                                            unsigned long val)
+static inline void instruction_pointer_set(struct pt_regs *regs, ulong val)
 {
        SET_IP(regs, val);
 }
@@ -82,8 +81,7 @@ static inline unsigned long user_stack_pointer(struct pt_regs *regs)
        return GET_USP(regs);
 }
 
-static inline void user_stack_pointer_set(struct pt_regs *regs,
-                                            unsigned long val)
+static inline void user_stack_pointer_set(struct pt_regs *regs, ulong val)
 {
        SET_USP(regs, val);
 }
@@ -97,8 +95,7 @@ static inline unsigned long frame_pointer(struct pt_regs *regs)
        return GET_FP(regs);
 }
 
-static inline void frame_pointer_set(struct pt_regs *regs,
-                                      unsigned long val)
+static inline void frame_pointer_set(struct pt_regs *regs, ulong val)
 {
        SET_FP(regs, val);
 }

diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h
index 731b0d96aaae3c0d4b5f93e58d88567331326f4a..4b182432f1e8128aa99f43f9dcdf5395c64f0d7d 100644 (file)
--- a/arch/riscv/include/asm/setup.h
+++ b/arch/riscv/include/asm/setup.h
@@ -145,14 +145,18 @@ struct tagtable {
        int (*parse)(const struct tag *);
 };
 
-#define tag_member_present(tag, member)                                \
+#define tag_member_present(_tag, member)                               \
+       typeof(_tag) (tag) = (_tag); \
        ((unsigned long)(&((struct tag *)0L)->member + 1)       \
                <= (tag)->hdr.size * 4)
 
-#define tag_next(t)    ((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_next(_t)   \
+       typeof(_t) (t) = (_t); \
+       ((struct tag *)((u32 *)(t) + (t)->hdr.size))
 #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
 
-#define for_each_tag(t, base) \
+#define for_each_tag(_t, base) \
+       typeof(_t) (t) = (_t); \
        for (t = base; t->hdr.size; t = tag_next(t))
 
 #ifdef __KERNEL__

diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
index 038cdaea72901ffd09388f35171bb05980a2b9eb..0fc3424a2f1a670b786fe091f9681ec0e06829c6 100644 (file)
--- a/arch/riscv/include/asm/string.h
+++ b/arch/riscv/include/asm/string.h
@@ -26,8 +26,11 @@
 #undef __HAVE_ARCH_MEMSET
 
 #ifdef CONFIG_MARCO_MEMSET
-#define memset(p, v, n)                                                        \
-       ({                                                              \
+#define memset(_p, _v, _n)     \
+       (typeof(_p) (p) = (_p); \
+        typeof(_v) (v) = (_v); \
+        typeof(_n) (n) = (_n); \
+        {                                                              \
                if ((n) != 0) {                                         \
                        if (__builtin_constant_p((v)) && (v) == 0)      \
                                __memzero((p), (n));                    \
@@ -37,7 +40,10 @@
                (p);                                                    \
        })
 
-#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#define memzero(_p, _n) \
+       (typeof(_p) (p) = (_p); \
+        typeof(_n) (n) = (_n); \
+        { if ((n) != 0) __memzero((p), (n)); (p); })
 #endif
 
 #endif /* __ASM_RISCV_STRING_H */

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 44ce38b614281a3a9e91b3e216958de800d945cd..9242fa891ac25795067dc3ede0c635342a258921 100644 (file)
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -21,36 +21,12 @@ int arch_fixup_fdt(void *blob)
        return 0;
 }
 
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-       defined(CONFIG_CMDLINE_TAG) || \
-       defined(CONFIG_INITRD_TAG) || \
-       defined(CONFIG_SERIAL_TAG) || \
-       defined(CONFIG_REVISION_TAG)
-static void setup_start_tag(bd_t *bd);
-
-# ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags(bd_t *bd);
-# endif
-static void setup_commandline_tag(bd_t *bd, char *commandline);
-
-# ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
-# endif
-static void setup_end_tag(bd_t *bd);
-
-static struct tag *params;
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
-
 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
        bd_t    *bd = gd->bd;
        char    *s;
        int     machid = bd->bi_arch_number;
-       void    (*theKernel)(int zero, int arch, uint params);
-
-#ifdef CONFIG_CMDLINE_TAG
-       char *commandline = env_get("bootargs");
-#endif
+       void    (*theKernel)(int arch, uint params);
 
        /*
         * allow the PREP bootm subcommand, it is required for bootm to work
@@ -61,7 +37,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
        if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
                return 1;
 
-       theKernel = (void (*)(int, int, uint))images->ep;
+       theKernel = (void (*)(int, uint))images->ep;
 
        s = env_get("machid");
        if (s) {
@@ -82,167 +58,16 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
                        hang();
                }
 #endif
-       } else if (BOOTM_ENABLE_TAGS) {
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-       defined(CONFIG_CMDLINE_TAG) || \
-       defined(CONFIG_INITRD_TAG) || \
-       defined(CONFIG_SERIAL_TAG) || \
-       defined(CONFIG_REVISION_TAG)
-       setup_start_tag(bd);
-#ifdef CONFIG_SERIAL_TAG
-       setup_serial_tag(&params);
-#endif
-#ifdef CONFIG_REVISION_TAG
-       setup_revision_tag(&params);
-#endif
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-       setup_memory_tags(bd);
-#endif
-#ifdef CONFIG_CMDLINE_TAG
-       setup_commandline_tag(bd, commandline);
-#endif
-#ifdef CONFIG_INITRD_TAG
-       if (images->rd_start && images->rd_end)
-               setup_initrd_tag(bd, images->rd_start, images->rd_end);
-#endif
-       setup_end_tag(bd);
-#endif
+       }
 
        /* we assume that the kernel is in place */
        printf("\nStarting kernel ...\n\n");
 
-#ifdef CONFIG_USB_DEVICE
-       {
-               extern void udc_disconnect(void);
-               udc_disconnect();
-       }
-#endif
-       }
        cleanup_before_linux();
        if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
-               theKernel(0, machid, (unsigned long)images->ft_addr);
-       else
-       theKernel(0, machid, bd->bi_boot_params);
+               theKernel(machid, (unsigned long)images->ft_addr);
+
        /* does not return */
 
        return 1;
 }
-
-#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
-       defined(CONFIG_CMDLINE_TAG) || \
-       defined(CONFIG_INITRD_TAG) || \
-       defined(CONFIG_SERIAL_TAG) || \
-       defined(CONFIG_REVISION_TAG)
-static void setup_start_tag(bd_t *bd)
-{
-       params = (struct tag *)bd->bi_boot_params;
-
-       params->hdr.tag = ATAG_CORE;
-       params->hdr.size = tag_size(tag_core);
-
-       params->u.core.flags = 0;
-       params->u.core.pagesize = 0;
-       params->u.core.rootdev = 0;
-
-       params = tag_next(params);
-}
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags(bd_t *bd)
-{
-       int i;
-
-       for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-               params->hdr.tag = ATAG_MEM;
-               params->hdr.size = tag_size(tag_mem32);
-
-               params->u.mem.start = bd->bi_dram[i].start;
-               params->u.mem.size = bd->bi_dram[i].size;
-
-               params = tag_next(params);
-       }
-}
-#endif /* CONFIG_SETUP_MEMORY_TAGS */
-
-static void setup_commandline_tag(bd_t *bd, char *commandline)
-{
-       char *p;
-
-       if (!commandline)
-               return;
-
-       /* eat leading white space */
-       for (p = commandline; *p == ' '; p++)
-               ;
-
-       /* skip non-existent command lines so the kernel will still
-        * use its default command line.
-        */
-       if (*p == '\0')
-               return;
-
-       params->hdr.tag = ATAG_CMDLINE;
-       params->hdr.size =
-               (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
-
-       strcpy(params->u.cmdline.cmdline, p)
-               ;
-
-       params = tag_next(params);
-}
-
-#ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
-{
-       /* an ATAG_INITRD node tells the kernel where the compressed
-        * ramdisk can be found. ATAG_RDIMG is a better name, actually.
-        */
-       params->hdr.tag = ATAG_INITRD2;
-       params->hdr.size = tag_size(tag_initrd);
-
-       params->u.initrd.start = initrd_start;
-       params->u.initrd.size = initrd_end - initrd_start;
-
-       params = tag_next(params);
-}
-#endif /* CONFIG_INITRD_TAG */
-
-#ifdef CONFIG_SERIAL_TAG
-void setup_serial_tag(struct tag **tmp)
-{
-       struct tag *params;
-       struct tag_serialnr serialnr;
-       void get_board_serial(struct tag_serialnr *serialnr);
-
-       params = *tmp;
-       get_board_serial(&serialnr);
-       params->hdr.tag = ATAG_SERIAL;
-       params->hdr.size = tag_size(tag_serialnr);
-       params->u.serialnr.low = serialnr.low;
-       params->u.serialnr.high = serialnr.high;
-       params = tag_next(params);
-       *tmp = params;
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-void setup_revision_tag(struct tag **in_params)
-{
-       u32 rev;
-       u32 get_board_rev(void);
-
-       rev = get_board_rev();
-       params->hdr.tag = ATAG_REVISION;
-       params->hdr.size = tag_size(tag_revision);
-       params->u.revision.rev = rev;
-       params = tag_next(params);
-}
-#endif  /* CONFIG_REVISION_TAG */
-
-static void setup_end_tag(bd_t *bd)
-{
-       params->hdr.tag = ATAG_NONE;
-       params->hdr.size = 0;
-}
-
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 075db8ba464dd9898888b397ce9c782cfea10737..923f75275bd4bd52c2d7156358f9224b5d279b6e 100644 (file)
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -63,7 +63,7 @@ __attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
 
 static void _exit_trap(int code, uint epc, struct pt_regs *regs)
 {
-       static const char *exception_code[] = {
+       static const char * const exception_code[] = {
                "Instruction address misaligned",
                "Instruction access fault",
                "Illegal instruction",

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b0f0ca8f19ce9104c58737ff8840aca58f26dfb3..06d0e8ce8506ae28add3fe8064c52b3583a409b9 100644 (file)
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -27,6 +27,10 @@
                testfdt3 = "/b-test";
                testfdt5 = "/some-bus/c-test@5";
                testfdt8 = "/a-test";
+               fdt_dummy0 = "/translation-test@8000/dev@0,0";
+               fdt_dummy1 = "/translation-test@8000/dev@1,100";
+               fdt_dummy2 = "/translation-test@8000/dev@2,200";
+               fdt_dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
                usb0 = &usb_0;
                usb1 = &usb_1;
                usb2 = &usb_2;
@@ -487,6 +491,50 @@
                        reg = <9 1>;
                };
        };
+
+       translation-test@8000 {
+               compatible = "simple-bus";
+               reg = <0x8000 0x4000>;
+
+               #address-cells = <0x2>;
+               #size-cells = <0x1>;
+
+               ranges = <0 0x0 0x8000 0x1000
+                         1 0x100 0x9000 0x1000
+                         2 0x200 0xA000 0x1000
+                         3 0x300 0xB000 0x1000
+                        >;
+
+               dev@0,0 {
+                       compatible = "denx,u-boot-fdt-dummy";
+                       reg = <0 0x0 0x1000>;
+               };
+
+               dev@1,100 {
+                       compatible = "denx,u-boot-fdt-dummy";
+                       reg = <1 0x100 0x1000>;
+
+               };
+
+               dev@2,200 {
+                       compatible = "denx,u-boot-fdt-dummy";
+                       reg = <2 0x200 0x1000>;
+               };
+
+
+               noxlatebus@3,300 {
+                       compatible = "simple-bus";
+                       reg = <3 0x300 0x1000>;
+
+                       #address-cells = <0x1>;
+                       #size-cells = <0x0>;
+
+                       dev@42 {
+                               compatible = "denx,u-boot-fdt-dummy";
+                               reg = <0x42>;
+                       };
+               };
+       };
 };
 
 #include "sandbox_pmic.dtsi"

diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index 90768a99ceb829d82d77bc61db7a947fa6daa27f..6aba61436123fc58774b379c30e3fd5ebab379dc 100644 (file)
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -10,8 +10,11 @@
 #include <asm/video/edid.h>
 
 /* setup data types */
-#define SETUP_NONE                     0
-#define SETUP_E820_EXT                 1
+enum {
+       SETUP_NONE = 0,
+       SETUP_E820_EXT,
+       SETUP_DTB,
+};
 
 /* extensible setup data list node */
 struct setup_data {

diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 2a82bc83d6cfcb19bc3b2513ae2bdc6920cca123..6af1bf46783b3b7a65f904cf5b18033951a66cae 100644 (file)
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -14,6 +14,7 @@
  */
 
 #include <common.h>
+#include <malloc.h>
 #include <asm/acpi_table.h>
 #include <asm/io.h>
 #include <asm/ptrace.h>
@@ -25,6 +26,7 @@
 #include <asm/arch/timestamp.h>
 #endif
 #include <linux/compiler.h>
+#include <linux/libfdt.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,6 +97,38 @@ static int get_boot_protocol(struct setup_header *hdr)
        }
 }
 
+static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob)
+{
+       int bootproto = get_boot_protocol(hdr);
+       struct setup_data *sd;
+       int size;
+
+       if (bootproto < 0x0209)
+               return -ENOTSUPP;
+
+       if (!fdt_blob)
+               return 0;
+
+       size = fdt_totalsize(fdt_blob);
+       if (size < 0)
+               return -EINVAL;
+
+       size += sizeof(struct setup_data);
+       sd = (struct setup_data *)malloc(size);
+       if (!sd) {
+               printf("Not enough memory for DTB setup data\n");
+               return -ENOMEM;
+       }
+
+       sd->next = hdr->setup_data;
+       sd->type = SETUP_DTB;
+       sd->len = fdt_totalsize(fdt_blob);
+       memcpy(sd->data, fdt_blob, sd->len);
+       hdr->setup_data = (unsigned long)sd;
+
+       return 0;
+}
+
 struct boot_params *load_zimage(char *image, unsigned long kernel_size,
                                ulong *load_addressp)
 {
@@ -261,6 +295,7 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
                hdr->acpi_rsdp_addr = acpi_get_rsdp_addr();
 #endif
 
+       setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0));
        setup_video(&setup_base->screen_info);
 
        return 0;

diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
index 8cffb6ba8bc45e453dcdef66c98224b855753401..52a89dc7a0008786240abc1dd8c13e2ce96720c1 100644 (file)
--- a/board/AndesTech/adp-ae3xx/adp-ae3xx.c
+++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
@@ -12,7 +12,6 @@
 #include <netdev.h>
 #endif
 #include <linux/io.h>
-#include <faraday/ftsdc010.h>
 #include <faraday/ftsmc020.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -75,13 +74,3 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
                return 0;
        }
 }
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
-       ftsdc010_mmc_init(0);
-#endif
-#endif
-       return 0;
-}

diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c
index f918c630c1720669f7564e7ca535012558663422..82928e78a4fca82f2601d70bef69d788b838c7c6 100644 (file)
--- a/board/AndesTech/adp-ag101p/adp-ag101p.c
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -14,7 +14,6 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <faraday/ftsdc010.h>
 #include <faraday/ftsmc020.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -82,13 +81,3 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
                return 0;
        }
 }
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
-       ftsdc010_mmc_init(0);
-#endif
-#endif
-       return 0;
-}

diff --git a/board/AndesTech/nx25-ae250/nx25-ae250.c b/board/AndesTech/nx25-ae250/nx25-ae250.c
index 12f2d3520bfbb23e8cf04bfed5577deedb495e62..6e31be35052328fe8861679d9bc44639795b99c5 100644 (file)
--- a/board/AndesTech/nx25-ae250/nx25-ae250.c
+++ b/board/AndesTech/nx25-ae250/nx25-ae250.c
@@ -11,7 +11,6 @@
 #include <netdev.h>
 #endif
 #include <linux/io.h>
-#include <faraday/ftsdc010.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -66,12 +65,11 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
        return 0;
 }
 
-int board_mmc_init(bd_t *bis)
+void *board_fdt_blob_setup(void)
 {
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
-       ftsdc010_mmc_init(0);
-#endif
-#endif
-       return 0;
+       void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
+       if (fdt_magic(*ptr) == FDT_MAGIC)
+                       return (void *)*ptr;
+
+       return (void *)CONFIG_SYS_FDT_BASE;
 }

diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index ac3e3a392fc2c73e299741d78bcce585679a531b..e20539624bafcd18becf9e9a0c668404336c3808 100644 (file)
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -50,29 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f(void)
 {
-       const void *blob = gd->fdt_blob;
-       const char *bank_name;
-       const char *compat = "marvell,armada-3700-pinctl";
-       int off, len;
-       void __iomem *addr;
-
-       /* FIXME
-        * Temporary WA for setting correct pin control values
-        * until the real pin control driver is awailable.
-        */
-       off = fdt_node_offset_by_compatible(blob, -1, compat);
-       while (off != -FDT_ERR_NOTFOUND) {
-               bank_name = fdt_getprop(blob, off, "bank-name", &len);
-               addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
-                               blob, off, "reg", 0, NULL, true);
-               if (!strncmp(bank_name, "armada-3700-nb", len))
-                       writel(PINCTRL_NB_REG_VALUE, addr);
-               else if (!strncmp(bank_name, "armada-3700-sb", len))
-                       writel(PINCTRL_SB_REG_VALUE, addr);
-
-               off = fdt_node_offset_by_compatible(blob, off, compat);
-       }
-
        return 0;
 }
 

diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 38bd91b191812ddb8854c98a44d177114aac54f2..22d521b6cf5cd152b3c701287c71d2c0c31f5e35 100644 (file)
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
 config SYS_CONFIG_NAME
        default "ls1012afrdm"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select PHYLIB
+       imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+       hex "Flash address of PFE firmware"
+       default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+       hex "PFE DDR physical base address"
+       default 0x03800000
+
+config DDR_PFE_BASEADDR
+       hex "PFE DDR base address"
+       default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif

diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
index dbfa2cea3830cde40d68bfe508c8595486602c0a..1e53c967304b79a9b6a2fe300a042b81d1936bdd 100644 (file)
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012afrdm.o
+obj-$(CONFIG_FSL_PFE) += eth.o

diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
new file mode 100644 (file)
index 0000000..cc6deb2
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST       0x00000100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+       unsigned int val;
+       struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+       setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
+
+       val = in_be32(&pgpio->gpdat);
+       setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
+       mdelay(10);
+
+       val = in_be32(&pgpio->gpdat);
+       setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
+       mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+       static int init_done;
+       struct mii_dev *bus;
+       struct pfe_mdio_info mac_mdio_info;
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+       if (!init_done) {
+               ls1012afrdm_reset_phy();
+
+               mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+               mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+               bus = pfe_mdio_init(&mac_mdio_info);
+               if (!bus) {
+                       printf("Failed to register mdio\n");
+                       return -1;
+               }
+
+               init_done = 1;
+       }
+
+       if (priv->gemac_port) {
+               mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+               mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+               bus = pfe_mdio_init(&mac_mdio_info);
+               if (!bus) {
+                       printf("Failed to register mdio\n");
+                       return -1;
+               }
+       }
+
+       pfe_set_mdio(priv->gemac_port,
+                    miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+       if (!priv->gemac_port)
+               /* MAC1 */
+               pfe_set_phy_address_mode(priv->gemac_port,
+                                        CONFIG_PFE_EMAC1_PHY_ADDR,
+                                        PHY_INTERFACE_MODE_SGMII);
+       else
+               /* MAC2 */
+               pfe_set_phy_address_mode(priv->gemac_port,
+                                        CONFIG_PFE_EMAC2_PHY_ADDR,
+                                        PHY_INTERFACE_MODE_SGMII);
+       return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+       .pfe_eth_pdata_mac = {
+               .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+               .phy_interface = 0,
+       },
+
+       .pfe_ddr_addr = {
+               .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+               .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+       },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+       .pfe_eth_pdata_mac = {
+               .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+               .phy_interface = 1,
+       },
+
+       .pfe_ddr_addr = {
+               .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+               .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+       },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+       .name = "pfe_eth",
+       .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+       .name = "pfe_eth",
+       .platdata = &pfe_pdata1,
+};

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 9afd1c469e42b7aa66de98586ab09629fab943bf..0145886e67441441827f42e8626e6f28bcb7d185 100644 (file)
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -57,11 +57,6 @@ int dram_init(void)
        return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-       return pci_eth_init(bis);
-}
-
 int board_early_init_f(void)
 {
        fsl_lsch2_early_init_f();

diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index fc9250b253ed43f66987caf3775e351f8dff56fe..c0b12ed78f265387a0724aad2db91665721aaffd 100644 (file)
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,6 +12,51 @@ config SYS_SOC
 config SYS_CONFIG_NAME
        default "ls1012aqds"
 
+
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select PHYLIB
+       imply PHY_VITESSE
+       imply PHY_REALTEK
+       imply PHY_AQUANTIA
+       imply PHYLIB_10G
+
+config PFE_RGMII_RESET_WA
+       def_bool y
+
+config SYS_LS_PFE_FW_ADDR
+       hex "Flash address of PFE firmware"
+       default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+       hex "PFE DDR physical base address"
+       default 0x03800000
+
+config DDR_PFE_BASEADDR
+       hex "PFE DDR base address"
+       default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x1e
+
+config PFE_EMAC2_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x1
+
+config PFE_SGMII_2500_PHY1_ADDR
+       hex "PFE DDR base address"
+       default 0x1
+
+config PFE_SGMII_2500_PHY2_ADDR
+       hex "PFE DDR base address"
+       default 0x2
+
+endif
+
+
 source "board/freescale/common/Kconfig"
 
 endif

diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
index 0b813f9784852603371d951d8bdd38b81e68d3fa..5aba9caf92754e5e03b8a17f9efb353231095acd 100644 (file)
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012aqds.o
+obj-$(CONFIG_FSL_PFE) += eth.o

diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644 (file)
index 0000000..f8026a2
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include "../common/qixis.h"
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE       0xFF
+#define EMI1_RGMII     1
+#define EMI1_SLOT1     2
+#define EMI1_SLOT2     3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+       "NULL",
+       "LS1012AQDS_MDIO_RGMII",
+       "LS1012AQDS_MDIO_SLOT1",
+       "LS1012AQDS_MDIO_SLOT2",
+       "NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+       return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+       u8 muxval;
+       struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+       u8 brdcfg4;
+
+       if (muxval < 7) {
+               brdcfg4 = QIXIS_READ(brdcfg[4]);
+               brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+               brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+               QIXIS_WRITE(brdcfg[4], brdcfg4);
+       }
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+                               int regnum)
+{
+       struct ls1012aqds_mdio *priv = bus->priv;
+
+       ls1012aqds_mux_mdio(priv->muxval);
+
+       return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+                                int regnum, u16 value)
+{
+       struct ls1012aqds_mdio *priv = bus->priv;
+
+       ls1012aqds_mux_mdio(priv->muxval);
+
+       return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+       struct ls1012aqds_mdio *priv = bus->priv;
+
+       if (priv->realbus->reset)
+               return priv->realbus->reset(priv->realbus);
+       else
+               return -1;
+}
+
+static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+{
+       struct ls1012aqds_mdio *pmdio;
+       struct mii_dev *bus = mdio_alloc();
+
+       if (!bus) {
+               printf("Failed to allocate ls1012aqds MDIO bus\n");
+               return -1;
+       }
+
+       pmdio = malloc(sizeof(*pmdio));
+       if (!pmdio) {
+               printf("Failed to allocate ls1012aqds private data\n");
+               free(bus);
+               return -1;
+       }
+
+       bus->read = ls1012aqds_mdio_read;
+       bus->write = ls1012aqds_mdio_write;
+       bus->reset = ls1012aqds_mdio_reset;
+       sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
+
+       pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+       if (!pmdio->realbus) {
+               printf("No bus with name %s\n", realbusname);
+               free(bus);
+               free(pmdio);
+               return -1;
+       }
+
+       pmdio->muxval = muxval;
+       bus->priv = pmdio;
+       return mdio_register(bus);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+       static int init_done;
+       struct mii_dev *bus;
+       static const char *mdio_name;
+       struct pfe_mdio_info mac_mdio_info;
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+       u8 data8;
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+       int srds_s1 = in_be32(&gur->rcwsr[4]) &
+                       FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+       srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+       ls1012aqds_mux_mdio(EMI1_SLOT1);
+
+       if (!init_done) {
+               mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+               mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+               bus = pfe_mdio_init(&mac_mdio_info);
+               if (!bus) {
+                       printf("Failed to register mdio\n");
+                       return -1;
+               }
+               init_done = 1;
+       }
+
+       if (priv->gemac_port) {
+               mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+               mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+               bus = pfe_mdio_init(&mac_mdio_info);
+               if (!bus) {
+                       printf("Failed to register mdio\n");
+                       return -1;
+               }
+       }
+
+       switch (srds_s1) {
+       case 0x3508:
+               printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+#ifdef CONFIG_PFE_RGMII_RESET_WA
+               /*
+                * Work around for FPGA registers initialization
+                * This is needed for RGMII to work.
+                */
+               printf("Reset RGMII WA....\n");
+               data8 = QIXIS_READ(rst_frc[0]);
+               data8 |= 0x2;
+               QIXIS_WRITE(rst_frc[0], data8);
+               data8 = QIXIS_READ(rst_frc[0]);
+
+               data8 = QIXIS_READ(res8[6]);
+               data8 |= 0xff;
+               QIXIS_WRITE(res8[6], data8);
+               data8 = QIXIS_READ(res8[6]);
+#endif
+       if (priv->gemac_port) {
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+               if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
+                   < 0) {
+                       printf("Failed to register mdio for %s\n", mdio_name);
+               }
+
+               /* MAC2 */
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+               bus = miiphy_get_dev_by_name(mdio_name);
+               pfe_set_mdio(priv->gemac_port, bus);
+               pfe_set_phy_address_mode(priv->gemac_port,
+                                        CONFIG_PFE_EMAC2_PHY_ADDR,
+                                        PHY_INTERFACE_MODE_RGMII);
+
+       } else {
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+               if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+               < 0) {
+                       printf("Failed to register mdio for %s\n", mdio_name);
+               }
+
+               /* MAC1 */
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+               bus = miiphy_get_dev_by_name(mdio_name);
+               pfe_set_mdio(priv->gemac_port, bus);
+               pfe_set_phy_address_mode(priv->gemac_port,
+                                        CONFIG_PFE_EMAC1_PHY_ADDR,
+                                        PHY_INTERFACE_MODE_SGMII);
+       }
+
+               break;
+
+       case 0x2205:
+               printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+               /*
+                * Work around for FPGA registers initialization
+                * This is needed for RGMII to work.
+                */
+               printf("Reset SLOT1 SLOT2....\n");
+               data8 = QIXIS_READ(rst_frc[2]);
+               data8 |= 0xc0;
+               QIXIS_WRITE(rst_frc[2], data8);
+               mdelay(100);
+               data8 = QIXIS_READ(rst_frc[2]);
+               data8 &= 0x3f;
+               QIXIS_WRITE(rst_frc[2], data8);
+
+       if (priv->gemac_port) {
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+               if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
+               < 0) {
+                       printf("Failed to register mdio for %s\n", mdio_name);
+               }
+               /* MAC2 */
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+               bus = miiphy_get_dev_by_name(mdio_name);
+               pfe_set_mdio(1, bus);
+               pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
+                                        PHY_INTERFACE_MODE_SGMII_2500);
+
+               data8 = QIXIS_READ(brdcfg[12]);
+               data8 |= 0x20;
+               QIXIS_WRITE(brdcfg[12], data8);
+
+       } else {
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+               if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+                   < 0) {
+                       printf("Failed to register mdio for %s\n", mdio_name);
+               }
+
+               /* MAC1 */
+               mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+               bus = miiphy_get_dev_by_name(mdio_name);
+               pfe_set_mdio(0, bus);
+               pfe_set_phy_address_mode(0,
+                                        CONFIG_PFE_SGMII_2500_PHY1_ADDR,
+                                        PHY_INTERFACE_MODE_SGMII_2500);
+       }
+               break;
+
+       default:
+               printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
+               break;
+       }
+       return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+       .pfe_eth_pdata_mac = {
+               .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+               .phy_interface = 0,
+       },
+
+       .pfe_ddr_addr = {
+               .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+               .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+       },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+       .pfe_eth_pdata_mac = {
+               .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+               .phy_interface = 1,
+       },
+
+       .pfe_ddr_addr = {
+               .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+               .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+       },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+       .name = "pfe_eth",
+       .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+       .name = "pfe_eth",
+       .platdata = &pfe_pdata1,
+};

diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 406194da27facce39f494eb1df634abdd6514e1e..4577917e8d2fa387b80c17c22da4b17ad5ded613 100644 (file)
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -25,9 +25,9 @@
 #include <fsl_mmdc.h>
 #include <spl.h>
 #include <netdev.h>
-
 #include "../common/qixis.h"
 #include "ls1012aqds_qixis.h"
+#include "ls1012aqds_pfe.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -128,11 +128,6 @@ int board_init(void)
        return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-       return pci_eth_init(bis);
-}
-
 int esdhc_status_fixup(void *blob, const char *compat)
 {
        char esdhc0_path[] = "/soc/esdhc@1560000";
@@ -161,12 +156,102 @@ int esdhc_status_fixup(void *blob, const char *compat)
        return 0;
 }
 
+static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
+                             char *enet_path, char *mdio_path)
+{
+       do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
+                        &prop_val.busid, PFE_PROP_LEN, 1);
+       do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
+                        &prop_val.phyid, PFE_PROP_LEN, 1);
+       do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
+                        &prop_val.mux_val, PFE_PROP_LEN, 1);
+       do_fixup_by_path(set_blob, enet_path, "phy-mode",
+                        prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
+       do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
+                        &prop_val.phy_mask, PFE_PROP_LEN, 1);
+       return 0;
+}
+
+static void fdt_fsl_fixup_of_pfe(void *blob)
+{
+       int i = 0;
+       struct pfe_prop_val prop_val;
+       void *l_blob = blob;
+
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+       unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
+               FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+       srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+       for (i = 0; i < NUM_ETH_NODE; i++) {
+               switch (srds_s1) {
+               case SERDES_1_G_PROTOCOL:
+                       if (i == 0) {
+                               prop_val.busid = cpu_to_fdt32(
+                                               ETH_1_1G_BUS_ID);
+                               prop_val.phyid = cpu_to_fdt32(
+                                               ETH_1_1G_PHY_ID);
+                               prop_val.mux_val = cpu_to_fdt32(
+                                               ETH_1_1G_MDIO_MUX);
+                               prop_val.phy_mask = cpu_to_fdt32(
+                                               ETH_1G_MDIO_PHY_MASK);
+                               prop_val.phy_mode = "sgmii";
+                               pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+                                                  ETH_1_MDIO);
+                       } else {
+                               prop_val.busid = cpu_to_fdt32(
+                                               ETH_2_1G_BUS_ID);
+                               prop_val.phyid = cpu_to_fdt32(
+                                               ETH_2_1G_PHY_ID);
+                               prop_val.mux_val = cpu_to_fdt32(
+                                               ETH_2_1G_MDIO_MUX);
+                               prop_val.phy_mask = cpu_to_fdt32(
+                                               ETH_1G_MDIO_PHY_MASK);
+                               prop_val.phy_mode = "rgmii";
+                               pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+                                                  ETH_2_MDIO);
+                       }
+               break;
+               case SERDES_2_5_G_PROTOCOL:
+                       if (i == 0) {
+                               prop_val.busid = cpu_to_fdt32(
+                                               ETH_1_2_5G_BUS_ID);
+                               prop_val.phyid = cpu_to_fdt32(
+                                               ETH_1_2_5G_PHY_ID);
+                               prop_val.mux_val = cpu_to_fdt32(
+                                               ETH_1_2_5G_MDIO_MUX);
+                               prop_val.phy_mask = cpu_to_fdt32(
+                                               ETH_2_5G_MDIO_PHY_MASK);
+                               prop_val.phy_mode = "sgmii-2500";
+                               pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+                                                  ETH_1_MDIO);
+                       } else {
+                               prop_val.busid = cpu_to_fdt32(
+                                               ETH_2_2_5G_BUS_ID);
+                               prop_val.phyid = cpu_to_fdt32(
+                                               ETH_2_2_5G_PHY_ID);
+                               prop_val.mux_val = cpu_to_fdt32(
+                                               ETH_2_2_5G_MDIO_MUX);
+                               prop_val.phy_mask = cpu_to_fdt32(
+                                               ETH_2_5G_MDIO_PHY_MASK);
+                               prop_val.phy_mode = "sgmii-2500";
+                               pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+                                                  ETH_2_MDIO);
+                       }
+               break;
+               default:
+                       printf("serdes:[%d]\n", srds_s1);
+               }
+       }
+}
+
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
        arch_fixup_fdt(blob);
 
        ft_cpu_setup(blob, bd);
+       fdt_fsl_fixup_of_pfe(blob);
 
        return 0;
 }

diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
new file mode 100644 (file)
index 0000000..b06f722
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#define ETH_1_1G_BUS_ID                0x1
+#define ETH_1_1G_PHY_ID                0x1e
+#define ETH_1_1G_MDIO_MUX      0x2
+#define ETH_1G_MDIO_PHY_MASK   0xBFFFFFFD
+#define ETH_1_1G_PHY_MODE      "sgmii"
+#define ETH_2_1G_BUS_ID                0x1
+#define ETH_2_1G_PHY_ID                0x1
+#define ETH_2_1G_MDIO_MUX      0x1
+#define ETH_2_1G_PHY_MODE      "rgmii"
+
+#define ETH_1_2_5G_BUS_ID      0x0
+#define ETH_1_2_5G_PHY_ID      0x1
+#define ETH_1_2_5G_MDIO_MUX    0x2
+#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
+#define ETH_2_5G_PHY_MODE      "sgmii-2500"
+#define ETH_2_2_5G_BUS_ID      0x1
+#define ETH_2_2_5G_PHY_ID      0x2
+#define ETH_2_2_5G_MDIO_MUX    0x3
+
+#define SERDES_1_G_PROTOCOL    0x3508
+#define SERDES_2_5_G_PROTOCOL  0x2205
+
+#define PFE_PROP_LEN           4
+
+#define ETH_1_PATH             "/pfe@04000000/ethernet@0"
+#define ETH_1_MDIO             ETH_1_PATH "/mdio@0"
+
+#define ETH_2_PATH             "/pfe@04000000/ethernet@1"
+#define ETH_2_MDIO             ETH_2_PATH "/mdio@0"
+
+#define NUM_ETH_NODE           2
+
+struct pfe_prop_val {
+       int busid;
+       int phyid;
+       int mux_val;
+       int phy_mask;
+       char *phy_mode;
+};

diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
index 584f604aa865174340c2a187651f95e9adb64360..7a1ba3d938c12374e7a0a1a68d47f088c77edfb4 100644 (file)
--- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -11,7 +11,7 @@
 
 /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
 #define BRDCFG4_EMISEL_MASK            0xe0
-#define BRDCFG4_EMISEL_SHIFT           5
+#define BRDCFG4_EMISEL_SHIFT           6
 
 /* SYSCLK */
 #define QIXIS_SYSCLK_66                        0x0

diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index d13b08ebe5884ac4c0524a971893a01307570965..493d4779bc2a0b3cb34d2ad9ab85b339b21c0849 100644 (file)
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,35 @@ config SYS_SOC
 config SYS_CONFIG_NAME
        default "ls1012ardb"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select PHYLIB
+       imply PHY_REALTEK
+
+config SYS_LS_PFE_FW_ADDR
+       hex "Flash address of PFE firmware"
+       default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+       hex "PFE DDR physical base address"
+       default 0x03800000
+
+config DDR_PFE_BASEADDR
+       hex "PFE DDR base address"
+       default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif
@@ -30,6 +59,36 @@ config SYS_SOC
 config SYS_CONFIG_NAME
         default "ls1012a2g5rdb"
 
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select PHYLIB
+       imply CONFIG_PHYLIB_10G
+       imply CONFIG_PHY_AQUANTIA
+
+config SYS_LS_PFE_FW_ADDR
+       hex "Flash address of PFE firmware"
+       default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+       hex "PFE DDR physical base address"
+       default 0x03800000
+
+config DDR_PFE_BASEADDR
+       hex "PFE DDR base address"
+       default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+       hex "PFE DDR base address"
+       default 0x1
+
+endif
+
 source "board/freescale/common/Kconfig"
 
 endif

diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
index 05fa9d9c5b243bbcc6b2abc7a3be024c6170a720..70c7b33273d738ffa370deae185b4317bfbb5ff7 100644 (file)
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1012ardb.o
+obj-$(CONFIG_FSL_PFE) += eth.o

diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644 (file)
index 0000000..8e6cd0a
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <i2c.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+#ifdef CONFIG_TARGET_LS1012ARDB
+       /* Through reset IO expander reset both RGMII and SGMII PHYs */
+       i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+       i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+       mdelay(10);
+       i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+       mdelay(10);
+       i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+       mdelay(50);
+#endif
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+       static int init_done;
+       struct mii_dev *bus;
+       struct pfe_mdio_info mac_mdio_info;
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+       int srds_s1 = in_be32(&gur->rcwsr[4]) &
+                       FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+       srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+       if (!init_done) {
+               ls1012ardb_reset_phy();
+               mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+               mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+               bus = pfe_mdio_init(&mac_mdio_info);
+               if (!bus) {
+                       printf("Failed to register mdio\n");
+                       return -1;
+               }
+               init_done = 1;
+       }
+
+       pfe_set_mdio(priv->gemac_port,
+                    miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+       switch (srds_s1) {
+       case 0x3508:
+               if (!priv->gemac_port) {
+                       /* MAC1 */
+                       pfe_set_phy_address_mode(priv->gemac_port,
+                                                CONFIG_PFE_EMAC1_PHY_ADDR,
+                                                PHY_INTERFACE_MODE_SGMII);
+               } else {
+                       /* MAC2 */
+                       pfe_set_phy_address_mode(priv->gemac_port,
+                                                CONFIG_PFE_EMAC2_PHY_ADDR,
+                                                PHY_INTERFACE_MODE_RGMII_TXID);
+               }
+               break;
+       case 0x2208:
+               if (!priv->gemac_port) {
+                       /* MAC1 */
+                       pfe_set_phy_address_mode(priv->gemac_port,
+                                                CONFIG_PFE_EMAC1_PHY_ADDR,
+                                                PHY_INTERFACE_MODE_SGMII_2500);
+               } else {
+                       /* MAC2 */
+                       pfe_set_phy_address_mode(priv->gemac_port,
+                                                CONFIG_PFE_EMAC2_PHY_ADDR,
+                                                PHY_INTERFACE_MODE_SGMII_2500);
+               }
+               break;
+       default:
+               printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+               break;
+       }
+       return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+       .pfe_eth_pdata_mac = {
+               .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+               .phy_interface = 0,
+       },
+
+       .pfe_ddr_addr = {
+               .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+               .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+       },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+       .pfe_eth_pdata_mac = {
+               .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+               .phy_interface = 1,
+       },
+
+       .pfe_ddr_addr = {
+               .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+               .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+       },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+       .name = "pfe_eth",
+       .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+       .name = "pfe_eth",
+       .platdata = &pfe_pdata1,
+};

diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index c9557bb2621c39fb2af0af73ae7da5035c29d00f..ed5a8e6fc2e80ef7e21e4770a3ea821c8fde6bd2 100644 (file)
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -114,10 +114,6 @@ int dram_init(void)
        return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-       return pci_eth_init(bis);
-}
 
 int board_early_init_f(void)
 {

diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index 371e5db9ad9d082686aab0f9bb4609fe8d67c0d2..4d804d944713cba390b87fc17667a479ff0f2ad5 100644 (file)
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -15,6 +15,8 @@ F:    board/freescale/ls1088a/
 F:     include/configs/ls1088aqds.h
 F:     configs/ls1088aqds_qspi_defconfig
 F:     configs/ls1088aqds_sdcard_qspi_defconfig
+F:     configs/ls1088aqds_defconfig
+F:     configs/ls1088aqds_sdcard_ifc_defconfig
 
 LS1088AQDS_QSPI_SECURE_BOOT BOARD
 M:     Udit Agarwal <udit.agarwal@nxp.com>

diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 56e454ff203df82dee86d9702cc8464e8664dc2b..a5fa0509910fca768a782e37302a8a0006f12f82 100644 (file)
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -31,6 +31,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f(void)
 {
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
+       i2c_early_init_f();
+#endif
        fsl_lsch3_early_init_f();
        return 0;
 }
@@ -168,6 +171,7 @@ int checkboard(void)
 
        return 0;
 }
+#endif
 
 bool if_board_diff_clk(void)
 {
@@ -221,7 +225,6 @@ unsigned long get_board_ddr_clk(void)
 
        return 66666666;
 }
-#endif
 
 int select_i2c_ch_pca9547(u8 ch)
 {

diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c
index 0d33cc4c28e62e7c27804067aed1f41c67fc4bef..8dbf4100e704816cc65772a28ebe904487a935b4 100644 (file)
--- a/board/micronas/vct/scc.c
+++ b/board/micronas/vct/scc.c
@@ -524,12 +524,14 @@ int scc_setup_dma(enum scc_id id, u32 buffer_tag,
        struct scc_dma_state *dma_state;
        int return_value = 0;
        union scc_dma_cfg dma_cfg;
-       u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+       u32 *buffer_tag_list;
        u32 tag_count, t, t_valid;
 
        if ((id >= SCC_MAX) || (id < 0))
                return -EINVAL;
 
+       buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+
        /* if the register is only configured by hw, cannot write! */
        if (1 == scc_descriptor_table[id].hw_dma_cfg)
                return -EACCES;

diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig
new file mode 100644 (file)
index 0000000..11af188
--- /dev/null
+++ b/board/netgear/dgnd3700v2/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_DGND3700V2
+
+config SYS_BOARD
+       default "dgnd3700v2"
+
+config SYS_VENDOR
+       default "netgear"
+
+config SYS_CONFIG_NAME
+       default "netgear_dgnd3700v2"
+
+endif

diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS
new file mode 100644 (file)
index 0000000..998077b
--- /dev/null
+++ b/board/netgear/dgnd3700v2/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR DGND3700V2 BOARD
+M:     Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+S:     Maintained
+F:     board/netgear/dgnd3700v2/
+F:     include/configs/netgear_dgnd3700v2.h
+F:     configs/netgear_dgnd3700v2_ram_defconfig

diff --git a/board/netgear/dgnd3700v2/Makefile b/board/netgear/dgnd3700v2/Makefile
new file mode 100644 (file)
index 0000000..89fd6c8
--- /dev/null
+++ b/board/netgear/dgnd3700v2/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += dgnd3700v2.o

diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c
new file mode 100644 (file)
index 0000000..3ae7f6a
--- /dev/null
+++ b/board/netgear/dgnd3700v2/dgnd3700v2.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define GPIO_BASE_6362                 0x10000080
+
+#define GPIO_MODE_6362_REG             0x18
+#define GPIO_MODE_6362_SERIAL_LED_DATA BIT(2)
+#define GPIO_MODE_6362_SERIAL_LED_CLK  BIT(3)
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+       void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE);
+
+       /* Enable Serial LEDs */
+       setbits_be32(gpio_regs + GPIO_MODE_6362_REG,
+                    GPIO_MODE_6362_SERIAL_LED_DATA |
+                    GPIO_MODE_6362_SERIAL_LED_CLK);
+
+       return 0;
+}
+#endif

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 05b316fe90a491199b85917ef149661eeb26db38..c4f263332c8b06b65a30ffab00f4499378e305d7 100644 (file)
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -7,8 +7,12 @@
 
 #include <common.h>
 #include <dm.h>
+#include <lcd.h>
 #include <ram.h>
 #include <spl.h>
+#include <splash.h>
+#include <st_logo_data.h>
+#include <video.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
@@ -153,5 +157,10 @@ int board_init(void)
        STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
 #endif
 
+#if defined(CONFIG_CMD_BMP)
+       bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
+                   BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
+#endif /* CONFIG_CMD_BMP */
+
        return 0;
 }

diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
new file mode 100644 (file)
index 0000000..5ab9415
--- /dev/null
+++ b/board/st/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STM32MP1
+
+config SYS_BOARD
+       default "stm32mp1"
+
+config SYS_VENDOR
+       default "st"
+
+config SYS_CONFIG_NAME
+       default "stm32mp1"
+
+endif

diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
new file mode 100644 (file)
index 0000000..65266bc
--- /dev/null
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32MP1 BOARD
+M:     Patrick Delaunay <patrick.delaunay@st.com>
+S:     Maintained
+F:     board/st/stm32mp1
+F:     include/configs/stm32mp1.h
+F:     configs/stm32mp15_basic_defconfig
+F:     arch/arm/dts/stm32mp157*

diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile
new file mode 100644 (file)
index 0000000..eaf45b7
--- /dev/null
+++ b/board/st/stm32mp1/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += stm32mp1.o
+endif
+
+obj-y += board.o

diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
new file mode 100644 (file)
index 0000000..4adc978
--- /dev/null
+++ b/board/st/stm32mp1/README
@@ -0,0 +1,191 @@
+#
+# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
+#
+
+U-Boot on STMicroelectronics STM32MP1
+======================================
+
+1. Summary
+==========
+This is a quick instruction for setup stm32mp1 boards.
+
+2. Supported devices
+====================
+U-Boot supports one STMP32MP1 SoCs: STM32MP157
+
+The STM32MP157 is a Cortex-A MPU aimed at various applications.
+It features:
+- Dual core Cortex-A7 application core
+- 2D/3D image composition with GPU
+- Standard memories interface support
+- Standard connectivity, widely inherited from the STM32 MCU family
+- Comprehensive security support
+
+Everything is supported in Linux but U-Boot is limited to:
+1. UART
+2. SDCard/MMC controller (SDMMC)
+
+And the necessary drivers
+1. I2C
+2. STPMU1
+3. Clock, Reset
+
+Currently the following boards are supported:
++ stm32mp157c-ed1
+
+3. Boot Sequences
+=================
+
+BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel)
+
+with FSBL = First Stage Bootloader
+     SSBL = Second Stage Bootloader
+
+One boot configuration is supported:
+
+   The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
+   BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
+   SPL has limited security initialisation
+   U-Boot is running in secure mode and provide a secure monitor to the kernel
+   with only PSCI support (Power State Coordination Interface defined by ARM)
+
+All the STM32MP1 board supported by U-Boot use the same generic board
+stm32mp1 which support all the bootable devices.
+
+Each board is configurated only with the associated device tree.
+
+4. Device Tree Selection
+========================
+
+You need to select the appropriate device tree for your board,
+the supported device trees for stm32mp157 are:
+
++ ed1: daughter board with pmic stpmu1
+  dts: stm32mp157c-ed1
+
+5. Build Procedure
+==================
+
+1. Install required tools for U-Boot
+
+   + install package needed in U-Boot makefile
+     (libssl-dev, swig, libpython-dev...)
+   + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
+     from SDK for STM32MP1, or any crosstoolchains from your distribution)
+
+2. Set the cross compiler:
+
+       # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
+       (you can use any gcc cross compiler compatible with U-Boot)
+
+3. Select the output directory (optional)
+
+       # export KBUILD_OUTPUT=/path/to/output
+
+       for example: use one output directory for each configuration
+       # export KBUILD_OUTPUT=stm32mp15_basic
+
+4. Configure the U-Boot:
+
+       # make <defconfig_file>
+
+       - For basic boot mode: "stm32mp15_basic_defconfig"
+
+5. Configure the device-tree and build the U-Boot image:
+
+       # make DEVICE_TREE=<name> all
+
+
+  example:
+     basic boot on ed1
+       # export KBUILD_OUTPUT=stm32mp15_basic
+       # make stm32mp15_basic_defconfig
+       # make DEVICE_TREE=stm32mp157c-ed1 all
+
+6. Output files
+
+  BootRom and ATF expect binaries with STM32 image header
+  SPL expects file with U-Boot uImage header
+
+  So in the output directory (selected by KBUILD_OUTPUT),
+  you can found the needed files:
+
+   + FSBL = spl/u-boot-spl.stm32
+   + SSBL = u-boot.img
+
+6. Prepare an SDCard
+===================
+
+The minimal requirements for STMP32MP1 boot up to U-Boot are:
+- GPT partitioning (with gdisk or with sgdisk)
+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
+- one ssbl partition for U-Boot
+
+Then the minimal GPT partition is:
+   ----- ------- --------- -------------
+  | Num | Name  | Size    |  Content    |
+   ----- ------- -------- --------------
+  |  1  | fsbl1 | 256 KiB |  ATF or SPL |
+  |  2  | fsbl2 | 256 KiB |  ATF or SPL |
+  |  3  | ssbl  | enought |  U-Boot     |
+  |  *  |  -    |  -      |  Boot/Rootfs|
+   ----- ------- --------- -------------
+
+(*) add bootable partition for extlinux.conf
+    following Generic Distribution
+    (doc/README.distro for use)
+
+  according the used card reader select the block device
+  (/dev/sdx or /dev/mmcblk0)
+  in the next example I use /dev/mmcblk0
+
+for example: with gpt table with 128 entries
+
+  a) remove previous formatting
+       # sgdisk -o /dev/<SDCard dev>
+
+  b) create minimal image
+       # sgdisk        --resize-table=128 -a 1 \
+               -n 1:34:545             -c 1:fsbl1 \
+               -n 2:546:1057           -c 2:fsbl2 \
+               -n 3:1058:5153          -c 3:ssbl \
+               -p /dev/<SDCard dev>
+
+       you can add other partition for kernel (rootfs)
+
+  c) copy the FSBL (2 times) and SSBL file on the correct partition.
+     in this example in partition 1 to 3
+
+     for basic boot mode : <SDCard dev> = /dev/mmcblk0
+       # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
+       # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
+       # dd if=u-boot.img of=/dev/mmcblk0p3
+
+7. Switch Setting
+==================
+
+You can select the boot mode, on the board ed1 with the switch SW1
+
+ -----------------------------------
+  Boot Mode   BOOT2   BOOT1   BOOT0
+ -----------------------------------
+  Reserved     0       0       0
+  NOR          0       0       1
+  SD-Card      1       1       1
+  SD-Card      1       0       1
+  eMMC         0       1       0
+  NAND         0       1       1
+  Recovery     1       1       0
+  Recovery     0       0       0
+
+
+To boot from SDCard, select BootPinMode = 1 1 1 and reset.
+
+Recovery is a boot from serial link (UART/USB) and it is used with
+STM32CubeProgrammer tool to load executable in RAM and to update the flash
+devices available on the board (NOR/NAND/eMMC/SDCARD).
+The communication between HOST and board is based on
+- for UARTs : the uart protocol used with all MCU STM32
+- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)

diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
new file mode 100644 (file)
index 0000000..03f900a
--- /dev/null
+++ b/board/st/stm32mp1/board.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#ifdef CONFIG_PMIC_STPMU1
+int board_ddr_power_init(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device_by_driver(UCLASS_PMIC,
+                                         DM_GET_DRIVER(pmic_stpmu1), &dev);
+       if (ret)
+               /* No PMIC on board */
+               return 0;
+
+       /* Set LDO3 to sync mode */
+       ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
+       if (ret < 0)
+               return ret;
+
+       ret &= ~STPMU1_LDO3_MODE;
+       ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
+       ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
+
+       ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+                            ret);
+       if (ret < 0)
+               return ret;
+
+       /* Set BUCK2 to 1.35V */
+       ret = pmic_clrsetbits(dev,
+                             STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+                             STPMU1_BUCK_OUTPUT_MASK,
+                             STPMU1_BUCK2_1350000V);
+       if (ret < 0)
+               return ret;
+
+       /* Enable BUCK2 and VREF */
+       ret = pmic_clrsetbits(dev,
+                             STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+                             STPMU1_BUCK_EN, STPMU1_BUCK_EN);
+       if (ret < 0)
+               return ret;
+
+       mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+       ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
+                             STPMU1_VREF_EN, STPMU1_VREF_EN);
+       if (ret < 0)
+               return ret;
+
+       mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+       /* Enable LDO3 */
+       ret = pmic_clrsetbits(dev,
+                             STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+                             STPMU1_LDO_EN, STPMU1_LDO_EN);
+       if (ret < 0)
+               return ret;
+
+       mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+       return 0;
+}
+#endif

diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
new file mode 100644 (file)
index 0000000..b7e5f24
--- /dev/null
+++ b/board/st/stm32mp1/spl.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <post.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+#include <asm/arch/ddr.h>
+
+void spl_board_init(void)
+{
+       /* Keep vdd on during the reset cycle */
+#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT)
+       struct udevice *dev;
+       int ret;
+
+       ret = uclass_get_device_by_driver(UCLASS_PMIC,
+                                         DM_GET_DRIVER(pmic_stpmu1), &dev);
+       if (!ret)
+               pmic_clrsetbits(dev,
+                               STPMU1_MASK_RESET_BUCK,
+                               STPMU1_MASK_RESET_BUCK3,
+                               STPMU1_MASK_RESET_BUCK3);
+#endif
+}

diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
new file mode 100644 (file)
index 0000000..84c971c
--- /dev/null
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+       return 0;
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+       return 0;
+}

diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index e6b69da3da7fb41c8a851d89f8ed6588bf5f5d90..18f7666b1582c18ca5fca37f5b333e4003e02f80 100644 (file)
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -47,6 +47,18 @@ int board_early_init_f(void)
 }
 
 #ifdef CONFIG_ISA_ARCV2
+
+void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+       void (*kernel_entry)(int zero, int arch, uint params);
+
+       kernel_entry = (void (*)(int, int, uint))entry;
+
+       smp_set_core_boot_addr(entry, -1);
+       smp_kick_all_cpus();
+       kernel_entry(zero, arch, params);
+}
+
 #define RESET_VECTOR_ADDR      0x0
 
 void smp_set_core_boot_addr(unsigned long addr, int corenr)

diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index d034bc479d067eaff57fd70676f72355480190a4..e22bd1e40b26d5bd3e283e77c90b500c3c6dd14c 100644 (file)
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -1,5 +1,5 @@
-AXS10X BOARD
-M:     Alexey Brodkin <abrodkin@synopsys.com>
+HSDK BOARD
+M:     Eugeniy Paltsev <paltsev@synopsys.com>
 S:     Maintained
 F:     board/synopsys/hsdk/
 F:     configs/hsdk_defconfig

diff --git a/board/synopsys/hsdk/Makefile b/board/synopsys/hsdk/Makefile
index d84dd03265243a07424b5d30760efaeb291b75a5..7ecff3d7400ef6172ddc0c0333a7891ccda2658e 100644 (file)
--- a/board/synopsys/hsdk/Makefile
+++ b/board/synopsys/hsdk/Makefile
@@ -5,3 +5,5 @@
 #
 
 obj-y  += hsdk.o
+obj-y  += env-lib.o
+obj-y  += clk-lib.o

diff --git a/board/synopsys/hsdk/clk-lib.c b/board/synopsys/hsdk/clk-lib.c
new file mode 100644 (file)
index 0000000..1ce54af
--- /dev/null
+++ b/board/synopsys/hsdk/clk-lib.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <clk.h>
+#include <dm/device.h>
+
+#include "clk-lib.h"
+
+#define HZ_IN_MHZ      1000000
+#define ceil(x, y)     ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; })
+
+int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl)
+{
+       int ret;
+       ulong mhz_rate, priv_rate;
+       struct clk clk;
+
+       /* Dummy fmeas device, just to be able to use standard clk_* api */
+       struct udevice fmeas = {
+               .name = "clk-fmeas",
+               .node = ofnode_path("/clk-fmeas"),
+       };
+
+       ret = clk_get_by_name(&fmeas, name, &clk);
+       if (ret) {
+               pr_err("clock '%s' not found, err=%d\n", name, ret);
+               return ret;
+       }
+
+       if (ctl & CLK_ON) {
+               ret = clk_enable(&clk);
+               if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+                       return ret;
+       }
+
+       if ((ctl & CLK_SET) && rate) {
+               priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate;
+               ret = clk_set_rate(&clk, priv_rate);
+               if (ret)
+                       return ret;
+       }
+
+       if (ctl & CLK_OFF) {
+               ret = clk_disable(&clk);
+               if (ret) {
+                       pr_err("clock '%s' can't be disabled, err=%d\n", name, ret);
+                       return ret;
+               }
+       }
+
+       priv_rate = clk_get_rate(&clk);
+
+       clk_free(&clk);
+
+       mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
+
+       if (ctl & CLK_MHZ)
+               priv_rate = mhz_rate;
+
+       if ((ctl & CLK_GET) && rate)
+               *rate = priv_rate;
+
+       if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ))
+               printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate);
+       else if (ctl & CLK_PRINT)
+               printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate);
+       else
+               debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);
+
+       return 0;
+}

diff --git a/board/synopsys/hsdk/clk-lib.h b/board/synopsys/hsdk/clk-lib.h
new file mode 100644 (file)
index 0000000..3b7dbc5
--- /dev/null
+++ b/board/synopsys/hsdk/clk-lib.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __BOARD_CLK_LIB_H
+#define __BOARD_CLK_LIB_H
+
+#include <common.h>
+
+enum clk_ctl_ops {
+       CLK_SET         = BIT(0), /* set frequency */
+       CLK_GET         = BIT(1), /* get frequency */
+       CLK_ON          = BIT(2), /* enable clock */
+       CLK_OFF         = BIT(3), /* disable clock */
+       CLK_PRINT       = BIT(4), /* print frequency */
+       CLK_MHZ         = BIT(5)  /* all values in MHZ instead of HZ */
+};
+
+/*
+ * Depending on the clk_ctl_ops enable / disable /
+ * set clock rate from 'rate' argument / read clock to 'rate' argument /
+ * print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz,
+ * otherwise - in Hz.
+ *
+ * This function expects "clk-fmeas" node in device tree:
+ * / {
+ *     clk-fmeas {
+ *             clocks = <&cpu_pll>, <&sys_pll>;
+ *             clock-names = "cpu-pll", "sys-pll";
+ *     };
+ * };
+ */
+int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl);
+
+#endif /* __BOARD_CLK_LIB_H */

diff --git a/board/synopsys/hsdk/env-lib.c b/board/synopsys/hsdk/env-lib.c
new file mode 100644 (file)
index 0000000..6b53d92
--- /dev/null
+++ b/board/synopsys/hsdk/env-lib.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "env-lib.h"
+
+#define MAX_CMD_LEN    25
+
+static void env_clear_common(u32 index, const struct env_map_common *map)
+{
+       map[index].val->val = 0;
+       map[index].val->set = false;
+}
+
+static int env_read_common(u32 index, const struct env_map_common *map)
+{
+       u32 val;
+
+       if (!env_get_yesno(map[index].env_name)) {
+               if (map[index].type == ENV_HEX) {
+                       val = (u32)env_get_hex(map[index].env_name, 0);
+                       debug("ENV: %s: = %#x\n", map[index].env_name, val);
+               } else {
+                       val = (u32)env_get_ulong(map[index].env_name, 10, 0);
+                       debug("ENV: %s: = %d\n", map[index].env_name, val);
+               }
+
+               map[index].val->val = val;
+               map[index].val->set = true;
+       }
+
+       return 0;
+}
+
+static void env_clear_core(u32 index, const struct env_map_percpu *map)
+{
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               (*map[index].val)[i].val = 0;
+               (*map[index].val)[i].set = false;
+       }
+}
+
+static int env_read_core(u32 index, const struct env_map_percpu *map)
+{
+       u32 val;
+       char command[MAX_CMD_LEN];
+
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               sprintf(command, "%s_%u", map[index].env_name, i);
+               if (!env_get_yesno(command)) {
+                       if (map[index].type == ENV_HEX) {
+                               val = (u32)env_get_hex(command, 0);
+                               debug("ENV: %s: = %#x\n", command, val);
+                       } else {
+                               val = (u32)env_get_ulong(command, 10, 0);
+                               debug("ENV: %s: = %d\n", command, val);
+                       }
+
+                       (*map[index].val)[i].val = val;
+                       (*map[index].val)[i].set = true;
+               }
+       }
+
+       return 0;
+}
+
+static int env_validate_common(u32 index, const struct env_map_common *map)
+{
+       u32 value = map[index].val->val;
+       bool set = map[index].val->set;
+       u32 min = map[index].min;
+       u32 max = map[index].max;
+
+       /* Check if environment is mandatory */
+       if (map[index].mandatory && !set) {
+               pr_err("Variable \'%s\' is mandatory, but it is not defined\n",
+                      map[index].env_name);
+
+               return -EINVAL;
+       }
+
+       /* Check environment boundary */
+       if (set && (value < min || value > max)) {
+               if (map[index].type == ENV_HEX)
+                       pr_err("Variable \'%s\' must be between %#x and %#x\n",
+                              map[index].env_name, min, max);
+               else
+                       pr_err("Variable \'%s\' must be between %u and %u\n",
+                              map[index].env_name, min, max);
+
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int env_validate_core(u32 index, const struct env_map_percpu *map,
+                            bool (*cpu_used)(u32))
+{
+       u32 value;
+       bool set;
+       bool mandatory = map[index].mandatory;
+       u32 min, max;
+
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               set = (*map[index].val)[i].set;
+               value = (*map[index].val)[i].val;
+
+               /* Check if environment is mandatory */
+               if (cpu_used(i) && mandatory && !set) {
+                       pr_err("CPU %u is used, but \'%s_%u\' is not defined\n",
+                              i, map[index].env_name, i);
+
+                       return -EINVAL;
+               }
+
+               min = map[index].min[i];
+               max = map[index].max[i];
+
+               /* Check environment boundary */
+               if (set && (value < min || value > max)) {
+                       if (map[index].type == ENV_HEX)
+                               pr_err("Variable \'%s_%u\' must be between %#x and %#x\n",
+                                      map[index].env_name, i, min, max);
+                       else
+                               pr_err("Variable \'%s_%u\' must be between %d and %d\n",
+                                      map[index].env_name, i, min, max);
+
+                       return -EINVAL;
+               }
+       }
+
+       return 0;
+}
+
+void envs_cleanup_core(const struct env_map_percpu *map)
+{
+       /* Cleanup env struct first */
+       for (u32 i = 0; map[i].env_name; i++)
+               env_clear_core(i, map);
+}
+
+void envs_cleanup_common(const struct env_map_common *map)
+{
+       /* Cleanup env struct first */
+       for (u32 i = 0; map[i].env_name; i++)
+               env_clear_common(i, map);
+}
+
+int envs_read_common(const struct env_map_common *map)
+{
+       int ret;
+
+       for (u32 i = 0; map[i].env_name; i++) {
+               ret = env_read_common(i, map);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+int envs_validate_common(const struct env_map_common *map)
+{
+       int ret;
+
+       for (u32 i = 0; map[i].env_name; i++) {
+               ret = env_validate_common(i, map);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+int envs_read_validate_common(const struct env_map_common *map)
+{
+       int ret;
+
+       envs_cleanup_common(map);
+
+       ret = envs_read_common(map);
+       if (ret)
+               return ret;
+
+       ret = envs_validate_common(map);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+int envs_read_validate_core(const struct env_map_percpu *map,
+                           bool (*cpu_used)(u32))
+{
+       int ret;
+
+       envs_cleanup_core(map);
+
+       for (u32 i = 0; map[i].env_name; i++) {
+               ret = env_read_core(i, map);
+               if (ret)
+                       return ret;
+       }
+
+       for (u32 i = 0; map[i].env_name; i++) {
+               ret = env_validate_core(i, map, cpu_used);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+int envs_process_and_validate(const struct env_map_common *common,
+                             const struct env_map_percpu *core,
+                             bool (*cpu_used)(u32))
+{
+       int ret;
+
+       ret = envs_read_validate_common(common);
+       if (ret)
+               return ret;
+
+       ret = envs_read_validate_core(core, cpu_used);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int args_envs_read_search(const struct env_map_common *map,
+                                int argc, char *const argv[])
+{
+       for (int i = 0; map[i].env_name; i++) {
+               if (!strcmp(argv[0], map[i].env_name))
+                       return i;
+       }
+
+       pr_err("Unexpected argument '%s', can't parse\n", argv[0]);
+
+       return -ENOENT;
+}
+
+static int arg_read_set(const struct env_map_common *map, u32 i, int argc,
+                       char *const argv[])
+{
+       char *endp = argv[1];
+
+       if (map[i].type == ENV_HEX)
+               map[i].val->val = simple_strtoul(argv[1], &endp, 16);
+       else
+               map[i].val->val = simple_strtoul(argv[1], &endp, 10);
+
+       map[i].val->set = true;
+
+       if (*endp == '\0')
+               return 0;
+
+       pr_err("Unexpected argument '%s', can't parse\n", argv[1]);
+
+       map[i].val->set = false;
+
+       return -EINVAL;
+}
+
+int args_envs_enumerate(const struct env_map_common *map, int enum_by,
+                       int argc, char *const argv[])
+{
+       u32 i;
+
+       if (argc % enum_by) {
+               pr_err("unexpected argument number: %d\n", argc);
+               return -EINVAL;
+       }
+
+       while (argc > 0) {
+               i = args_envs_read_search(map, argc, argv);
+               if (i < 0)
+                       return i;
+
+               debug("ARG: found '%s' with index %d\n", map[i].env_name, i);
+
+               if (i < 0) {
+                       pr_err("unknown arg: %s\n", argv[0]);
+                       return -EINVAL;
+               }
+
+               if (arg_read_set(map, i, argc, argv))
+                       return -EINVAL;
+
+               debug("ARG: value.s '%s' == %#x\n", argv[1], map[i].val->val);
+
+               argc -= enum_by;
+               argv += enum_by;
+       }
+
+       return 0;
+}

diff --git a/board/synopsys/hsdk/env-lib.h b/board/synopsys/hsdk/env-lib.h
new file mode 100644 (file)
index 0000000..606e802
--- /dev/null
+++ b/board/synopsys/hsdk/env-lib.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __BOARD_ENV_LIB_H
+#define __BOARD_ENV_LIB_H
+
+#include <common.h>
+#include <config.h>
+#include <linux/kernel.h>
+
+enum env_type {
+       ENV_DEC,
+       ENV_HEX
+};
+
+typedef struct {
+       u32 val;
+       bool set;
+} u32_env;
+
+struct env_map_common {
+       const char *const env_name;
+       enum env_type type;
+       bool mandatory;
+       u32 min;
+       u32 max;
+       u32_env *val;
+};
+
+struct env_map_percpu {
+       const char *const env_name;
+       enum env_type type;
+       bool mandatory;
+       u32 min[NR_CPUS];
+       u32 max[NR_CPUS];
+       u32_env (*val)[NR_CPUS];
+};
+
+void envs_cleanup_common(const struct env_map_common *map);
+int envs_read_common(const struct env_map_common *map);
+int envs_validate_common(const struct env_map_common *map);
+int envs_read_validate_common(const struct env_map_common *map);
+
+void envs_cleanup_core(const struct env_map_percpu *map);
+int envs_read_validate_core(const struct env_map_percpu *map,
+                           bool (*cpu_used)(u32));
+int envs_process_and_validate(const struct env_map_common *common,
+                             const struct env_map_percpu *core,
+                             bool (*cpu_used)(u32));
+
+int args_envs_enumerate(const struct env_map_common *map,
+                       int enum_by, int argc, char *const argv[]);
+
+#endif /* __BOARD_ENV_LIB_H */

diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 7641978a7b13d7b5bd17cccca06b640499c8b49e..65f937fd0fe8ca1c7315ef8520ef84d6b3c23842 100644 (file)
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -1,34 +1,1024 @@
 /*
- * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <config.h>
+#include <linux/printk.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/arcregs.h>
+#include <fdt_support.h>
 #include <dwmmc.h>
 #include <malloc.h>
+#include <usb.h>
+
+#include "clk-lib.h"
+#include "env-lib.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define        CREG_BASE       (ARC_PERIPHERAL_BASE + 0x1000)
-#define        CREG_PAE        (CREG_BASE + 0x180)
-#define        CREG_PAE_UPDATE (CREG_BASE + 0x194)
-#define        CREG_CPU_START  (CREG_BASE + 0x400)
+#define ALL_CPU_MASK           GENMASK(NR_CPUS - 1, 0)
+#define MASTER_CPU_ID          0
+#define APERTURE_SHIFT         28
+#define NO_CCM                 0x10
+#define SLAVE_CPU_READY                0x12345678
+#define BOOTSTAGE_1            1 /* after SP, FP setup, before HW init */
+#define BOOTSTAGE_2            2 /* after HW init, before self halt */
+#define BOOTSTAGE_3            3 /* after self halt */
+#define BOOTSTAGE_4            4 /* before app launch */
+#define BOOTSTAGE_5            5 /* after app launch, unreachable */
+
+#define RESET_VECTOR_ADDR      0x0
+
+#define CREG_BASE              (ARC_PERIPHERAL_BASE + 0x1000)
+#define CREG_CPU_START         (CREG_BASE + 0x400)
+#define CREG_CPU_START_MASK    0xF
+
+#define SDIO_BASE              (ARC_PERIPHERAL_BASE + 0xA000)
+#define SDIO_UHS_REG_EXT       (SDIO_BASE + 0x108)
+#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+
+/* Uncached access macros */
+#define arc_read_uncached_32(ptr)      \
+({                                     \
+       unsigned int __ret;             \
+       __asm__ __volatile__(           \
+       "       ld.di %0, [%1]  \n"     \
+       : "=r"(__ret)                   \
+       : "r"(ptr));                    \
+       __ret;                          \
+})
+
+#define arc_write_uncached_32(ptr, data)\
+({                                     \
+       __asm__ __volatile__(           \
+       "       st.di %0, [%1]  \n"     \
+       :                               \
+       : "r"(data), "r"(ptr));         \
+})
+
+struct hsdk_env_core_ctl {
+       u32_env entry[NR_CPUS];
+       u32_env iccm[NR_CPUS];
+       u32_env dccm[NR_CPUS];
+};
+
+struct hsdk_env_common_ctl {
+       bool halt_on_boot;
+       u32_env core_mask;
+       u32_env cpu_freq;
+       u32_env axi_freq;
+       u32_env tun_freq;
+       u32_env nvlim;
+       u32_env icache;
+       u32_env dcache;
+};
+
+/*
+ * Uncached cross-cpu structure. All CPUs must access to this structure fields
+ * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
+ * implement ld.di / st.di instructions). Simultaneous cached and uncached
+ * access to this area will lead to data loss.
+ * We flush all data caches in board_early_init_r() as we don't want to have
+ * any dirty line in L1d$ or SL$ in this area.
+ */
+struct hsdk_cross_cpu {
+       /* slave CPU ready flag */
+       u32 ready_flag;
+       /* address of the area, which can be used for stack by slave CPU */
+       u32 stack_ptr;
+       /* slave CPU status - bootstage number */
+       s32 status[NR_CPUS];
+
+       /*
+        * Slave CPU data - it is copy of corresponding fields in
+        * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
+        * required for slave CPUs initialization.
+        * This fields can be populated by copying from hsdk_env_core_ctl
+        * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
+        * function.
+        */
+       u32 entry[NR_CPUS];
+       u32 iccm[NR_CPUS];
+       u32 dccm[NR_CPUS];
+
+       u32 core_mask;
+       u32 icache;
+       u32 dcache;
+
+       u8 cache_padding[ARCH_DMA_MINALIGN];
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Place for slave CPUs temporary stack */
+static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
+
+static struct hsdk_env_common_ctl env_common = {};
+static struct hsdk_env_core_ctl env_core = {};
+static struct hsdk_cross_cpu cross_cpu_data;
+
+static const struct env_map_common env_map_common[] = {
+       { "core_mask",  ENV_HEX, true,  0x1, 0xF,       &env_common.core_mask },
+       { "non_volatile_limit", ENV_HEX, true, 0, 0xF,  &env_common.nvlim },
+       { "icache_ena", ENV_HEX, true,  0, 1,           &env_common.icache },
+       { "dcache_ena", ENV_HEX, true,  0, 1,           &env_common.dcache },
+       {}
+};
+
+static const struct env_map_common env_map_clock[] = {
+       { "cpu_freq",   ENV_DEC, false, 100, 1000,      &env_common.cpu_freq },
+       { "axi_freq",   ENV_DEC, false, 200, 800,       &env_common.axi_freq },
+       { "tun_freq",   ENV_DEC, false, 0, 150,         &env_common.tun_freq },
+       {}
+};
+
+static const struct env_map_percpu env_map_core[] = {
+       { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
+       { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
+       {}
+};
+
+static const struct env_map_common env_map_mask[] = {
+       { "core_mask",  ENV_HEX, false, 0x1, 0xF,       &env_common.core_mask },
+       {}
+};
+
+static const struct env_map_percpu env_map_go[] = {
+       { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
+       {}
+};
+
+static void sync_cross_cpu_data(void)
+{
+       u32 value;
+
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               value = env_core.entry[i].val;
+               arc_write_uncached_32(&cross_cpu_data.entry[i], value);
+       }
+
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               value = env_core.iccm[i].val;
+               arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
+       }
+
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               value = env_core.dccm[i].val;
+               arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
+       }
+
+       value = env_common.core_mask.val;
+       arc_write_uncached_32(&cross_cpu_data.core_mask, value);
+
+       value = env_common.icache.val;
+       arc_write_uncached_32(&cross_cpu_data.icache, value);
+
+       value = env_common.dcache.val;
+       arc_write_uncached_32(&cross_cpu_data.dcache, value);
+}
+
+/* Can be used only on master CPU */
+static bool is_cpu_used(u32 cpu_id)
+{
+       return !!(env_common.core_mask.val & BIT(cpu_id));
+}
+
+/* TODO: add ICCM BCR and DCCM BCR runtime check */
+static void init_slave_cpu_func(u32 core)
+{
+       u32 val;
+
+       /* Remap ICCM to another memory region if it exists */
+       val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
+       if (val != NO_CCM)
+               write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
+
+       /* Remap DCCM to another memory region if it exists */
+       val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
+       if (val != NO_CCM)
+               write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
+
+       if (arc_read_uncached_32(&cross_cpu_data.icache))
+               icache_enable();
+       else
+               icache_disable();
+
+       if (arc_read_uncached_32(&cross_cpu_data.dcache))
+               dcache_enable();
+       else
+               dcache_disable();
+}
+
+static void init_cluster_nvlim(void)
+{
+       u32 val = env_common.nvlim.val << APERTURE_SHIFT;
+
+       flush_dcache_all();
+       write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
+       write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
+       flush_n_invalidate_dcache_all();
+}
+
+static void init_master_icache(void)
+{
+       if (icache_status()) {
+               /* I$ is enabled - we need to disable it */
+               if (!env_common.icache.val)
+                       icache_disable();
+       } else {
+               /* I$ is disabled - we need to enable it */
+               if (env_common.icache.val) {
+                       icache_enable();
+
+                       /* invalidate I$ right after enable */
+                       invalidate_icache_all();
+               }
+       }
+}
+
+static void init_master_dcache(void)
+{
+       if (dcache_status()) {
+               /* D$ is enabled - we need to disable it */
+               if (!env_common.dcache.val)
+                       dcache_disable();
+       } else {
+               /* D$ is disabled - we need to enable it */
+               if (env_common.dcache.val)
+                       dcache_enable();
+
+               /* TODO: probably we need ti invalidate D$ right after enable */
+       }
+}
+
+static int cleanup_before_go(void)
+{
+       disable_interrupts();
+       sync_n_cleanup_cache_all();
+
+       return 0;
+}
+
+void slave_cpu_set_boot_addr(u32 addr)
+{
+       /* All cores have reset vector pointing to 0 */
+       writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+       /* Make sure other cores see written value in memory */
+       sync_n_cleanup_cache_all();
+}
+
+static inline void halt_this_cpu(void)
+{
+       __builtin_arc_flag(1);
+}
+
+static void smp_kick_cpu_x(u32 cpu_id)
+{
+       int cmd = readl((void __iomem *)CREG_CPU_START);
+
+       if (cpu_id > NR_CPUS)
+               return;
+
+       cmd &= ~CREG_CPU_START_MASK;
+       cmd |= (1 << cpu_id);
+       writel(cmd, (void __iomem *)CREG_CPU_START);
+}
+
+static u32 prepare_cpu_ctart_reg(void)
+{
+       int cmd = readl((void __iomem *)CREG_CPU_START);
+
+       cmd &= ~CREG_CPU_START_MASK;
+
+       return cmd | env_common.core_mask.val;
+}
+
+/* slave CPU entry for configuration */
+__attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
+{
+       __asm__ __volatile__(
+               "ld.di  r8,     [%0]\n"
+               "mov    %%sp,   r8\n"
+               "mov    %%fp,   %%sp\n"
+               : /* no output */
+               : "r" (&cross_cpu_data.stack_ptr));
+
+       invalidate_icache_all();
+
+       arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
+       init_slave_cpu_func(CPU_ID_GET());
+
+       arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
+       arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
+
+       /* Halt the processor until the master kick us again */
+       halt_this_cpu();
+
+       /*
+        * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
+        * cores but we leave them for gebug purposes.
+        */
+       __builtin_arc_nop();
+       __builtin_arc_nop();
+       __builtin_arc_nop();
+
+       arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
+
+       /* get the updated entry - invalidate i$ */
+       invalidate_icache_all();
+
+       arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
+
+       /* Run our program */
+       ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
+
+       /* This bootstage is unreachable as we don't return from app we launch */
+       arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
+
+       /* Something went terribly wrong */
+       while (true)
+               halt_this_cpu();
+}
+
+static void clear_cross_cpu_data(void)
+{
+       arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
+       arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
+
+       for (u32 i = 0; i < NR_CPUS; i++)
+               arc_write_uncached_32(&cross_cpu_data.status[i], 0);
+}
+
+static noinline void do_init_slave_cpu(u32 cpu_id)
+{
+       /* attempts number for check clave CPU ready_flag */
+       u32 attempts = 100;
+       u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
+
+       if (cpu_id >= NR_CPUS)
+               return;
+
+       arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
+
+       /* Use global unique place for each slave cpu stack */
+       arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
+
+       debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
+       debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
+       slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
+
+       smp_kick_cpu_x(cpu_id);
+
+       debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
+             arc_read_uncached_32(&cross_cpu_data.ready_flag));
+
+       while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
+               mdelay(10);
+
+       /* Just to be sure that slave cpu is halted after it set ready_flag */
+       mdelay(20);
+
+       /*
+        * Only print error here if we reach timeout as there is no option to
+        * halt slave cpu (or check that slave cpu is halted)
+        */
+       if (!attempts)
+               pr_err("CPU %u is not responding after init!\n", cpu_id);
+
+       /* Check current stage of slave cpu */
+       if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
+               pr_err("CPU %u status is unexpected: %d\n", cpu_id,
+                      arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
+
+       debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
+             arc_read_uncached_32(&cross_cpu_data.ready_flag));
+       debug("CPU %u: status: %d [after timeout]\n", cpu_id,
+             arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
+}
+
+static void do_init_slave_cpus(void)
+{
+       clear_cross_cpu_data();
+       sync_cross_cpu_data();
+
+       debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
+
+       for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
+               if (is_cpu_used(i))
+                       do_init_slave_cpu(i);
+}
+
+static void do_init_master_cpu(void)
+{
+       /*
+        * Setup master caches even if master isn't used as we want to use
+        * same cache configuration on all running CPUs
+        */
+       init_master_icache();
+       init_master_dcache();
+}
+
+enum hsdk_axi_masters {
+       M_HS_CORE = 0,
+       M_HS_RTT,
+       M_AXI_TUN,
+       M_HDMI_VIDEO,
+       M_HDMI_AUDIO,
+       M_USB_HOST,
+       M_ETHERNET,
+       M_SDIO,
+       M_GPU,
+       M_DMAC_0,
+       M_DMAC_1,
+       M_DVFS
+};
+
+#define UPDATE_VAL     1
+
+/*
+ * m   master          AXI_M_m_SLV0    AXI_M_m_SLV1    AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
+ * 0   HS (CBU)        0x11111111      0x63111111      0xFEDCBA98      0x0E543210
+ * 1   HS (RTT)        0x77777777      0x77777777      0xFEDCBA98      0x76543210
+ * 2   AXI Tunnel      0x88888888      0x88888888      0xFEDCBA98      0x76543210
+ * 3   HDMI-VIDEO      0x77777777      0x77777777      0xFEDCBA98      0x76543210
+ * 4   HDMI-ADUIO      0x77777777      0x77777777      0xFEDCBA98      0x76543210
+ * 5   USB-HOST        0x77777777      0x77999999      0xFEDCBA98      0x76DCBA98
+ * 6   ETHERNET        0x77777777      0x77999999      0xFEDCBA98      0x76DCBA98
+ * 7   SDIO            0x77777777      0x77999999      0xFEDCBA98      0x76DCBA98
+ * 8   GPU             0x77777777      0x77777777      0xFEDCBA98      0x76543210
+ * 9   DMAC (port #1)  0x77777777      0x77777777      0xFEDCBA98      0x76543210
+ * 10  DMAC (port #2)  0x77777777      0x77777777      0xFEDCBA98      0x76543210
+ * 11  DVFS            0x00000000      0x60000000      0x00000000      0x00000000
+ *
+ * Please read ARC HS Development IC Specification, section 17.2 for more
+ * information about apertures configuration.
+ * NOTE: we intentionally modify default settings in U-boot. Default settings
+ * are specified in "Table 111 CREG Address Decoder register reset values".
+ */
+
+#define CREG_AXI_M_SLV0(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m)))
+#define CREG_AXI_M_SLV1(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
+#define CREG_AXI_M_OFT0(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
+#define CREG_AXI_M_OFT1(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
+#define CREG_AXI_M_UPDT(m)  ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
+
+#define CREG_AXI_M_HS_CORE_BOOT        ((void __iomem *)(CREG_BASE + 0x010))
+
+#define CREG_PAE       ((void __iomem *)(CREG_BASE + 0x180))
+#define CREG_PAE_UPDT  ((void __iomem *)(CREG_BASE + 0x194))
+
+void init_memory_bridge(void)
+{
+       u32 reg;
+
+       /*
+        * M_HS_CORE has one unic register - BOOT.
+        * We need to clean boot mirror (BOOT[1:0]) bits in them.
+        */
+       reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
+       writel(reg, CREG_AXI_M_HS_CORE_BOOT);
+       writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
+       writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
+       writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
+       writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
+
+       writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
+       writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
+       writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
+       writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
+       writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
+       writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
+       writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
+       writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
+       writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
+       writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
+       writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
+       writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
+
+       writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
+       writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
+       writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
+       writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
+
+       writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
+       writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
+       writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
+       writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
+       writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
+
+       writel(0x00000000, CREG_PAE);
+       writel(UPDATE_VAL, CREG_PAE_UPDT);
+}
+
+static void setup_clocks(void)
+{
+       ulong rate;
+
+       /* Setup CPU clock */
+       if (env_common.cpu_freq.set) {
+               rate = env_common.cpu_freq.val;
+               soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
+       }
+
+       /* Setup TUN clock */
+       if (env_common.tun_freq.set) {
+               rate = env_common.tun_freq.val;
+               if (rate)
+                       soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
+               else
+                       soc_clk_ctl("tun-clk", NULL, CLK_OFF);
+       }
+
+       if (env_common.axi_freq.set) {
+               rate = env_common.axi_freq.val;
+               soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
+       }
+}
 
+static void do_init_cluster(void)
+{
+       /*
+        * A multi-core ARC HS configuration always includes only one
+        * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
+        * cores.
+        */
+       init_cluster_nvlim();
+}
+
+static int check_master_cpu_id(void)
+{
+       if (CPU_ID_GET() == MASTER_CPU_ID)
+               return 0;
+
+       pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
+
+       return -ENOENT;
+}
+
+static noinline int prepare_cpus(void)
+{
+       int ret;
+
+       ret = check_master_cpu_id();
+       if (ret)
+               return ret;
+
+       ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
+       if (ret)
+               return ret;
+
+       printf("CPU start mask is %#x\n", env_common.core_mask.val);
+
+       do_init_slave_cpus();
+       do_init_master_cpu();
+       do_init_cluster();
+
+       return 0;
+}
+
+static int hsdk_go_run(u32 cpu_start_reg)
+{
+       /* Cleanup caches, disable interrupts */
+       cleanup_before_go();
+
+       if (env_common.halt_on_boot)
+               halt_this_cpu();
+
+       /*
+        * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
+        * cores but we leave them for gebug purposes.
+        */
+       __builtin_arc_nop();
+       __builtin_arc_nop();
+       __builtin_arc_nop();
+
+       /* Kick chosen slave CPUs */
+       writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
+
+       if (is_cpu_used(MASTER_CPU_ID))
+               ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
+       else
+               halt_this_cpu();
+
+       pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
+
+       /*
+        * We will never return after executing our program if master cpu used
+        * otherwise halt master cpu manually.
+        */
+       while (true)
+               halt_this_cpu();
+
+       return 0;
+}
+
+int board_prep_linux(bootm_headers_t *images)
+{
+       int ret, ofst;
+       char mask[15];
+
+       ret = envs_read_validate_common(env_map_mask);
+       if (ret)
+               return ret;
+
+       /* Rollback to default values */
+       if (!env_common.core_mask.set) {
+               env_common.core_mask.val = ALL_CPU_MASK;
+               env_common.core_mask.set = true;
+       }
+
+       printf("CPU start mask is %#x\n", env_common.core_mask.val);
+
+       if (!is_cpu_used(MASTER_CPU_ID))
+               pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
+
+       /*
+        * If we want to launch linux on all CPUs we don't need to patch
+        * linux DTB as it is default configuration
+        */
+       if (env_common.core_mask.val == ALL_CPU_MASK)
+               return 0;
+
+       if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
+               pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
+               return 0;
+       }
+
+       /* patch '/possible-cpus' property according to cpu mask */
+       ofst = fdt_path_offset(images->ft_addr, "/");
+       sprintf(mask, "%s%s%s%s",
+               is_cpu_used(0) ? "0," : "",
+               is_cpu_used(1) ? "1," : "",
+               is_cpu_used(2) ? "2," : "",
+               is_cpu_used(3) ? "3," : "");
+       ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
+       /*
+        * If we failed to patch '/possible-cpus' property we don't need break
+        * linux loading process: kernel will handle it but linux will print
+        * warning like "Timeout: CPU1 FAILED to comeup !!!".
+        * So warn here about error, but return 0 like no error had occurred.
+        */
+       if (ret)
+               pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
+                      ret);
+
+       return 0;
+}
+
+void board_jump_and_run(ulong entry, int zero, int arch, uint params)
+{
+       void (*kernel_entry)(int zero, int arch, uint params);
+       u32 cpu_start_reg;
+
+       kernel_entry = (void (*)(int, int, uint))entry;
+
+       /* Prepare CREG_CPU_START for kicking chosen CPUs */
+       cpu_start_reg = prepare_cpu_ctart_reg();
+
+       /* In case of run without hsdk_init */
+       slave_cpu_set_boot_addr(entry);
+
+       /* In case of run with hsdk_init */
+       for (u32 i = 0; i < NR_CPUS; i++) {
+               env_core.entry[i].val = entry;
+               env_core.entry[i].set = true;
+       }
+       /* sync cross_cpu struct as we updated core-entry variables */
+       sync_cross_cpu_data();
+
+       /* Kick chosen slave CPUs */
+       writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
+
+       if (is_cpu_used(0))
+               kernel_entry(zero, arch, params);
+}
+
+static int hsdk_go_prepare_and_run(void)
+{
+       /* Prepare CREG_CPU_START for kicking chosen CPUs */
+       u32 reg = prepare_cpu_ctart_reg();
+
+       if (env_common.halt_on_boot)
+               printf("CPU will halt before application start, start application with debugger.\n");
+
+       return hsdk_go_run(reg);
+}
+
+static int do_hsdk_go(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       int ret;
+
+       /*
+        * Check for 'halt' parameter. 'halt' = enter halt-mode just before
+        * starting the application; can be used for debug.
+        */
+       if (argc > 1) {
+               env_common.halt_on_boot = !strcmp(argv[1], "halt");
+               if (!env_common.halt_on_boot) {
+                       pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
+                       return CMD_RET_FAILURE;
+               }
+       }
+
+       ret = check_master_cpu_id();
+       if (ret)
+               return ret;
+
+       ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
+       if (ret)
+               return ret;
+
+       /* sync cross_cpu struct as we updated core-entry variables */
+       sync_cross_cpu_data();
+
+       ret = hsdk_go_prepare_and_run();
+
+       return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+       hsdk_go, 3, 0, do_hsdk_go,
+       "Synopsys HSDK specific command",
+       "     - Boot stand-alone application on HSDK\n"
+       "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
+);
+
+static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       static bool done = false;
+       int ret;
+
+       /* hsdk_init can be run only once */
+       if (done) {
+               printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
+               return CMD_RET_FAILURE;
+       }
+
+       ret = prepare_cpus();
+       if (!ret)
+               done = true;
+
+       return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+       hsdk_init, 1, 0, do_hsdk_init,
+       "Synopsys HSDK specific command",
+       "- Init HSDK HW\n"
+);
+
+static int do_hsdk_clock_set(cmd_tbl_t *cmdtp, int flag, int argc,
+                            char *const argv[])
+{
+       int ret = 0;
+
+       /* Strip off leading subcommand argument */
+       argc--;
+       argv++;
+
+       envs_cleanup_common(env_map_clock);
+
+       if (!argc) {
+               printf("Set clocks to values specified in environment\n");
+               ret = envs_read_common(env_map_clock);
+       } else {
+               printf("Set clocks to values specified in args\n");
+               ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
+       }
+
+       if (ret)
+               return CMD_RET_FAILURE;
+
+       ret = envs_validate_common(env_map_clock);
+       if (ret)
+               return CMD_RET_FAILURE;
+
+       /* Setup clock tree HW */
+       setup_clocks();
+
+       return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_get(cmd_tbl_t *cmdtp, int flag, int argc,
+                            char *const argv[])
+{
+       ulong rate;
+
+       if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
+               return CMD_RET_FAILURE;
+
+       if (env_set_ulong("cpu_freq", rate))
+               return CMD_RET_FAILURE;
+
+       if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
+               return CMD_RET_FAILURE;
+
+       if (env_set_ulong("tun_freq", rate))
+               return CMD_RET_FAILURE;
+
+       if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
+               return CMD_RET_FAILURE;
+
+       if (env_set_ulong("axi_freq", rate))
+               return CMD_RET_FAILURE;
+
+       printf("Clock values are saved to environment\n");
+
+       return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_print(cmd_tbl_t *cmdtp, int flag, int argc,
+                              char *const argv[])
+{
+       /* Main clocks */
+       soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
+
+       return CMD_RET_SUCCESS;
+}
+
+static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int flag, int argc,
+                                  char *const argv[])
+{
+       /*
+        * NOTE: as of today we don't use some peripherals like HDMI / EBI
+        * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
+        * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
+        * functional and we can print their clocks if it is required
+        */
+
+       /* CPU clock domain */
+       soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
+       printf("\n");
+
+       /* SYS clock domain */
+       soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
+/*     soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
+       soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
+/*     soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
+       soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
+       printf("\n");
+
+       /* DDR clock domain */
+       soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
+       printf("\n");
+
+       /* HDMI clock domain */
+/*     soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
+/*     soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
+/*     printf("\n"); */
+
+       /* TUN clock domain */
+       soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
+       soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
+       printf("\n");
+
+       return CMD_RET_SUCCESS;
+}
+
+cmd_tbl_t cmd_hsdk_clock[] = {
+       U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
+       U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
+       U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
+       U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
+};
+
+static int do_hsdk_clock(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       cmd_tbl_t *c;
+
+       if (argc < 2)
+               return CMD_RET_USAGE;
+
+       /* Strip off leading 'hsdk_clock' command argument */
+       argc--;
+       argv++;
+
+       c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
+       if (!c)
+               return CMD_RET_USAGE;
+
+       return c->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+       hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
+       "Synopsys HSDK specific clock command",
+       "set   - Set clock to values specified in environment / command line arguments\n"
+       "hsdk_clock get   - Save clock values to environment\n"
+       "hsdk_clock print - Print main clock values to console\n"
+       "hsdk_clock print_all - Print all clock values to console\n"
+);
+
+/* init calls */
 int board_early_init_f(void)
 {
-       /* In current chip PAE support for DMA is broken, disabling it. */
-       writel(0, (void __iomem *) CREG_PAE);
+       /*
+        * Setup AXI apertures unconditionally as we want to have DDR
+        * in 0x00000000 region when we are kicking slave cpus.
+        */
+       init_memory_bridge();
 
-       /* Really apply settings made above */
-       writel(1, (void __iomem *) CREG_PAE_UPDATE);
+       return 0;
+}
+
+int board_early_init_r(void)
+{
+       /*
+        * TODO: Init USB here to be able read environment from USB MSD.
+        * It can be done with usb_init() call. We can't do it right now
+        * due to brocken USB IP SW reset and lack of USB IP HW reset in
+        * linux kernel (if we init USB here we will break USB in linux)
+        */
+
+       /*
+        * Flush all d$ as we want to use uncached area with st.di / ld.di
+        * instructions and we don't want to have any dirty line in L1d$ or SL$
+        * in this area. It is enough to flush all d$ once here as we access to
+        * uncached area with regular st (non .di) instruction only when we copy
+        * data during u-boot relocation.
+        */
+       flush_dcache_all();
+
+       printf("Relocation Offset is: %08lx\n", gd->reloc_off);
 
        return 0;
 }
 
-#define SDIO_BASE              (ARC_PERIPHERAL_BASE + 0xA000)
-#define SDIO_UHS_REG_EXT       (SDIO_BASE + 0x108)
-#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+int board_late_init(void)
+{
+       /*
+        * Populate environment with clock frequency values -
+        * run hsdk_clock get callback without uboot command run.
+        */
+       do_hsdk_clock_get(NULL, 0, 0, NULL);
+
+       return 0;
+}
 
 int board_mmc_init(bd_t *bis)
 {
@@ -44,7 +1034,7 @@ int board_mmc_init(bd_t *bis)
         * Switch SDIO external ciu clock divider from default div-by-8 to
         * minimum possible div-by-2.
         */
-       writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
+       writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
 
        memset(host, 0, sizeof(struct dwmci_host));
        host->name = "Synopsys Mobile storage";
@@ -57,28 +1047,3 @@ int board_mmc_init(bd_t *bis)
 
        return 0;
 }
-
-#define RESET_VECTOR_ADDR      0x0
-
-void smp_set_core_boot_addr(unsigned long addr, int corenr)
-{
-       /* All cores have reset vector pointing to 0 */
-       writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
-
-       /* Make sure other cores see written value in memory */
-       flush_dcache_all();
-}
-
-void smp_kick_all_cpus(void)
-{
-#define BITS_START_CORE1       1
-#define BITS_START_CORE2       2
-#define BITS_START_CORE3       3
-
-       int cmd = readl((void __iomem *)CREG_CPU_START);
-
-       cmd |= (1 << BITS_START_CORE1) |
-              (1 << BITS_START_CORE2) |
-              (1 << BITS_START_CORE3);
-       writel(cmd, (void __iomem *)CREG_CPU_START);
-}

diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index e0dc4fed4833f16a9571beab9d63a97d1b007405..fc6463a8c61769ecb683fddfbfa2fde2e845ecc2 100644 (file)
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -1,6 +1,7 @@
 ZYNQ BOARD
 M:     Michal Simek <monstr@monstr.eu>
 S:     Maintained
+F:     arch/arm/dts/zynq-*
 F:     board/xilinx/zynq/
 F:     include/configs/zynq*.h
 F:     configs/zynq_*_defconfig

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index fb8eab07d76820dbc5fcc77756205b919d538a7e..838ac0f4c4eacb39defea2e8d946473b0ab81969 100644 (file)
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -6,9 +6,11 @@
  */
 
 #include <common.h>
+#include <dm/uclass.h>
 #include <fdtdec.h>
 #include <fpga.h>
 #include <mmc.h>
+#include <wdt.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
@@ -33,6 +35,22 @@ static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+static struct udevice *watchdog_dev;
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+# if defined(CONFIG_WDT)
+       /* bss is not cleared at time when watchdog_reset() is called */
+       watchdog_dev = NULL;
+# endif
+
+       return 0;
+}
+#endif
+
 int board_init(void)
 {
 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
@@ -75,6 +93,15 @@ int board_init(void)
        }
 #endif
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+       if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+               puts("Watchdog: Not found!\n");
+       } else {
+               wdt_start(watchdog_dev, 0, 0);
+               puts("Watchdog: Started\n");
+       }
+# endif
+
 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
     (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        fpga_init();
@@ -164,3 +191,25 @@ int dram_init(void)
        return 0;
 }
 #endif
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+# if !defined(CONFIG_SPL_BUILD)
+       static ulong next_reset;
+       ulong now;
+
+       if (!watchdog_dev)
+               return;
+
+       now = timer_get_us();
+
+       /* Do not reset the watchdog too often */
+       if (now > next_reset) {
+               wdt_reset(watchdog_dev);
+               next_reset = now + 1000;
+       }
+# endif
+}
+#endif

diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig
new file mode 100644 (file)
index 0000000..7d1f739
--- /dev/null
+++ b/board/xilinx/zynqmp/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQMP
+
+config CMD_ZYNQMP
+       bool "Enable ZynqMP specific commands"
+       default y
+       help
+         Enable ZynqMP specific commands like "zynqmp secure"
+         which is used for zynqmp secure image verification.
+         The secure image is a xilinx specific BOOT.BIN with
+         either authentication or encryption or both encryption
+         and authentication feature enabled while generating
+         BOOT.BIN using Xilinx bootgen tool.
+
+endif

diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 69edbf21f91c1023f5b76b9517a892727042246a..bb39f875fe06d0daf70f183da4db8836cec0533b 100644 (file)
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,6 +1,7 @@
 XILINX_ZYNQMP BOARDS
 M:     Michal Simek <michal.simek@xilinx.com>
 S:     Maintained
+F:     arch/arm/dts/zynqmp-*
 F:     board/xilinx/zynqmp/
 F:     include/configs/xilinx_zynqmp*
 F:     configs/xilinx_zynqmp*

diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 75aab92f047321eebbb59b4da8b72be25742d364..3b7a10e202e5623331eb2701667f41b7fda51080 100644 (file)
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -26,6 +26,10 @@ ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),)
 obj-y += $(init-objs)
 endif
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
+endif
+
 # Suppress "warning: function declaration isn't a prototype"
 CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
 

diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
new file mode 100644 (file)
index 0000000..6712d7b
--- /dev/null
+++ b/board/xilinx/zynqmp/cmds.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static int zynqmp_verify_secure(u8 *key_ptr, u8 *src_ptr, u32 len)
+{
+       int ret;
+       u32 src_lo, src_hi;
+       u32 key_lo = 0;
+       u32 key_hi = 0;
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       u64 addr;
+
+       if ((ulong)src_ptr != ALIGN((ulong)src_ptr,
+                                   CONFIG_SYS_CACHELINE_SIZE)) {
+               printf("Failed: source address not aligned:%p\n", src_ptr);
+               return -EINVAL;
+       }
+
+       src_lo = lower_32_bits((ulong)src_ptr);
+       src_hi = upper_32_bits((ulong)src_ptr);
+       flush_dcache_range((ulong)src_ptr, (ulong)(src_ptr + len));
+
+       if (key_ptr) {
+               key_lo = lower_32_bits((ulong)key_ptr);
+               key_hi = upper_32_bits((ulong)key_ptr);
+               flush_dcache_range((ulong)key_ptr,
+                                  (ulong)(key_ptr + KEY_PTR_LEN));
+       }
+
+       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD, src_lo, src_hi,
+                        key_lo, key_hi, ret_payload);
+       if (ret) {
+               printf("Failed: secure op status:0x%x\n", ret);
+       } else {
+               addr = (u64)ret_payload[1] << 32 | ret_payload[2];
+               printf("Verified image at 0x%llx\n", addr);
+               env_set_hex("zynqmp_verified_img_addr", addr);
+       }
+
+       return ret;
+}
+
+/**
+ * do_zynqmp - Handle the "zynqmp" command-line command
+ * @cmdtp:     Command data struct pointer
+ * @flag:      Command flag
+ * @argc:      Command-line argument count
+ * @argv:      Array of command-line arguments
+ *
+ * Processes the zynqmp specific commands
+ *
+ * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error
+ */
+static int do_zynqmp(cmd_tbl_t *cmdtp, int flag, int argc,
+                    char *const argv[])
+{
+       u64 src_addr;
+       u32 len;
+       u8 *key_ptr = NULL;
+       u8 *src_ptr;
+       int ret;
+
+       if (argc > 5 || argc < 4 || strncmp(argv[1], "secure", 6))
+               return CMD_RET_USAGE;
+
+       src_addr = simple_strtoull(argv[2], NULL, 16);
+
+       len = simple_strtoul(argv[3], NULL, 16);
+
+       if (argc > 4)
+               key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4],
+                                                               NULL, 16);
+
+       src_ptr = (uint8_t *)(uintptr_t)src_addr;
+
+       ret = zynqmp_verify_secure(key_ptr, src_ptr, len);
+       if (ret)
+               return CMD_RET_FAILURE;
+
+       return CMD_RET_SUCCESS;
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char zynqmp_help_text[] =
+       "secure src len [key_addr] - verifies secure images of $len bytes\n"
+       "                            long at address $src. Optional key_addr\n"
+       "                            can be specified if user key needs to\n"
+       "                            be used for decryption\n";
+#endif
+
+U_BOOT_CMD(
+       zynqmp, 5, 1, do_zynqmp,
+       "Verify and load secure images",
+       zynqmp_help_text
+)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ff0b3c75f53327faa489afab503fc9d3fce020bd..0d1bd5412b166e37f04f7cf67197e668def35edb 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -31,6 +31,7 @@ static const struct {
        u32 id;
        u32 ver;
        char *name;
+       bool evexists;
 } zynqmp_devices[] = {
        {
                .id = 0x10,
@@ -53,11 +54,13 @@ static const struct {
        {
                .id = 0x20,
                .name = "5ev",
+               .evexists = 1,
        },
        {
                .id = 0x20,
                .ver = 0x100,
                .name = "5eg",
+               .evexists = 1,
        },
        {
                .id = 0x20,
@@ -67,11 +70,13 @@ static const struct {
        {
                .id = 0x21,
                .name = "4ev",
+               .evexists = 1,
        },
        {
                .id = 0x21,
                .ver = 0x100,
                .name = "4eg",
+               .evexists = 1,
        },
        {
                .id = 0x21,
@@ -81,11 +86,13 @@ static const struct {
        {
                .id = 0x30,
                .name = "7ev",
+               .evexists = 1,
        },
        {
                .id = 0x30,
                .ver = 0x100,
                .name = "7eg",
+               .evexists = 1,
        },
        {
                .id = 0x30,
@@ -219,20 +226,48 @@ int chip_id(unsigned char id)
        return val;
 }
 
+#define ZYNQMP_VERSION_SIZE            9
+#define ZYNQMP_PL_STATUS_BIT           9
+#define ZYNQMP_PL_STATUS_MASK          BIT(ZYNQMP_PL_STATUS_BIT)
+#define ZYNQMP_CSU_VERSION_MASK                ~(ZYNQMP_PL_STATUS_MASK)
+
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
        !defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
        u32 i, id, ver;
+       char *buf;
+       static char name[ZYNQMP_VERSION_SIZE];
 
        id = chip_id(IDCODE);
        ver = chip_id(IDCODE2);
 
        for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-               if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
-                       return zynqmp_devices[i].name;
+               if ((zynqmp_devices[i].id == id) &&
+                   (zynqmp_devices[i].ver == (ver &
+                   ZYNQMP_CSU_VERSION_MASK))) {
+                       strncat(name, "zu", 2);
+                       strncat(name, zynqmp_devices[i].name,
+                               ZYNQMP_VERSION_SIZE - 3);
+                       break;
+               }
+       }
+
+       if (i >= ARRAY_SIZE(zynqmp_devices))
+               return "unknown";
+
+       if (!zynqmp_devices[i].evexists)
+               return name;
+
+       if (ver & ZYNQMP_PL_STATUS_MASK)
+               return name;
+
+       if (strstr(name, "eg") || strstr(name, "ev")) {
+               buf = strstr(name, "e");
+               *buf = '\0';
        }
-       return "unknown";
+
+       return name;
 }
 #endif
 
@@ -250,8 +285,6 @@ int board_early_init_f(void)
        return ret;
 }
 
-#define ZYNQMP_VERSION_SIZE    9
-
 int board_init(void)
 {
        printf("EL Level:\tEL%d\n", current_el());
@@ -260,12 +293,7 @@ int board_init(void)
     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
     defined(CONFIG_SPL_BUILD))
        if (current_el() != 3) {
-               static char version[ZYNQMP_VERSION_SIZE];
-
-               strncat(version, "zu", 2);
-               zynqmppl.name = strncat(version,
-                                       zynqmp_get_silicon_idcode_name(),
-                                       ZYNQMP_VERSION_SIZE - 3);
+               zynqmppl.name = zynqmp_get_silicon_idcode_name();
                printf("Chip ID:\t%s\n", zynqmppl.name);
                fpga_init();
                fpga_add(fpga_xilinx, &zynqmppl);
@@ -316,6 +344,23 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
        return 0;
 }
 
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+                        char * const argv[])
+{
+       int ret = 0;
+
+       if (current_el() > 1) {
+               smp_kick_all_cpus();
+               dcache_disable();
+               armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
+                                   ES_TO_AARCH64);
+       } else {
+               printf("FAIL: current EL is not above EL1\n");
+               ret = EINVAL;
+       }
+       return ret;
+}
+
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {

diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index 799ba01fcc8efbfb14a6a5b5f80947e37cb23d22..736f8c4527dfb9807a7edc7443676b6869a55585 100644 (file)
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -22,7 +22,7 @@ static int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc,
                return 0;
        }
        if (argc == 2) {
-               end_of_rom = (int)simple_strtoul(argv[1], &ep, 16);
+               end_of_rom = simple_strtoul(argv[1], &ep, 16);
                if (*ep) {
                        puts("\n** Invalid end of ROM **\n");
                        return 1;

diff --git a/cmd/sf.c b/cmd/sf.c
index f971eec781cc88978f181a9a24ec9d37dff6b11d..e7ff9a6462087239ca7a570c1a97f278d737468a 100644 (file)
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -287,7 +287,7 @@ static int do_spi_flash_read_write(int argc, char * const argv[])
        }
 
        buf = map_physmem(addr, len, MAP_WRBACK);
-       if (!buf) {
+       if (!buf && addr) {
                puts("Failed to map physical memory\n");
                return 1;
        }

diff --git a/common/board_f.c b/common/board_f.c
index 62588c5bad326f857f128b99f084082352c8528a..ae8bdb7c5c0c577df2d1999603bc5224f8318a97 100644 (file)
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -900,7 +900,8 @@ void board_init_f(ulong boot_flags)
                hang();
 
 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
-               !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
+               !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
+               !defined(CONFIG_ARC)
        /* NOTREACHED - jump_to_copy() does not return */
        hang();
 #endif

diff --git a/common/bootm_os.c b/common/bootm_os.c
index 5e6b1777e48ab04ff75776ef73d05f20a30e10a9..b84a8e26d2ce04000478c2cbccdf82e3b060b75c 100644 (file)
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -11,6 +11,7 @@
 #include <linux/libfdt.h>
 #include <malloc.h>
 #include <vxworks.h>
+#include <tee/optee.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -433,6 +434,34 @@ static int do_bootm_openrtos(int flag, int argc, char * const argv[],
 }
 #endif
 
+#ifdef CONFIG_BOOTM_OPTEE
+static int do_bootm_tee(int flag, int argc, char * const argv[],
+                       bootm_headers_t *images)
+{
+       int ret;
+
+       /* Verify OS type */
+       if (images->os.os != IH_OS_TEE) {
+               return 1;
+       };
+
+       /* Validate OPTEE header */
+       ret = optee_verify_bootm_image(images->os.image_start,
+                                      images->os.load,
+                                      images->os.image_len);
+       if (ret)
+               return ret;
+
+       /* Locate FDT etc */
+       ret = bootm_find_images(flag, argc, argv);
+       if (ret)
+               return ret;
+
+       /* From here we can run the regular linux boot path */
+       return do_bootm_linux(flag, argc, argv, images);
+}
+#endif
+
 static boot_os_fn *boot_os[] = {
        [IH_OS_U_BOOT] = do_bootm_standalone,
 #ifdef CONFIG_BOOTM_LINUX
@@ -466,6 +495,9 @@ static boot_os_fn *boot_os[] = {
 #ifdef CONFIG_BOOTM_OPENRTOS
        [IH_OS_OPENRTOS] = do_bootm_openrtos,
 #endif
+#ifdef CONFIG_BOOTM_OPTEE
+       [IH_OS_TEE] = do_bootm_tee,
+#endif
 };
 
 /* Allow for arch specific config before we boot */

diff --git a/common/image-fdt.c b/common/image-fdt.c
index 25103ba3b5d9debdd254631b47e78705a0a0b925..3dc02a12191d515fc19e10ba3abfe8c55633d234 100644 (file)
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -21,6 +21,9 @@
 #define CONFIG_SYS_FDT_PAD 0x3000
 #endif
 
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD   0x80
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static void fdt_error(const char *msg)

diff --git a/common/image-fit.c b/common/image-fit.c
index f6e956ad963a0d2a390c64bed812b23de9d4dbbc..4b0339045421c062ab0976b68eba60145e28ee20 100644 (file)
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1068,34 +1068,14 @@ static int fit_image_check_hash(const void *fit, int noffset, const void *data,
        return 0;
 }
 
-/**
- * fit_image_verify - verify data integrity
- * @fit: pointer to the FIT format image header
- * @image_noffset: component image node offset
- *
- * fit_image_verify() goes over component image hash nodes,
- * re-calculates each data hash and compares with the value stored in hash
- * node.
- *
- * returns:
- *     1, if all hashes are valid
- *     0, otherwise (or on error)
- */
-int fit_image_verify(const void *fit, int image_noffset)
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+                              const void *data, size_t size)
 {
-       const void      *data;
-       size_t          size;
        int             noffset = 0;
        char            *err_msg = "";
        int verify_all = 1;
        int ret;
 
-       /* Get image data and data length */
-       if (fit_image_get_data(fit, image_noffset, &data, &size)) {
-               err_msg = "Can't get image data/size";
-               goto error;
-       }
-
        /* Verify all required signatures */
        if (IMAGE_ENABLE_VERIFY &&
            fit_image_verify_required_sigs(fit, image_noffset, data, size,
@@ -1152,6 +1132,38 @@ error:
        return 0;
 }
 
+/**
+ * fit_image_verify - verify data integrity
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: component image node offset
+ *
+ * fit_image_verify() goes over component image hash nodes,
+ * re-calculates each data hash and compares with the value stored in hash
+ * node.
+ *
+ * returns:
+ *     1, if all hashes are valid
+ *     0, otherwise (or on error)
+ */
+int fit_image_verify(const void *fit, int image_noffset)
+{
+       const void      *data;
+       size_t          size;
+       int             noffset = 0;
+       char            *err_msg = "";
+
+       /* Get image data and data length */
+       if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+               err_msg = "Can't get image data/size";
+               printf("error!\n%s for '%s' hash node in '%s' image node\n",
+                      err_msg, fit_get_name(fit, noffset, NULL),
+                      fit_get_name(fit, image_noffset, NULL));
+               return 0;
+       }
+
+       return fit_image_verify_with_data(fit, image_noffset, data, size);
+}
+
 /**
  * fit_all_image_verify - verify data integrity for all images
  * @fit: pointer to the FIT format image header

diff --git a/common/image.c b/common/image.c
index 14be3caf97303ce8de9e3ee0701d798a0695e08a..e1c50eb25d0e5e2814c200a3e8c025ac17cf756b 100644 (file)
--- a/common/image.c
+++ b/common/image.c
@@ -86,6 +86,7 @@ static const table_entry_t uimage_arch[] = {
        {       IH_ARCH_ARC,            "arc",          "ARC",          },
        {       IH_ARCH_X86_64,         "x86_64",       "AMD x86_64",   },
        {       IH_ARCH_XTENSA,         "xtensa",       "Xtensa",       },
+       {       IH_ARCH_RISCV,          "riscv",        "RISC-V",       },
        {       -1,                     "",             "",             },
 };
 
@@ -100,6 +101,7 @@ static const table_entry_t uimage_os[] = {
        {       IH_OS_OSE,      "ose",          "Enea OSE",             },
        {       IH_OS_PLAN9,    "plan9",        "Plan 9",               },
        {       IH_OS_RTEMS,    "rtems",        "RTEMS",                },
+       {       IH_OS_TEE,      "tee",          "Trusted Execution Environment" },
        {       IH_OS_U_BOOT,   "u-boot",       "U-Boot",               },
        {       IH_OS_VXWORKS,  "vxworks",      "VxWorks",              },
 #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
@@ -161,6 +163,7 @@ static const table_entry_t uimage_type[] = {
        {       IH_TYPE_TEE,        "tee",        "Trusted Execution Environment Image",},
        {       IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
        {       IH_TYPE_PMMC,        "pmmc",        "TI Power Management Micro-Controller Firmware",},
+       {       IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
        {       -1,                 "",           "",                   },
 };
 

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 9609fceea59fef0aa8725abc9b401a469990950d..b9b9e0f3a0a991c8a5621098bb142cf7da072dc6 100644 (file)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -568,6 +568,15 @@ config SPL_POST_MEM_SUPPORT
          performed before booting. This enables the drivers in post/drivers
          as part of an SPL build.
 
+config SPL_RESET_SUPPORT
+       bool "Support reset drivers"
+       depends on SPL
+       help
+         Enable support for reset control in SPL.
+         That can be useful in SPL to handle IP reset in driver, as in U-Boot,
+         by using the generic reset API provided by driver model.
+         This enables the drivers in drivers/reset as part of an SPL build.
+
 config SPL_POWER_SUPPORT
        bool "Support power drivers"
        help

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index b705d030e77521e497f8a2067d4387adc3858543..be92ca4b4fd0f0ce04a6e360429d04e420f2c230 100644 (file)
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -174,6 +174,9 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
        uint8_t image_comp = -1, type = -1;
        const void *data;
        bool external_data = false;
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+       int ret;
+#endif
 
        if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
                if (fit_image_get_comp(fit, node, &image_comp))
@@ -252,7 +255,16 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
                image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
        }
 
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+       printf("## Checking hash(es) for Image %s ...\n",
+              fit_get_name(fit, node, NULL));
+       ret = fit_image_verify_with_data(fit, node,
+                                        (const void *)load_addr, length);
+       printf("\n");
+       return !ret;
+#else
        return 0;
+#endif
 }
 
 static int spl_fit_append_fdt(struct spl_image_info *spl_image,

diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index faaee831cec21f295692364b7bc3216981a9dab1..2e204d539393e4220affbfdab8dfc2ee4a1ac36a 100644 (file)
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -5,7 +5,7 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
 CONFIG_USB0_VBUS_PIN="PB10"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
-CONFIG_SYS_NAND_OOBSIZE=0x1000
+CONFIG_SYS_NAND_PAGE_SIZE=0x1000
 CONFIG_SYS_NAND_OOBSIZE=0x100
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y

diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index f3eabea70e55560551e552448f58959a6a122b9c..af17718f90173b3d1c11f1c134187918fba498f9 100644 (file)
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -24,8 +24,8 @@ CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MMC=y
 CONFIG_DM_MMC=y
-CONFIG_MMC_NDS32=y
 CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y

diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 742d9046ad075bc98ceee062696de899fefc6f93..481ef5b8706da95b5b268d3a8eecb860b94888cc 100644 (file)
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -21,8 +21,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_MMC=y
 CONFIG_DM_MMC=y
-CONFIG_MMC_NDS32=y
 CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_DM_ETH=y
 CONFIG_FTMAC100=y

diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 60120bf163debcab37b3957454cf3dafe3a80dae..d1c78fa4898aa0cd54922312d50109750b71c315 100644 (file)
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -4,6 +4,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_AM33XX=y
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y

diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index c903cc780d934f14df02cb6976766816814d1799..a8ab3e6206f17cf412d3b19ffa626e2b4a8a91fe 100644 (file)
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -9,6 +9,7 @@ CONFIG_ISW_ENTRY_ADDR=0x40300350
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_LOAD_FIT=y

diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index d2026da7b34f3dcbb210a43a634f95fa6142ffaa..be4f1122861eab41a4459ca48fc07e071df09e7e 100644 (file)
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -37,8 +37,10 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),-(UBI)"
 CONFIG_CMD_UBI=y
+CONFIG_UBI_SILENCE_MSG=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_ENV_IS_IN_UBI=y
+CONFIG_UBIFS_SILENCE_MSG=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y
 CONFIG_MTD_UBI_FASTMAP=y

diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 2359ad2ebecc4e266bc44d2f484e70fc018f1039..ff954c76e2e55d3a766abb2cd46bc288740641b6 100644 (file)
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -30,6 +30,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y

diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig
index 892977a649b4bd9b49886d93d6904f37b42a6b67..6b2c3555fe64c11f59fa734ff84269375d012d2b 100644 (file)
--- a/configs/comtrend_ar5315u_ram_defconfig
+++ b/configs/comtrend_ar5315u_ram_defconfig
@@ -27,7 +27,9 @@ CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
@@ -38,7 +40,8 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
-CONFIG_POWER_DOMAIN=y
+CONFIG_PHY=y
+CONFIG_BCM6318_USBH_PHY=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
@@ -47,3 +50,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_DM_SPI=y
 CONFIG_BCM63XX_HSSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig
index 12dbf0bc27a289dc03a3ae9042a3f62b6049b340..efccf9adec798ccd5e3d429d16bec90dfe0a4d70 100644 (file)
--- a/configs/comtrend_ar5387un_ram_defconfig
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -27,7 +27,9 @@ CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
@@ -38,6 +40,8 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
@@ -47,3 +51,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
 CONFIG_DM_SPI=y
 CONFIG_BCM63XX_HSSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
index 108e8ea267c14bfc6f32c88230a968541fcdc395..708dcda3ddd11f0013937c596e77e60433e31183 100644 (file)
--- a/configs/comtrend_ct5361_ram_defconfig
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -24,7 +24,9 @@ CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
@@ -34,9 +36,15 @@ CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6348_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
 CONFIG_WDT_BCM6345=y

diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig
index 8149fabbc3e3c961e2a97a94fcbffa80861b4344..3920f3381c333f6b4730854778c424e9e086e968 100644 (file)
--- a/configs/comtrend_vr3032u_ram_defconfig
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -25,13 +25,17 @@ CONFIG_CMD_LICENSE=y
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_BCM6328=y
 CONFIG_LED_BLINK=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_BCM6328_POWER_DOMAIN=y
 CONFIG_DM_RESET=y
@@ -39,3 +43,9 @@ CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig
index 6112725a81a91e2eee2e7800053c09320a443140..a9c00e9122e66ce5f1c7c672961f9b7f569e452b 100644 (file)
--- a/configs/comtrend_wap5813n_ram_defconfig
+++ b/configs/comtrend_wap5813n_ram_defconfig
@@ -24,7 +24,9 @@ CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
@@ -34,8 +36,16 @@ CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index 11cb7e03a65996c064d992f752508e0b5155b94b..476ce6a9741d9f972d1a9708da0a9012ff7b0b20 100644 (file)
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -7,13 +7,18 @@ CONFIG_DEFAULT_DEVICE_TREE="hsdk"
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200n8"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="hsdk# "
+CONFIG_CMD_ENV_FLAGS=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -25,12 +30,20 @@ CONFIG_ENV_FAT_INTERFACE="mmc"
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
+CONFIG_CLK_HSDK=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
 CONFIG_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig
index b9208ff325c4e1b819e9d2b76d7a174b2f561ac2..4a13de46642db7455215fcaf77d53e57a4b8a529 100644 (file)
--- a/configs/huawei_hg556a_ram_defconfig
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -24,7 +24,9 @@ CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
@@ -34,8 +36,16 @@ CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6358_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index 0a3dff77968e5d151267511487f2dcba5559f981..7683e7412bdf7be200fb01f0cc088daa9243ba59 100644 (file)
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -27,7 +27,9 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_UBI=y
+CONFIG_UBI_SILENCE_MSG=y
 # CONFIG_CMD_UBIFS is not set
+CONFIG_UBIFS_SILENCE_MSG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y

diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 872766939ae6a2261f31b56c805335bd7f29cbcb..fef1331c0a4cfbffb0d2ba72d43728d86528a33c 100644 (file)
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -27,7 +27,9 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_UBI=y
+CONFIG_UBI_SILENCE_MSG=y
 # CONFIG_CMD_UBIFS is not set
+CONFIG_UBIFS_SILENCE_MSG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 26dcb1abb1694d0d0f6e8e62bad79049b565834a..af676e2898f556788e6635b97d3a8ad75bc3667e 100644 (file)
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -31,7 +31,9 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1164361b50cff5c42a06c7518547756e772b8d0f..c02e5205f6396ad7b04bcc3c3ae491b6597508e7 100644 (file)
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -29,8 +29,10 @@ CONFIG_DM=y
 # CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 9fdf3330aebfd08173902cec00e6a9d6a765113e..25470cb5fd79222267bed6f1737039f16b7b7b58 100644 (file)
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -36,8 +36,10 @@ CONFIG_SCSI_AHCI=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 43472635be8b53376962f92453097e1be547e7e1..1f629536eb9e4dfdac368af645b33750822d74c0 100644 (file)
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -32,8 +32,10 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_FSL_PFE=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y

diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
new file mode 100644 (file)
index 0000000..acb9d7b
--- /dev/null
+++ b/configs/ls1088aqds_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SYS_TEXT_BASE=0x30100000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_FSL_IFC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_USE_BOOTCOMMAND is not set

diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
new file mode 100644 (file)
index 0000000..d415026
--- /dev/null
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+CONFIG_SYS_TEXT_BASE=0x80400000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_PARTITIONS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SD_BOOT=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SPL=y
+CONFIG_SPL_BUILD=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FSL_IFC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y

diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 699dc447f0ff6d6f6cd539b78312db1cc3e848e1..18bec1f2e5de5f6e3548dda0aeb85bb170c9ac3b 100644 (file)
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x29000000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
 CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
@@ -15,7 +16,6 @@ CONFIG_BOOTDELAY=-1
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=romfs"
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_NOR_SUPPORT=y

diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 1d6233a6ffad0157fa9d3d5c5d226869734a44bb..980c0df479df47ffbbe5209eca77ed1c73225b0b 100644 (file)
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -17,6 +17,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -44,6 +45,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_AARDVARK=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ARMADA_37XX=y

diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 314d405ea3da289f6da5050c82e483102ac72999..aedb83ac01558d6901664b0d2af69475c98959db 100644 (file)
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -14,8 +14,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -29,6 +31,7 @@ CONFIG_MAC_PARTITION=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SCSI_AHCI=y
 CONFIG_BLOCK_CACHE=y
+CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
@@ -42,7 +45,13 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_AARDVARK=y
 CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_37XX=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DEBUG_MVEBU_A3700_UART=y
 CONFIG_DEBUG_UART_BASE=0xd0012000

diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig
index 595ad6cfaff2aba20ffe01dd0ea6bb9ff2d1255f..f1ceb5c2c769e8417878db322ae7a6cf1bdb0902 100644 (file)
--- a/configs/netgear_cg3100d_ram_defconfig
+++ b/configs/netgear_cg3100d_ram_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y

diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig
new file mode 100644 (file)
index 0000000..4968336
--- /dev/null
+++ b/configs/netgear_dgnd3700v2_ram_defconfig
@@ -0,0 +1,55 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6362=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="DGND3700v2 # "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_GPIO=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_PHY=y
+CONFIG_BCM6368_USBH_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_BCM6345=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/nx25-ae250_defconfig b/configs/nx25-ae250_defconfig
index 47b83db5eaef8fe30f8513437a85a81014b0dd25..4f9bd58f75568341970fbdfff7c542e346d433b7 100644 (file)
--- a/configs/nx25-ae250_defconfig
+++ b/configs/nx25-ae250_defconfig
@@ -16,14 +16,15 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_MMC=y
 CONFIG_DM_MMC=y
-CONFIG_MMC_NDS32=y
 CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y

diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index ccb308bf0177cf467cdb69ad1986a3922474121f..2c1bdb2e299462c19684a5bd3992b5a337dd9e24 100644 (file)
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_SYS_TEXT_BASE=0xc1080000
 CONFIG_TARGET_OMAPL138_LCDK=y
+CONFIG_SYS_DA850_PLL0_POSTDIV=0
 CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -9,11 +10,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
 CONFIG_BOOTDELAY=3
 CONFIG_LOGLEVEL=3
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
 CONFIG_SPL_BOARD_INIT=y
@@ -27,9 +28,13 @@ CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DIAG=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOOTP_DNS=y
+CONFIG_DM=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_COMPAT=y
 CONFIG_NAND=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
@@ -38,6 +43,6 @@ CONFIG_SPL_NAND_SIMPLE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_DAVINCI_SPI=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index a4ca68a752faf3bf71ef63a84c52463fb8549f8f..c512c1846d2126a9e4bee9553033ed7f23463278 100644 (file)
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -13,3 +13,5 @@ CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y

diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index a8b4bacbecf24b429dbf0a951b6a4a452cfbad11..32aa72c9e2454e881c38bd92ebe0eea16429e597 100644 (file)
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -56,6 +56,7 @@ CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y

diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig
index 886e3676af24986b557baf9cb56f6a5734313eea..7b049fceaa7ba3410d08b76af05ae2945dcebfe9 100644 (file)
--- a/configs/sagem_f@st1704_ram_defconfig
+++ b/configs/sagem_f@st1704_ram_defconfig
@@ -28,6 +28,7 @@ CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y

diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig
index 57ca22c4d6f574de6459c28171569bee7d06cc1e..f2031df8454d255e316cd80bb85f723e35d01d09 100644 (file)
--- a/configs/sfr_nb4-ser_ram_defconfig
+++ b/configs/sfr_nb4-ser_ram_defconfig
@@ -25,7 +25,9 @@ CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_EMBED=y
 # CONFIG_NET is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
@@ -36,8 +38,16 @@ CONFIG_LED_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_PHY=y
+CONFIG_BCM6358_USBH_PHY=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_BCM6345=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DM_SERIAL=y
 CONFIG_BCM6345_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y

diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 99eecd6487f6bb67bacb06eef83a166b7527c4af..8139ab1c0a405267da98cecb8fc384fc3cbec103 100644 (file)
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -29,6 +29,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -53,5 +54,10 @@ CONFIG_ETH_DESIGNWARE=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=640
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set

diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
new file mode 100644 (file)
index 0000000..4ab1d4c
--- /dev/null
+++ b/configs/stm32mp15_basic_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_STM32MP1=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ed1"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMU1=y
+CONFIG_STM32_SERIAL=y
+# CONFIG_EFI_LOADER is not set

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 67d1f545d713b68a54274734a3b2315c6838148c..005cb9ce2eb666d64a801c130f72ce52473baaaf 100644 (file)
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="opalkelly"
 CONFIG_SYS_CONFIG_NAME="syzygy_hub"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
 CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 8b02599b260ebf3566968ea3f44007876245815f..2dd938d09a74a360bf0843d854281041e5c02dbb 100644 (file)
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y

diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 572b2f5149eaf4ff71a4e31b11d3cdc7e25e7aa9..638cc34ac9450bd457cfa46415abe72f0325795a 100644 (file)
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y

diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 3e8504d6a0a38610d02162f114e7265e894afddb..ef91bd582513d7be5cab09b94df33282766aa1f8 100644 (file)
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="zynq-uboot> "
 CONFIG_CMD_THOR_DOWNLOAD=y

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
deleted file mode 100644 (file)
index a0c8f28..0000000
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_THOR_DOWNLOAD=y
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_SPL_ISO_PARTITION is not set
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
-CONFIG_NAND=y
-CONFIG_NAND_ARASAN=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=25000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_ZYNQMP=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

diff --git a/configs/xilinx_zynqmp_mini_emmc_defconfig b/configs/xilinx_zynqmp_mini_emmc_defconfig
index b15120e0fae4be95fea949dc6e188b789ed0ea82..8f2596a8940efb9eb358e1ac7f6a34e71a12d7ad 100644 (file)
--- a/configs/xilinx_zynqmp_mini_emmc_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y

diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index 55200bcb058d7509b390b5b6c5ed4df1b8ea48e5..1fec9bab7c0c7979dbd1068112bf9af73e3a310f 100644 (file)
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7da0ca8789be01bba27dde87744c81d728c49ac2..1125ebda8a9f02a44e9f183112461e7a4a2a158f 100644 (file)
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -45,6 +45,7 @@ CONFIG_ENV_IS_IN_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 3e531661eb63ac99906a478fd9f632b5a1d19574..8fc13ef0ecc4e8c3b9fbf3e81ddec225a73cdb36 100644 (file)
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
 # CONFIG_SPL_FAT_SUPPORT is not set
 CONFIG_ZYNQMP_USB=y
@@ -15,7 +16,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -44,6 +44,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 9bc0b77c2c8afe2cdb45cc4988fe57f6c0b2ce1c..0a057bf3fefd1e2f5fd4cfb770b35fba9ee17ae6 100644 (file)
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
 CONFIG_DEBUG_UART=y
@@ -11,7 +12,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y

diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ac565ecf8f9cde7547e7e807cc2f34d25e3a4a1c..47edf519f95300b8e7d6701a9b3c320435184858 100644 (file)
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_DEBUG_UART=y
@@ -12,7 +13,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
@@ -44,6 +45,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART_ZYNQ=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000

diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 1df5b0b5c6f98510431f931c37fd51bdd9958c52..cb3e2f5ca9f228cd33dcbf6cf78c5ddb5160e8bc 100644 (file)
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 rev1.0"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index c8a8362148d535d2e6a62474b34731790fc0bf53..19b9683f023b78fb1ab94d44b4da772dd4ae9c46 100644 (file)
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revA"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 8f85b5f6758e5a4e3e62f9e7c01bac536eff6604..b660200508f919c26d9ea01f8f18cb83884d29d1 100644 (file)
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102 revB"
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
@@ -14,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
 CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y

diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 3a4de92e4c4af77eff7448e0f526c970b3405606..d328fe6cfe940a75b6b266d659d096932e66812d 100644 (file)
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
 CONFIG_DEBUG_UART=y
@@ -10,7 +11,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_DFU=y

diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 80bb26c69f3aff214bd9146d11b5bf6845f8dc6d..d93cdbfba56804af40b39a57cee6a2f4c6334158 100644 (file)
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_cse"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_ZYNQ_DDRC_INIT is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
@@ -11,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=-1
 # CONFIG_USE_BOOTCOMMAND is not set
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_BDI is not set

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 94a1a40efb7456fc2eb3403ba5a13160cad9dfb9..25331cac86ab6843e16bed237efa2e0c5b20f0fc 100644 (file)
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_DISTRO_DEFAULTS=y
@@ -9,7 +10,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index f9ee904bd405e8390eb13a21da06c72fbd8a9650..6a841f8ecd7e06dd5991b50918731b0944a4eb69 100644 (file)
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,12 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index 7a51b85ac822b3f0db873c507e17bcb36ee8fd5b..9013239a8f1bdf62d0c568dcdd9b79ac3323a5f6 100644 (file)
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
 CONFIG_DEBUG_UART=y
@@ -10,7 +11,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 8e8b80053af1d0bfd62333ee7f6602cb8a4e416b..72c109b2e3dd265c88aacd58f3c59ec359ccbdab 100644 (file)
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC702"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 8f83d173c5354399d0bdc0d55a4ef95186a01a53..825a7263d22f71635b18b0c1cde6de6c05f57238 100644 (file)
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC706"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "
@@ -73,3 +73,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y

diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 8db30d0818079b5d22bdea52081bfa65b2e91e16..683dfe8d19c1b02acd52e293a4fee6015f6e0175 100644 (file)
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index b6ddf986c5403e4ad66735e5bd63e18c5b985330..9613b8af258cb260c25d7df08f682085cda77c87 100644 (file)
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -12,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index bd0ec7b33b784690b0fd1b08092b593c8b97aef9..884186a4600386e67d20c6fdd9b422bbc83e2291 100644 (file)
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -10,9 +11,8 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "
@@ -29,7 +29,6 @@ CONFIG_CMD_CACHE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQPL=y

diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 8dbba6589deb92d7f26d9f23cb90d9e235596e66..0b3db398f9cff4fcb211d0e9dcfad61c92b9a72f 100644 (file)
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index f9eabb12b500dbb03281fb9545532bb5d4e60032..d7d9d80ce6d8f028dce0f965081dd07a019e867b 100644 (file)
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_SPL_FAT_SUPPORT is not set
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7ed012833ad8f4763906563593904304b6b11ef0..9f76e5ed8f11a7317db1c67211ae788a34fd2987 100644 (file)
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,15 +1,16 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
+CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "
@@ -47,6 +48,9 @@ CONFIG_PHY_MARVELL=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_XILINX=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y

diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 92f3e1ec26acf8fe6e66523ec90b1e80f5932c21..15922d2fa1fc1bba824a90eb23a1b523fadf6748 100644 (file)
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="zynq_zybo"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
 CONFIG_DEBUG_UART=y
@@ -11,7 +12,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SYS_PROMPT="Zynq> "

diff --git a/doc/README.ae250 b/doc/README.ae250
index a80bb39b15750b84c6c9577adeba13f624070aa5..77c168af34c1d446b56314ca83a2080e3885e020 100644 (file)
--- a/doc/README.ae250
+++ b/doc/README.ae250
@@ -49,8 +49,8 @@ Steps
 5. Burn this u-boot image to spi rom by spi driver
 6. Re-boot u-boot from spi flash with power off and power on.
 
-Messages
-====================
+Messages of U-Boot boot on AE250 board
+======================================
 U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
 
 DRAM:  1 GiB
@@ -131,7 +131,145 @@ Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
 eth0: mac@e0100000
 RISC-V #
 
-TODO
-====================
 
-Boot bbl and riscv-linux
+Boot bbl and riscv-linux via U-Boot on QEMU
+===========================================
+1. Build riscv-linux
+2. Build bbl and riscv-linux with --with-payload
+3. Prepare ae250.dtb
+4. Creating OS-kernel images
+       ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
+       Image Name:
+       Created:      Tue Mar 13 10:06:42 2018
+       Image Type:   RISC-V Linux Kernel Image (uncompressed)
+       Data Size:    17901204 Bytes = 17481.64 KiB = 17.07 MiB
+       Load Address: 00000000
+       Entry Point:  00000000
+
+4. Copy bootmImage-bbl.bin and ae250.dtb to qemu sd card image
+5. Message of booting riscv-linux from bbl via u-boot on qemu
+
+U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
+
+DRAM:  1 GiB
+main-loop: WARNING: I/O thread spun for 1000 iterations
+MMC:   mmc@f0e00000: 0
+Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
+
+Failed (-22)
+In:    serial@f0300000
+Out:   serial@f0300000
+Err:   serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
+eth0: mac@e0100000
+RISC-V # mmc rescan
+RISC-V # mmc part
+
+Partition Map for MMC device 0  --   Partition Type: DOS
+
+Part    Start Sector    Num Sectors     UUID            Type
+RISC-V # fatls mmc 0:0
+ 17901268   bootmImage-bbl.bin
+     1954   ae2xx.dtb
+
+2 file(s), 0 dir(s)
+
+RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
+17901268 bytes read in 4642 ms (3.7 MiB/s)
+RISC-V # fatload mmc 0:0 0x2000000 ae250.dtb
+1954 bytes read in 1 ms (1.9 MiB/s)
+RISC-V # setenv bootm_size 0x2000000
+RISC-V # setenv fdt_high 0x1f00000
+RISC-V # bootm 0x00600000 - 0x2000000
+## Booting kernel from Legacy Image at 00600000 ...
+   Image Name:
+   Image Type:   RISC-V Linux Kernel Image (uncompressed)
+   Data Size:    17901204 Bytes = 17.1 MiB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+## Flattened Device Tree blob at 02000000
+   Booting using the fdt blob at 0x2000000
+   Loading Kernel Image ... OK
+   Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
+[    0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
+[    0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
+[    0.000000] bootconsole [early0] enabled
+[    0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
+[    0.000000] Zone ranges:
+[    0.000000]   DMA      [mem 0x0000000000200000-0x000000007fffffff]
+[    0.000000]   Normal   empty
+[    0.000000] Movable zone start for each node
+[    0.000000] Early memory node ranges
+[    0.000000]   node   0: [mem 0x0000000000200000-0x000000007fffffff]
+[    0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
+[    0.000000] elf_hwcap is 0x112d
+[    0.000000] random: fast init done
+[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 516615
+[    0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
+[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
+[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
+[    0.000000] Sorting __ex_table...
+[    0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
+[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+[    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+[    0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
+[    0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
+[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
+[    0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
+[    0.000000] pid_max: default: 32768 minimum: 301
+[    0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
+[    0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
+[    0.056000] devtmpfs: initialized
+[    0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+[    0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
+[    0.068000] NET: Registered protocol family 16
+[    0.080000] vgaarb: loaded
+[    0.084000] clocksource: Switched to clocksource riscv_clocksource
+[    0.088000] NET: Registered protocol family 2
+[    0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
+[    0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
+[    0.096000] TCP: Hash tables configured (established 16384 bind 16384)
+[    0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
+[    0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
+[    0.104000] NET: Registered protocol family 1
+[    0.616000] Unpacking initramfs...
+[    1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
+[    1.244000] io scheduler noop registered
+[    1.244000] io scheduler cfq registered (default)
+[    1.244000] io scheduler mq-deadline registered
+[    1.248000] io scheduler kyber registered
+[    1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[    1.368000] console [ttyS0] disabled
+[    1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
+[    1.392000] console [ttyS0] enabled
+[    1.392000] ftmac100: Loading version 0.2 ...
+[    1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
+[    1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
+[    1.404000] IR NEC protocol handler initialized
+[    1.404000] IR RC5(x/sz) protocol handler initialized
+[    1.404000] IR RC6 protocol handler initialized
+[    1.404000] IR JVC protocol handler initialized
+[    1.408000] IR Sony protocol handler initialized
+[    1.408000] IR SANYO protocol handler initialized
+[    1.408000] IR Sharp protocol handler initialized
+[    1.408000] IR MCE Keyboard/mouse protocol handler initialized
+[    1.412000] IR XMP protocol handler initialized
+[    1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
+[    1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
+[    1.464000] bootconsole [early0] disabled
+[    1.508000] Freeing unused kernel memory: 12076K
+[    1.512000] This architecture does not have kernel memory protection.
+[    1.520000] mmc0: new SD card at address 4567
+[    1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
+[    1.844000]  mmcblk0:
+Wed Dec  1 10:00:00 CST 2010
+/ #
+
+
+
+TODO
+==================================================
+Boot bbl and riscv-linux via U-Boot on AE250 board

diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
new file mode 100644 (file)
index 0000000..c29d90f
--- /dev/null
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -0,0 +1,226 @@
+STMicroelectronics STM32MP1 clock tree initialization
+=====================================================
+
+The STM32MP clock tree initialization is based on device tree information
+for RCC IP and on fixed clocks.
+
+-------------------------------
+RCC CLOCK = st,stm32mp1-rcc-clk
+-------------------------------
+
+The RCC IP is both a reset and a clock controller but this documentation only
+describes the fields added for clock tree initialization which are not present
+in Linux binding.
+
+Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
+with Linux.
+
+Required properties:
+
+- compatible: Should be "st,stm32mp1-rcc-clk"
+
+- st,clksrc : The clock source in this order
+
+       for STM32MP15x: 9 clock sources are requested
+               MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
+
+       with value equals to RCC clock specifier as defined in
+       dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
+
+- st,clkdiv : The div parameters in this order
+       for STM32MP15x: 11 dividers value are requested
+               MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
+
+       with DIV coding defined in RCC associated register RCC_xxxDIVR
+
+       most the case, it is:
+               0x0: not divided
+               0x1: division by 2
+               0x2: division by 4
+               0x3: division by 8
+               ...
+
+       but for RTC MCO1 MCO2, the coding is different:
+               0x0: not divided
+               0x1: division by 2
+               0x2: division by 3
+               0x3: division by 4
+               ...
+
+Optional Properties:
+- st,pll
+    PLL children node for PLL1 to PLL4 : (see ref manual for details)
+    with associated index 0 to 3 (st,pll@0 to st,pll@4)
+    PLLx is off when the associated node is absent
+
+    - Sub-nodes:
+
+       - cfg:  The parameters for PLL configuration in this order:
+               DIVM DIVN DIVP DIVQ DIVR Output
+
+               with DIV value as defined in RCC spec:
+                       0x0: bypass (division by 1)
+                       0x1: division by 2
+                       0x2: division by 3
+                       0x3: division by 4
+                       ...
+
+               and Output = bitfield for each output value = 1:ON/0:OFF
+                       BIT(0) => output P : DIVPEN
+                       BIT(1) => output Q : DIVQEN
+                       BIT(2) => output R : DIVREN
+                 NB : macro PQR(p,q,r) can be used to build this value
+                      with p,p,r = 0 or 1
+
+       - frac : Fractional part of the multiplication factor
+               (optional, PLL is in integer mode when absent)
+
+       - csg : Clock Spreading Generator (optional)
+               with parameters in this order:
+               MOD_PER INC_STEP SSCG_MODE
+
+               * MOD_PER: Modulation Period Adjustment
+               * INC_STEP: Modulation Depth Adjustment
+               * SSCG_MODE: Spread spectrum clock generator mode
+                 you can use associated defines from stm32mp1-clksrc.h
+                 * SSCG_MODE_CENTER_SPREAD = 0
+                 * SSCG_MODE_DOWN_SPREAD = 1
+
+
+- st,pkcs : used to configure the peripherals kernel clock selection
+  containing a list of peripheral kernel clock source identifier as defined
+  in the file dt-bindings/clock/stm32mp1-clksrc.h
+
+  Example:
+
+       rcc: rcc@50000000 {
+               compatible = "syscon", "simple-mfd";
+
+               reg = <0x50000000 0x1000>;
+
+               rcc_clk: rcc-clk@50000000 {
+                       #clock-cells = <1>;
+                       compatible = "st,stm32mp1-rcc-clk";
+
+                       st,clksrc = <   CLK_MPU_PLL1P
+                                       CLK_AXI_PLL2P
+                                       CLK_MCU_HSI
+                                       CLK_PLL12_HSE
+                                       CLK_PLL3_HSE
+                                       CLK_PLL4_HSE
+                                       CLK_RTC_HSE
+                                       CLK_MCO1_DISABLED
+                                       CLK_MCO2_DISABLED
+                       >;
+
+                       st,clkdiv = <
+                               1 /*MPU*/
+                               0 /*AXI*/
+                               0 /*MCU*/
+                               1 /*APB1*/
+                               1 /*APB2*/
+                               1 /*APB3*/
+                               1 /*APB4*/
+                               5 /*APB5*/
+                               23 /*RTC*/
+                               0 /*MCO1*/
+                               0 /*MCO2*/
+                       >;
+
+                       st,pll@0 {
+                               cfg = < 1 53 0 0 0 1 >;
+                               frac = < 0x810 >;
+                       };
+                       st,pll@1 {
+                               cfg = < 1 43 1 0 0 PQR(0,1,1)>;
+                               csg = <10 20 1>;
+                       };
+                       st,pll@2 {
+                               cfg = < 2 85 3 13 3 0>;
+                               csg = <10 20 SSCG_MODE_CENTER_SPREAD>;
+                       };
+                       st,pll@3 {
+                               cfg = < 2 78 4 7 9 3>;
+                       };
+                       st,pkcs = <
+                                       CLK_STGEN_HSE
+                                       CLK_CKPER_HSI
+                                       CLK_USBPHY_PLL2P
+                                       CLK_DSI_PLL2Q
+                                 >;
+               };
+       };
+
+--------------------------
+other clocks = fixed-clock
+--------------------------
+The clock tree is also based on 5 fixed-clock in clocks node
+used to define the state of associated ST32MP1 oscillators:
+- clk-lsi
+- clk-lse
+- clk-hsi
+- clk-hse
+- clk-csi
+
+At boot the clock tree initialization will
+- enable the oscillator present in device tree
+- disable HSI oscillator if the node is absent (always activated by bootrom)
+
+Optional properties :
+
+a) for external oscillator: "clk-lse", "clk-hse"
+
+       3 optional fields are managed
+       - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
+       - "st,css" Activate the clock security system (HSECSSON, LSECSSON)
+       - "st,drive" (only for LSE) value of the drive for the oscillator
+          (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
+
+       Example board file:
+
+       / {
+               clocks {
+                       clk_hse: clk-hse {
+                               #clock-cells = <0>;
+                               compatible = "fixed-clock";
+                               clock-frequency = <64000000>;
+                               st,bypass;
+                       };
+
+                       clk_lse: clk-lse {
+                               #clock-cells = <0>;
+                               compatible = "fixed-clock";
+                               clock-frequency = <32768>;
+                               st,css;
+                               st,drive = <LSEDRV_LOWEST>;
+                       };
+       };
+
+b) for internal oscillator: "clk-hsi"
+
+       internally HSI clock is fixed to 64MHz for STM32MP157 soc
+       in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
+       So this clock frequency is used to compute the expected HSI_DIV
+       for the clock tree initialisation
+
+       ex: for HSIDIV = /1
+
+       / {
+               clocks {
+                       clk_hsi: clk-hsi {
+                               #clock-cells = <0>;
+                               compatible = "fixed-clock";
+                               clock-frequency = <64000000>;
+                       };
+       };
+
+       ex: for HSIDIV = /2
+
+       / {
+               clocks {
+                       clk_hsi: clk-hsi {
+                               #clock-cells = <0>;
+                               compatible = "fixed-clock";
+                               clock-frequency = <32000000>;
+                       };
+       };

diff --git a/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
new file mode 100644 (file)
index 0000000..86ec113
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
@@ -0,0 +1,186 @@
+* Marvell Armada 37xx SoC pin and GPIO controller
+
+Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
+South Bridge and the other for the North Bridge.
+
+GPIO and pin controller:
+------------------------
+
+Main node:
+
+Refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning
+of the phrase "pin configuration node".
+
+Required properties for pinctrl driver:
+
+- compatible:  "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
+               for the South Bridge
+               "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
+               for the North Bridge
+- reg: The first set of registers is for pinctrl/GPIO and the second
+  set is for the interrupt controller
+- interrupts: list of interrupts used by the GPIO
+
+Available groups and functions for the North Bridge:
+
+group: jtag
+ - pins 20-24
+ - functions jtag, gpio
+
+group sdio0
+ - pins 8-10
+ - functions sdio, gpio
+
+group emmc_nb
+ - pins 27-35
+ - functions emmc, gpio
+
+group pwm0
+ - pin 11 (GPIO1-11)
+ - functions pwm, gpio
+
+group pwm1
+ - pin 12
+ - functions pwm, gpio
+
+group pwm2
+ - pin 13
+ - functions pwm, gpio
+
+group pwm3
+ - pin 14
+ - functions pwm, gpio
+
+group pmic1
+ - pin 7
+ - functions pmic, gpio
+
+group pmic0
+ - pin 6
+ - functions pmic, gpio
+
+group i2c2
+ - pins 2-3
+ - functions i2c, gpio
+
+group i2c1
+ - pins 0-1
+ - functions i2c, gpio
+
+group spi_cs1
+ - pin 17
+ - functions spi, gpio
+
+group spi_cs2
+ - pin 18
+ - functions spi, gpio
+
+group spi_cs3
+ - pin 19
+ - functions spi, gpio
+
+group onewire
+ - pin 4
+ - functions onewire, gpio
+
+group uart1
+ - pins 25-26
+ - functions uart, gpio
+
+group spi_quad
+ - pins 15-16
+ - functions spi, gpio
+
+group uart_2
+ - pins 9-10
+ - functions uart, gpio
+
+Available groups and functions for the South Bridge:
+
+group usb32_drvvbus0
+ - pin 36
+ - functions drvbus, gpio
+
+group usb2_drvvbus1
+ - pin 37
+ - functions drvbus, gpio
+
+group sdio_sb
+ - pins 60-65
+ - functions sdio, gpio
+
+group rgmii
+ - pins 42-53
+ - functions mii, gpio
+
+group pcie1
+ - pins 39-41
+ - functions pcie, gpio
+
+group smi
+ - pins 54-55
+ - functions smi, gpio
+
+group ptp
+ - pins 56-58
+ - functions ptp, gpio
+
+group ptp_clk
+ - pin 57
+ - functions ptp, mii
+
+group ptp_trig
+ - pin 58
+ - functions ptp, mii
+
+group mii_col
+ - pin 59
+ - functions mii, mii_err
+
+GPIO subnode:
+
+Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property
+and the common GPIO bindings used by client devices.
+
+Required properties for the GPIO driver under the gpio subnode:
+- interrupts: List of interrupt specifiers for the controllers interrupt.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be 2. The first cell is the GPIO number and the
+   second cell specifies GPIO flags, as defined in
+   <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
+   GPIO_ACTIVE_LOW flags are supported.
+- gpio-ranges: Range of pins managed by the GPIO controller.
+
+Example:
+pinctrl_sb: pinctrl-sb@18800 {
+       compatible = "marvell,armada3710-sb-pinctrl",
+       "syscon", "simple-mfd";
+       reg = <0x18800 0x100>, <0x18C00 0x20>;
+       gpiosb: gpiosb {
+               #gpio-cells = <2>;
+               gpio-ranges = <&pinctrl_sb 0 0 30>;
+               gpio-controller;
+               interrupts =
+               <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+               <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+               <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+               <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+               <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       rgmii_pins: mii-pins {
+               groups = "rgmii";
+               function = "mii";
+       };
+
+       sdio_pins: sdio-pins {
+               groups = "sdio_sb";
+               function = "sdio";
+       };
+
+       pcie_pins: pcie-pins {
+               groups = "pcie1";
+               function = "pcie";
+       };
+};
\ No newline at end of file

diff --git a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
new file mode 100644 (file)
index 0000000..3028636
--- /dev/null
+++ b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
@@ -0,0 +1,299 @@
+ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
+
+--------------------
+Required properties:
+--------------------
+- compatible   : Should be "st,stm32mp1-ddr"
+- reg          : controleur (DDRCTRL) and phy (DDRPHYC) base address
+- clocks       : controller clocks handle
+- clock-names  : associated controller clock names
+                 the "ddrphyc" clock is used to check the DDR frequency
+                 at phy level according the expected value in "mem-speed" field
+
+the next attributes are DDR parameters, they are generated by DDR tools
+included in STM32 Cube tool
+
+info attributes:
+----------------
+- st,mem-name  : name for DDR configuration, simple string for information
+- st,mem-speed : DDR expected speed for the setting in MHz
+- st,mem-size  : DDR mem size in byte
+
+
+controlleur attributes:
+-----------------------
+- st,ctl-reg   : controleur values depending of the DDR type
+                 (DDR3/LPDDR2/LPDDR3)
+       for STM32MP15x: 25 values are requested in this order
+               MSTR
+               MRCTRL0
+               MRCTRL1
+               DERATEEN
+               DERATEINT
+               PWRCTL
+               PWRTMG
+               HWLPCTL
+               RFSHCTL0
+               RFSHCTL3
+               CRCPARCTL0
+               ZQCTL0
+               DFITMG0
+               DFITMG1
+               DFILPCFG0
+               DFIUPD0
+               DFIUPD1
+               DFIUPD2
+               DFIPHYMSTR
+               ODTMAP
+               DBG0
+               DBG1
+               DBGCMD
+               POISONCFG
+               PCCFG
+
+- st,ctl-timing        : controleur values depending of frequency and timing parameter
+                 of DDR
+       for STM32MP15x: 12 values are requested in this order
+               RFSHTMG
+               DRAMTMG0
+               DRAMTMG1
+               DRAMTMG2
+               DRAMTMG3
+               DRAMTMG4
+               DRAMTMG5
+               DRAMTMG6
+               DRAMTMG7
+               DRAMTMG8
+               DRAMTMG14
+               ODTCFG
+
+- st,ctl-map   : controleur values depending of address mapping
+       for STM32MP15x: 9 values are requested in this order
+               ADDRMAP1
+               ADDRMAP2
+               ADDRMAP3
+               ADDRMAP4
+               ADDRMAP5
+               ADDRMAP6
+               ADDRMAP9
+               ADDRMAP10
+               ADDRMAP11
+
+- st,ctl-perf  : controleur values depending of performance and scheduling
+       for STM32MP15x: 17 values are requested in this order
+               SCHED
+               SCHED1
+               PERFHPR1
+               PERFLPR1
+               PERFWR1
+               PCFGR_0
+               PCFGW_0
+               PCFGQOS0_0
+               PCFGQOS1_0
+               PCFGWQOS0_0
+               PCFGWQOS1_0
+               PCFGR_1
+               PCFGW_1
+               PCFGQOS0_1
+               PCFGQOS1_1
+               PCFGWQOS0_1
+               PCFGWQOS1_1
+
+phyc attributes:
+----------------
+- st,phy-reg   : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
+       for STM32MP15x: 10 values are requested in this order
+               PGCR
+               ACIOCR
+               DXCCR
+               DSGCR
+               DCR
+               ODTCR
+               ZQ0CR1
+               DX0GCR
+               DX1GCR
+               DX2GCR
+               DX3GCR
+
+- st,phy-timing        : phy values depending of frequency and timing parameter of DDR
+       for STM32MP15x: 10 values are requested in this order
+               PTR0
+               PTR1
+               PTR2
+               DTPR0
+               DTPR1
+               DTPR2
+               MR0
+               MR1
+               MR2
+               MR3
+
+- st,phy-cal   : phy cal depending of calibration or tuning of DDR
+       for STM32MP15x: 12 values are requested in this order
+               DX0DLLCR
+               DX0DQTR
+               DX0DQSTR
+               DX1DLLCR
+               DX1DQTR
+               DX1DQSTR
+               DX2DLLCR
+               DX2DQTR
+               DX2DQSTR
+               DX3DLLCR
+               DX3DQTR
+               DX3DQSTR
+
+Example:
+
+/ {
+       soc {
+               u-boot,dm-spl;
+
+               ddr: ddr@0x5A003000{
+                       u-boot,dm-spl;
+                       u-boot,dm-pre-reloc;
+
+                       compatible = "st,stm32mp1-ddr";
+
+                       reg = <0x5A003000 0x550
+                              0x5A004000 0x234>;
+
+                       clocks = <&rcc_clk AXIDCG>,
+                                <&rcc_clk DDRC1>,
+                                <&rcc_clk DDRC2>,
+                                <&rcc_clk DDRPHYC>,
+                                <&rcc_clk DDRCAPB>,
+                                <&rcc_clk DDRPHYCAPB>;
+
+                       clock-names = "axidcg",
+                                     "ddrc1",
+                                     "ddrc2",
+                                     "ddrphyc",
+                                     "ddrcapb",
+                                     "ddrphycapb";
+
+                       st,mem-name = "DDR3 2x4Gb 533MHz";
+                       st,mem-speed = <533>;
+                       st,mem-size = <0x40000000>;
+
+                       st,ctl-reg = <
+                               0x00040401 /*MSTR*/
+                               0x00000010 /*MRCTRL0*/
+                               0x00000000 /*MRCTRL1*/
+                               0x00000000 /*DERATEEN*/
+                               0x00800000 /*DERATEINT*/
+                               0x00000000 /*PWRCTL*/
+                               0x00400010 /*PWRTMG*/
+                               0x00000000 /*HWLPCTL*/
+                               0x00210000 /*RFSHCTL0*/
+                               0x00000000 /*RFSHCTL3*/
+                               0x00000000 /*CRCPARCTL0*/
+                               0xC2000040 /*ZQCTL0*/
+                               0x02050105 /*DFITMG0*/
+                               0x00000202 /*DFITMG1*/
+                               0x07000000 /*DFILPCFG0*/
+                               0xC0400003 /*DFIUPD0*/
+                               0x00000000 /*DFIUPD1*/
+                               0x00000000 /*DFIUPD2*/
+                               0x00000000 /*DFIPHYMSTR*/
+                               0x00000001 /*ODTMAP*/
+                               0x00000000 /*DBG0*/
+                               0x00000000 /*DBG1*/
+                               0x00000000 /*DBGCMD*/
+                               0x00000000 /*POISONCFG*/
+                               0x00000010 /*PCCFG*/
+                       >;
+
+                       st,ctl-timing = <
+                               0x0080008A /*RFSHTMG*/
+                               0x121B2414 /*DRAMTMG0*/
+                               0x000D041B /*DRAMTMG1*/
+                               0x0607080E /*DRAMTMG2*/
+                               0x0050400C /*DRAMTMG3*/
+                               0x07040407 /*DRAMTMG4*/
+                               0x06060303 /*DRAMTMG5*/
+                               0x02020002 /*DRAMTMG6*/
+                               0x00000202 /*DRAMTMG7*/
+                               0x00001005 /*DRAMTMG8*/
+                               0x000D041B /*DRAMTMG1*/4
+                               0x06000600 /*ODTCFG*/
+                       >;
+
+                       st,ctl-map = <
+                               0x00080808 /*ADDRMAP1*/
+                               0x00000000 /*ADDRMAP2*/
+                               0x00000000 /*ADDRMAP3*/
+                               0x00001F1F /*ADDRMAP4*/
+                               0x07070707 /*ADDRMAP5*/
+                               0x0F070707 /*ADDRMAP6*/
+                               0x00000000 /*ADDRMAP9*/
+                               0x00000000 /*ADDRMAP10*/
+                               0x00000000 /*ADDRMAP11*/
+                       >;
+
+                       st,ctl-perf = <
+                               0x00001201 /*SCHED*/
+                               0x00001201 /*SCHED*/1
+                               0x01000001 /*PERFHPR1*/
+                               0x08000200 /*PERFLPR1*/
+                               0x08000400 /*PERFWR1*/
+                               0x00010000 /*PCFGR_0*/
+                               0x00000000 /*PCFGW_0*/
+                               0x02100B03 /*PCFGQOS0_0*/
+                               0x00800100 /*PCFGQOS1_0*/
+                               0x01100B03 /*PCFGWQOS0_0*/
+                               0x01000200 /*PCFGWQOS1_0*/
+                               0x00010000 /*PCFGR_1*/
+                               0x00000000 /*PCFGW_1*/
+                               0x02100B03 /*PCFGQOS0_1*/
+                               0x00800000 /*PCFGQOS1_1*/
+                               0x01100B03 /*PCFGWQOS0_1*/
+                               0x01000200 /*PCFGWQOS1_1*/
+                       >;
+
+                       st,phy-reg = <
+                               0x01442E02 /*PGCR*/
+                               0x10400812 /*ACIOCR*/
+                               0x00000C40 /*DXCCR*/
+                               0xF200001F /*DSGCR*/
+                               0x0000000B /*DCR*/
+                               0x00010000 /*ODTCR*/
+                               0x0000007B /*ZQ0CR1*/
+                               0x0000CE81 /*DX0GCR*/
+                               0x0000CE81 /*DX1GCR*/
+                               0x0000CE81 /*DX2GCR*/
+                               0x0000CE81 /*DX3GCR*/
+                       >;
+
+                       st,phy-timing = <
+                               0x0022A41B /*PTR0*/
+                               0x047C0740 /*PTR1*/
+                               0x042D9C80 /*PTR2*/
+                               0x369477D0 /*DTPR0*/
+                               0x098A00D8 /*DTPR1*/
+                               0x10023600 /*DTPR2*/
+                               0x00000830 /*MR0*/
+                               0x00000000 /*MR1*/
+                               0x00000208 /*MR2*/
+                               0x00000000 /*MR3*/
+                       >;
+
+                       st,phy-cal = <
+                               0x40000000 /*DX0DLLCR*/
+                               0xFFFFFFFF /*DX0DQTR*/
+                               0x3DB02000 /*DX0DQSTR*/
+                               0x40000000 /*DX1DLLCR*/
+                               0xFFFFFFFF /*DX1DQTR*/
+                               0x3DB02000 /*DX1DQSTR*/
+                               0x40000000 /*DX2DLLCR*/
+                               0xFFFFFFFF /*DX2DQTR*/
+                               0x3DB02000 /*DX2DQSTR*/
+                               0x40000000 /*DX3DLLCR*/
+                               0xFFFFFFFF /*DX3DQTR*/
+                               0x3DB02000 /*DX3DQSTR*/
+                       >;
+
+                       status = "okay";
+               };
+       };
+};

diff --git a/drivers/Makefile b/drivers/Makefile
index 2673428cb693ebc085e29b533642857a087f5e43..6846d181aa02631a16dfe8bbb12070ae9d79225a 100644 (file)
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
 obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_RESET_SUPPORT) += reset/
 obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
 obj-$(CONFIG_SPL_UBI) += mtd/ubispl/

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cdfa052c16a9717a97134ecd927b71a20a7ba177..c382e8865f71e256e5cf81aa5ecefcc2d248b00c 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -75,6 +75,14 @@ config CLK_ZYNQMP
          This clock driver adds support for clock realted settings for
          ZynqMP platform.
 
+config CLK_STM32MP1
+       bool "Enable RCC clock driver for STM32MP1"
+       depends on ARCH_STM32MP && CLK
+       default y
+       help
+         Enable the STM32 clock (RCC) driver. Enable support for
+         manipulating STM32MP1's on-SoC clocks.
+
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 source "drivers/clk/exynos/Kconfig"

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dab106ab7fcd3502c5bf46f51296e4607f9fd7ac..e05c607223396d200a7e7e01611e625fd354fe58 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_RENESAS) += renesas/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
 obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
new file mode 100644 (file)
index 0000000..55b0f79
--- /dev/null
+++ b/drivers/clk/clk_stm32mp1.c
@@ -0,0 +1,1733 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <regmap.h>
+#include <spl.h>
+#include <syscon.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+/* activate clock tree initialization in the driver */
+#define STM32MP1_CLOCK_TREE_INIT
+#endif
+
+#define MAX_HSI_HZ             64000000
+
+/* TIMEOUT */
+#define TIMEOUT_200MS          200000
+#define TIMEOUT_1S             1000000
+
+/* RCC registers */
+#define RCC_OCENSETR           0x0C
+#define RCC_OCENCLRR           0x10
+#define RCC_HSICFGR            0x18
+#define RCC_MPCKSELR           0x20
+#define RCC_ASSCKSELR          0x24
+#define RCC_RCK12SELR          0x28
+#define RCC_MPCKDIVR           0x2C
+#define RCC_AXIDIVR            0x30
+#define RCC_APB4DIVR           0x3C
+#define RCC_APB5DIVR           0x40
+#define RCC_RTCDIVR            0x44
+#define RCC_MSSCKSELR          0x48
+#define RCC_PLL1CR             0x80
+#define RCC_PLL1CFGR1          0x84
+#define RCC_PLL1CFGR2          0x88
+#define RCC_PLL1FRACR          0x8C
+#define RCC_PLL1CSGR           0x90
+#define RCC_PLL2CR             0x94
+#define RCC_PLL2CFGR1          0x98
+#define RCC_PLL2CFGR2          0x9C
+#define RCC_PLL2FRACR          0xA0
+#define RCC_PLL2CSGR           0xA4
+#define RCC_I2C46CKSELR                0xC0
+#define RCC_CPERCKSELR         0xD0
+#define RCC_STGENCKSELR                0xD4
+#define RCC_DDRITFCR           0xD8
+#define RCC_BDCR               0x140
+#define RCC_RDLSICR            0x144
+#define RCC_MP_APB4ENSETR      0x200
+#define RCC_MP_APB5ENSETR      0x208
+#define RCC_MP_AHB5ENSETR      0x210
+#define RCC_MP_AHB6ENSETR      0x218
+#define RCC_OCRDYR             0x808
+#define RCC_DBGCFGR            0x80C
+#define RCC_RCK3SELR           0x820
+#define RCC_RCK4SELR           0x824
+#define RCC_MCUDIVR            0x830
+#define RCC_APB1DIVR           0x834
+#define RCC_APB2DIVR           0x838
+#define RCC_APB3DIVR           0x83C
+#define RCC_PLL3CR             0x880
+#define RCC_PLL3CFGR1          0x884
+#define RCC_PLL3CFGR2          0x888
+#define RCC_PLL3FRACR          0x88C
+#define RCC_PLL3CSGR           0x890
+#define RCC_PLL4CR             0x894
+#define RCC_PLL4CFGR1          0x898
+#define RCC_PLL4CFGR2          0x89C
+#define RCC_PLL4FRACR          0x8A0
+#define RCC_PLL4CSGR           0x8A4
+#define RCC_I2C12CKSELR                0x8C0
+#define RCC_I2C35CKSELR                0x8C4
+#define RCC_UART6CKSELR                0x8E4
+#define RCC_UART24CKSELR       0x8E8
+#define RCC_UART35CKSELR       0x8EC
+#define RCC_UART78CKSELR       0x8F0
+#define RCC_SDMMC12CKSELR      0x8F4
+#define RCC_SDMMC3CKSELR       0x8F8
+#define RCC_ETHCKSELR          0x8FC
+#define RCC_QSPICKSELR         0x900
+#define RCC_FMCCKSELR          0x904
+#define RCC_USBCKSELR          0x91C
+#define RCC_MP_APB1ENSETR      0xA00
+#define RCC_MP_APB2ENSETR      0XA08
+#define RCC_MP_AHB2ENSETR      0xA18
+#define RCC_MP_AHB4ENSETR      0xA28
+
+/* used for most of SELR register */
+#define RCC_SELR_SRC_MASK      GENMASK(2, 0)
+#define RCC_SELR_SRCRDY                BIT(31)
+
+/* Values of RCC_MPCKSELR register */
+#define RCC_MPCKSELR_HSI       0
+#define RCC_MPCKSELR_HSE       1
+#define RCC_MPCKSELR_PLL       2
+#define RCC_MPCKSELR_PLL_MPUDIV        3
+
+/* Values of RCC_ASSCKSELR register */
+#define RCC_ASSCKSELR_HSI      0
+#define RCC_ASSCKSELR_HSE      1
+#define RCC_ASSCKSELR_PLL      2
+
+/* Values of RCC_MSSCKSELR register */
+#define RCC_MSSCKSELR_HSI      0
+#define RCC_MSSCKSELR_HSE      1
+#define RCC_MSSCKSELR_CSI      2
+#define RCC_MSSCKSELR_PLL      3
+
+/* Values of RCC_CPERCKSELR register */
+#define RCC_CPERCKSELR_HSI     0
+#define RCC_CPERCKSELR_CSI     1
+#define RCC_CPERCKSELR_HSE     2
+
+/* used for most of DIVR register : max div for RTC */
+#define RCC_DIVR_DIV_MASK      GENMASK(5, 0)
+#define RCC_DIVR_DIVRDY                BIT(31)
+
+/* Masks for specific DIVR registers */
+#define RCC_APBXDIV_MASK       GENMASK(2, 0)
+#define RCC_MPUDIV_MASK                GENMASK(2, 0)
+#define RCC_AXIDIV_MASK                GENMASK(2, 0)
+#define RCC_MCUDIV_MASK                GENMASK(3, 0)
+
+/*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET   4
+
+/* Fields of RCC_BDCR register */
+#define RCC_BDCR_LSEON         BIT(0)
+#define RCC_BDCR_LSEBYP                BIT(1)
+#define RCC_BDCR_LSERDY                BIT(2)
+#define RCC_BDCR_LSEDRV_MASK   GENMASK(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT  4
+#define RCC_BDCR_LSECSSON      BIT(8)
+#define RCC_BDCR_RTCCKEN       BIT(20)
+#define RCC_BDCR_RTCSRC_MASK   GENMASK(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT  16
+
+/* Fields of RCC_RDLSICR register */
+#define RCC_RDLSICR_LSION      BIT(0)
+#define RCC_RDLSICR_LSIRDY     BIT(1)
+
+/* used for ALL PLLNCR registers */
+#define RCC_PLLNCR_PLLON       BIT(0)
+#define RCC_PLLNCR_PLLRDY      BIT(1)
+#define RCC_PLLNCR_DIVPEN      BIT(4)
+#define RCC_PLLNCR_DIVQEN      BIT(5)
+#define RCC_PLLNCR_DIVREN      BIT(6)
+#define RCC_PLLNCR_DIVEN_SHIFT 4
+
+/* used for ALL PLLNCFGR1 registers */
+#define RCC_PLLNCFGR1_DIVM_SHIFT       16
+#define RCC_PLLNCFGR1_DIVM_MASK                GENMASK(21, 16)
+#define RCC_PLLNCFGR1_DIVN_SHIFT       0
+#define RCC_PLLNCFGR1_DIVN_MASK                GENMASK(8, 0)
+/* only for PLL3 and PLL4 */
+#define RCC_PLLNCFGR1_IFRGE_SHIFT      24
+#define RCC_PLLNCFGR1_IFRGE_MASK       GENMASK(25, 24)
+
+/* used for ALL PLLNCFGR2 registers */
+#define RCC_PLLNCFGR2_DIVX_MASK                GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVP_SHIFT       0
+#define RCC_PLLNCFGR2_DIVP_MASK                GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVQ_SHIFT       8
+#define RCC_PLLNCFGR2_DIVQ_MASK                GENMASK(14, 8)
+#define RCC_PLLNCFGR2_DIVR_SHIFT       16
+#define RCC_PLLNCFGR2_DIVR_MASK                GENMASK(22, 16)
+
+/* used for ALL PLLNFRACR registers */
+#define RCC_PLLNFRACR_FRACV_SHIFT      3
+#define RCC_PLLNFRACR_FRACV_MASK       GENMASK(15, 3)
+#define RCC_PLLNFRACR_FRACLE           BIT(16)
+
+/* used for ALL PLLNCSGR registers */
+#define RCC_PLLNCSGR_INC_STEP_SHIFT    16
+#define RCC_PLLNCSGR_INC_STEP_MASK     GENMASK(30, 16)
+#define RCC_PLLNCSGR_MOD_PER_SHIFT     0
+#define RCC_PLLNCSGR_MOD_PER_MASK      GENMASK(12, 0)
+#define RCC_PLLNCSGR_SSCG_MODE_SHIFT   15
+#define RCC_PLLNCSGR_SSCG_MODE_MASK    BIT(15)
+
+/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
+#define RCC_OCENR_HSION                        BIT(0)
+#define RCC_OCENR_CSION                        BIT(4)
+#define RCC_OCENR_HSEON                        BIT(8)
+#define RCC_OCENR_HSEBYP               BIT(10)
+#define RCC_OCENR_HSECSSON             BIT(11)
+
+/* Fields of RCC_OCRDYR register */
+#define RCC_OCRDYR_HSIRDY              BIT(0)
+#define RCC_OCRDYR_HSIDIVRDY           BIT(2)
+#define RCC_OCRDYR_CSIRDY              BIT(4)
+#define RCC_OCRDYR_HSERDY              BIT(8)
+
+/* Fields of DDRITFCR register */
+#define RCC_DDRITFCR_DDRCKMOD_MASK     GENMASK(22, 20)
+#define RCC_DDRITFCR_DDRCKMOD_SHIFT    20
+#define RCC_DDRITFCR_DDRCKMOD_SSR      0
+
+/* Fields of RCC_HSICFGR register */
+#define RCC_HSICFGR_HSIDIV_MASK                GENMASK(1, 0)
+
+/* used for MCO related operations */
+#define RCC_MCOCFG_MCOON               BIT(12)
+#define RCC_MCOCFG_MCODIV_MASK         GENMASK(7, 4)
+#define RCC_MCOCFG_MCODIV_SHIFT                4
+#define RCC_MCOCFG_MCOSRC_MASK         GENMASK(2, 0)
+
+enum stm32mp1_parent_id {
+/*
+ * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
+ * they are used as index in osc[] as entry point
+ */
+       _HSI,
+       _HSE,
+       _CSI,
+       _LSI,
+       _LSE,
+       _I2S_CKIN,
+       _USB_PHY_48,
+       NB_OSC,
+
+/* other parent source */
+       _HSI_KER = NB_OSC,
+       _HSE_KER,
+       _HSE_KER_DIV2,
+       _CSI_KER,
+       _PLL1_P,
+       _PLL1_Q,
+       _PLL1_R,
+       _PLL2_P,
+       _PLL2_Q,
+       _PLL2_R,
+       _PLL3_P,
+       _PLL3_Q,
+       _PLL3_R,
+       _PLL4_P,
+       _PLL4_Q,
+       _PLL4_R,
+       _ACLK,
+       _PCLK1,
+       _PCLK2,
+       _PCLK3,
+       _PCLK4,
+       _PCLK5,
+       _HCLK6,
+       _HCLK2,
+       _CK_PER,
+       _CK_MPU,
+       _CK_MCU,
+       _PARENT_NB,
+       _UNKNOWN_ID = 0xff,
+};
+
+enum stm32mp1_parent_sel {
+       _I2C12_SEL,
+       _I2C35_SEL,
+       _I2C46_SEL,
+       _UART6_SEL,
+       _UART24_SEL,
+       _UART35_SEL,
+       _UART78_SEL,
+       _SDMMC12_SEL,
+       _SDMMC3_SEL,
+       _ETH_SEL,
+       _QSPI_SEL,
+       _FMC_SEL,
+       _USBPHY_SEL,
+       _USBO_SEL,
+       _STGEN_SEL,
+       _PARENT_SEL_NB,
+       _UNKNOWN_SEL = 0xff,
+};
+
+enum stm32mp1_pll_id {
+       _PLL1,
+       _PLL2,
+       _PLL3,
+       _PLL4,
+       _PLL_NB
+};
+
+enum stm32mp1_div_id {
+       _DIV_P,
+       _DIV_Q,
+       _DIV_R,
+       _DIV_NB,
+};
+
+enum stm32mp1_clksrc_id {
+       CLKSRC_MPU,
+       CLKSRC_AXI,
+       CLKSRC_MCU,
+       CLKSRC_PLL12,
+       CLKSRC_PLL3,
+       CLKSRC_PLL4,
+       CLKSRC_RTC,
+       CLKSRC_MCO1,
+       CLKSRC_MCO2,
+       CLKSRC_NB
+};
+
+enum stm32mp1_clkdiv_id {
+       CLKDIV_MPU,
+       CLKDIV_AXI,
+       CLKDIV_MCU,
+       CLKDIV_APB1,
+       CLKDIV_APB2,
+       CLKDIV_APB3,
+       CLKDIV_APB4,
+       CLKDIV_APB5,
+       CLKDIV_RTC,
+       CLKDIV_MCO1,
+       CLKDIV_MCO2,
+       CLKDIV_NB
+};
+
+enum stm32mp1_pllcfg {
+       PLLCFG_M,
+       PLLCFG_N,
+       PLLCFG_P,
+       PLLCFG_Q,
+       PLLCFG_R,
+       PLLCFG_O,
+       PLLCFG_NB
+};
+
+enum stm32mp1_pllcsg {
+       PLLCSG_MOD_PER,
+       PLLCSG_INC_STEP,
+       PLLCSG_SSCG_MODE,
+       PLLCSG_NB
+};
+
+enum stm32mp1_plltype {
+       PLL_800,
+       PLL_1600,
+       PLL_TYPE_NB
+};
+
+struct stm32mp1_pll {
+       u8 refclk_min;
+       u8 refclk_max;
+       u8 divn_max;
+};
+
+struct stm32mp1_clk_gate {
+       u16 offset;
+       u8 bit;
+       u8 index;
+       u8 set_clr;
+       u8 sel;
+       u8 fixed;
+};
+
+struct stm32mp1_clk_sel {
+       u16 offset;
+       u8 src;
+       u8 msk;
+       u8 nb_parent;
+       const u8 *parent;
+};
+
+#define REFCLK_SIZE 4
+struct stm32mp1_clk_pll {
+       enum stm32mp1_plltype plltype;
+       u16 rckxselr;
+       u16 pllxcfgr1;
+       u16 pllxcfgr2;
+       u16 pllxfracr;
+       u16 pllxcr;
+       u16 pllxcsgr;
+       u8 refclk[REFCLK_SIZE];
+};
+
+struct stm32mp1_clk_data {
+       const struct stm32mp1_clk_gate *gate;
+       const struct stm32mp1_clk_sel *sel;
+       const struct stm32mp1_clk_pll *pll;
+       const int nb_gate;
+};
+
+struct stm32mp1_clk_priv {
+       fdt_addr_t base;
+       const struct stm32mp1_clk_data *data;
+       ulong osc[NB_OSC];
+       struct udevice *osc_dev[NB_OSC];
+};
+
+#define STM32MP1_CLK(off, b, idx, s)           \
+       {                                       \
+               .offset = (off),                \
+               .bit = (b),                     \
+               .index = (idx),                 \
+               .set_clr = 0,                   \
+               .sel = (s),                     \
+               .fixed = _UNKNOWN_ID,           \
+       }
+
+#define STM32MP1_CLK_F(off, b, idx, f)         \
+       {                                       \
+               .offset = (off),                \
+               .bit = (b),                     \
+               .index = (idx),                 \
+               .set_clr = 0,                   \
+               .sel = _UNKNOWN_SEL,            \
+               .fixed = (f),                   \
+       }
+
+#define STM32MP1_CLK_SET_CLR(off, b, idx, s)   \
+       {                                       \
+               .offset = (off),                \
+               .bit = (b),                     \
+               .index = (idx),                 \
+               .set_clr = 1,                   \
+               .sel = (s),                     \
+               .fixed = _UNKNOWN_ID,           \
+       }
+
+#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
+       {                                       \
+               .offset = (off),                \
+               .bit = (b),                     \
+               .index = (idx),                 \
+               .set_clr = 1,                   \
+               .sel = _UNKNOWN_SEL,            \
+               .fixed = (f),                   \
+       }
+
+#define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
+       [(idx)] = {                             \
+               .offset = (off),                \
+               .src = (s),                     \
+               .msk = (m),                     \
+               .parent = (p),                  \
+               .nb_parent = ARRAY_SIZE((p))    \
+       }
+
+#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
+                       p1, p2, p3, p4) \
+       [(idx)] = {                             \
+               .plltype = (type),                      \
+               .rckxselr = (off1),             \
+               .pllxcfgr1 = (off2),            \
+               .pllxcfgr2 = (off3),            \
+               .pllxfracr = (off4),            \
+               .pllxcr = (off5),               \
+               .pllxcsgr = (off6),             \
+               .refclk[0] = (p1),              \
+               .refclk[1] = (p2),              \
+               .refclk[2] = (p3),              \
+               .refclk[3] = (p4),              \
+       }
+
+static const u8 stm32mp1_clks[][2] = {
+       {CK_PER, _CK_PER},
+       {CK_MPU, _CK_MPU},
+       {CK_AXI, _ACLK},
+       {CK_MCU, _CK_MCU},
+       {CK_HSE, _HSE},
+       {CK_CSI, _CSI},
+       {CK_LSI, _LSI},
+       {CK_LSE, _LSE},
+       {CK_HSI, _HSI},
+       {CK_HSE_DIV2, _HSE_KER_DIV2},
+};
+
+static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
+       STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
+       STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
+       STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
+       STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
+       STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
+
+       STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
+};
+
+static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
+static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
+static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
+static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
+                                       _HSE_KER};
+static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+                                        _HSE_KER};
+static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+                                        _HSE_KER};
+static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+                                        _HSE_KER};
+static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
+static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
+static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
+static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
+static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
+static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
+static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
+static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
+
+static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
+       STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
+       STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
+       STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
+       STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
+       STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
+                           uart24_parents),
+       STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
+                           uart35_parents),
+       STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
+                           uart78_parents),
+       STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
+                           sdmmc12_parents),
+       STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
+                           sdmmc3_parents),
+       STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
+       STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
+       STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
+       STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
+       STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
+       STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+};
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+/* define characteristic of PLL according type */
+#define DIVN_MIN       24
+static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
+       [PLL_800] = {
+               .refclk_min = 4,
+               .refclk_max = 16,
+               .divn_max = 99,
+               },
+       [PLL_1600] = {
+               .refclk_min = 8,
+               .refclk_max = 16,
+               .divn_max = 199,
+               },
+};
+#endif /* STM32MP1_CLOCK_TREE_INIT */
+
+static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
+       STM32MP1_CLK_PLL(_PLL1, PLL_1600,
+                        RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
+                        RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
+                        _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
+       STM32MP1_CLK_PLL(_PLL2, PLL_1600,
+                        RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
+                        RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
+                        _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
+       STM32MP1_CLK_PLL(_PLL3, PLL_800,
+                        RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
+                        RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
+                        _HSI, _HSE, _CSI, _UNKNOWN_ID),
+       STM32MP1_CLK_PLL(_PLL4, PLL_800,
+                        RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
+                        RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
+                        _HSI, _HSE, _CSI, _I2S_CKIN),
+};
+
+/* Prescaler table lookups for clock computation */
+/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
+static const u8 stm32mp1_mcu_div[16] = {
+       0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
+};
+
+/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
+#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
+#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
+static const u8 stm32mp1_mpu_apbx_div[8] = {
+       0, 1, 2, 3, 4, 4, 4, 4
+};
+
+/* div = /1 /2 /3 /4 */
+static const u8 stm32mp1_axi_div[8] = {
+       1, 2, 3, 4, 4, 4, 4, 4
+};
+
+#ifdef DEBUG
+static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
+       [_HSI] = "HSI",
+       [_HSE] = "HSE",
+       [_CSI] = "CSI",
+       [_LSI] = "LSI",
+       [_LSE] = "LSE",
+       [_I2S_CKIN] = "I2S_CKIN",
+       [_HSI_KER] = "HSI_KER",
+       [_HSE_KER] = "HSE_KER",
+       [_HSE_KER_DIV2] = "HSE_KER_DIV2",
+       [_CSI_KER] = "CSI_KER",
+       [_PLL1_P] = "PLL1_P",
+       [_PLL1_Q] = "PLL1_Q",
+       [_PLL1_R] = "PLL1_R",
+       [_PLL2_P] = "PLL2_P",
+       [_PLL2_Q] = "PLL2_Q",
+       [_PLL2_R] = "PLL2_R",
+       [_PLL3_P] = "PLL3_P",
+       [_PLL3_Q] = "PLL3_Q",
+       [_PLL3_R] = "PLL3_R",
+       [_PLL4_P] = "PLL4_P",
+       [_PLL4_Q] = "PLL4_Q",
+       [_PLL4_R] = "PLL4_R",
+       [_ACLK] = "ACLK",
+       [_PCLK1] = "PCLK1",
+       [_PCLK2] = "PCLK2",
+       [_PCLK3] = "PCLK3",
+       [_PCLK4] = "PCLK4",
+       [_PCLK5] = "PCLK5",
+       [_HCLK6] = "KCLK6",
+       [_HCLK2] = "HCLK2",
+       [_CK_PER] = "CK_PER",
+       [_CK_MPU] = "CK_MPU",
+       [_CK_MCU] = "CK_MCU",
+       [_USB_PHY_48] = "USB_PHY_48"
+};
+
+static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
+       [_I2C12_SEL] = "I2C12",
+       [_I2C35_SEL] = "I2C35",
+       [_I2C46_SEL] = "I2C46",
+       [_UART6_SEL] = "UART6",
+       [_UART24_SEL] = "UART24",
+       [_UART35_SEL] = "UART35",
+       [_UART78_SEL] = "UART78",
+       [_SDMMC12_SEL] = "SDMMC12",
+       [_SDMMC3_SEL] = "SDMMC3",
+       [_ETH_SEL] = "ETH",
+       [_QSPI_SEL] = "QSPI",
+       [_FMC_SEL] = "FMC",
+       [_USBPHY_SEL] = "USBPHY",
+       [_USBO_SEL] = "USBO",
+       [_STGEN_SEL] = "STGEN"
+};
+#endif
+
+static const struct stm32mp1_clk_data stm32mp1_data = {
+       .gate = stm32mp1_clk_gate,
+       .sel = stm32mp1_clk_sel,
+       .pll = stm32mp1_clk_pll,
+       .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
+};
+
+static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
+{
+       if (idx >= NB_OSC) {
+               debug("%s: clk id %d not found\n", __func__, idx);
+               return 0;
+       }
+
+       debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
+             (u32)priv->osc[idx], priv->osc[idx] / 1000);
+
+       return priv->osc[idx];
+}
+
+static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
+{
+       const struct stm32mp1_clk_gate *gate = priv->data->gate;
+       int i, nb_clks = priv->data->nb_gate;
+
+       for (i = 0; i < nb_clks; i++) {
+               if (gate[i].index == id)
+                       break;
+       }
+
+       if (i == nb_clks) {
+               printf("%s: clk id %d not found\n", __func__, (u32)id);
+               return -EINVAL;
+       }
+
+       return i;
+}
+
+static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
+                               int i)
+{
+       const struct stm32mp1_clk_gate *gate = priv->data->gate;
+
+       if (gate[i].sel > _PARENT_SEL_NB) {
+               printf("%s: parents for clk id %d not found\n",
+                      __func__, i);
+               return -EINVAL;
+       }
+
+       return gate[i].sel;
+}
+
+static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
+                                        int i)
+{
+       const struct stm32mp1_clk_gate *gate = priv->data->gate;
+
+       if (gate[i].fixed == _UNKNOWN_ID)
+               return -ENOENT;
+
+       return gate[i].fixed;
+}
+
+static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
+                                  unsigned long id)
+{
+       const struct stm32mp1_clk_sel *sel = priv->data->sel;
+       int i;
+       int s, p;
+
+       for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
+               if (stm32mp1_clks[i][0] == id)
+                       return stm32mp1_clks[i][1];
+
+       i = stm32mp1_clk_get_id(priv, id);
+       if (i < 0)
+               return i;
+
+       p = stm32mp1_clk_get_fixed_parent(priv, i);
+       if (p >= 0 && p < _PARENT_NB)
+               return p;
+
+       s = stm32mp1_clk_get_sel(priv, i);
+       if (s < 0)
+               return s;
+
+       p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
+
+       if (p < sel[s].nb_parent) {
+#ifdef DEBUG
+               debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
+                     stm32mp1_clk_parent_name[sel[s].parent[p]],
+                     stm32mp1_clk_parent_sel_name[s],
+                     (u32)id);
+#endif
+               return sel[s].parent[p];
+       }
+
+       pr_err("%s: no parents defined for clk id %d\n",
+              __func__, (u32)id);
+
+       return -EINVAL;
+}
+
+static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
+                                   int pll_id, int div_id)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+       int divm, divn, divy, src;
+       ulong refclk, dfout;
+       u32 selr, cfgr1, cfgr2, fracr;
+       const u8 shift[_DIV_NB] = {
+               [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
+               [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
+               [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
+
+       debug("%s(%d, %d)\n", __func__, pll_id, div_id);
+       if (div_id > _DIV_NB)
+               return 0;
+
+       selr = readl(priv->base + pll[pll_id].rckxselr);
+       cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
+       cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
+       fracr = readl(priv->base + pll[pll_id].pllxfracr);
+
+       debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
+             pll_id, selr, cfgr1, cfgr2, fracr);
+
+       divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
+       divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
+       divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
+
+       debug("        DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
+
+       src = selr & RCC_SELR_SRC_MASK;
+       refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+
+       debug("        refclk = %d kHz\n", (u32)(refclk / 1000));
+
+       /*
+        * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
+        * So same final result than PLL2 et 4
+        * with FRACV :
+        *   Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
+        *               / (DIVM + 1) * (DIVy + 1)
+        * without FRACV
+        *   Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
+        */
+       if (fracr & RCC_PLLNFRACR_FRACLE) {
+               u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
+                           >> RCC_PLLNFRACR_FRACV_SHIFT;
+               dfout = (ulong)lldiv((unsigned long long)refclk *
+                                    (((divn + 1) << 13) + fracv),
+                                    ((unsigned long long)(divm + 1) *
+                                     (divy + 1)) << 13);
+       } else {
+               dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
+       }
+       debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
+
+       return dfout;
+}
+
+static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
+{
+       u32 reg;
+       ulong clock = 0;
+
+       switch (p) {
+       case _CK_MPU:
+       /* MPU sub system */
+               reg = readl(priv->base + RCC_MPCKSELR);
+               switch (reg & RCC_SELR_SRC_MASK) {
+               case RCC_MPCKSELR_HSI:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSI);
+                       break;
+               case RCC_MPCKSELR_HSE:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSE);
+                       break;
+               case RCC_MPCKSELR_PLL:
+               case RCC_MPCKSELR_PLL_MPUDIV:
+                       clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
+                       if (p == RCC_MPCKSELR_PLL_MPUDIV) {
+                               reg = readl(priv->base + RCC_MPCKDIVR);
+                               clock /= stm32mp1_mpu_div[reg &
+                                                         RCC_MPUDIV_MASK];
+                       }
+                       break;
+               }
+               break;
+       /* AXI sub system */
+       case _ACLK:
+       case _HCLK2:
+       case _HCLK6:
+       case _PCLK4:
+       case _PCLK5:
+               reg = readl(priv->base + RCC_ASSCKSELR);
+               switch (reg & RCC_SELR_SRC_MASK) {
+               case RCC_ASSCKSELR_HSI:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSI);
+                       break;
+               case RCC_ASSCKSELR_HSE:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSE);
+                       break;
+               case RCC_ASSCKSELR_PLL:
+                       clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
+                       break;
+               }
+
+               /* System clock divider */
+               reg = readl(priv->base + RCC_AXIDIVR);
+               clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
+
+               switch (p) {
+               case _PCLK4:
+                       reg = readl(priv->base + RCC_APB4DIVR);
+                       clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+                       break;
+               case _PCLK5:
+                       reg = readl(priv->base + RCC_APB5DIVR);
+                       clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+                       break;
+               default:
+                       break;
+               }
+               break;
+       /* MCU sub system */
+       case _CK_MCU:
+       case _PCLK1:
+       case _PCLK2:
+       case _PCLK3:
+               reg = readl(priv->base + RCC_MSSCKSELR);
+               switch (reg & RCC_SELR_SRC_MASK) {
+               case RCC_MSSCKSELR_HSI:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSI);
+                       break;
+               case RCC_MSSCKSELR_HSE:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSE);
+                       break;
+               case RCC_MSSCKSELR_CSI:
+                       clock = stm32mp1_clk_get_fixed(priv, _CSI);
+                       break;
+               case RCC_MSSCKSELR_PLL:
+                       clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
+                       break;
+               }
+
+               /* MCU clock divider */
+               reg = readl(priv->base + RCC_MCUDIVR);
+               clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
+
+               switch (p) {
+               case _PCLK1:
+                       reg = readl(priv->base + RCC_APB1DIVR);
+                       clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+                       break;
+               case _PCLK2:
+                       reg = readl(priv->base + RCC_APB2DIVR);
+                       clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+                       break;
+               case _PCLK3:
+                       reg = readl(priv->base + RCC_APB3DIVR);
+                       clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+                       break;
+               case _CK_MCU:
+               default:
+                       break;
+               }
+               break;
+       case _CK_PER:
+               reg = readl(priv->base + RCC_CPERCKSELR);
+               switch (reg & RCC_SELR_SRC_MASK) {
+               case RCC_CPERCKSELR_HSI:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSI);
+                       break;
+               case RCC_CPERCKSELR_HSE:
+                       clock = stm32mp1_clk_get_fixed(priv, _HSE);
+                       break;
+               case RCC_CPERCKSELR_CSI:
+                       clock = stm32mp1_clk_get_fixed(priv, _CSI);
+                       break;
+               }
+               break;
+       case _HSI:
+       case _HSI_KER:
+               clock = stm32mp1_clk_get_fixed(priv, _HSI);
+               break;
+       case _CSI:
+       case _CSI_KER:
+               clock = stm32mp1_clk_get_fixed(priv, _CSI);
+               break;
+       case _HSE:
+       case _HSE_KER:
+       case _HSE_KER_DIV2:
+               clock = stm32mp1_clk_get_fixed(priv, _HSE);
+               if (p == _HSE_KER_DIV2)
+                       clock >>= 1;
+               break;
+       case _LSI:
+               clock = stm32mp1_clk_get_fixed(priv, _LSI);
+               break;
+       case _LSE:
+               clock = stm32mp1_clk_get_fixed(priv, _LSE);
+               break;
+       /* PLL */
+       case _PLL1_P:
+       case _PLL1_Q:
+       case _PLL1_R:
+               clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
+               break;
+       case _PLL2_P:
+       case _PLL2_Q:
+       case _PLL2_R:
+               clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
+               break;
+       case _PLL3_P:
+       case _PLL3_Q:
+       case _PLL3_R:
+               clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
+               break;
+       case _PLL4_P:
+       case _PLL4_Q:
+       case _PLL4_R:
+               clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
+               break;
+       /* other */
+       case _USB_PHY_48:
+               clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
+               break;
+
+       default:
+               break;
+       }
+
+       debug("%s(%d) clock = %lx : %ld kHz\n",
+             __func__, p, clock, clock / 1000);
+
+       return clock;
+}
+
+static int stm32mp1_clk_enable(struct clk *clk)
+{
+       struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+       const struct stm32mp1_clk_gate *gate = priv->data->gate;
+       int i = stm32mp1_clk_get_id(priv, clk->id);
+
+       if (i < 0)
+               return i;
+
+       if (gate[i].set_clr)
+               writel(BIT(gate[i].bit), priv->base + gate[i].offset);
+       else
+               setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
+
+       debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
+
+       return 0;
+}
+
+static int stm32mp1_clk_disable(struct clk *clk)
+{
+       struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+       const struct stm32mp1_clk_gate *gate = priv->data->gate;
+       int i = stm32mp1_clk_get_id(priv, clk->id);
+
+       if (i < 0)
+               return i;
+
+       if (gate[i].set_clr)
+               writel(BIT(gate[i].bit),
+                      priv->base + gate[i].offset
+                      + RCC_MP_ENCLRR_OFFSET);
+       else
+               clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
+
+       debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
+
+       return 0;
+}
+
+static ulong stm32mp1_clk_get_rate(struct clk *clk)
+{
+       struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+       int p = stm32mp1_clk_get_parent(priv, clk->id);
+       ulong rate;
+
+       if (p < 0)
+               return 0;
+
+       rate = stm32mp1_clk_get(priv, p);
+
+#ifdef DEBUG
+       debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
+             __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
+#endif
+       return rate;
+}
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
+                               u32 mask_on)
+{
+       u32 address = rcc + offset;
+
+       if (enable)
+               setbits_le32(address, mask_on);
+       else
+               clrbits_le32(address, mask_on);
+}
+
+static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
+{
+       if (enable)
+               setbits_le32(rcc + RCC_OCENSETR, mask_on);
+       else
+               setbits_le32(rcc + RCC_OCENCLRR, mask_on);
+}
+
+static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
+                            u32 mask_rdy)
+{
+       u32 mask_test = 0;
+       u32 address = rcc + offset;
+       u32 val;
+       int ret;
+
+       if (enable)
+               mask_test = mask_rdy;
+
+       ret = readl_poll_timeout(address, val,
+                                (val & mask_rdy) == mask_test,
+                                TIMEOUT_1S);
+
+       if (ret)
+               pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
+                      mask_rdy, address, enable, readl(address));
+
+       return ret;
+}
+
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+{
+       u32 value;
+
+       if (bypass)
+               setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
+
+       /*
+        * warning: not recommended to switch directly from "high drive"
+        * to "medium low drive", and vice-versa.
+        */
+       value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
+               >> RCC_BDCR_LSEDRV_SHIFT;
+
+       while (value != lsedrv) {
+               if (value > lsedrv)
+                       value--;
+               else
+                       value++;
+
+               clrsetbits_le32(rcc + RCC_BDCR,
+                               RCC_BDCR_LSEDRV_MASK,
+                               value << RCC_BDCR_LSEDRV_SHIFT);
+       }
+
+       stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
+}
+
+static void stm32mp1_lse_wait(fdt_addr_t rcc)
+{
+       stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
+}
+
+static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
+{
+       stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
+       stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
+}
+
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+{
+       if (bypass)
+               setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
+
+       stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
+       stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
+
+       if (css)
+               setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
+}
+
+static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
+{
+       stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
+       stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
+}
+
+static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
+{
+       stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
+       stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
+}
+
+static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
+{
+       u32 address = rcc + RCC_OCRDYR;
+       u32 val;
+       int ret;
+
+       clrsetbits_le32(rcc + RCC_HSICFGR,
+                       RCC_HSICFGR_HSIDIV_MASK,
+                       RCC_HSICFGR_HSIDIV_MASK & hsidiv);
+
+       ret = readl_poll_timeout(address, val,
+                                val & RCC_OCRDYR_HSIDIVRDY,
+                                TIMEOUT_200MS);
+       if (ret)
+               pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
+                      address, readl(address));
+
+       return ret;
+}
+
+static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
+{
+       u8 hsidiv;
+       u32 hsidivfreq = MAX_HSI_HZ;
+
+       for (hsidiv = 0; hsidiv < 4; hsidiv++,
+            hsidivfreq = hsidivfreq / 2)
+               if (hsidivfreq == hsifreq)
+                       break;
+
+       if (hsidiv == 4) {
+               pr_err("clk-hsi frequency invalid");
+               return -1;
+       }
+
+       if (hsidiv > 0)
+               return stm32mp1_set_hsidiv(rcc, hsidiv);
+
+       return 0;
+}
+
+static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+
+       writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
+}
+
+static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+       u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+       u32 val;
+       int ret;
+
+       ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
+                                TIMEOUT_200MS);
+
+       if (ret) {
+               pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
+                      pll_id, pllxcr, readl(pllxcr));
+               return ret;
+       }
+
+       /* start the requested output */
+       setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
+
+       return 0;
+}
+
+static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+       u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+       u32 val;
+
+       /* stop all output */
+       clrbits_le32(pllxcr,
+                    RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
+
+       /* stop PLL */
+       clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
+
+       /* wait PLL stopped */
+       return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
+                                 TIMEOUT_200MS);
+}
+
+static void pll_config_output(struct stm32mp1_clk_priv *priv,
+                             int pll_id, u32 *pllcfg)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+       fdt_addr_t rcc = priv->base;
+       u32 value;
+
+       value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
+               & RCC_PLLNCFGR2_DIVP_MASK;
+       value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
+                & RCC_PLLNCFGR2_DIVQ_MASK;
+       value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
+                & RCC_PLLNCFGR2_DIVR_MASK;
+       writel(value, rcc + pll[pll_id].pllxcfgr2);
+}
+
+static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
+                     u32 *pllcfg, u32 fracv)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+       fdt_addr_t rcc = priv->base;
+       enum stm32mp1_plltype type = pll[pll_id].plltype;
+       int src;
+       ulong refclk;
+       u8 ifrge = 0;
+       u32 value;
+
+       src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
+
+       refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
+                (pllcfg[PLLCFG_M] + 1);
+
+       if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
+           refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
+               debug("invalid refclk = %x\n", (u32)refclk);
+               return -EINVAL;
+       }
+       if (type == PLL_800 && refclk >= 8000000)
+               ifrge = 1;
+
+       value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
+                & RCC_PLLNCFGR1_DIVN_MASK;
+       value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
+                & RCC_PLLNCFGR1_DIVM_MASK;
+       value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
+                & RCC_PLLNCFGR1_IFRGE_MASK;
+       writel(value, rcc + pll[pll_id].pllxcfgr1);
+
+       /* fractional configuration: load sigma-delta modulator (SDM) */
+
+       /* Write into FRACV the new fractional value , and FRACLE to 0 */
+       writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
+              rcc + pll[pll_id].pllxfracr);
+
+       /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
+       setbits_le32(rcc + pll[pll_id].pllxfracr,
+                    RCC_PLLNFRACR_FRACLE);
+
+       pll_config_output(priv, pll_id, pllcfg);
+
+       return 0;
+}
+
+static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
+{
+       const struct stm32mp1_clk_pll *pll = priv->data->pll;
+       u32 pllxcsg;
+
+       pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
+                   RCC_PLLNCSGR_MOD_PER_MASK) |
+                 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
+                   RCC_PLLNCSGR_INC_STEP_MASK) |
+                 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
+                   RCC_PLLNCSGR_SSCG_MODE_MASK);
+
+       writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
+}
+
+static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
+{
+       u32 address = priv->base + (clksrc >> 4);
+       u32 val;
+       int ret;
+
+       clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
+       ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
+                                TIMEOUT_200MS);
+       if (ret)
+               pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
+                      clksrc, address, readl(address));
+
+       return ret;
+}
+
+static int set_clkdiv(unsigned int clkdiv, u32 address)
+{
+       u32 val;
+       int ret;
+
+       clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
+       ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
+                                TIMEOUT_200MS);
+       if (ret)
+               pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
+                      clkdiv, address, readl(address));
+
+       return ret;
+}
+
+static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
+                            u32 clksrc, u32 clkdiv)
+{
+       u32 address = priv->base + (clksrc >> 4);
+
+       /*
+        * binding clksrc : bit15-4 offset
+        *                  bit3:   disable
+        *                  bit2-0: MCOSEL[2:0]
+        */
+       if (clksrc & 0x8) {
+               clrbits_le32(address, RCC_MCOCFG_MCOON);
+       } else {
+               clrsetbits_le32(address,
+                               RCC_MCOCFG_MCOSRC_MASK,
+                               clksrc & RCC_MCOCFG_MCOSRC_MASK);
+               clrsetbits_le32(address,
+                               RCC_MCOCFG_MCODIV_MASK,
+                               clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
+               setbits_le32(address, RCC_MCOCFG_MCOON);
+       }
+}
+
+static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
+                      unsigned int clksrc,
+                      int lse_css)
+{
+       u32 address = priv->base + RCC_BDCR;
+
+       if (readl(address) & RCC_BDCR_RTCCKEN)
+               goto skip_rtc;
+
+       if (clksrc == CLK_RTC_DISABLED)
+               goto skip_rtc;
+
+       clrsetbits_le32(address,
+                       RCC_BDCR_RTCSRC_MASK,
+                       clksrc << RCC_BDCR_RTCSRC_SHIFT);
+
+       setbits_le32(address, RCC_BDCR_RTCCKEN);
+
+skip_rtc:
+       if (lse_css)
+               setbits_le32(address, RCC_BDCR_LSECSSON);
+}
+
+static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
+{
+       u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
+       u32 value = pkcs & 0xF;
+       u32 mask = 0xF;
+
+       if (pkcs & BIT(31)) {
+               mask <<= 4;
+               value <<= 4;
+       }
+       clrsetbits_le32(address, mask, value);
+}
+
+static int stm32mp1_clktree(struct udevice *dev)
+{
+       struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+       fdt_addr_t rcc = priv->base;
+       unsigned int clksrc[CLKSRC_NB];
+       unsigned int clkdiv[CLKDIV_NB];
+       unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
+       ofnode plloff[_PLL_NB];
+       int ret;
+       int i, len;
+       int lse_css = 0;
+       const u32 *pkcs_cell;
+
+       /* check mandatory field */
+       ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
+       if (ret < 0) {
+               debug("field st,clksrc invalid: error %d\n", ret);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
+       if (ret < 0) {
+               debug("field st,clkdiv invalid: error %d\n", ret);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       /* check mandatory field in each pll */
+       for (i = 0; i < _PLL_NB; i++) {
+               char name[12];
+
+               sprintf(name, "st,pll@%d", i);
+               plloff[i] = dev_read_subnode(dev, name);
+               if (!ofnode_valid(plloff[i]))
+                       continue;
+               ret = ofnode_read_u32_array(plloff[i], "cfg",
+                                           pllcfg[i], PLLCFG_NB);
+               if (ret < 0) {
+                       debug("field cfg invalid: error %d\n", ret);
+                       return -FDT_ERR_NOTFOUND;
+               }
+       }
+
+       debug("configuration MCO\n");
+       stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
+       stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
+
+       debug("switch ON osillator\n");
+       /*
+        * switch ON oscillator found in device-tree,
+        * HSI already ON after bootrom
+        */
+       if (priv->osc[_LSI])
+               stm32mp1_lsi_set(rcc, 1);
+
+       if (priv->osc[_LSE]) {
+               int bypass;
+               int lsedrv;
+               struct udevice *dev = priv->osc_dev[_LSE];
+
+               bypass = dev_read_bool(dev, "st,bypass");
+               lse_css = dev_read_bool(dev, "st,css");
+               lsedrv = dev_read_u32_default(dev, "st,drive",
+                                             LSEDRV_MEDIUM_HIGH);
+
+               stm32mp1_lse_enable(rcc, bypass, lsedrv);
+       }
+
+       if (priv->osc[_HSE]) {
+               int bypass, css;
+               struct udevice *dev = priv->osc_dev[_HSE];
+
+               bypass = dev_read_bool(dev, "st,bypass");
+               css = dev_read_bool(dev, "st,css");
+
+               stm32mp1_hse_enable(rcc, bypass, css);
+       }
+       /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
+        * => switch on CSI even if node is not present in device tree
+        */
+       stm32mp1_csi_set(rcc, 1);
+
+       /* come back to HSI */
+       debug("come back to HSI\n");
+       set_clksrc(priv, CLK_MPU_HSI);
+       set_clksrc(priv, CLK_AXI_HSI);
+       set_clksrc(priv, CLK_MCU_HSI);
+
+       debug("pll stop\n");
+       for (i = 0; i < _PLL_NB; i++)
+               pll_stop(priv, i);
+
+       /* configure HSIDIV */
+       debug("configure HSIDIV\n");
+       if (priv->osc[_HSI])
+               stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
+
+       /* select DIV */
+       debug("select DIV\n");
+       /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
+       writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
+       set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
+       set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
+       set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
+       set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
+       set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
+       set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
+       set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
+
+       /* no ready bit for RTC */
+       writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
+
+       /* configure PLLs source */
+       debug("configure PLLs source\n");
+       set_clksrc(priv, clksrc[CLKSRC_PLL12]);
+       set_clksrc(priv, clksrc[CLKSRC_PLL3]);
+       set_clksrc(priv, clksrc[CLKSRC_PLL4]);
+
+       /* configure and start PLLs */
+       debug("configure PLLs\n");
+       for (i = 0; i < _PLL_NB; i++) {
+               u32 fracv;
+               u32 csg[PLLCSG_NB];
+
+               debug("configure PLL %d @ %d\n", i,
+                     ofnode_to_offset(plloff[i]));
+               if (!ofnode_valid(plloff[i]))
+                       continue;
+
+               fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
+               pll_config(priv, i, pllcfg[i], fracv);
+               ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
+               if (!ret) {
+                       pll_csg(priv, i, csg);
+               } else if (ret != -FDT_ERR_NOTFOUND) {
+                       debug("invalid csg node for pll@%d res=%d\n", i, ret);
+                       return ret;
+               }
+               pll_start(priv, i);
+       }
+
+       /* wait and start PLLs ouptut when ready */
+       for (i = 0; i < _PLL_NB; i++) {
+               if (!ofnode_valid(plloff[i]))
+                       continue;
+               debug("output PLL %d\n", i);
+               pll_output(priv, i, pllcfg[i][PLLCFG_O]);
+       }
+
+       /* wait LSE ready before to use it */
+       if (priv->osc[_LSE])
+               stm32mp1_lse_wait(rcc);
+
+       /* configure with expected clock source */
+       debug("CLKSRC\n");
+       set_clksrc(priv, clksrc[CLKSRC_MPU]);
+       set_clksrc(priv, clksrc[CLKSRC_AXI]);
+       set_clksrc(priv, clksrc[CLKSRC_MCU]);
+       set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
+
+       /* configure PKCK */
+       debug("PKCK\n");
+       pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
+       if (pkcs_cell) {
+               bool ckper_disabled = false;
+
+               for (i = 0; i < len / sizeof(u32); i++) {
+                       u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
+
+                       if (pkcs == CLK_CKPER_DISABLED) {
+                               ckper_disabled = true;
+                               continue;
+                       }
+                       pkcs_config(priv, pkcs);
+               }
+               /* CKPER is source for some peripheral clock
+                * (FMC-NAND / QPSI-NOR) and switching source is allowed
+                * only if previous clock is still ON
+                * => deactivated CKPER only after switching clock
+                */
+               if (ckper_disabled)
+                       pkcs_config(priv, CLK_CKPER_DISABLED);
+       }
+
+       debug("oscillator off\n");
+       /* switch OFF HSI if not found in device-tree */
+       if (!priv->osc[_HSI])
+               stm32mp1_hsi_set(rcc, 0);
+
+       /* Software Self-Refresh mode (SSR) during DDR initilialization */
+       clrsetbits_le32(priv->base + RCC_DDRITFCR,
+                       RCC_DDRITFCR_DDRCKMOD_MASK,
+                       RCC_DDRITFCR_DDRCKMOD_SSR <<
+                       RCC_DDRITFCR_DDRCKMOD_SHIFT);
+
+       return 0;
+}
+#endif /* STM32MP1_CLOCK_TREE_INIT */
+
+static void stm32mp1_osc_clk_init(const char *name,
+                                 struct stm32mp1_clk_priv *priv,
+                                 int index)
+{
+       struct clk clk;
+       struct udevice *dev = NULL;
+
+       priv->osc[index] = 0;
+       clk.id = 0;
+       if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
+               if (clk_request(dev, &clk))
+                       pr_err("%s request", name);
+               else
+                       priv->osc[index] = clk_get_rate(&clk);
+       }
+       priv->osc_dev[index] = dev;
+}
+
+static void stm32mp1_osc_init(struct udevice *dev)
+{
+       struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+       int i;
+       const char *name[NB_OSC] = {
+               [_LSI] = "clk-lsi",
+               [_LSE] = "clk-lse",
+               [_HSI] = "clk-hsi",
+               [_HSE] = "clk-hse",
+               [_CSI] = "clk-csi",
+               [_I2S_CKIN] = "i2s_ckin",
+               [_USB_PHY_48] = "ck_usbo_48m"};
+
+       for (i = 0; i < NB_OSC; i++) {
+               stm32mp1_osc_clk_init(name[i], priv, i);
+               debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
+       }
+}
+
+static int stm32mp1_clk_probe(struct udevice *dev)
+{
+       int result = 0;
+       struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+
+       priv->base = dev_read_addr(dev->parent);
+       if (priv->base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->data = (void *)&stm32mp1_data;
+
+       if (!priv->data->gate || !priv->data->sel ||
+           !priv->data->pll)
+               return -EINVAL;
+
+       stm32mp1_osc_init(dev);
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+       /* clock tree init is done only one time, before relocation */
+       if (!(gd->flags & GD_FLG_RELOC))
+               result = stm32mp1_clktree(dev);
+#endif
+
+       return result;
+}
+
+static const struct clk_ops stm32mp1_clk_ops = {
+       .enable = stm32mp1_clk_enable,
+       .disable = stm32mp1_clk_disable,
+       .get_rate = stm32mp1_clk_get_rate,
+};
+
+static const struct udevice_id stm32mp1_clk_ids[] = {
+       { .compatible = "st,stm32mp1-rcc-clk" },
+       { }
+};
+
+U_BOOT_DRIVER(stm32mp1_clock) = {
+       .name = "stm32mp1_clk",
+       .id = UCLASS_CLK,
+       .of_match = stm32mp1_clk_ids,
+       .ops = &stm32mp1_clk_ops,
+       .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
+       .probe = stm32mp1_clk_probe,
+};

diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index 50f2a65c205edc1dbc41c2d6c1a8a5f8d260b314..3845e0730978e602e6df83e317c8fe1a2ab0e846 100644 (file)
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -394,7 +394,7 @@ static ulong zynq_clk_get_rate(struct clk *clk)
                return zynq_clk_get_peripheral_rate(priv, id, two_divs);
        case dma_clk:
                return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
-       case usb0_aper_clk ... smc_aper_clk:
+       case usb0_aper_clk ... swdt_clk:
                return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
        default:
                return -ENXIO;

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index bcc62904f174730162351e86ac737a4a868504e1..4ef8662af56035720a22f92d9460cff52bd7e370 100644 (file)
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -226,6 +226,18 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
                return CRL_APB_CAN0_REF_CTRL;
        case can1_ref:
                return CRL_APB_CAN1_REF_CTRL;
+       case pl0:
+               return CRL_APB_PL0_REF_CTRL;
+       case pl1:
+               return CRL_APB_PL1_REF_CTRL;
+       case pl2:
+               return CRL_APB_PL2_REF_CTRL;
+       case pl3:
+               return CRL_APB_PL3_REF_CTRL;
+       case wdt:
+               return CRF_APB_TOPSW_LSBUS_CTRL;
+       case iopll_to_fpd:
+               return CRL_APB_IOPLL_TO_FPD_CTRL;
        default:
                debug("Invalid clk id%d\n", id);
        }
@@ -278,6 +290,22 @@ static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
        }
 }
 
+static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
+{
+       u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
+                     CLK_CTRL_SRCSEL_SHIFT;
+
+       switch (srcsel) {
+       case 2:
+               return iopll_to_fpd;
+       case 3:
+               return dpll;
+       case 0 ... 1:
+       default:
+               return apll;
+       }
+}
+
 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
                                    struct zynqmp_clk_priv *priv,
                                    bool is_pre_src)
@@ -420,6 +448,49 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
                        DIV_ROUND_CLOSEST(pllrate, div0), div1);
 }
 
+static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
+                                    enum zynqmp_clk id, bool two_divs)
+{
+       enum zynqmp_clk pll;
+       u32 clk_ctrl, div0;
+       u32 div1 = 1;
+       int ret;
+       ulong pllrate;
+
+       ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
+       if (ret) {
+               printf("%d %s mio read fail\n", __LINE__, __func__);
+               return -EIO;
+       }
+
+       div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+       if (!div0)
+               div0 = 1;
+
+       pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
+       if (two_divs) {
+               ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
+               if (ret) {
+                       printf("%d %s mio read fail\n", __LINE__, __func__);
+                       return -EIO;
+               }
+               div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+               if (!div1)
+                       div1 = 1;
+       }
+
+       if (pll == iopll_to_fpd)
+               pll = iopll;
+
+       pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+       if (IS_ERR_VALUE(pllrate))
+               return pllrate;
+
+       return
+               DIV_ROUND_CLOSEST(
+                       DIV_ROUND_CLOSEST(pllrate, div0), div1);
+}
+
 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
                                                       ulong pll_rate,
                                                       u32 *div0, u32 *div1)
@@ -510,8 +581,12 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
                return zynqmp_clk_get_ddr_rate(priv);
        case gem0_ref ... gem3_ref:
        case qspi_ref ... can1_ref:
+       case pl0 ... pl3:
                two_divs = true;
                return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
+       case wdt:
+               two_divs = true;
+               return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
        default:
                return -ENXIO;
        }

diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index ad8df5a45902fe450064c5ada8e994d75b95394d..cfe6abe470104a514fb5dd24acbb1a3aeebe3062 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
                               unsigned int hz, bool has_bwadj)
 {
        static const struct pll_div dpll_cfg[] = {
-               {.nf = 25, .nr = 2, .no = 1},
+               {.nf = 75, .nr = 1, .no = 6},
                {.nf = 400, .nr = 9, .no = 2},
                {.nf = 500, .nr = 9, .no = 2},
                {.nf = 100, .nr = 3, .no = 1},

diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 3847dd836e30540b8a03406f7c623fbbd1bc811b..9a3b4c312af9f8eba5f0d29c8e7a9fe8122dc151 100644 (file)
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -49,12 +49,17 @@ fdt_addr_t devfdt_get_addr_index(struct udevice *dev, int index)
 
                reg += index * (na + ns);
 
-               /*
-                * Use the full-fledged translate function for complex
-                * bus setups.
-                */
-               addr = fdt_translate_address((void *)gd->fdt_blob,
-                                            dev_of_offset(dev), reg);
+               if (ns) {
+                       /*
+                        * Use the full-fledged translate function for complex
+                        * bus setups.
+                        */
+                       addr = fdt_translate_address((void *)gd->fdt_blob,
+                                                    dev_of_offset(dev), reg);
+               } else {
+                       /* Non translatable if #size-cells == 0 */
+                       addr = fdt_read_number(reg, na);
+               }
        } else {
                /*
                 * Use the "simple" translate function for less complex

diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 4e4532651fca608ae96a0d4d7b2e8bb28bacd44f..5909a25f85645bb61f1b1b7ea58d4cbc690306ab 100644 (file)
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -227,13 +227,16 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
                uint flags;
                u64 size;
                int na;
+               int ns;
 
                prop_val = of_get_address(ofnode_to_np(node), index, &size,
                                          &flags);
                if (!prop_val)
                        return FDT_ADDR_T_NONE;
 
-               if (IS_ENABLED(CONFIG_OF_TRANSLATE)) {
+               ns = of_n_size_cells(ofnode_to_np(node));
+
+               if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
                        return of_translate_address(ofnode_to_np(node), prop_val);
                } else {
                        na = of_n_addr_cells(ofnode_to_np(node));

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 3a426ab4b75f9e98ce71d7ead042aa5c7851ff28..9000ed55ca583f0c84abe81e0c209e8240fad6e2 100644 (file)
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -333,7 +333,8 @@ static int dm_scan_fdt_node(struct udevice *parent, const void *blob,
 
 int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
 {
-       int node, ret;
+       int ret;
+       ofnode node;
 
        ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
        if (ret) {
@@ -342,13 +343,18 @@ int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
        }
 
        /* bind fixed-clock */
-       node = ofnode_to_offset(ofnode_path("/clocks"));
+       node = ofnode_path("/clocks");
        /* if no DT "clocks" node, no need to go further */
-       if (node < 0)
+       if (!ofnode_valid(node))
                return ret;
 
-       ret = dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node,
-                              pre_reloc_only);
+#if CONFIG_IS_ENABLED(OF_LIVE)
+       if (of_live_active())
+               ret = dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only);
+       else
+#endif
+               ret = dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node.of_offset,
+                                      pre_reloc_only);
        if (ret)
                debug("dm_scan_fdt_node() failed: %d\n", ret);
 

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 1aedaa08f0c2ee4058d9ddf9054ee03db45937a0..628e2e13ff61c7c22168d0ec6336143152c6ce2e 100644 (file)
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -457,6 +457,32 @@ int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node,
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
+                                   struct udevice **devp)
+{
+       struct udevice *dev;
+       struct uclass *uc;
+       int ret;
+
+       *devp = NULL;
+       ret = uclass_get(id, &uc);
+       if (ret)
+               return ret;
+
+       list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+               uint phandle;
+
+               phandle = dev_read_phandle(dev);
+
+               if (phandle == phandle_id) {
+                       *devp = dev;
+                       return uclass_get_device_tail(dev, ret, devp);
+               }
+       }
+
+       return -ENODEV;
+}
+
 int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,
                                 const char *name, struct udevice **devp)
 {

diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 4ad291a56e2a93d9ed50facecd8e47fd05edec5d..6c612bacdc90471ef1a5f6f7f2e9926caadb32eb 100644 (file)
--- a/drivers/cpu/bmips_cpu.c
+++ b/drivers/cpu/bmips_cpu.c
@@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DMIPSPLLCFG_6358_N2_SHIFT      29
 #define DMIPSPLLCFG_6358_N2_MASK       (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
 
+#define REG_BCM6362_MISC_STRAPBUS      0x1814
+#define STRAPBUS_6362_FCVO_SHIFT       1
+#define STRAPBUS_6362_FCVO_MASK                (0x1f << STRAPBUS_6362_FCVO_SHIFT)
+
 #define REG_BCM6368_DDR_DMIPSPLLCFG    0x12a0
 #define DMIPSPLLCFG_6368_P1_SHIFT      0
 #define DMIPSPLLCFG_6368_P1_MASK       (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
@@ -194,6 +198,44 @@ static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
        return (16 * 1000000 * n1 * n2) / m1;
 }
 
+static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+       unsigned int mips_pll_fcvo;
+
+       mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
+       mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
+                       >> STRAPBUS_6362_FCVO_SHIFT;
+
+       switch (mips_pll_fcvo) {
+       case 0x03:
+       case 0x0b:
+       case 0x13:
+       case 0x1b:
+               return 240000000;
+       case 0x04:
+       case 0x0c:
+       case 0x14:
+       case 0x1c:
+               return 160000000;
+       case 0x05:
+       case 0x0e:
+       case 0x16:
+       case 0x1e:
+       case 0x1f:
+               return 400000000;
+       case 0x06:
+               return 440000000;
+       case 0x07:
+       case 0x17:
+               return 384000000;
+       case 0x15:
+       case 0x1d:
+               return 200000000;
+       default:
+               return 320000000;
+       }
+}
+
 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
        unsigned int tmp, p1, p2, ndiv, m1;
@@ -289,6 +331,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
        .get_cpu_count = bcm6358_get_cpu_count,
 };
 
+static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
+       .get_cpu_desc = bmips_short_cpu_desc,
+       .get_cpu_freq = bcm6362_get_cpu_freq,
+       .get_cpu_count = bcm6358_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
        .get_cpu_desc = bmips_short_cpu_desc,
        .get_cpu_freq = bcm6368_get_cpu_freq,
@@ -394,6 +442,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
        }, {
                .compatible = "brcm,bcm6358-cpu",
                .data = (ulong)&bmips_cpu_bcm6358,
+       }, {
+               .compatible = "brcm,bcm6362-cpu",
+               .data = (ulong)&bmips_cpu_bcm6362,
        }, {
                .compatible = "brcm,bcm6368-cpu",
                .data = (ulong)&bmips_cpu_bcm6368,

diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 6aead27f16265e5a3f66973ec5343da1a156baeb..ac01612d7518549ca4c245ef997adbb3919eb7ef 100644 (file)
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -148,20 +148,21 @@ int fpga_add(fpga_type devtype, void *desc)
 {
        int devnum = FPGA_INVALID_DEVICE;
 
+       if (!desc) {
+               printf("%s: NULL device descriptor\n", __func__);
+               return devnum;
+       }
+
        if (next_desc < 0) {
                printf("%s: FPGA support not initialized!\n", __func__);
        } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
-               if (desc) {
-                       if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
-                               devnum = next_desc;
-                               desc_table[next_desc].devtype = devtype;
-                               desc_table[next_desc++].devdesc = desc;
-                       } else {
-                               printf("%s: Exceeded Max FPGA device count\n",
-                                      __func__);
-                       }
+               if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
+                       devnum = next_desc;
+                       desc_table[next_desc].devtype = devtype;
+                       desc_table[next_desc++].devdesc = desc;
                } else {
-                       printf("%s: NULL device descriptor\n", __func__);
+                       printf("%s: Exceeded Max FPGA device count\n",
+                              __func__);
                }
        } else {
                printf("%s: Unsupported FPGA type %d\n", __func__, devtype);

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index cc75aece6a110f782748a6857d7a4b3d4c1aac0d..b7e4ffb09d691c93934e7b5a3a01cfc9116e712e 100644 (file)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -234,7 +234,7 @@ config PIC32_GPIO
 
 config STM32F7_GPIO
        bool "ST STM32 GPIO driver"
-       depends on DM_GPIO && STM32
+       depends on DM_GPIO && (STM32 || ARCH_STM32MP)
        default y
        help
          Device model driver support for STM32 GPIO controller. It should be

diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index 7243100219a99399dd7b9985ed393a944ca42883..559f29b8018ce832253b484e9d2330c1a183cd24 100644 (file)
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -345,6 +345,7 @@ U_BOOT_DRIVER(gpio_omap) = {
        .bind   = omap_gpio_bind,
        .probe  = omap_gpio_probe,
        .priv_auto_alloc_size = sizeof(struct gpio_bank),
+       .flags = DM_FLAG_PRE_RELOC,
 };
 
 #endif /* CONFIG_DM_GPIO */

diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
index a7cfb8c92323862e83c6dca95bc8d3215f798f23..376e86cd6995b61b46e89af00d89d37e1ee3309c 100644 (file)
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -16,14 +16,11 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#define MAX_SIZE_BANK_NAME             5
 #define STM32_GPIOS_PER_BANK           16
 #define MODE_BITS(gpio_pin)            (gpio_pin * 2)
 #define MODE_BITS_MASK                 3
 #define IN_OUT_BIT_INDEX(gpio_pin)     (1UL << (gpio_pin))
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
 {
        struct stm32_gpio_priv *priv = dev_get_priv(dev);
@@ -82,21 +79,19 @@ static int gpio_stm32_probe(struct udevice *dev)
        struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
        struct stm32_gpio_priv *priv = dev_get_priv(dev);
        fdt_addr_t addr;
-       char *name;
+       const char *name;
 
-       addr = devfdt_get_addr(dev);
+       addr = dev_read_addr(dev);
        if (addr == FDT_ADDR_T_NONE)
                return -EINVAL;
 
        priv->regs = (struct stm32_gpio_regs *)addr;
-       name = (char *)fdtdec_locate_byte_array(gd->fdt_blob,
-                                               dev_of_offset(dev),
-                                               "st,bank-name",
-                                               MAX_SIZE_BANK_NAME);
+       name = dev_read_string(dev, "st,bank-name");
        if (!name)
                return -EINVAL;
        uc_priv->bank_name = name;
-       uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
+       uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
+                                                  STM32_GPIOS_PER_BANK);
        debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
              uc_priv->bank_name);
 

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 932abd305970e23aab3efc3618a07419732103c5..3299ef0fead2f2aa5b028142c30a8689f6917b0b 100644 (file)
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -207,7 +207,7 @@ config SYS_I2C_S3C24X0
 
 config SYS_I2C_STM32F7
        bool "STMicroelectronics STM32F7 I2C support"
-       depends on (STM32F7 || STM32H7) && DM_I2C
+       depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
        help
          Enable this option to add support for STM32 I2C controller
          introduced with STM32F7/H7 SoCs. This I2C controller supports :

diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index de74e89efdc0510e9a3e82154295906405da785e..32d7809dba6500908ab4c2a060e24c6d7040eae6 100644 (file)
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -156,7 +156,7 @@ static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len)
 
 static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir)
 {
-       lpi2c_status_t result = LPI2C_SUCESS;
+       lpi2c_status_t result;
        u32 val;
 
        result = imx_lpci2c_check_busy_bus(regs);
@@ -184,7 +184,7 @@ static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir)
 
 static int bus_i2c_stop(struct imx_lpi2c_reg *regs)
 {
-       lpi2c_status_t result = LPI2C_SUCESS;
+       lpi2c_status_t result;
        u32 status;
 
        result = bus_i2c_wait_for_tx_ready(regs);
@@ -213,7 +213,7 @@ static int bus_i2c_stop(struct imx_lpi2c_reg *regs)
 
 static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
 {
-       lpi2c_status_t result = LPI2C_SUCESS;
+       lpi2c_status_t result;
 
        result = bus_i2c_start(regs, chip, 1);
        if (result)
@@ -230,7 +230,7 @@ static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
 
 static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
 {
-       lpi2c_status_t result = LPI2C_SUCESS;
+       lpi2c_status_t result;
 
        result = bus_i2c_start(regs, chip, 0);
        if (result)
@@ -354,7 +354,7 @@ static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
                                u32 chip_flags)
 {
        struct imx_lpi2c_reg *regs;
-       lpi2c_status_t result = LPI2C_SUCESS;
+       lpi2c_status_t result;
 
        regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
        result = bus_i2c_start(regs, chip, 0);

diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 86624878e2eacc77cfe2cf42bd8793d5d8a44b04..81f061aecd8da97fa0e66a060ae99ed163edeade 100644 (file)
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -533,7 +533,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
                                if (((sdadel >= sdadel_min) &&
                                     (sdadel <= sdadel_max)) &&
                                    (p != p_prev)) {
-                                       v = kmalloc(sizeof(*v), GFP_KERNEL);
+                                       v = calloc(1, sizeof(*v));
                                        if (!v)
                                                return -ENOMEM;
 
@@ -689,7 +689,7 @@ exit:
        /* Release list and memory */
        list_for_each_entry_safe(v, _v, &solutions, node) {
                list_del(&v->node);
-               kfree(v);
+               free(v);
        }
 
        return ret;

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5f67e336dba58f04056087fc9d1741f09537e179..3a79cbf16578a1c8ea3cfaa51e6c707bfde6b498 100644 (file)
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -523,18 +523,18 @@ config STM32_SDMMC2
          If you have a board based on such a SoC and with a SD/MMC slot,
          say Y or M here.
 
-config MMC_NDS32
-       bool "Andestech SD/MMC controller support"
-       depends on DM_MMC && OF_CONTROL && BLK && FTSDC010
-       help
-         This enables support for the Andestech SD/MMM controller, which is
-         based on Faraday IP.
-
 config FTSDC010
        bool "Ftsdc010 SD/MMC controller Support"
        help
          This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP.
 
+config FTSDC010_SDIO
+       bool "Support ftsdc010 sdio"
+       default n
+       depends on FTSDC010
+       help
+               This can enable ftsdc010 sdio function.
+
 endif
 
 config TEGRA124_MMC_DISABLE_EXT_LOOPBACK

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 42113e260324a6454e7cee3b989767a4fa76a395..958341017c7830d7511d7fa1d467da95c0892bda 100644 (file)
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_MMC_SANDBOX)             += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
-obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)                        += sdhci.o

diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index 6ac4f83bd1cf34c38cae3aa8a1d6f19fbc567e8f..9de3a1503dee8ed9a2bdb785187e354fb877fe62 100644 (file)
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -4,23 +4,63 @@
  * (C) Copyright 2010 Faraday Technology
  * Dante Su <dantesu@faraday-tech.com>
  *
+ * Copyright 2018 Andes Technology, Inc.
+ * Author: Rick Chen (rick@andestech.com)
+ *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <clk.h>
 #include <malloc.h>
 #include <part.h>
 #include <mmc.h>
-
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <asm/byteorder.h>
 #include <faraday/ftsdc010.h>
 #include "ftsdc010_mci.h"
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <pwrseq.h>
+#include <syscon.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct ftsdc010 {
+       fdt32_t         bus_width;
+       bool            cap_mmc_highspeed;
+       bool            cap_sd_highspeed;
+       fdt32_t         clock_freq_min_max[2];
+       struct phandle_2_cell   clocks[4];
+       fdt32_t         fifo_depth;
+       fdt32_t         reg[2];
+};
+#endif
+
+struct ftsdc010_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct ftsdc010 dtplat;
+#endif
+       struct mmc_config cfg;
+       struct mmc mmc;
+};
+
+struct ftsdc_priv {
+       struct clk clk;
+       struct ftsdc010_chip chip;
+       int fifo_depth;
+       bool fifo_mode;
+       u32 minmax[2];
+};
+
 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
 {
        struct ftsdc010_chip *chip = mmc->priv;
@@ -138,16 +178,10 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
 /*
  * u-boot mmc api
  */
-#ifdef CONFIG_DM_MMC
 static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
        struct mmc_data *data)
 {
        struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
-       struct mmc_data *data)
-{
-#endif
        int ret = -EOPNOTSUPP;
        uint32_t len = 0;
        struct ftsdc010_chip *chip = mmc->priv;
@@ -248,14 +282,9 @@ static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
        return ret;
 }
 
-#ifdef CONFIG_DM_MMC
 static int ftsdc010_set_ios(struct udevice *dev)
 {
        struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_set_ios(struct mmc *mmc)
-{
-#endif
        struct ftsdc010_chip *chip = mmc->priv;
        struct ftsdc010_mmc __iomem *regs = chip->regs;
 
@@ -277,27 +306,17 @@ static int ftsdc010_set_ios(struct mmc *mmc)
        return 0;
 }
 
-#ifdef CONFIG_DM_MMC
 static int ftsdc010_get_cd(struct udevice *dev)
 {
        struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_get_cd(struct mmc *mmc)
-{
-#endif
        struct ftsdc010_chip *chip = mmc->priv;
        struct ftsdc010_mmc __iomem *regs = chip->regs;
        return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
 }
 
-#ifdef CONFIG_DM_MMC
 static int ftsdc010_get_wp(struct udevice *dev)
 {
        struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int ftsdc010_get_wp(struct mmc *mmc)
-{
-#endif
        struct ftsdc010_chip *chip = mmc->priv;
        struct ftsdc010_mmc __iomem *regs = chip->regs;
        if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
@@ -337,31 +356,20 @@ static int ftsdc010_init(struct mmc *mmc)
        return 0;
 }
 
-#ifdef CONFIG_DM_MMC
-int ftsdc010_probe(struct udevice *dev)
+static int ftsdc010_probe(struct udevice *dev)
 {
        struct mmc *mmc = mmc_get_mmc_dev(dev);
        return ftsdc010_init(mmc);
 }
 
-const struct dm_mmc_ops dm_ftsdc010_ops = {
+const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
        .send_cmd       = ftsdc010_request,
        .set_ios        = ftsdc010_set_ios,
        .get_cd         = ftsdc010_get_cd,
        .get_wp         = ftsdc010_get_wp,
 };
 
-#else
-static const struct mmc_ops ftsdc010_ops = {
-       .send_cmd       = ftsdc010_request,
-       .set_ios        = ftsdc010_set_ios,
-       .getcd          = ftsdc010_get_cd,
-       .getwp          = ftsdc010_get_wp,
-       .init           = ftsdc010_init,
-};
-#endif
-
-void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
                     uint caps, u32 max_clk, u32 min_clk)
 {
        cfg->name = name;
@@ -380,73 +388,94 @@ void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 }
 
-void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg)
+static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
 {
-       switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
-       case FTSDC010_BWR_CAPS_4BIT:
-               cfg->host_caps |= MMC_MODE_4BIT;
-               break;
-       case FTSDC010_BWR_CAPS_8BIT:
-               cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
-               break;
-       default:
-               break;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct ftsdc_priv *priv = dev_get_priv(dev);
+       struct ftsdc010_chip *chip = &priv->chip;
+       chip->name = dev->name;
+       chip->ioaddr = (void *)devfdt_get_addr(dev);
+       chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+                                       "bus-width", 4);
+       chip->priv = dev;
+       priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+                                   "fifo-depth", 0);
+       priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+                                         "fifo-mode");
+       if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
+                        "clock-freq-min-max", priv->minmax, 2)) {
+               int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+                                 "max-frequency", -EINVAL);
+               if (val < 0)
+                       return val;
+
+               priv->minmax[0] = 400000;  /* 400 kHz */
+               priv->minmax[1] = val;
+       } else {
+               debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+               __func__);
        }
+#endif
+       chip->sclk = priv->minmax[1];
+       chip->regs = chip->ioaddr;
+       return 0;
 }
 
-#ifdef CONFIG_BLK
-int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+static int ftsdc010_mmc_probe(struct udevice *dev)
 {
-       return mmc_bind(dev, mmc, cfg);
+       struct ftsdc010_plat *plat = dev_get_platdata(dev);
+       struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+       struct ftsdc_priv *priv = dev_get_priv(dev);
+       struct ftsdc010_chip *chip = &priv->chip;
+       struct udevice *pwr_dev __maybe_unused;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       int ret;
+       struct ftsdc010 *dtplat = &plat->dtplat;
+       chip->name = dev->name;
+       chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+       chip->buswidth = dtplat->bus_width;
+       chip->priv = dev;
+       chip->dev_index = 1;
+       memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
+       ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+       if (ret < 0)
+               return ret;
+#endif
+
+       if (dev_read_bool(dev, "cap-mmc-highspeed") || \
+                 dev_read_bool(dev, "cap-sd-highspeed"))
+               chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+       ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
+                       priv->minmax[1] , priv->minmax[0]);
+       chip->mmc = &plat->mmc;
+       chip->mmc->priv = &priv->chip;
+       chip->mmc->dev = dev;
+       upriv->mmc = chip->mmc;
+       return ftsdc010_probe(dev);
 }
-#else
 
-int ftsdc010_mmc_init(int devid)
+int ftsdc010_mmc_bind(struct udevice *dev)
 {
-       struct mmc *mmc;
-       struct ftsdc010_chip *chip;
-       struct ftsdc010_mmc __iomem *regs;
-#ifdef CONFIG_FTSDC010_BASE_LIST
-       uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
-
-       if (devid < 0 || devid >= ARRAY_SIZE(base_list))
-               return -1;
-       regs = (void __iomem *)base_list[devid];
-#else
-       regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
-#endif
-
-       chip = malloc(sizeof(struct ftsdc010_chip));
-       if (!chip)
-               return -ENOMEM;
-       memset(chip, 0, sizeof(struct ftsdc010_chip));
+       struct ftsdc010_plat *plat = dev_get_platdata(dev);
 
-       chip->regs = regs;
-#ifdef CONFIG_SYS_CLK_FREQ
-       chip->sclk = CONFIG_SYS_CLK_FREQ;
-#else
-       chip->sclk = clk_get_rate("SDC");
-#endif
+       return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
 
-       chip->cfg.name = "ftsdc010";
-#ifndef CONFIG_DM_MMC
-       chip->cfg.ops = &ftsdc010_ops;
-#endif
-       chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
-       set_bus_width(regs , &chip->cfg);
-       chip->cfg.voltages  = MMC_VDD_32_33 | MMC_VDD_33_34;
-       chip->cfg.f_max     = chip->sclk / 2;
-       chip->cfg.f_min     = chip->sclk / 0x100;
-
-       chip->cfg.part_type = PART_TYPE_DOS;
-       chip->cfg.b_max     = CONFIG_SYS_MMC_MAX_BLK_COUNT;
-
-       mmc = mmc_create(&chip->cfg, chip);
-       if (mmc == NULL) {
-               free(chip);
-               return -ENOMEM;
-       }
+static const struct udevice_id ftsdc010_mmc_ids[] = {
+       { .compatible = "andestech,atsdc010" },
+       { }
+};
 
-       return 0;
-}
-#endif
+U_BOOT_DRIVER(ftsdc010_mmc) = {
+       .name           = "ftsdc010_mmc",
+       .id             = UCLASS_MMC,
+       .of_match       = ftsdc010_mmc_ids,
+       .ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
+       .ops            = &dm_ftsdc010_mmc_ops,
+       .bind           = ftsdc010_mmc_bind,
+       .probe          = ftsdc010_mmc_probe,
+       .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
+       .platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),
+};

diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h
index 31a27fd77281136cef04750c55332a3dc2c20cea..e41736066217c0a88b71b2b2f8d558ab00506e14 100644 (file)
--- a/drivers/mmc/ftsdc010_mci.h
+++ b/drivers/mmc/ftsdc010_mci.h
@@ -35,19 +35,4 @@ struct ftsdc010_chip {
        bool fifo_mode;
 };
 
-
-#ifdef CONFIG_DM_MMC
-/* Export the operations to drivers */
-int ftsdc010_probe(struct udevice *dev);
-extern const struct dm_mmc_ops dm_ftsdc010_ops;
-#endif
-void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
-                    uint caps, u32 max_clk, u32 min_clk);
-void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg);
-
-#ifdef CONFIG_BLK
-int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
-#endif
-
-
 #endif /* __FTSDC010_MCI_H */

diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c
deleted file mode 100644 (file)
index 6d3c857..0000000
--- a/drivers/mmc/nds32_mmc.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Andestech ATFSDC010 SD/MMC driver
- *
- * (C) Copyright 2017
- * Rick Chen, NDS32 Software Engineering, rick@andestech.com
-
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <dt-structs.h>
-#include <errno.h>
-#include <mapmem.h>
-#include <mmc.h>
-#include <pwrseq.h>
-#include <syscon.h>
-#include <linux/err.h>
-#include <faraday/ftsdc010.h>
-#include "ftsdc010_mci.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-struct nds_mmc {
-       fdt32_t         bus_width;
-       bool            cap_mmc_highspeed;
-       bool            cap_sd_highspeed;
-       fdt32_t         clock_freq_min_max[2];
-       struct phandle_2_cell   clocks[4];
-       fdt32_t         fifo_depth;
-       fdt32_t         reg[2];
-};
-#endif
-
-struct nds_mmc_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-       struct nds_mmc dtplat;
-#endif
-       struct mmc_config cfg;
-       struct mmc mmc;
-};
-
-struct ftsdc_priv {
-       struct clk clk;
-       struct ftsdc010_chip chip;
-       int fifo_depth;
-       bool fifo_mode;
-       u32 minmax[2];
-};
-
-static int nds32_mmc_ofdata_to_platdata(struct udevice *dev)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-       struct ftsdc_priv *priv = dev_get_priv(dev);
-       struct ftsdc010_chip *chip = &priv->chip;
-       chip->name = dev->name;
-       chip->ioaddr = (void *)devfdt_get_addr(dev);
-       chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-                                       "bus-width", 4);
-       chip->priv = dev;
-       priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-                                   "fifo-depth", 0);
-       priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
-                                         "fifo-mode");
-       if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
-                        "clock-freq-min-max", priv->minmax, 2)) {
-               int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-                                 "max-frequency", -EINVAL);
-               if (val < 0)
-                       return val;
-
-               priv->minmax[0] = 400000;  /* 400 kHz */
-               priv->minmax[1] = val;
-       } else {
-               debug("%s: 'clock-freq-min-max' property was deprecated.\n",
-               __func__);
-       }
-#endif
-       chip->sclk = priv->minmax[1];
-       chip->regs = chip->ioaddr;
-       return 0;
-}
-
-static int nds32_mmc_probe(struct udevice *dev)
-{
-       struct nds_mmc_plat *plat = dev_get_platdata(dev);
-       struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-       struct ftsdc_priv *priv = dev_get_priv(dev);
-       struct ftsdc010_chip *chip = &priv->chip;
-       struct udevice *pwr_dev __maybe_unused;
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-       int ret;
-       struct nds_mmc *dtplat = &plat->dtplat;
-       chip->name = dev->name;
-       chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
-       chip->buswidth = dtplat->bus_width;
-       chip->priv = dev;
-       chip->dev_index = 1;
-       memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
-       ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
-       if (ret < 0)
-               return ret;
-#endif
-       ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
-                       priv->minmax[1] , priv->minmax[0]);
-       chip->mmc = &plat->mmc;
-       chip->mmc->priv = &priv->chip;
-       chip->mmc->dev = dev;
-       upriv->mmc = chip->mmc;
-       return ftsdc010_probe(dev);
-}
-
-static int nds32_mmc_bind(struct udevice *dev)
-{
-       struct nds_mmc_plat *plat = dev_get_platdata(dev);
-       return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);
-}
-
-static const struct udevice_id nds32_mmc_ids[] = {
-       { .compatible = "andestech,atsdc010" },
-       { }
-};
-
-U_BOOT_DRIVER(nds32_mmc_drv) = {
-       .name           = "nds32_mmc",
-       .id             = UCLASS_MMC,
-       .of_match       = nds32_mmc_ids,
-       .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
-       .ops            = &dm_ftsdc010_ops,
-       .bind           = nds32_mmc_bind,
-       .probe          = nds32_mmc_probe,
-       .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
-       .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),
-};

diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 05c0044a7a001148fc8e3183a2229fc171ed6b33..b7a2ebfe3f8e8428ae80b877e314d1d53e9feaf9 100644 (file)
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -29,11 +29,10 @@ static int pci_mmc_probe(struct udevice *dev)
        struct pci_mmc_plat *plat = dev_get_platdata(dev);
        struct pci_mmc_priv *priv = dev_get_priv(dev);
        struct sdhci_host *host = &priv->host;
-       u32 ioaddr;
        int ret;
 
-       dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &ioaddr);
-       host->ioaddr = map_sysmem(ioaddr, 0);
+       host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
+                                             PCI_REGION_MEM);
        host->name = dev->name;
        ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
        if (ret)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index be6edb2eaed0ffd1cc8a92894355d0a7825bf13b..ab89be47644e9dc3359255ce0a4be7a4d42b7ddb 100644 (file)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -62,6 +62,13 @@ static int arasan_sdhci_probe(struct udevice *dev)
 
        host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
        host->max_clk = max_frequency;
+       /*
+        * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
+        * doesn't allow us to clear MMC_MODE_4BIT.  Consequently, we don't
+        * check for other bus-width values.
+        */
+       if (host->bus_width == 8)
+               host->host_caps |= MMC_MODE_8BIT;
 
        ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
 
@@ -82,6 +89,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 
        host->name = dev->name;
        host->ioaddr = dev_read_addr_ptr(dev);
+       host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
 #endif
 
        return 0;

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 9f7d9d6ff7ae2ca04edfe29bd09f4af9da810fc1..332d905a3af9f5d2e2a9d6da20e07b32c5842b93 100644 (file)
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -57,7 +57,6 @@ obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand.o
-obj-$(CONFIG_NAND_NDFC) += ndfc.o
 obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
 obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
 obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o

diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 3c9a0215c53e6fc5e310a22dee17d01909ecc271..9c82c7db33fb40b259e2ec480dded85efbbbf197 100644 (file)
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK         0x70000000
 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT                28
 
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK                0xFFFF0000
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK                0xFFFF
 #define ARASAN_NAND_MEM_ADDR1_COL_MASK         0xFFFF
 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT       16
 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK                0xFF
@@ -795,10 +795,11 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 
        writel(reg_val, &arasan_nand_base->cmd_reg);
 
-       page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
+       page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
                ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
        column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
-       writel(page | column, &arasan_nand_base->memadr_reg1);
+       writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
+              &arasan_nand_base->memadr_reg1);
 
        reg_val = readl(&arasan_nand_base->memadr_reg2);
        reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;

diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 8b548b204d68fc0ddd3079bd61b535e11de2d379..13a6535bd5a36442fa89cfcde4c7f5b6a957a18e 100644 (file)
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -29,11 +29,6 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand_ecc.h>
 
-/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
-#ifdef CONFIG_NAND_NDFC
-#define CONFIG_MTD_NAND_ECC_SMC
-#endif
-
 /*
  * NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
  * only nand_correct_data() is needed
@@ -110,13 +105,8 @@ int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
        tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
 
        /* Calculate final ECC code */
-#ifdef CONFIG_MTD_NAND_ECC_SMC
-       ecc_code[0] = ~tmp2;
-       ecc_code[1] = ~tmp1;
-#else
        ecc_code[0] = ~tmp1;
        ecc_code[1] = ~tmp2;
-#endif
        ecc_code[2] = ((~reg1) << 2) | 0x03;
 
        return 0;
@@ -146,15 +136,9 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat,
 {
        uint8_t s0, s1, s2;
 
-#ifdef CONFIG_MTD_NAND_ECC_SMC
-       s0 = calc_ecc[0] ^ read_ecc[0];
-       s1 = calc_ecc[1] ^ read_ecc[1];
-       s2 = calc_ecc[2] ^ read_ecc[2];
-#else
        s1 = calc_ecc[0] ^ read_ecc[0];
        s0 = calc_ecc[1] ^ read_ecc[1];
        s2 = calc_ecc[2] ^ read_ecc[2];
-#endif
        if ((s0 | s1 | s2) == 0)
                return 0;
 

diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
deleted file mode 100644 (file)
index 0a9849e..0000000
--- a/drivers/mtd/nand/ndfc.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Overview:
- *   Platform independent driver for NDFC (NanD Flash Controller)
- *   integrated into IBM/AMCC PPC4xx cores
- *
- * (C) Copyright 2006-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- *     Thomas Gleixner
- *     Copyright 2006 IBM
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <linux/mtd/ndfc.h>
-#include <linux/mtd/nand_ecc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx.h>
-
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
-#endif
-#ifndef CONFIG_SYS_NDFC_EBC0_CFG
-#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
-#endif
-
-/*
- * We need to store the info, which chip-select (CS) is used for the
- * chip number. For example on Sequoia NAND chip #0 uses
- * CS #3.
- */
-static int ndfc_cs[NDFC_MAX_BANKS];
-
-static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-       struct nand_chip *this = mtd_to_nand(mtd);
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
-       if (cmd == NAND_CMD_NONE)
-               return;
-
-       if (ctrl & NAND_CLE)
-               out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
-       else
-               out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
-}
-
-static int ndfc_dev_ready(struct mtd_info *mtdinfo)
-{
-       struct nand_chip *this = mtd_to_nand(mtdinfo);
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
-       return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
-}
-
-static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
-{
-       struct nand_chip *this = mtd_to_nand(mtdinfo);
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-       u32 ccr;
-
-       ccr = in_be32((u32 *)(base + NDFC_CCR));
-       ccr |= NDFC_CCR_RESET_ECC;
-       out_be32((u32 *)(base + NDFC_CCR), ccr);
-}
-
-static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
-                             const u_char *dat, u_char *ecc_code)
-{
-       struct nand_chip *this = mtd_to_nand(mtdinfo);
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-       u32 ecc;
-       u8 *p = (u8 *)&ecc;
-
-       ecc = in_be32((u32 *)(base + NDFC_ECC));
-
-       /* The NDFC uses Smart Media (SMC) bytes order
-        */
-       ecc_code[0] = p[1];
-       ecc_code[1] = p[2];
-       ecc_code[2] = p[3];
-
-       return 0;
-}
-
-/*
- * Speedups for buffer read/write/verify
- *
- * NDFC allows 32bit read/write of data. So we can speed up the buffer
- * functions. No further checking, as nand_base will always read/write
- * page aligned.
- */
-static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
-       struct nand_chip *this = mtd_to_nand(mtdinfo);
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-       uint32_t *p = (uint32_t *) buf;
-
-       for (;len > 0; len -= 4)
-               *p++ = in_be32((u32 *)(base + NDFC_DATA));
-}
-
-/*
- * Don't use these speedup functions in NAND boot image, since the image
- * has to fit into 4kByte.
- */
-static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-       struct nand_chip *this = mtd_to_nand(mtdinfo);
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-       uint32_t *p = (uint32_t *) buf;
-
-       for (; len > 0; len -= 4)
-               out_be32((u32 *)(base + NDFC_DATA), *p++);
-}
-
-/*
- * Read a byte from the NDFC.
- */
-static uint8_t ndfc_read_byte(struct mtd_info *mtd)
-{
-
-       struct nand_chip *chip = mtd_to_nand(mtd);
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
-       return (uint8_t) readw(chip->IO_ADDR_R);
-#else
-       return readb(chip->IO_ADDR_R);
-#endif
-
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-       /*
-        * Don't use "chip" to address the NAND device,
-        * generate the cs from the address where it is encoded.
-        */
-       ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
-       int cs = ndfc_cs[chip];
-
-       /* Set NandFlash Core Configuration Register */
-       /* 1 col x 2 rows */
-       out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
-       out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
-}
-
-static void ndfc_select_chip(struct mtd_info *mtd, int chip)
-{
-       /*
-        * Nothing to do here!
-        */
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-       int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
-       ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
-       static int chip = 0;
-
-       /*
-        * Save chip-select for this chip #
-        */
-       ndfc_cs[chip] = cs;
-
-       /*
-        * Select required NAND chip in NDFC
-        */
-       board_nand_select_device(nand, chip);
-
-       nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
-       nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
-       nand->cmd_ctrl = ndfc_hwcontrol;
-       nand->chip_delay = 50;
-       nand->read_buf = ndfc_read_buf;
-       nand->dev_ready = ndfc_dev_ready;
-       nand->ecc.correct = nand_correct_data;
-       nand->ecc.hwctl = ndfc_enable_hwecc;
-       nand->ecc.calculate = ndfc_calculate_ecc;
-       nand->ecc.mode = NAND_ECC_HW;
-       nand->ecc.size = 256;
-       nand->ecc.bytes = 3;
-       nand->ecc.strength = 1;
-       nand->select_chip = ndfc_select_chip;
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
-       nand->options |= NAND_BUSWIDTH_16;
-#endif
-
-       nand->write_buf  = ndfc_write_buf;
-       nand->read_byte = ndfc_read_byte;
-
-       chip++;
-
-       return 0;
-}

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 294d9f9d79c6eb123dec396bd56fac801d8da860..2e61685d3ea462509c40c431c8dd6129ca48a6bc 100644 (file)
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -320,7 +320,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 
        erase_size = flash->erase_size;
        if (offset % erase_size || len % erase_size) {
-               debug("SF: Erase offset/length not multiple of erase size\n");
+               printf("SF: Erase offset/length not multiple of erase size\n");
                return -1;
        }
 

diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index caa5197df5062b83fea37f8d77ad1015621ff627..cf847833562da1034b906fa78763a9f262acc3f8 100644 (file)
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -1,5 +1,12 @@
 menu "UBI support"
 
+config CONFIG_UBI_SILENCE_MSG
+       bool "UBI silence verbose messages"
+       default ENV_IS_IN_UBI
+       help
+         Make the verbose messages from UBI stop printing. This leaves
+         warnings and errors enabled.
+
 config MTD_UBI
        bool "Enable UBI - Unsorted block images"
        select CRC32

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947ccc1731938b5abe07622584f8e4f5171fe..f589978b43584335708b93c2a1a2e5098d4a5f52 100644 (file)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,4 +1,5 @@
 source "drivers/net/phy/Kconfig"
+source "drivers/net/pfe_eth/Kconfig"
 
 config DM_ETH
        bool "Enable Driver Model for Ethernet drivers"

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4a16c62bac09c271ee264e5cda7b19944ab8e9c8..2687fbbdb27c9e396009744dc1f4c09d3cee2678 100644 (file)
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
 obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
 obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
-obj-$(CONFIG_ENC28J60) += enc28j60.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
 obj-$(CONFIG_ETHOC) += ethoc.o
 obj-$(CONFIG_FEC_MXC) += fec_mxc.o
@@ -73,3 +72,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index b72258f83bfec9694d42637da38620e35b1c09ed..e2395dbeb9ccc4a9715ed91b8525491a8edbc365 100644 (file)
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -949,7 +949,7 @@ static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 {
        void *buffer;
        int len;
-       int ret = -EAGAIN;
+       int ret;
 
        ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
        if (ret < 0)

diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
deleted file mode 100644 (file)
index 588a84d..0000000
--- a/drivers/net/enc28j60.c
+++ /dev/null
@@ -1,959 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- * Martin Krause, Martin.Krause@tqs.de
- * reworked original enc28j60.c
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <spi.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include "enc28j60.h"
-
-/*
- * IMPORTANT: spi_claim_bus() and spi_release_bus()
- * are called at begin and end of each of the following functions:
- * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
- * enc_init(), enc_recv(), enc_send(), enc_halt()
- * ALL other functions assume that the bus has already been claimed!
- * Since net_process_received_packet() might call enc_send() in return, the bus
- * must be released, net_process_received_packet() called and claimed again.
- */
-
-/*
- * Controller memory layout.
- * We only allow 1 frame for transmission and reserve the rest
- * for reception to handle as many broadcast packets as possible.
- * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
- * 0x0000 - 0x19ff 6656 bytes receive buffer
- * 0x1a00 - 0x1fff 1536 bytes transmit buffer =
- * control(1)+frame(1518)+status(7)+reserve(10).
- */
-#define ENC_RX_BUF_START       0x0000
-#define ENC_RX_BUF_END         0x19ff
-#define ENC_TX_BUF_START       0x1a00
-#define ENC_TX_BUF_END         0x1fff
-#define ENC_MAX_FRM_LEN                1518
-#define RX_RESET_COUNTER       1000
-
-/*
- * For non data transfer functions, like phy read/write, set hwaddr, init
- * we do not need a full, time consuming init including link ready wait.
- * This enum helps to bring the chip through the minimum necessary inits.
- */
-enum enc_initstate {none=0, setupdone, linkready};
-typedef struct enc_device {
-       struct eth_device       *dev;   /* back pointer */
-       struct spi_slave        *slave;
-       int                     rx_reset_counter;
-       u16                     next_pointer;
-       u8                      bank;   /* current bank in enc28j60 */
-       enum enc_initstate      initstate;
-} enc_dev_t;
-
-/*
- * enc_bset:           set bits in a common register
- * enc_bclr:           clear bits in a common register
- *
- * making the reg parameter u8 will give a compile time warning if the
- * functions are called with a register not accessible in all Banks
- */
-static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
-{
-       u8 dout[2];
-
-       dout[0] = CMD_BFS(reg);
-       dout[1] = data;
-       spi_xfer(enc->slave, 2 * 8, dout, NULL,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
-{
-       u8 dout[2];
-
-       dout[0] = CMD_BFC(reg);
-       dout[1] = data;
-       spi_xfer(enc->slave, 2 * 8, dout, NULL,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-/*
- * high byte of the register contains bank number:
- * 0: no bank switch necessary
- * 1: switch to bank 0
- * 2: switch to bank 1
- * 3: switch to bank 2
- * 4: switch to bank 3
- */
-static void enc_set_bank(enc_dev_t *enc, const u16 reg)
-{
-       u8 newbank = reg >> 8;
-
-       if (newbank == 0 || newbank == enc->bank)
-               return;
-       switch (newbank) {
-       case 1:
-               enc_bclr(enc, CTL_REG_ECON1,
-                       ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
-               break;
-       case 2:
-               enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
-               enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
-               break;
-       case 3:
-               enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
-               enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
-               break;
-       case 4:
-               enc_bset(enc, CTL_REG_ECON1,
-                       ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
-               break;
-       }
-       enc->bank = newbank;
-}
-
-/*
- * local functions to access SPI
- *
- * reg: register inside ENC28J60
- * data: 8/16 bits to write
- * c: number of retries
- *
- * enc_r8:             read 8 bits
- * enc_r16:            read 16 bits
- * enc_w8:             write 8 bits
- * enc_w16:            write 16 bits
- * enc_w8_retry:       write 8 bits, verify and retry
- * enc_rbuf:           read from ENC28J60 into buffer
- * enc_wbuf:           write from buffer into ENC28J60
- */
-
-/*
- * MAC and MII registers need a 3 byte SPI transfer to read,
- * all other registers need a 2 byte SPI transfer.
- */
-static int enc_reg2nbytes(const u16 reg)
-{
-       /* check if MAC or MII register */
-       return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
-               (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
-               (reg == CTL_REG_MISTAT)) ? 3 : 2;
-}
-
-/*
- * Read a byte register
- */
-static u8 enc_r8(enc_dev_t *enc, const u16 reg)
-{
-       u8 dout[3];
-       u8 din[3];
-       int nbytes = enc_reg2nbytes(reg);
-
-       enc_set_bank(enc, reg);
-       dout[0] = CMD_RCR(reg);
-       spi_xfer(enc->slave, nbytes * 8, dout, din,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-       return din[nbytes-1];
-}
-
-/*
- * Read a L/H register pair and return a word.
- * Must be called with the L register's address.
- */
-static u16 enc_r16(enc_dev_t *enc, const u16 reg)
-{
-       u8 dout[3];
-       u8 din[3];
-       u16 result;
-       int nbytes = enc_reg2nbytes(reg);
-
-       enc_set_bank(enc, reg);
-       dout[0] = CMD_RCR(reg);
-       spi_xfer(enc->slave, nbytes * 8, dout, din,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-       result = din[nbytes-1];
-       dout[0]++; /* next register */
-       spi_xfer(enc->slave, nbytes * 8, dout, din,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-       result |= din[nbytes-1] << 8;
-       return result;
-}
-
-/*
- * Write a byte register
- */
-static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
-{
-       u8 dout[2];
-
-       enc_set_bank(enc, reg);
-       dout[0] = CMD_WCR(reg);
-       dout[1] = data;
-       spi_xfer(enc->slave, 2 * 8, dout, NULL,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-/*
- * Write a L/H register pair.
- * Must be called with the L register's address.
- */
-static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
-{
-       u8 dout[2];
-
-       enc_set_bank(enc, reg);
-       dout[0] = CMD_WCR(reg);
-       dout[1] = data;
-       spi_xfer(enc->slave, 2 * 8, dout, NULL,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-       dout[0]++; /* next register */
-       dout[1] = data >> 8;
-       spi_xfer(enc->slave, 2 * 8, dout, NULL,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-/*
- * Write a byte register, verify and retry
- */
-static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
-{
-       u8 dout[2];
-       u8 readback;
-       int i;
-
-       enc_set_bank(enc, reg);
-       for (i = 0; i < c; i++) {
-               dout[0] = CMD_WCR(reg);
-               dout[1] = data;
-               spi_xfer(enc->slave, 2 * 8, dout, NULL,
-                       SPI_XFER_BEGIN | SPI_XFER_END);
-               readback = enc_r8(enc, reg);
-               if (readback == data)
-                       break;
-               /* wait 1ms */
-               udelay(1000);
-       }
-       if (i == c) {
-               printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
-       }
-}
-
-/*
- * Read ENC RAM into buffer
- */
-static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
-{
-       u8 dout[1];
-
-       dout[0] = CMD_RBM;
-       spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
-       spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
-#ifdef DEBUG
-       puts("Rx:\n");
-       print_buffer(0, buf, 1, length, 0);
-#endif
-}
-
-/*
- * Write buffer into ENC RAM
- */
-static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
-{
-       u8 dout[2];
-       dout[0] = CMD_WBM;
-       dout[1] = control;
-       spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
-       spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
-#ifdef DEBUG
-       puts("Tx:\n");
-       print_buffer(0, buf, 1, length, 0);
-#endif
-}
-
-/*
- * Try to claim the SPI bus.
- * Print error message on failure.
- */
-static int enc_claim_bus(enc_dev_t *enc)
-{
-       int rc = spi_claim_bus(enc->slave);
-       if (rc)
-               printf("%s: failed to claim SPI bus\n", enc->dev->name);
-       return rc;
-}
-
-/*
- * Release previously claimed SPI bus.
- * This function is mainly for symmetry to enc_claim_bus().
- * Let the toolchain decide to inline it...
- */
-static void enc_release_bus(enc_dev_t *enc)
-{
-       spi_release_bus(enc->slave);
-}
-
-/*
- * Read PHY register
- */
-static u16 enc_phy_read(enc_dev_t *enc, const u8 addr)
-{
-       uint64_t etime;
-       u8 status;
-
-       enc_w8(enc, CTL_REG_MIREGADR, addr);
-       enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
-       /* 1 second timeout - only happens on hardware problem */
-       etime = get_ticks() + get_tbclk();
-       /* poll MISTAT.BUSY bit until operation is complete */
-       do
-       {
-               status = enc_r8(enc, CTL_REG_MISTAT);
-       } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
-       if (status & ENC_MISTAT_BUSY) {
-               printf("%s: timeout reading phy\n", enc->dev->name);
-               return 0;
-       }
-       enc_w8(enc, CTL_REG_MICMD, 0);
-       return enc_r16(enc, CTL_REG_MIRDL);
-}
-
-/*
- * Write PHY register
- */
-static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
-{
-       uint64_t etime;
-       u8 status;
-
-       enc_w8(enc, CTL_REG_MIREGADR, addr);
-       enc_w16(enc, CTL_REG_MIWRL, data);
-       /* 1 second timeout - only happens on hardware problem */
-       etime = get_ticks() + get_tbclk();
-       /* poll MISTAT.BUSY bit until operation is complete */
-       do
-       {
-               status = enc_r8(enc, CTL_REG_MISTAT);
-       } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
-       if (status & ENC_MISTAT_BUSY) {
-               printf("%s: timeout writing phy\n", enc->dev->name);
-               return;
-       }
-}
-
-/*
- * Verify link status, wait if necessary
- *
- * Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
- * half/full duplex is a pure setup matter. For the time being, this driver
- * will setup in half duplex mode only.
- */
-static int enc_phy_link_wait(enc_dev_t *enc)
-{
-       u16 status;
-       int duplex;
-       uint64_t etime;
-
-#ifdef CONFIG_ENC_SILENTLINK
-       /* check if we have a link, then just return */
-       status = enc_phy_read(enc, PHY_REG_PHSTAT1);
-       if (status & ENC_PHSTAT1_LLSTAT)
-               return 0;
-#endif
-
-       /* wait for link with 1 second timeout */
-       etime = get_ticks() + get_tbclk();
-       while (get_ticks() <= etime) {
-               status = enc_phy_read(enc, PHY_REG_PHSTAT1);
-               if (status & ENC_PHSTAT1_LLSTAT) {
-                       /* now we have a link */
-                       status = enc_phy_read(enc, PHY_REG_PHSTAT2);
-                       duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
-                       printf("%s: link up, 10Mbps %s-duplex\n",
-                               enc->dev->name, duplex ? "full" : "half");
-                       return 0;
-               }
-               udelay(1000);
-       }
-
-       /* timeout occurred */
-       printf("%s: link down\n", enc->dev->name);
-       return 1;
-}
-
-/*
- * This function resets the receiver only.
- */
-static void enc_reset_rx(enc_dev_t *enc)
-{
-       u8 econ1;
-
-       econ1 = enc_r8(enc, CTL_REG_ECON1);
-       if ((econ1 & ENC_ECON1_RXRST) == 0) {
-               enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
-               enc->rx_reset_counter = RX_RESET_COUNTER;
-       }
-}
-
-/*
- * Reset receiver and reenable it.
- */
-static void enc_reset_rx_call(enc_dev_t *enc)
-{
-       enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
-       enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
-}
-
-/*
- * Copy a packet from the receive ring and forward it to
- * the protocol stack.
- */
-static void enc_receive(enc_dev_t *enc)
-{
-       u8 *packet = (u8 *)net_rx_packets[0];
-       u16 pkt_len;
-       u16 copy_len;
-       u16 status;
-       u8 pkt_cnt = 0;
-       u16 rxbuf_rdpt;
-       u8 hbuf[6];
-
-       enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
-       do {
-               enc_rbuf(enc, 6, hbuf);
-               enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
-               pkt_len = hbuf[2] | (hbuf[3] << 8);
-               status = hbuf[4] | (hbuf[5] << 8);
-               debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
-                       enc->next_pointer, pkt_len, status);
-               if (pkt_len <= ENC_MAX_FRM_LEN)
-                       copy_len = pkt_len;
-               else
-                       copy_len = 0;
-               if ((status & (1L << 7)) == 0) /* check Received Ok bit */
-                       copy_len = 0;
-               /* check if next pointer is resonable */
-               if (enc->next_pointer >= ENC_TX_BUF_START)
-                       copy_len = 0;
-               if (copy_len > 0) {
-                       enc_rbuf(enc, copy_len, packet);
-               }
-               /* advance read pointer to next pointer */
-               enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
-               /* decrease packet counter */
-               enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
-               /*
-                * Only odd values should be written to ERXRDPTL,
-                * see errata B4 pt.13
-                */
-               rxbuf_rdpt = enc->next_pointer - 1;
-               if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
-                       (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
-                       enc_w16(enc, CTL_REG_ERXRDPTL,
-                               enc_r16(enc, CTL_REG_ERXNDL));
-               } else {
-                       enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
-               }
-               /* read pktcnt */
-               pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
-               if (copy_len == 0) {
-                       (void)enc_r8(enc, CTL_REG_EIR);
-                       enc_reset_rx(enc);
-                       printf("%s: receive copy_len=0\n", enc->dev->name);
-                       continue;
-               }
-               /*
-                * Because net_process_received_packet() might call enc_send(),
-                * we need to release the SPI bus, call
-                * net_process_received_packet(), reclaim the bus.
-                */
-               enc_release_bus(enc);
-               net_process_received_packet(packet, pkt_len);
-               if (enc_claim_bus(enc))
-                       return;
-               (void)enc_r8(enc, CTL_REG_EIR);
-       } while (pkt_cnt);
-       /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
-}
-
-/*
- * Poll for completely received packets.
- */
-static void enc_poll(enc_dev_t *enc)
-{
-       u8 eir_reg;
-       u8 pkt_cnt;
-
-       (void)enc_r8(enc, CTL_REG_ESTAT);
-       eir_reg = enc_r8(enc, CTL_REG_EIR);
-       if (eir_reg & ENC_EIR_TXIF) {
-               /* clear TXIF bit in EIR */
-               enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
-       }
-       /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
-       pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
-       if (pkt_cnt > 0) {
-               if ((eir_reg & ENC_EIR_PKTIF) == 0) {
-                       debug("enc_poll: pkt cnt > 0, but pktif not set\n");
-               }
-               enc_receive(enc);
-               /*
-                * clear PKTIF bit in EIR, this should not need to be done
-                * but it seems like we get problems if we do not
-                */
-               enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
-       }
-       if (eir_reg & ENC_EIR_RXERIF) {
-               printf("%s: rx error\n", enc->dev->name);
-               enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
-       }
-       if (eir_reg & ENC_EIR_TXERIF) {
-               printf("%s: tx error\n", enc->dev->name);
-               enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
-       }
-}
-
-/*
- * Completely Reset the ENC
- */
-static void enc_reset(enc_dev_t *enc)
-{
-       u8 dout[1];
-
-       dout[0] = CMD_SRC;
-       spi_xfer(enc->slave, 8, dout, NULL,
-               SPI_XFER_BEGIN | SPI_XFER_END);
-       /* sleep 1 ms. See errata pt. 2 */
-       udelay(1000);
-}
-
-/*
- * Initialisation data for most of the ENC registers
- */
-static const u16 enc_initdata[] = {
-       /*
-        * Setup the buffer space. The reset values are valid for the
-        * other pointers.
-        *
-        * We shall not write to ERXST, see errata pt. 5. Instead we
-        * have to make sure that ENC_RX_BUS_START is 0.
-        */
-       CTL_REG_ERXSTL, ENC_RX_BUF_START,
-       CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
-       CTL_REG_ERXNDL, ENC_RX_BUF_END,
-       CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
-       CTL_REG_ERDPTL, ENC_RX_BUF_START,
-       CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
-       /*
-        * Set the filter to receive only good-CRC, unicast and broadcast
-        * frames.
-        * Note: some DHCP servers return their answers as broadcasts!
-        * So its unwise to remove broadcast from this. This driver
-        * might incur receiver overruns with packet loss on a broadcast
-        * flooded network.
-        */
-       CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
-
-       /* enable MAC to receive frames */
-       CTL_REG_MACON1,
-               ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
-
-       /* configure pad, tx-crc and duplex */
-       CTL_REG_MACON3,
-               ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
-               ENC_MACON3_FRMLNEN,
-
-       /* Allow infinite deferals if the medium is continously busy */
-       CTL_REG_MACON4, ENC_MACON4_DEFER,
-
-       /* Late collisions occur beyond 63 bytes */
-       CTL_REG_MACLCON2, 63,
-
-       /*
-        * Set (low byte) Non-Back-to_Back Inter-Packet Gap.
-        * Recommended 0x12
-        */
-       CTL_REG_MAIPGL, 0x12,
-
-       /*
-        * Set (high byte) Non-Back-to_Back Inter-Packet Gap.
-        * Recommended 0x0c for half-duplex. Nothing for full-duplex
-        */
-       CTL_REG_MAIPGH, 0x0C,
-
-       /* set maximum frame length */
-       CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
-       CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
-
-       /*
-        * Set MAC back-to-back inter-packet gap.
-        * Recommended 0x12 for half duplex
-        * and 0x15 for full duplex.
-        */
-       CTL_REG_MABBIPG, 0x12,
-
-       /* end of table */
-       0xffff
-};
-
-/*
- * Wait for the XTAL oscillator to become ready
- */
-static int enc_clock_wait(enc_dev_t *enc)
-{
-       uint64_t etime;
-
-       /* one second timeout */
-       etime = get_ticks() + get_tbclk();
-
-       /*
-        * Wait for CLKRDY to become set (i.e., check that we can
-        * communicate with the ENC)
-        */
-       do
-       {
-               if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
-                       return 0;
-       } while (get_ticks() <= etime);
-
-       printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
-       return -1;
-}
-
-/*
- * Write the MAC address into the ENC
- */
-static int enc_write_macaddr(enc_dev_t *enc)
-{
-       unsigned char *p = enc->dev->enetaddr;
-
-       enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
-       enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
-       enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
-       enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
-       enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
-       enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
-       return 0;
-}
-
-/*
- * Setup most of the ENC registers
- */
-static int enc_setup(enc_dev_t *enc)
-{
-       u16 phid1 = 0;
-       u16 phid2 = 0;
-       const u16 *tp;
-
-       /* reset enc struct values */
-       enc->next_pointer = ENC_RX_BUF_START;
-       enc->rx_reset_counter = RX_RESET_COUNTER;
-       enc->bank = 0xff;       /* invalidate current bank in enc28j60 */
-
-       /* verify PHY identification */
-       phid1 = enc_phy_read(enc, PHY_REG_PHID1);
-       phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
-       if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
-               printf("%s: failed to identify PHY. Found %04x:%04x\n",
-                       enc->dev->name, phid1, phid2);
-               return -1;
-       }
-
-       /* now program registers */
-       for (tp = enc_initdata; *tp != 0xffff; tp += 2)
-               enc_w8_retry(enc, tp[0], tp[1], 10);
-
-       /*
-        * Prevent automatic loopback of data beeing transmitted by setting
-        * ENC_PHCON2_HDLDIS
-        */
-       enc_phy_write(enc, PHY_REG_PHCON2, (1<<8));
-
-       /*
-        * LEDs configuration
-        * LEDA: LACFG = 0100 -> display link status
-        * LEDB: LBCFG = 0111 -> display TX & RX activity
-        * STRCH = 1 -> LED pulses
-        */
-       enc_phy_write(enc, PHY_REG_PHLCON, 0x0472);
-
-       /* Reset PDPXMD-bit => half duplex */
-       enc_phy_write(enc, PHY_REG_PHCON1, 0);
-
-       return 0;
-}
-
-/*
- * Check if ENC has been initialized.
- * If not, try to initialize it.
- * Remember initialized state in struct.
- */
-static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
-{
-       if (enc->initstate >= requiredstate)
-               return 0;
-
-       if (enc->initstate < setupdone) {
-               /* Initialize the ENC only */
-               enc_reset(enc);
-               /* if any of functions fails, skip the rest and return an error */
-               if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
-                       return -1;
-               }
-               enc->initstate = setupdone;
-       }
-       /* if that's all we need, return here */
-       if (enc->initstate >= requiredstate)
-               return 0;
-
-       /* now wait for link ready condition */
-       if (enc_phy_link_wait(enc)) {
-               return -1;
-       }
-       enc->initstate = linkready;
-       return 0;
-}
-
-#if defined(CONFIG_CMD_MII)
-/*
- * Read a PHY register.
- *
- * This function is registered with miiphy_register().
- */
-int enc_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
-{
-       u16 value = 0;
-       struct eth_device *dev = eth_get_dev_by_name(bus->name);
-       enc_dev_t *enc;
-
-       if (!dev || phy_adr != 0)
-               return -1;
-
-       enc = dev->priv;
-       if (enc_claim_bus(enc))
-               return -1;
-       if (enc_initcheck(enc, setupdone)) {
-               enc_release_bus(enc);
-               return -1;
-       }
-       value = enc_phy_read(enc, reg);
-       enc_release_bus(enc);
-       return value;
-}
-
-/*
- * Write a PHY register.
- *
- * This function is registered with miiphy_register().
- */
-int enc_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
-                    u16 value)
-{
-       struct eth_device *dev = eth_get_dev_by_name(bus->name);
-       enc_dev_t *enc;
-
-       if (!dev || phy_adr != 0)
-               return -1;
-
-       enc = dev->priv;
-       if (enc_claim_bus(enc))
-               return -1;
-       if (enc_initcheck(enc, setupdone)) {
-               enc_release_bus(enc);
-               return -1;
-       }
-       enc_phy_write(enc, reg, value);
-       enc_release_bus(enc);
-       return 0;
-}
-#endif
-
-/*
- * Write hardware (MAC) address.
- *
- * This function entered into eth_device structure.
- */
-static int enc_write_hwaddr(struct eth_device *dev)
-{
-       enc_dev_t *enc = dev->priv;
-
-       if (enc_claim_bus(enc))
-               return -1;
-       if (enc_initcheck(enc, setupdone)) {
-               enc_release_bus(enc);
-               return -1;
-       }
-       enc_release_bus(enc);
-       return 0;
-}
-
-/*
- * Initialize ENC28J60 for use.
- *
- * This function entered into eth_device structure.
- */
-static int enc_init(struct eth_device *dev, bd_t *bis)
-{
-       enc_dev_t *enc = dev->priv;
-
-       if (enc_claim_bus(enc))
-               return -1;
-       if (enc_initcheck(enc, linkready)) {
-               enc_release_bus(enc);
-               return -1;
-       }
-       /* enable receive */
-       enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
-       enc_release_bus(enc);
-       return 0;
-}
-
-/*
- * Check for received packets.
- *
- * This function entered into eth_device structure.
- */
-static int enc_recv(struct eth_device *dev)
-{
-       enc_dev_t *enc = dev->priv;
-
-       if (enc_claim_bus(enc))
-               return -1;
-       if (enc_initcheck(enc, linkready)) {
-               enc_release_bus(enc);
-               return -1;
-       }
-       /* Check for dead receiver */
-       if (enc->rx_reset_counter > 0)
-               enc->rx_reset_counter--;
-       else
-               enc_reset_rx_call(enc);
-       enc_poll(enc);
-       enc_release_bus(enc);
-       return 0;
-}
-
-/*
- * Send a packet.
- *
- * This function entered into eth_device structure.
- *
- * Should we wait here until we have a Link? Or shall we leave that to
- * protocol retries?
- */
-static int enc_send(
-       struct eth_device *dev,
-       void *packet,
-       int length)
-{
-       enc_dev_t *enc = dev->priv;
-
-       if (enc_claim_bus(enc))
-               return -1;
-       if (enc_initcheck(enc, linkready)) {
-               enc_release_bus(enc);
-               return -1;
-       }
-       /* setup transmit pointers */
-       enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
-       enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
-       enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
-       /* write packet to ENC */
-       enc_wbuf(enc, length, (u8 *) packet, 0x00);
-       /*
-        * Check that the internal transmit logic has not been altered
-        * by excessive collisions. Reset transmitter if so.
-        * See Errata B4 12 and 14.
-        */
-       if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
-               enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
-               enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
-       }
-       enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
-       /* start transmitting */
-       enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
-       enc_release_bus(enc);
-       return 0;
-}
-
-/*
- * Finish use of ENC.
- *
- * This function entered into eth_device structure.
- */
-static void enc_halt(struct eth_device *dev)
-{
-       enc_dev_t *enc = dev->priv;
-
-       if (enc_claim_bus(enc))
-               return;
-       /* Just disable receiver */
-       enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
-       enc_release_bus(enc);
-}
-
-/*
- * This is the only exported function.
- *
- * It may be called several times with different bus:cs combinations.
- */
-int enc28j60_initialize(unsigned int bus, unsigned int cs,
-       unsigned int max_hz, unsigned int mode)
-{
-       struct eth_device *dev;
-       enc_dev_t *enc;
-
-       /* try to allocate, check and clear eth_device object */
-       dev = malloc(sizeof(*dev));
-       if (!dev) {
-               return -1;
-       }
-       memset(dev, 0, sizeof(*dev));
-
-       /* try to allocate, check and clear enc_dev_t object */
-       enc = malloc(sizeof(*enc));
-       if (!enc) {
-               free(dev);
-               return -1;
-       }
-       memset(enc, 0, sizeof(*enc));
-
-       /* try to setup the SPI slave */
-       enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
-       if (!enc->slave) {
-               printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
-               free(enc);
-               free(dev);
-               return -1;
-       }
-
-       enc->dev = dev;
-       /* now fill the eth_device object */
-       dev->priv = enc;
-       dev->init = enc_init;
-       dev->halt = enc_halt;
-       dev->send = enc_send;
-       dev->recv = enc_recv;
-       dev->write_hwaddr = enc_write_hwaddr;
-       sprintf(dev->name, "enc%i.%i", bus, cs);
-       eth_register(dev);
-#if defined(CONFIG_CMD_MII)
-       int retval;
-       struct mii_dev *mdiodev = mdio_alloc();
-       if (!mdiodev)
-               return -ENOMEM;
-       strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-       mdiodev->read = enc_miiphy_read;
-       mdiodev->write = enc_miiphy_write;
-
-       retval = mdio_register(mdiodev);
-       if (retval < 0)
-               return retval;
-#endif
-       return 0;
-}

diff --git a/drivers/net/enc28j60.h b/drivers/net/enc28j60.h
deleted file mode 100644 (file)
index 289e412..0000000
--- a/drivers/net/enc28j60.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * (X) extracted from enc28j60.c
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _enc28j60_h
-#define _enc28j60_h
-
-/*
- * SPI Commands
- *
- * Bits 7-5: Command
- * Bits 4-0: Register
- */
-#define CMD_RCR(x)     (0x00+((x)&0x1f))       /* Read Control Register */
-#define CMD_RBM                0x3a                    /* Read Buffer Memory */
-#define CMD_WCR(x)     (0x40+((x)&0x1f))       /* Write Control Register */
-#define CMD_WBM                0x7a                    /* Write Buffer Memory */
-#define CMD_BFS(x)     (0x80+((x)&0x1f))       /* Bit Field Set */
-#define CMD_BFC(x)     (0xa0+((x)&0x1f))       /* Bit Field Clear */
-#define CMD_SRC                0xff                    /* System Reset Command */
-
-/* NEW: encode (bank number+1) in upper byte */
-
-/* Common Control Registers accessible in all Banks */
-#define CTL_REG_EIE            0x01B
-#define CTL_REG_EIR            0x01C
-#define CTL_REG_ESTAT          0x01D
-#define CTL_REG_ECON2          0x01E
-#define CTL_REG_ECON1          0x01F
-
-/* Control Registers accessible in Bank 0 */
-#define CTL_REG_ERDPTL         0x100
-#define CTL_REG_ERDPTH         0x101
-#define CTL_REG_EWRPTL         0x102
-#define CTL_REG_EWRPTH         0x103
-#define CTL_REG_ETXSTL         0x104
-#define CTL_REG_ETXSTH         0x105
-#define CTL_REG_ETXNDL         0x106
-#define CTL_REG_ETXNDH         0x107
-#define CTL_REG_ERXSTL         0x108
-#define CTL_REG_ERXSTH         0x109
-#define CTL_REG_ERXNDL         0x10A
-#define CTL_REG_ERXNDH         0x10B
-#define CTL_REG_ERXRDPTL       0x10C
-#define CTL_REG_ERXRDPTH       0x10D
-#define CTL_REG_ERXWRPTL       0x10E
-#define CTL_REG_ERXWRPTH       0x10F
-#define CTL_REG_EDMASTL                0x110
-#define CTL_REG_EDMASTH                0x111
-#define CTL_REG_EDMANDL                0x112
-#define CTL_REG_EDMANDH                0x113
-#define CTL_REG_EDMADSTL       0x114
-#define CTL_REG_EDMADSTH       0x115
-#define CTL_REG_EDMACSL                0x116
-#define CTL_REG_EDMACSH                0x117
-
-/* Control Registers accessible in Bank 1 */
-#define CTL_REG_EHT0           0x200
-#define CTL_REG_EHT1           0x201
-#define CTL_REG_EHT2           0x202
-#define CTL_REG_EHT3           0x203
-#define CTL_REG_EHT4           0x204
-#define CTL_REG_EHT5           0x205
-#define CTL_REG_EHT6           0x206
-#define CTL_REG_EHT7           0x207
-#define CTL_REG_EPMM0          0x208
-#define CTL_REG_EPMM1          0x209
-#define CTL_REG_EPMM2          0x20A
-#define CTL_REG_EPMM3          0x20B
-#define CTL_REG_EPMM4          0x20C
-#define CTL_REG_EPMM5          0x20D
-#define CTL_REG_EPMM6          0x20E
-#define CTL_REG_EPMM7          0x20F
-#define CTL_REG_EPMCSL         0x210
-#define CTL_REG_EPMCSH         0x211
-#define CTL_REG_EPMOL          0x214
-#define CTL_REG_EPMOH          0x215
-#define CTL_REG_EWOLIE         0x216
-#define CTL_REG_EWOLIR         0x217
-#define CTL_REG_ERXFCON                0x218
-#define CTL_REG_EPKTCNT                0x219
-
-/* Control Registers accessible in Bank 2 */
-#define CTL_REG_MACON1         0x300
-#define CTL_REG_MACON2         0x301
-#define CTL_REG_MACON3         0x302
-#define CTL_REG_MACON4         0x303
-#define CTL_REG_MABBIPG                0x304
-#define CTL_REG_MAIPGL         0x306
-#define CTL_REG_MAIPGH         0x307
-#define CTL_REG_MACLCON1       0x308
-#define CTL_REG_MACLCON2       0x309
-#define CTL_REG_MAMXFLL                0x30A
-#define CTL_REG_MAMXFLH                0x30B
-#define CTL_REG_MAPHSUP                0x30D
-#define CTL_REG_MICON          0x311
-#define CTL_REG_MICMD          0x312
-#define CTL_REG_MIREGADR       0x314
-#define CTL_REG_MIWRL          0x316
-#define CTL_REG_MIWRH          0x317
-#define CTL_REG_MIRDL          0x318
-#define CTL_REG_MIRDH          0x319
-
-/* Control Registers accessible in Bank 3 */
-#define CTL_REG_MAADR1         0x400
-#define CTL_REG_MAADR0         0x401
-#define CTL_REG_MAADR3         0x402
-#define CTL_REG_MAADR2         0x403
-#define CTL_REG_MAADR5         0x404
-#define CTL_REG_MAADR4         0x405
-#define CTL_REG_EBSTSD         0x406
-#define CTL_REG_EBSTCON                0x407
-#define CTL_REG_EBSTCSL                0x408
-#define CTL_REG_EBSTCSH                0x409
-#define CTL_REG_MISTAT         0x40A
-#define CTL_REG_EREVID         0x412
-#define CTL_REG_ECOCON         0x415
-#define CTL_REG_EFLOCON                0x417
-#define CTL_REG_EPAUSL         0x418
-#define CTL_REG_EPAUSH         0x419
-
-/* PHY Register */
-#define PHY_REG_PHCON1         0x00
-#define PHY_REG_PHSTAT1                0x01
-#define PHY_REG_PHID1          0x02
-#define PHY_REG_PHID2          0x03
-#define PHY_REG_PHCON2         0x10
-#define PHY_REG_PHSTAT2                0x11
-#define PHY_REG_PHLCON         0x14
-
-/* Receive Filter Register (ERXFCON) bits */
-#define ENC_RFR_UCEN           0x80
-#define ENC_RFR_ANDOR          0x40
-#define ENC_RFR_CRCEN          0x20
-#define ENC_RFR_PMEN           0x10
-#define ENC_RFR_MPEN           0x08
-#define ENC_RFR_HTEN           0x04
-#define ENC_RFR_MCEN           0x02
-#define ENC_RFR_BCEN           0x01
-
-/* ECON1 Register Bits */
-#define ENC_ECON1_TXRST                0x80
-#define ENC_ECON1_RXRST                0x40
-#define ENC_ECON1_DMAST                0x20
-#define ENC_ECON1_CSUMEN       0x10
-#define ENC_ECON1_TXRTS                0x08
-#define ENC_ECON1_RXEN         0x04
-#define ENC_ECON1_BSEL1                0x02
-#define ENC_ECON1_BSEL0                0x01
-
-/* ECON2 Register Bits */
-#define ENC_ECON2_AUTOINC      0x80
-#define ENC_ECON2_PKTDEC       0x40
-#define ENC_ECON2_PWRSV                0x20
-#define ENC_ECON2_VRPS         0x08
-
-/* EIR Register Bits */
-#define ENC_EIR_PKTIF          0x40
-#define ENC_EIR_DMAIF          0x20
-#define ENC_EIR_LINKIF         0x10
-#define ENC_EIR_TXIF           0x08
-#define ENC_EIR_WOLIF          0x04
-#define ENC_EIR_TXERIF         0x02
-#define ENC_EIR_RXERIF         0x01
-
-/* ESTAT Register Bits */
-#define ENC_ESTAT_INT          0x80
-#define ENC_ESTAT_LATECOL      0x10
-#define ENC_ESTAT_RXBUSY       0x04
-#define ENC_ESTAT_TXABRT       0x02
-#define ENC_ESTAT_CLKRDY       0x01
-
-/* EIE Register Bits */
-#define ENC_EIE_INTIE          0x80
-#define ENC_EIE_PKTIE          0x40
-#define ENC_EIE_DMAIE          0x20
-#define ENC_EIE_LINKIE         0x10
-#define ENC_EIE_TXIE           0x08
-#define ENC_EIE_WOLIE          0x04
-#define ENC_EIE_TXERIE         0x02
-#define ENC_EIE_RXERIE         0x01
-
-/* MACON1 Register Bits */
-#define ENC_MACON1_LOOPBK      0x10
-#define ENC_MACON1_TXPAUS      0x08
-#define ENC_MACON1_RXPAUS      0x04
-#define ENC_MACON1_PASSALL     0x02
-#define ENC_MACON1_MARXEN      0x01
-
-/* MACON2 Register Bits */
-#define ENC_MACON2_MARST       0x80
-#define ENC_MACON2_RNDRST      0x40
-#define ENC_MACON2_MARXRST     0x08
-#define ENC_MACON2_RFUNRST     0x04
-#define ENC_MACON2_MATXRST     0x02
-#define ENC_MACON2_TFUNRST     0x01
-
-/* MACON3 Register Bits */
-#define ENC_MACON3_PADCFG2     0x80
-#define ENC_MACON3_PADCFG1     0x40
-#define ENC_MACON3_PADCFG0     0x20
-#define ENC_MACON3_TXCRCEN     0x10
-#define ENC_MACON3_PHDRLEN     0x08
-#define ENC_MACON3_HFRMEN      0x04
-#define ENC_MACON3_FRMLNEN     0x02
-#define ENC_MACON3_FULDPX      0x01
-
-/* MACON4 Register Bits */
-#define ENC_MACON4_DEFER       0x40
-
-/* MICMD Register Bits */
-#define ENC_MICMD_MIISCAN      0x02
-#define ENC_MICMD_MIIRD                0x01
-
-/* MISTAT Register Bits */
-#define ENC_MISTAT_NVALID      0x04
-#define ENC_MISTAT_SCAN                0x02
-#define ENC_MISTAT_BUSY                0x01
-
-/* PHID1 and PHID2 values */
-#define ENC_PHID1_VALUE                0x0083
-#define ENC_PHID2_VALUE                0x1400
-#define ENC_PHID2_MASK         0xFC00
-
-/* PHCON1 values */
-#define        ENC_PHCON1_PDPXMD       0x0100
-
-/* PHSTAT1 values */
-#define        ENC_PHSTAT1_LLSTAT      0x0004
-
-/* PHSTAT2 values */
-#define        ENC_PHSTAT2_LSTAT       0x0400
-#define        ENC_PHSTAT2_DPXSTAT     0x0200
-
-#endif

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e62aefcd0d6cadf257dd56807983c5a5b830f9e4..fe370bf728975321d7cdb09a943d9290977fb044 100644 (file)
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -915,7 +915,7 @@ static int macb_recv(struct eth_device *netdev)
                if (length >= 0) {
                        net_process_received_packet(packet, length);
                        reclaim_rx_buffers(macb, macb->next_rx_tail);
-               } else if (length < 0) {
+               } else {
                        return length;
                }
        }

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e3d31a560d54af4697cf8d48d678e878b4dd3fae..62c0c2be0626d36608893467cfd406d76f4db6c5 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5598,6 +5598,10 @@ static int mvpp2_base_bind(struct udevice *parent)
                id += base_id_add;
 
                name = calloc(1, 16);
+               if (!name) {
+                       free(plat);
+                       return -ENOMEM;
+               }
                sprintf(name, "mvpp2-%d", id);
 
                /* Create child device UCLASS_ETH and bind it */

diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644 (file)
index 0000000..a13b331
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,12 @@
+menuconfig FSL_PFE
+       bool "NXP PFE Ethernet driver"
+       help
+         This driver provides support for NXP's Packet Forwarding Engine.
+
+if FSL_PFE
+
+config SYS_FSL_PFE_ADDR
+       hex "PFE base address"
+       default 0x04000000
+
+endif

diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644 (file)
index 0000000..6b5248f
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,12 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe_cmd.o     \
+        pfe_driver.o   \
+        pfe_eth.o      \
+        pfe_firmware.o \
+        pfe_hw.o       \
+        pfe_mdio.o

diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644 (file)
index 0000000..822dc0f
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include <net/pfe_eth/pfe_eth.h>
+
+static inline void pfe_command_help(void)
+{
+       printf("Usage: pfe [pe | status | expt ] <options>\n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+       if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+               if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+                       int i;
+                       int num;
+                       int id;
+                       u32 addr;
+                       u32 size;
+                       u32 val;
+
+                       if (argc == 7) {
+                               num = simple_strtoul(argv[6], NULL, 0);
+                       } else if (argc == 6) {
+                               num = 1;
+                       } else {
+                               printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
+                               return;
+                       }
+
+                       id = simple_strtoul(argv[4], NULL, 0);
+                       addr = simple_strtoul(argv[5], NULL, 16);
+                       size = 4;
+
+                       for (i = 0; i < num; i++, addr += 4) {
+                               val = pe_pmem_read(id, addr, size);
+                               val = be32_to_cpu(val);
+                               if (!(i & 3))
+                                       printf("%08x: ", addr);
+                               printf("%08x%s", val, i == num - 1 || (i & 3)
+                                      == 3 ? "\n" : " ");
+                       }
+
+               } else {
+                       printf("Usage: pfe pe pmem read <parameters>\n");
+               }
+       } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+               if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+                       int i;
+                       int num;
+                       int id;
+                       u32 addr;
+                       u32 size;
+                       u32 val;
+
+                       if (argc == 7) {
+                               num = simple_strtoul(argv[6], NULL, 0);
+                       } else if (argc == 6) {
+                               num = 1;
+                       } else {
+                               printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
+                               return;
+                       }
+
+                       id = simple_strtoul(argv[4], NULL, 0);
+                       addr = simple_strtoul(argv[5], NULL, 16);
+                       size = 4;
+
+                       for (i = 0; i < num; i++, addr += 4) {
+                               val = pe_dmem_read(id, addr, size);
+                               val = be32_to_cpu(val);
+                               if (!(i & 3))
+                                       printf("%08x: ", addr);
+                               printf("%08x%s", val, i == num - 1 || (i & 3)
+                                      == 3 ? "\n" : " ");
+                       }
+
+               } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+                       int id;
+                       u32 val;
+                       u32 addr;
+                       u32 size;
+
+                       if (argc != 7) {
+                               printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
+                               return;
+                       }
+
+                       id = simple_strtoul(argv[4], NULL, 0);
+                       val = simple_strtoul(argv[5], NULL, 16);
+                       val = cpu_to_be32(val);
+                       addr = simple_strtoul(argv[6], NULL, 16);
+                       size = 4;
+                       pe_dmem_write(id, val, addr, size);
+               } else {
+                       printf("Usage: pfe pe dmem [read | write] <parameters>\n");
+               }
+       } else if (argc >= 3 && strcmp(argv[2], "lmem") == 0) {
+               if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+                       int i;
+                       int num;
+                       u32 val;
+                       u32 offset;
+
+                       if (argc == 6) {
+                               num = simple_strtoul(argv[5], NULL, 0);
+                       } else if (argc == 5) {
+                               num = 1;
+                       } else {
+                               printf("Usage: pfe pe lmem read <offset> [<num>]\n");
+                               return;
+                       }
+
+                       offset = simple_strtoul(argv[4], NULL, 16);
+
+                       for (i = 0; i < num; i++, offset += 4) {
+                               pe_lmem_read(&val, 4, offset);
+                               val = be32_to_cpu(val);
+                               printf("%08x%s", val, i == num - 1 || (i & 7)
+                                      == 7 ? "\n" : " ");
+                       }
+
+               } else if (argc >= 4 && strcmp(argv[3], "write") == 0)  {
+                       u32 val;
+                       u32 offset;
+
+                       if (argc != 6) {
+                               printf("Usage: pfe pe lmem write <val> <offset>\n");
+                               return;
+                       }
+
+                       val = simple_strtoul(argv[4], NULL, 16);
+                       val = cpu_to_be32(val);
+                       offset = simple_strtoul(argv[5], NULL, 16);
+                       pe_lmem_write(&val, 4, offset);
+               } else {
+                       printf("Usage: pfe pe lmem [read | write] <parameters>\n");
+               }
+       } else {
+               if (strcmp(argv[2], "help") != 0)
+                       printf("Unknown option: %s\n", argv[2]);
+
+               printf("Usage: pfe pe <parameters>\n");
+       }
+}
+
+#define NUM_QUEUES             16
+
+/*
+ * qm_read_drop_stat
+ * This function is used to read the drop statistics from the TMU
+ * hw drop counter.  Since the hw counter is always cleared afer
+ * reading, this function maintains the previous drop count, and
+ * adds the new value to it.  That value can be retrieved by
+ * passing a pointer to it with the total_drops arg.
+ *
+ * @param tmu           TMU number (0 - 3)
+ * @param queue         queue number (0 - 15)
+ * @param total_drops   pointer to location to store total drops (or NULL)
+ * @param do_reset      if TRUE, clear total drops after updating
+ *
+ */
+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
+{
+       static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
+       u32 val;
+
+       writel((tmu << 8) | queue, TMU_TEQ_CTRL);
+       writel((tmu << 8) | queue, TMU_LLM_CTRL);
+       val = readl(TMU_TEQ_DROP_STAT);
+       qtotal[tmu][queue] += val;
+       if (total_drops)
+               *total_drops = qtotal[tmu][queue];
+       if (do_reset)
+               qtotal[tmu][queue] = 0;
+       return val;
+}
+
+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
+{
+       ssize_t len = 0;
+       u32 drops;
+
+       printf("%d-%02d, ", tmu, queue);
+
+       drops = qm_read_drop_stat(tmu, queue, NULL, 0);
+
+       /* Select queue */
+       writel((tmu << 8) | queue, TMU_TEQ_CTRL);
+       writel((tmu << 8) | queue, TMU_LLM_CTRL);
+
+       printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
+              drops, readl(TMU_TEQ_TRANS_STAT),
+              readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
+              readl(TMU_LLM_QUE_DROPCNT));
+
+       return len;
+}
+
+static ssize_t tmu_queues(char *buf, int tmu)
+{
+       ssize_t len = 0;
+       int queue;
+
+       for (queue = 0; queue < 16; queue++)
+               len += tmu_queue_stats(buf + len, tmu, queue);
+
+       return len;
+}
+
+static inline void hif_status(void)
+{
+       printf("hif:\n");
+
+       printf("  tx curr bd:    %x\n", readl(HIF_TX_CURR_BD_ADDR));
+       printf("  tx status:     %x\n", readl(HIF_TX_STATUS));
+       printf("  tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
+
+       printf("  rx curr bd:    %x\n", readl(HIF_RX_CURR_BD_ADDR));
+       printf("  rx status:     %x\n", readl(HIF_RX_STATUS));
+       printf("  rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
+
+       printf("hif nocopy:\n");
+
+       printf("  tx curr bd:    %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
+       printf("  tx status:     %x\n", readl(HIF_NOCPY_TX_STATUS));
+       printf("  tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
+
+       printf("  rx curr bd:    %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
+       printf("  rx status:     %x\n", readl(HIF_NOCPY_RX_STATUS));
+       printf("  rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
+}
+
+static void gpi(int id, void *base)
+{
+       u32 val;
+
+       printf("%s%d:\n", __func__, id);
+
+       printf("  tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
+       val = readl(base + GPI_FIFO_DEBUG);
+       printf("  tx pkts:        %x\n", (val >> 23) & 0x3f);
+       printf("  rx pkts:        %x\n", (val >> 18) & 0x3f);
+       printf("  tx bytes:       %x\n", (val >> 9) & 0x1ff);
+       printf("  rx bytes:       %x\n", (val >> 0) & 0x1ff);
+       printf("  overrun:        %x\n", readl(base + GPI_OVERRUN_DROPCNT));
+}
+
+static void  bmu(int id, void *base)
+{
+       printf("%s%d:\n", __func__, id);
+
+       printf("  buf size:  %x\n", (1 << readl(base + BMU_BUF_SIZE)));
+       printf("  buf count: %x\n", readl(base + BMU_BUF_CNT));
+       printf("  buf rem:   %x\n", readl(base + BMU_REM_BUF_CNT));
+       printf("  buf curr:  %x\n", readl(base + BMU_CURR_BUF_CNT));
+       printf("  free err:  %x\n", readl(base + BMU_FREE_ERR_ADDR));
+}
+
+#define        PESTATUS_ADDR_CLASS     0x800
+#define PEMBOX_ADDR_CLASS      0x890
+#define        PESTATUS_ADDR_TMU       0x80
+#define PEMBOX_ADDR_TMU                0x290
+#define        PESTATUS_ADDR_UTIL      0x0
+
+static void pfe_pe_status(int argc, char * const argv[])
+{
+       int do_clear = 0;
+       u32 id;
+       u32 dmem_addr;
+       u32 cpu_state;
+       u32 activity_counter;
+       u32 rx;
+       u32 tx;
+       u32 drop;
+       char statebuf[5];
+       u32 class_debug_reg = 0;
+
+       if (argc == 4 && strcmp(argv[3], "clear") == 0)
+               do_clear = 1;
+
+       for (id = CLASS0_ID; id < MAX_PE; id++) {
+               if (id >= TMU0_ID) {
+                       if (id == TMU2_ID)
+                               continue;
+                       if (id == TMU0_ID)
+                               printf("tmu:\n");
+                       dmem_addr = PESTATUS_ADDR_TMU;
+               } else {
+                       if (id == CLASS0_ID)
+                               printf("class:\n");
+                       dmem_addr = PESTATUS_ADDR_CLASS;
+                       class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
+               }
+
+               cpu_state = pe_dmem_read(id, dmem_addr, 4);
+               dmem_addr += 4;
+               memcpy(statebuf, (char *)&cpu_state, 4);
+               statebuf[4] = '\0';
+               activity_counter = pe_dmem_read(id, dmem_addr, 4);
+               dmem_addr += 4;
+               rx = pe_dmem_read(id, dmem_addr, 4);
+               if (do_clear)
+                       pe_dmem_write(id, 0, dmem_addr, 4);
+               dmem_addr += 4;
+               tx = pe_dmem_read(id, dmem_addr, 4);
+               if (do_clear)
+                       pe_dmem_write(id, 0, dmem_addr, 4);
+               dmem_addr += 4;
+               drop = pe_dmem_read(id, dmem_addr, 4);
+               if (do_clear)
+                       pe_dmem_write(id, 0, dmem_addr, 4);
+               dmem_addr += 4;
+
+               if (id >= TMU0_ID) {
+                       printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
+                              id - TMU0_ID, statebuf,
+                              cpu_to_be32(activity_counter),
+                              cpu_to_be32(rx), cpu_to_be32(tx));
+               } else {
+                       printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
+                              id - CLASS0_ID, class_debug_reg & 0xFFFF,
+                              class_debug_reg >> 16,
+                              statebuf, cpu_to_be32(activity_counter),
+                              cpu_to_be32(rx), cpu_to_be32(tx),
+                              cpu_to_be32(drop));
+               }
+       }
+}
+
+static void pfe_command_status(int argc, char * const argv[])
+{
+       if (argc >= 3 && strcmp(argv[2], "pe") == 0) {
+               pfe_pe_status(argc, argv);
+       } else if (argc == 3 && strcmp(argv[2], "bmu") == 0) {
+               bmu(1, BMU1_BASE_ADDR);
+               bmu(2, BMU2_BASE_ADDR);
+       } else if (argc == 3 && strcmp(argv[2], "hif") == 0) {
+               hif_status();
+       } else if (argc == 3 && strcmp(argv[2], "gpi") == 0) {
+               gpi(0, EGPI1_BASE_ADDR);
+               gpi(1, EGPI2_BASE_ADDR);
+               gpi(3, HGPI_BASE_ADDR);
+       } else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0) {
+               tmu_queues(NULL, 0);
+       } else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0) {
+               tmu_queues(NULL, 1);
+       } else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0) {
+               tmu_queues(NULL, 3);
+       } else {
+               printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
+       }
+}
+
+#define EXPT_DUMP_ADDR 0x1fa8
+#define EXPT_REG_COUNT 20
+static const char *register_names[EXPT_REG_COUNT] = {
+               "  pc", "ECAS", " EID", "  ED",
+               "  sp", "  r1", "  r2", "  r3",
+               "  r4", "  r5", "  r6", "  r7",
+               "  r8", "  r9", " r10", " r11",
+               " r12", " r13", " r14", " r15"
+};
+
+static void pfe_command_expt(int argc, char * const argv[])
+{
+       unsigned int id, i, val, addr;
+
+       if (argc == 3) {
+               id = simple_strtoul(argv[2], NULL, 0);
+               addr = EXPT_DUMP_ADDR;
+               printf("Exception information for PE %d:\n", id);
+               for (i = 0; i < EXPT_REG_COUNT; i++) {
+                       val = pe_dmem_read(id, addr, 4);
+                       val = be32_to_cpu(val);
+                       printf("%s:%08x%s", register_names[i], val,
+                              (i & 3) == 3 ? "\n" : " ");
+                       addr += 4;
+               }
+       } else {
+               printf("Usage: pfe expt <id>\n");
+       }
+}
+
+#ifdef PFE_RESET_WA
+/*This function sends a dummy packet to HIF through TMU3 */
+static void send_dummy_pkt_to_hif(void)
+{
+       u32 buf;
+       static u32 dummy_pkt[] =  {
+               0x4200800a, 0x01000003, 0x00018100, 0x00000000,
+               0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
+               0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
+               0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
+               0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
+
+       /*Allocate BMU2 buffer */
+       buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
+
+       debug("Sending a dummy pkt to HIF %x\n", buf);
+       buf += 0x80;
+       memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
+
+       /*Write length and pkt to TMU*/
+       writel(0x03000042, TMU_PHY_INQ_PKTPTR);
+       writel(buf, TMU_PHY_INQ_PKTINFO);
+}
+
+static void pfe_command_stop(int argc, char * const argv[])
+{
+       int pfe_pe_id, hif_stop_loop = 10;
+       u32 rx_status;
+
+       printf("Stopping PFE...\n");
+
+       /*Mark all descriptors as LAST_BD */
+       hif_rx_desc_disable();
+
+       /*If HIF Rx BDP is busy send a dummy packet */
+       do {
+               rx_status = readl(HIF_RX_STATUS);
+               if (rx_status & BDP_CSR_RX_DMA_ACTV)
+                       send_dummy_pkt_to_hif();
+               udelay(10);
+       } while (hif_stop_loop--);
+
+       if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
+               printf("Unable to stop HIF\n");
+
+       /*Disable Class PEs */
+       for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
+               /*Inform PE to stop */
+               pe_dmem_write(pfe_pe_id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
+               udelay(10);
+
+               /*Read status */
+               if (!pe_dmem_read(pfe_pe_id, PEMBOX_ADDR_CLASS + 4, 4))
+                       printf("Failed to stop PE%d\n", pfe_pe_id);
+       }
+
+       /*Disable TMU PEs */
+       for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
+               if (pfe_pe_id == TMU2_ID)
+                       continue;
+
+               /*Inform PE to stop */
+               pe_dmem_write(pfe_pe_id, 1, PEMBOX_ADDR_TMU, 4);
+               udelay(10);
+
+               /*Read status */
+               if (!pe_dmem_read(pfe_pe_id, PEMBOX_ADDR_TMU + 4, 4))
+                       printf("Failed to stop PE%d\n", pfe_pe_id);
+       }
+}
+#endif
+
+static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
+                      char * const argv[])
+{
+       if (argc == 1 || strcmp(argv[1], "help") == 0) {
+               pfe_command_help();
+               return CMD_RET_SUCCESS;
+       }
+
+       if (strcmp(argv[1], "pe") == 0) {
+               pfe_command_pe(argc, argv);
+       } else if (strcmp(argv[1], "status") == 0) {
+               pfe_command_status(argc, argv);
+       } else if (strcmp(argv[1], "expt") == 0) {
+               pfe_command_expt(argc, argv);
+#ifdef PFE_RESET_WA
+       } else if (strcmp(argv[1], "stop") == 0) {
+               pfe_command_stop(argc, argv);
+#endif
+       } else {
+               printf("Unknown option: %s\n", argv[1]);
+               pfe_command_help();
+               return CMD_RET_FAILURE;
+       }
+       return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+       pfe,    7,      1,      pfe_command,
+       "Performs PFE lib utility functions",
+       "Usage:\n"
+       "pfe <options>"
+);

diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
new file mode 100644 (file)
index 0000000..a9991f5
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe_firmware.h>
+
+static struct tx_desc_s *g_tx_desc;
+static struct rx_desc_s *g_rx_desc;
+
+/*
+ * HIF Rx interface function
+ * Reads the rx descriptor from the current location (rx_to_read).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
+ *
+ * @return -1 if no packet, else return length of packet.
+ */
+int pfe_recv(uchar **pkt_ptr, int *phy_port)
+{
+       struct rx_desc_s *rx_desc = g_rx_desc;
+       struct buf_desc *bd;
+       int len = 0;
+
+       struct hif_header_s *hif_header;
+
+       bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+       if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+               return len; /* No pending Rx packet */
+
+       /* this len include hif_header(8 bytes) */
+       len = readl(&bd->ctrl) & 0xFFFF;
+
+       hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
+
+       /* Get the receive port info from the packet */
+       debug("Pkt received:");
+       debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+             hif_header, len, hif_header->port_no, readl(&bd->status));
+#ifdef DEBUG
+       {
+               int i;
+               unsigned char *p = (unsigned char *)hif_header;
+
+               for (i = 0; i < len; i++) {
+                       if (!(i % 16))
+                               printf("\n");
+                       printf(" %02x", p[i]);
+               }
+               printf("\n");
+       }
+#endif
+
+       *pkt_ptr = (uchar *)(hif_header + 1);
+       *phy_port = hif_header->port_no;
+       len -= sizeof(struct hif_header_s);
+
+       return len;
+}
+
+/*
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
+ * locations
+ * if success, moves the rx_to_read to next location.
+ */
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+       struct rx_desc_s *rx_desc = g_rx_desc;
+       struct buf_desc *bd;
+
+       debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+             rx_desc->rx_to_read);
+
+       bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+       /* reset the control field */
+       writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+                   | BD_CTRL_DIR), &bd->ctrl);
+       writel(0, &bd->status);
+
+       debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
+             readl(&bd->ctrl));
+
+       /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
+        * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
+        * In idle state (ie., no rx pkt), BDP will not fetch
+        * the descriptor even if strobe is given.
+        */
+       writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+       /* increment the rx_to_read index to next location */
+       rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
+                              & (rx_desc->rx_ring_size - 1);
+
+       debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
+
+       return 0;
+}
+
+/*
+ * HIF Tx interface function
+ * This function sends a single packet to PFE from HIF interface.
+ * - No interrupt indication on tx completion.
+ * - Data is copied to tx buffers before tx descriptor is updated
+ *   and TX DMA is enabled.
+ *
+ * @param[in] phy_port Phy port number to send out this packet
+ * @param[in] data     Pointer to the data
+ * @param[in] length   Length of the ethernet packet to be transferred.
+ *
+ * @return -1 if tx Q is full, else returns the tx location where the pkt is
+ * placed.
+ */
+int pfe_send(int phy_port, void *data, int length)
+{
+       struct tx_desc_s *tx_desc = g_tx_desc;
+       struct buf_desc *bd;
+       struct hif_header_s hif_header;
+       u8 *tx_buf_va;
+
+       debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
+             data, length, tx_desc->tx_base, tx_desc->tx_to_send);
+
+       bd = tx_desc->tx_base + tx_desc->tx_to_send;
+
+       /* check queue-full condition */
+       if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+               return -1;
+
+       /* PFE checks for min pkt size */
+       if (length < MIN_PKT_SIZE)
+               length = MIN_PKT_SIZE;
+
+       tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
+       debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
+             readl(&bd->data));
+
+       /* Fill the gemac/phy port number to send this packet out */
+       memset(&hif_header, 0, sizeof(struct hif_header_s));
+       hif_header.port_no = phy_port;
+
+       memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
+       memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
+       length += sizeof(struct hif_header_s);
+
+#ifdef DEBUG
+       {
+               int i;
+               unsigned char *p = (unsigned char *)tx_buf_va;
+
+               for (i = 0; i < length; i++) {
+                       if (!(i % 16))
+                               printf("\n");
+                       printf("%02x ", p[i]);
+               }
+       }
+#endif
+
+       debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
+             readl(&bd->ctrl));
+
+       /* fill the tx desc */
+       writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
+              &bd->ctrl);
+       writel(0, &bd->status);
+
+       writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
+
+       udelay(100);
+
+       return tx_desc->tx_to_send;
+}
+
+/*
+ * HIF function to check the Tx done
+ *  This function will check the tx done indication of the current tx_to_send
+ *  locations
+ *  if success, moves the tx_to_send to next location.
+ *
+ * @return -1 if TX ownership bit is not cleared by hw.
+ * else on success (tx done completion) return zero.
+ */
+int pfe_tx_done(void)
+{
+       struct tx_desc_s *tx_desc = g_tx_desc;
+       struct buf_desc *bd;
+
+       debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
+             tx_desc->tx_to_send);
+
+       bd = tx_desc->tx_base + tx_desc->tx_to_send;
+
+       /* check queue-full condition */
+       if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+               return -1;
+
+       /* reset the control field */
+       writel(0, &bd->ctrl);
+       writel(0, &bd->status);
+
+       debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
+             readl(&bd->ctrl));
+
+       /* increment the txtosend index to next location */
+       tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
+                              & (tx_desc->tx_ring_size - 1);
+
+       debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
+
+       return 0;
+}
+
+/*
+ * Helper function to dump Rx descriptors.
+ */
+static inline void hif_rx_desc_dump(void)
+{
+       struct buf_desc *bd_va;
+       int i;
+       struct rx_desc_s *rx_desc;
+
+       if (!g_rx_desc) {
+               printf("%s: HIF Rx desc no init\n", __func__);
+               return;
+       }
+
+       rx_desc = g_rx_desc;
+       bd_va = rx_desc->rx_base;
+
+       debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
+             rx_desc->rx_base_pa);
+       for (i = 0; i < rx_desc->rx_ring_size; i++) {
+               debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
+                     readl(&bd_va->status),
+                     readl(&bd_va->ctrl),
+                     readl(&bd_va->data),
+                     readl(&bd_va->next));
+               bd_va++;
+       }
+}
+
+/*
+ * This function mark all Rx descriptors as LAST_BD.
+ */
+void hif_rx_desc_disable(void)
+{
+       int i;
+       struct rx_desc_s *rx_desc;
+       struct buf_desc *bd_va;
+
+       if (!g_rx_desc) {
+               printf("%s: HIF Rx desc not initialized\n", __func__);
+               return;
+       }
+
+       rx_desc = g_rx_desc;
+       bd_va = rx_desc->rx_base;
+
+       for (i = 0; i < rx_desc->rx_ring_size; i++) {
+               writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
+               bd_va++;
+       }
+}
+
+/*
+ * HIF Rx Desc initialization function.
+ */
+static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
+{
+       u32 ctrl;
+       struct buf_desc *bd_va;
+       struct buf_desc *bd_pa;
+       struct rx_desc_s *rx_desc;
+       u32 rx_buf_pa;
+       int i;
+
+       /* sanity check */
+       if (g_rx_desc) {
+               printf("%s: HIF Rx desc re-init request\n", __func__);
+               return 0;
+       }
+
+       rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
+       if (!rx_desc) {
+               printf("%s: Memory allocation failure\n", __func__);
+               return -ENOMEM;
+       }
+       memset(rx_desc, 0, sizeof(struct rx_desc_s));
+
+       /* init: Rx ring buffer */
+       rx_desc->rx_ring_size = HIF_RX_DESC_NT;
+
+       /* NOTE: must be 64bit aligned  */
+       bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
+                + RX_BD_BASEADDR);
+       bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
+                                   + RX_BD_BASEADDR);
+
+       rx_desc->rx_base = bd_va;
+       rx_desc->rx_base_pa = (unsigned long)bd_pa;
+
+       rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
+
+       debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
+             __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
+             rx_desc->rx_ring_size);
+
+       memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
+
+       ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+
+       for (i = 0; i < rx_desc->rx_ring_size; i++) {
+               writel((unsigned long)(bd_pa + 1), &bd_va->next);
+               writel(ctrl, &bd_va->ctrl);
+               writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
+               bd_va++;
+               bd_pa++;
+       }
+       --bd_va;
+       writel((u32)rx_desc->rx_base_pa, &bd_va->next);
+
+       writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
+       writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+       g_rx_desc = rx_desc;
+
+       return 0;
+}
+
+/*
+ * Helper function to dump Tx Descriptors.
+ */
+static inline void hif_tx_desc_dump(void)
+{
+       struct tx_desc_s *tx_desc;
+       int i;
+       struct buf_desc *bd_va;
+
+       if (!g_tx_desc) {
+               printf("%s: HIF Tx desc no init\n", __func__);
+               return;
+       }
+
+       tx_desc = g_tx_desc;
+       bd_va = tx_desc->tx_base;
+
+       debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
+             tx_desc->tx_base_pa);
+
+       for (i = 0; i < tx_desc->tx_ring_size; i++)
+               bd_va++;
+}
+
+/*
+ * HIF Tx descriptor initialization function.
+ */
+static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
+{
+       struct buf_desc *bd_va;
+       struct buf_desc *bd_pa;
+       int i;
+       struct tx_desc_s *tx_desc;
+       u32 tx_buf_pa;
+
+       /* sanity check */
+       if (g_tx_desc) {
+               printf("%s: HIF Tx desc re-init request\n", __func__);
+               return 0;
+       }
+
+       tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
+       if (!tx_desc) {
+               printf("%s:%d:Memory allocation failure\n", __func__,
+                      __LINE__);
+               return -ENOMEM;
+       }
+       memset(tx_desc, 0, sizeof(struct tx_desc_s));
+
+       /* init: Tx ring buffer */
+       tx_desc->tx_ring_size = HIF_TX_DESC_NT;
+
+       /* NOTE: must be 64bit aligned  */
+       bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
+                + TX_BD_BASEADDR);
+       bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
+                                   + TX_BD_BASEADDR);
+
+       tx_desc->tx_base_pa = (unsigned long)bd_pa;
+       tx_desc->tx_base = bd_va;
+
+       debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
+             __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
+             tx_desc->tx_ring_size);
+
+       memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
+
+       tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
+
+       for (i = 0; i < tx_desc->tx_ring_size; i++) {
+               writel((unsigned long)(bd_pa + 1), &bd_va->next);
+               writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
+               bd_va++;
+               bd_pa++;
+       }
+       --bd_va;
+       writel((u32)tx_desc->tx_base_pa, &bd_va->next);
+
+       writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
+
+       g_tx_desc = tx_desc;
+
+       return 0;
+}
+
+/*
+ * PFE/Class initialization.
+ */
+static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
+{
+       struct class_cfg class_cfg = {
+               .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
+                                       ROUTE_TABLE_BASEADDR,
+               .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
+       };
+
+       class_init(&class_cfg);
+
+       debug("class init complete\n");
+}
+
+/*
+ * PFE/TMU initialization.
+ */
+static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
+{
+       struct tmu_cfg tmu_cfg = {
+               .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
+                                + TMU_LLM_BASEADDR,
+               .llm_queue_len = TMU_LLM_QUEUE_LEN,
+       };
+
+       tmu_init(&tmu_cfg);
+
+       debug("tmu init complete\n");
+}
+
+/*
+ * PFE/BMU (both BMU1 & BMU2) initialization.
+ */
+static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
+{
+       struct bmu_cfg bmu1_cfg = {
+               .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
+                                               BMU1_LMEM_BASEADDR),
+               .count = BMU1_BUF_COUNT,
+               .size = BMU1_BUF_SIZE,
+       };
+
+       struct bmu_cfg bmu2_cfg = {
+               .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
+               .count = BMU2_BUF_COUNT,
+               .size = BMU2_BUF_SIZE,
+       };
+
+       bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
+       debug("bmu1 init: done\n");
+
+       bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
+       debug("bmu2 init: done\n");
+}
+
+/*
+ * PFE/GPI initialization function.
+ *  - egpi1, egpi2, egpi3, hgpi
+ */
+static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
+{
+       struct gpi_cfg egpi1_cfg = {
+               .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
+               .tmlf_txthres = EGPI1_TMLF_TXTHRES,
+               .aseq_len = EGPI1_ASEQ_LEN,
+       };
+
+       struct gpi_cfg egpi2_cfg = {
+               .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
+               .tmlf_txthres = EGPI2_TMLF_TXTHRES,
+               .aseq_len = EGPI2_ASEQ_LEN,
+       };
+
+       struct gpi_cfg hgpi_cfg = {
+               .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
+               .tmlf_txthres = HGPI_TMLF_TXTHRES,
+               .aseq_len = HGPI_ASEQ_LEN,
+       };
+
+       gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
+       debug("GPI1 init complete\n");
+
+       gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
+       debug("GPI2 init complete\n");
+
+       gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
+       debug("HGPI init complete\n");
+}
+
+/*
+ * PFE/HIF initialization function.
+ */
+static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
+{
+       int ret = 0;
+
+       hif_tx_disable();
+       hif_rx_disable();
+
+       ret = hif_tx_desc_init(pfe_addr);
+       if (ret)
+               return ret;
+       ret = hif_rx_desc_init(pfe_addr);
+       if (ret)
+               return ret;
+
+       hif_init();
+
+       hif_tx_enable();
+       hif_rx_enable();
+
+       hif_rx_desc_dump();
+       hif_tx_desc_dump();
+
+       debug("HIF init complete\n");
+       return ret;
+}
+
+/*
+ * PFE initialization
+ * - Firmware loading (CLASS-PE and TMU-PE)
+ * - BMU1 and BMU2 init
+ * - GEMAC init
+ * - GPI init
+ * - CLASS-PE init
+ * - TMU-PE init
+ * - HIF tx and rx descriptors init
+ *
+ * @param[in]  edev    Pointer to eth device structure.
+ *
+ * @return 0, on success.
+ */
+static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
+{
+       int ret = 0;
+
+       debug("%s: start\n", __func__);
+
+       writel(0x3, CLASS_PE_SYS_CLK_RATIO);
+       writel(0x3, TMU_PE_SYS_CLK_RATIO);
+       writel(0x3, UTIL_PE_SYS_CLK_RATIO);
+       udelay(10);
+
+       pfe_class_init(pfe_addr);
+
+       pfe_tmu_init(pfe_addr);
+
+       pfe_bmu_init(pfe_addr);
+
+       pfe_gpi_init(pfe_addr);
+
+       ret = pfe_hif_init(pfe_addr);
+       if (ret)
+               return ret;
+
+       bmu_enable(BMU1_BASE_ADDR);
+       debug("bmu1 enabled\n");
+
+       bmu_enable(BMU2_BASE_ADDR);
+       debug("bmu2 enabled\n");
+
+       debug("%s: done\n", __func__);
+
+       return ret;
+}
+
+/*
+ * PFE driver init function.
+ * - Initializes pfe_lib
+ * - pfe hw init
+ * - fw loading and enables PEs
+ * - should be executed once.
+ *
+ * @param[in] pfe  Pointer the pfe control block
+ */
+int pfe_drv_init(struct pfe_ddr_address  *pfe_addr)
+{
+       int ret = 0;
+
+       pfe_lib_init();
+
+       ret = pfe_hw_init(pfe_addr);
+       if (ret)
+               return ret;
+
+       /* Load the class,TM, Util fw.
+        * By now pfe is:
+        * - out of reset + disabled + configured.
+        * Fw loading should be done after pfe_hw_init()
+        */
+       /* It loads default inbuilt sbl firmware */
+       pfe_firmware_init();
+
+       return ret;
+}
+
+/*
+ * PFE remove function
+ *  - stops PEs
+ *  - frees tx/rx descriptor resources
+ *  - should be called once.
+ *
+ * @param[in] pfe Pointer to pfe control block.
+ */
+int pfe_eth_remove(struct udevice *dev)
+{
+       if (g_tx_desc)
+               free(g_tx_desc);
+
+       if (g_rx_desc)
+               free(g_rx_desc);
+
+       pfe_firmware_exit();
+
+       return 0;
+}

diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
new file mode 100644 (file)
index 0000000..e6c6c8c
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <net.h>
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe_mdio.h>
+
+struct gemac_s gem_info[] = {
+       /* PORT_0 configuration */
+       {
+               /* GEMAC config */
+               .gemac_speed = PFE_MAC_SPEED_1000M,
+               .gemac_duplex = DUPLEX_FULL,
+
+               /* phy iface */
+               .phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
+               .phy_mode = PHY_INTERFACE_MODE_SGMII,
+       },
+       /* PORT_1 configuration */
+       {
+               /* GEMAC config */
+               .gemac_speed = PFE_MAC_SPEED_1000M,
+               .gemac_duplex = DUPLEX_FULL,
+
+               /* phy iface */
+               .phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
+               .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
+       },
+};
+
+static inline void pfe_gemac_enable(void *gemac_base)
+{
+       writel(readl(gemac_base + EMAC_ECNTRL_REG) |
+               EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+}
+
+static inline void pfe_gemac_disable(void *gemac_base)
+{
+       writel(readl(gemac_base + EMAC_ECNTRL_REG) &
+               ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+}
+
+static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
+{
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
+       u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
+       u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
+                       ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
+
+       if (speed == _1000BASET) {
+               ecr |= EMAC_ECNTRL_SPEED;
+               rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
+       } else if (speed != _100BASET) {
+               rcr |= EMAC_RCNTRL_RMII_10T;
+               rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
+       }
+
+       writel(ecr, gemac_base + EMAC_ECNTRL_REG);
+       out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
+
+       /* remove loop back */
+       rcr &= ~EMAC_RCNTRL_LOOP;
+       /* enable flow control */
+       rcr |= EMAC_RCNTRL_FCE;
+
+       /* Enable MII mode */
+       rcr |= EMAC_RCNTRL_MII_MODE;
+
+       writel(rcr, gemac_base + EMAC_RCNTRL_REG);
+
+       /* Enable Tx full duplex */
+       writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
+              gemac_base + EMAC_TCNTRL_REG);
+}
+
+static int pfe_eth_write_hwaddr(struct udevice *dev)
+{
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+       struct gemac_s *gem = priv->gem;
+       struct eth_pdata *pdata = dev_get_platdata(dev);
+       uchar *mac = pdata->enetaddr;
+
+       writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
+              gem->gemac_base + EMAC_PHY_ADDR_LOW);
+       writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
+              EMAC_PHY_ADDR_HIGH);
+       return 0;
+}
+
+/** Stops or Disables GEMAC pointing to this eth iface.
+ *
+ * @param[in]   edev    Pointer to eth device structure.
+ *
+ * @return      none
+ */
+static inline void pfe_eth_stop(struct udevice *dev)
+{
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+       pfe_gemac_disable(priv->gem->gemac_base);
+
+       gpi_disable(priv->gem->egpi_base);
+}
+
+static int pfe_eth_start(struct udevice *dev)
+{
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+       struct gemac_s *gem = priv->gem;
+       int speed;
+
+       /* set ethernet mac address */
+       pfe_eth_write_hwaddr(dev);
+
+       writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
+       writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
+       writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
+       writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
+              + EMAC_TX_SECTION_EMPTY);
+       writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
+              + EMAC_MIB_CTRL_STS_REG);
+
+#ifdef CONFIG_PHYLIB
+       /* Start up the PHY */
+       if (phy_startup(priv->phydev)) {
+               printf("Could not initialize PHY %s\n",
+                      priv->phydev->dev->name);
+               return -1;
+       }
+       speed = priv->phydev->speed;
+       printf("Speed detected %x\n", speed);
+       if (priv->phydev->duplex == DUPLEX_HALF) {
+               printf("Half duplex not supported\n");
+               return -1;
+       }
+#endif
+
+       pfe_gemac_set_speed(gem->gemac_base, speed);
+
+       /* Enable GPI */
+       gpi_enable(gem->egpi_base);
+
+       /* Enable GEMAC */
+       pfe_gemac_enable(gem->gemac_base);
+
+       return 0;
+}
+
+static int pfe_eth_send(struct udevice *dev, void *packet, int length)
+{
+       struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev->priv;
+
+       int rc;
+       int i = 0;
+
+       rc = pfe_send(priv->gemac_port, packet, length);
+
+       if (rc < 0) {
+               printf("Tx Queue full\n");
+               return rc;
+       }
+
+       while (1) {
+               rc = pfe_tx_done();
+               if (rc == 0)
+                       break;
+
+               udelay(100);
+               i++;
+               if (i == 30000)
+                       printf("Tx timeout, send failed\n");
+               break;
+       }
+
+       return 0;
+}
+
+static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+       uchar *pkt_buf;
+       int len;
+       int phy_port;
+
+       len = pfe_recv(&pkt_buf, &phy_port);
+
+       if (len == 0)
+               return -EAGAIN; /* no packet in rx */
+       else if  (len < 0)
+               return -EAGAIN;
+
+       debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
+             phy_port, len);
+       if (phy_port != priv->gemac_port)  {
+               printf("Rx pkt not on expected port\n");
+               return -EAGAIN;
+       }
+
+       *packetp = pkt_buf;
+
+       return len;
+}
+
+static int pfe_eth_probe(struct udevice *dev)
+{
+       struct pfe_eth_dev *priv = dev_get_priv(dev);
+       struct pfe_ddr_address *pfe_addr;
+       struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+       int ret = 0;
+       static int init_done;
+
+       if (!init_done) {
+               pfe_addr = (struct pfe_ddr_address *)malloc(sizeof
+                                                   (struct pfe_ddr_address));
+               if (!pfe_addr)
+                       return -ENOMEM;
+
+               pfe_addr->ddr_pfe_baseaddr =
+                               (void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
+               pfe_addr->ddr_pfe_phys_baseaddr =
+               (unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
+
+               debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
+                     pfe_addr->ddr_pfe_baseaddr,
+                     (u32)pfe_addr->ddr_pfe_phys_baseaddr);
+
+               ret = pfe_drv_init(pfe_addr);
+               if (ret)
+                       return ret;
+
+               init_pfe_scfg_dcfg_regs();
+               init_done = 1;
+       }
+
+       priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
+       priv->gem = &gem_info[priv->gemac_port];
+       priv->dev = dev;
+
+       switch (priv->gemac_port)  {
+       case EMAC_PORT_0:
+       default:
+               priv->gem->gemac_base = EMAC1_BASE_ADDR;
+               priv->gem->egpi_base = EGPI1_BASE_ADDR;
+               break;
+       case EMAC_PORT_1:
+               priv->gem->gemac_base = EMAC2_BASE_ADDR;
+               priv->gem->egpi_base = EGPI2_BASE_ADDR;
+               break;
+       }
+
+       ret = pfe_eth_board_init(dev);
+       if (ret)
+               return ret;
+
+#if defined(CONFIG_PHYLIB)
+       ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
+                               gem_info[priv->gemac_port].phy_address);
+#endif
+       return ret;
+}
+
+static int pfe_eth_bind(struct udevice *dev)
+{
+       struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+       char name[20];
+
+       sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
+
+       return device_set_name(dev, name);
+}
+
+static const struct eth_ops pfe_eth_ops = {
+       .start          = pfe_eth_start,
+       .send           = pfe_eth_send,
+       .recv           = pfe_eth_recv,
+       .free_pkt       = pfe_eth_free_pkt,
+       .stop           = pfe_eth_stop,
+       .write_hwaddr   = pfe_eth_write_hwaddr,
+};
+
+U_BOOT_DRIVER(pfe_eth) = {
+       .name   = "pfe_eth",
+       .id     = UCLASS_ETH,
+       .bind   = pfe_eth_bind,
+       .probe  = pfe_eth_probe,
+       .remove = pfe_eth_remove,
+       .ops    = &pfe_eth_ops,
+       .priv_auto_alloc_size = sizeof(struct pfe_eth_dev),
+       .platdata_auto_alloc_size = sizeof(struct pfe_eth_pdata)
+};

diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
new file mode 100644 (file)
index 0000000..9dc063d
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * @file
+ *  Contains all the functions to handle parsing and loading of PE firmware
+ * files.
+ */
+
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe_firmware.h>
+
+#define PFE_FIRMEWARE_FIT_CNF_NAME     "config@1"
+
+static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR;
+
+/*
+ * PFE elf firmware loader.
+ * Loads an elf firmware image into a list of PE's (specified using a bitmask)
+ *
+ * @param pe_mask      Mask of PE id's to load firmware to
+ * @param pfe_firmware Pointer to the firmware image
+ *
+ * @return             0 on success, a negative value on error
+ */
+static int pfe_load_elf(int pe_mask, uint8_t *pfe_firmware)
+{
+       Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)pfe_firmware;
+       Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
+       Elf32_Shdr *shdr = (Elf32_Shdr *)(pfe_firmware +
+                                               be32_to_cpu(elf_hdr->e_shoff));
+       int id, section;
+       int ret;
+
+       debug("%s: no of sections: %d\n", __func__, sections);
+
+       /* Some sanity checks */
+       if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
+               printf("%s: incorrect elf magic number\n", __func__);
+               return -1;
+       }
+
+       if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {
+               printf("%s: incorrect elf class(%x)\n", __func__,
+                      elf_hdr->e_ident[EI_CLASS]);
+               return -1;
+       }
+
+       if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {
+               printf("%s: incorrect elf data(%x)\n", __func__,
+                      elf_hdr->e_ident[EI_DATA]);
+               return -1;
+       }
+
+       if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {
+               printf("%s: incorrect elf file type(%x)\n", __func__,
+                      be16_to_cpu(elf_hdr->e_type));
+               return -1;
+       }
+
+       for (section = 0; section < sections; section++, shdr++) {
+               if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |
+                       SHF_EXECINSTR)))
+                       continue;
+               for (id = 0; id < MAX_PE; id++)
+                       if (pe_mask & BIT(id)) {
+                               ret = pe_load_elf_section(id,
+                                                         pfe_firmware, shdr);
+                               if (ret < 0)
+                                       goto err;
+                       }
+       }
+       return 0;
+
+err:
+       return ret;
+}
+
+/*
+ * Get PFE firmware from FIT image
+ *
+ * @param data pointer to PFE firmware
+ * @param size pointer to size of the firmware
+ * @param fw_name pfe firmware name, either class or tmu
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_get_fw(const void **data,
+                     size_t *size, char *fw_name)
+{
+       int conf_node_off, fw_node_off;
+       char *conf_node_name = NULL;
+       char *desc;
+       int ret = 0;
+
+       conf_node_name = PFE_FIRMEWARE_FIT_CNF_NAME;
+
+       conf_node_off = fit_conf_get_node(pfe_fit_addr, conf_node_name);
+       if (conf_node_off < 0) {
+               printf("PFE Firmware: %s: no such config\n", conf_node_name);
+               return -ENOENT;
+       }
+
+       fw_node_off = fit_conf_get_prop_node(pfe_fit_addr, conf_node_off,
+                                            fw_name);
+       if (fw_node_off < 0) {
+               printf("PFE Firmware: No '%s' in config\n",
+                      fw_name);
+               return -ENOLINK;
+       }
+
+       if (!(fit_image_verify(pfe_fit_addr, fw_node_off))) {
+               printf("PFE Firmware: Bad firmware image (bad CRC)\n");
+               return -EINVAL;
+       }
+
+       if (fit_image_get_data(pfe_fit_addr, fw_node_off, data, size)) {
+               printf("PFE Firmware: Can't get %s subimage data/size",
+                      fw_name);
+               return -ENOENT;
+       }
+
+       ret = fit_get_desc(pfe_fit_addr, fw_node_off, &desc);
+       if (ret)
+               printf("PFE Firmware: Can't get description\n");
+       else
+               printf("%s\n", desc);
+
+       return ret;
+}
+
+/*
+ * Check PFE FIT image
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_fit_check(void)
+{
+       int ret = 0;
+
+       ret = fdt_check_header(pfe_fit_addr);
+       if (ret) {
+               printf("PFE Firmware: Bad firmware image (not a FIT image)\n");
+               return ret;
+       }
+
+       if (!fit_check_format(pfe_fit_addr)) {
+               printf("PFE Firmware: Bad firmware image (bad FIT header)\n");
+               ret = -1;
+               return ret;
+       }
+
+       return ret;
+}
+
+/*
+ * PFE firmware initialization.
+ * Loads different firmware files from FIT image.
+ * Initializes PE IMEM/DMEM and UTIL-PE DDR
+ * Initializes control path symbol addresses (by looking them up in the elf
+ * firmware files
+ * Takes PE's out of reset
+ *
+ * @return 0 on success, a negative value on error
+ */
+int pfe_firmware_init(void)
+{
+       char *pfe_firmware_name;
+       const void *raw_image_addr;
+       size_t raw_image_size = 0;
+       u8 *pfe_firmware;
+       int ret = 0;
+       int fw_count;
+
+       ret = pfe_fit_check();
+       if (ret)
+               goto err;
+
+       for (fw_count = 0; fw_count < 2; fw_count++) {
+               if (fw_count == 0)
+                       pfe_firmware_name = "class";
+               else if (fw_count == 1)
+                       pfe_firmware_name = "tmu";
+
+               pfe_get_fw(&raw_image_addr, &raw_image_size, pfe_firmware_name);
+               pfe_firmware = malloc(raw_image_size);
+               if (!pfe_firmware)
+                       return -ENOMEM;
+               memcpy((void *)pfe_firmware, (void *)raw_image_addr,
+                      raw_image_size);
+
+               if (fw_count == 0)
+                       ret = pfe_load_elf(CLASS_MASK, pfe_firmware);
+               else if (fw_count == 1)
+                       ret = pfe_load_elf(TMU_MASK, pfe_firmware);
+
+               if (ret < 0) {
+                       printf("%s: %s firmware load failed\n", __func__,
+                              pfe_firmware_name);
+                       goto err;
+               }
+               debug("%s: %s firmware loaded\n", __func__, pfe_firmware_name);
+               free(pfe_firmware);
+       }
+
+       tmu_enable(0xb);
+       class_enable();
+       gpi_enable(HGPI_BASE_ADDR);
+
+err:
+       return ret;
+}
+
+/*
+ * PFE firmware cleanup
+ * Puts PE's in reset
+ */
+void pfe_firmware_exit(void)
+{
+       debug("%s\n", __func__);
+
+       class_disable();
+       tmu_disable(0xf);
+       hif_tx_disable();
+       hif_rx_disable();
+}

diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c
new file mode 100644 (file)
index 0000000..12bb0da
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_hw.c
@@ -0,0 +1,999 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include <net/pfe_eth/pfe_eth.h>
+#include <net/pfe_eth/pfe/pfe_hw.h>
+
+static struct pe_info pe[MAX_PE];
+
+/*
+ * Initializes the PFE library.
+ * Must be called before using any of the library functions.
+ */
+void pfe_lib_init(void)
+{
+       int pfe_pe_id;
+
+       for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
+               pe[pfe_pe_id].dmem_base_addr =
+                       (u32)CLASS_DMEM_BASE_ADDR(pfe_pe_id);
+               pe[pfe_pe_id].pmem_base_addr =
+                       (u32)CLASS_IMEM_BASE_ADDR(pfe_pe_id);
+               pe[pfe_pe_id].pmem_size = (u32)CLASS_IMEM_SIZE;
+               pe[pfe_pe_id].mem_access_wdata =
+                       (void *)CLASS_MEM_ACCESS_WDATA;
+               pe[pfe_pe_id].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+               pe[pfe_pe_id].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+       }
+
+       for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
+               if (pfe_pe_id == TMU2_ID)
+                       continue;
+               pe[pfe_pe_id].dmem_base_addr =
+                       (u32)TMU_DMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
+               pe[pfe_pe_id].pmem_base_addr =
+                       (u32)TMU_IMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
+               pe[pfe_pe_id].pmem_size = (u32)TMU_IMEM_SIZE;
+               pe[pfe_pe_id].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
+               pe[pfe_pe_id].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
+               pe[pfe_pe_id].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
+       }
+}
+
+/*
+ * Writes a buffer to PE internal memory from the host
+ * through indirect access registers.
+ *
+ * @param[in] id              PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                             ..., UTIL_ID)
+ * @param[in] mem_access_addr  DMEM destination address (must be 32bit
+ *                             aligned)
+ * @param[in] src              Buffer source address
+ * @param[in] len              Number of bytes to copy
+ */
+static void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src,
+                              unsigned int len)
+{
+       u32 offset = 0, val, addr;
+       unsigned int len32 = len >> 2;
+       int i;
+
+       addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
+               PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
+
+       for (i = 0; i < len32; i++, offset += 4, src += 4) {
+               val = *(u32 *)src;
+               writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+               writel(addr + offset, pe[id].mem_access_addr);
+       }
+
+       len = (len & 0x3);
+       if (len) {
+               val = 0;
+
+               addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
+                       PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
+
+               for (i = 0; i < len; i++, src++)
+                       val |= (*(u8 *)src) << (8 * i);
+
+               writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+               writel(addr, pe[id].mem_access_addr);
+       }
+}
+
+/*
+ * Writes a buffer to PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                     ..., UTIL_ID)
+ * @param[in] dst      DMEM destination address (must be 32bit
+ *                     aligned)
+ * @param[in] src      Buffer source address
+ * @param[in] len      Number of bytes to copy
+ */
+static void pe_dmem_memcpy_to32(int id, u32 dst, const void *src,
+                               unsigned int len)
+{
+       pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM,
+                          src, len);
+}
+
+/*
+ * Writes a buffer to PE internal program memory (PMEM) from the host
+ * through indirect access registers.
+ * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                     ..., TMU3_ID)
+ * @param[in] dst      PMEM destination address (must be 32bit
+ *                     aligned)
+ * @param[in] src      Buffer source address
+ * @param[in] len      Number of bytes to copy
+ */
+static void pe_pmem_memcpy_to32(int id, u32 dst, const void *src,
+                               unsigned int len)
+{
+       pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
+                               - 1)) | PE_MEM_ACCESS_IMEM, src, len);
+}
+
+/*
+ * Reads PE internal program memory (IMEM) from the host
+ * through indirect access registers.
+ * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                             ..., TMU3_ID)
+ * @param[in] addr             PMEM read address (must be aligned on size)
+ * @param[in] size             Number of bytes to read (maximum 4, must not
+ *                             cross 32bit boundaries)
+ * @return                     the data read (in PE endianness, i.e BE).
+ */
+u32 pe_pmem_read(int id, u32 addr, u8 size)
+{
+       u32 offset = addr & 0x3;
+       u32 mask = 0xffffffff >> ((4 - size) << 3);
+       u32 val;
+
+       addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
+               | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM |
+               PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+       writel(addr, pe[id].mem_access_addr);
+       val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+       return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * Writes PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                     ..., UTIL_ID)
+ * @param[in] val      Value to write (in PE endianness, i.e BE)
+ * @param[in] addr     DMEM write address (must be aligned on size)
+ * @param[in] size     Number of bytes to write (maximum 4, must not
+ *                     cross 32bit boundaries)
+ */
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
+{
+       u32 offset = addr & 0x3;
+
+       addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
+               PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+       /* Indirect access interface is byte swapping data being written */
+       writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
+       writel(addr, pe[id].mem_access_addr);
+}
+
+/*
+ * Reads PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                             ..., UTIL_ID)
+ * @param[in] addr             DMEM read address (must be aligned on size)
+ * @param[in] size             Number of bytes to read (maximum 4, must not
+ *                             cross 32bit boundaries)
+ * @return                     the data read (in PE endianness, i.e BE).
+ */
+u32 pe_dmem_read(int id, u32 addr, u8 size)
+{
+       u32 offset = addr & 0x3;
+       u32 mask = 0xffffffff >> ((4 - size) << 3);
+       u32 val;
+
+       addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ |
+               PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+       writel(addr, pe[id].mem_access_addr);
+
+       /* Indirect access interface is byte swapping data being read */
+       val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+       return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * This function is used to write to CLASS internal bus peripherals (ccu,
+ * pe-lem) from the host
+ * through indirect access registers.
+ * @param[in]  val     value to write
+ * @param[in]  addr    Address to write to (must be aligned on size)
+ * @param[in]  size    Number of bytes to write (1, 2 or 4)
+ *
+ */
+static void class_bus_write(u32 val, u32 addr, u8 size)
+{
+       u32 offset = addr & 0x3;
+
+       writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+       addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
+               (size << 24);
+
+       writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
+       writel(addr, CLASS_BUS_ACCESS_ADDR);
+}
+
+/*
+ * Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
+ * through indirect access registers.
+ * @param[in] addr     Address to read from (must be aligned on size)
+ * @param[in] size     Number of bytes to read (1, 2 or 4)
+ * @return             the read data
+ */
+static u32 class_bus_read(u32 addr, u8 size)
+{
+       u32 offset = addr & 0x3;
+       u32 mask = 0xffffffff >> ((4 - size) << 3);
+       u32 val;
+
+       writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+       addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
+
+       writel(addr, CLASS_BUS_ACCESS_ADDR);
+       val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
+
+       return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * Writes data to the cluster memory (PE_LMEM)
+ * @param[in] dst      PE LMEM destination address (must be 32bit aligned)
+ * @param[in] src      Buffer source address
+ * @param[in] len      Number of bytes to copy
+ */
+static void class_pe_lmem_memcpy_to32(u32 dst, const void *src,
+                                     unsigned int len)
+{
+       u32 len32 = len >> 2;
+       int i;
+
+       for (i = 0; i < len32; i++, src += 4, dst += 4)
+               class_bus_write(*(u32 *)src, dst, 4);
+
+       if (len & 0x2) {
+               class_bus_write(*(u16 *)src, dst, 2);
+               src += 2;
+               dst += 2;
+       }
+
+       if (len & 0x1) {
+               class_bus_write(*(u8 *)src, dst, 1);
+               src++;
+               dst++;
+       }
+}
+
+/*
+ * Writes value to the cluster memory (PE_LMEM)
+ * @param[in] dst      PE LMEM destination address (must be 32bit aligned)
+ * @param[in] val      Value to write
+ * @param[in] len      Number of bytes to write
+ */
+static void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
+{
+       u32 len32 = len >> 2;
+       int i;
+
+       val = val | (val << 8) | (val << 16) | (val << 24);
+
+       for (i = 0; i < len32; i++, dst += 4)
+               class_bus_write(val, dst, 4);
+
+       if (len & 0x2) {
+               class_bus_write(val, dst, 2);
+               dst += 2;
+       }
+
+       if (len & 0x1) {
+               class_bus_write(val, dst, 1);
+               dst++;
+       }
+}
+
+/*
+ * Reads data from the cluster memory (PE_LMEM)
+ * @param[out] dst     pointer to the source buffer data are copied to
+ * @param[in] len      length in bytes of the amount of data to read
+ *                     from cluster memory
+ * @param[in] offset   offset in bytes in the cluster memory where data are
+ *                     read from
+ */
+void pe_lmem_read(u32 *dst, u32 len, u32 offset)
+{
+       u32 len32 = len >> 2;
+       int i = 0;
+
+       for (i = 0; i < len32; dst++, i++, offset += 4)
+               *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
+
+       if (len & 0x03)
+               *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+}
+
+/*
+ * Writes data to the cluster memory (PE_LMEM)
+ * @param[in] src      pointer to the source buffer data are copied from
+ * @param[in] len      length in bytes of the amount of data to write to the
+ *                             cluster memory
+ * @param[in] offset   offset in bytes in the cluster memory where data are
+ *                             written to
+ */
+void pe_lmem_write(u32 *src, u32 len, u32 offset)
+{
+       u32 len32 = len >> 2;
+       int i = 0;
+
+       for (i = 0; i < len32; src++, i++, offset += 4)
+               class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
+
+       if (len & 0x03)
+               class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len &
+                                       0x03));
+}
+
+/*
+ * Loads an elf section into pmem
+ * Code needs to be at least 16bit aligned and only PROGBITS sections are
+ * supported
+ *
+ * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID, ...,
+ *                                     TMU3_ID)
+ * @param[in] data     pointer to the elf firmware
+ * @param[in] shdr     pointer to the elf section header
+ */
+static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+       u32 offset = be32_to_cpu(shdr->sh_offset);
+       u32 addr = be32_to_cpu(shdr->sh_addr);
+       u32 size = be32_to_cpu(shdr->sh_size);
+       u32 type = be32_to_cpu(shdr->sh_type);
+
+       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+               printf(
+                       "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+                       __func__, addr, (unsigned long)data + offset);
+
+               return -1;
+       }
+
+       if (addr & 0x1) {
+               printf("%s: load address(%x) is not 16bit aligned\n",
+                      __func__, addr);
+               return -1;
+       }
+
+       if (size & 0x1) {
+               printf("%s: load size(%x) is not 16bit aligned\n", __func__,
+                      size);
+               return -1;
+       }
+
+               debug("pmem pe%d @%x len %d\n", id, addr, size);
+       switch (type) {
+       case SHT_PROGBITS:
+               pe_pmem_memcpy_to32(id, addr, data + offset, size);
+               break;
+
+       default:
+               printf("%s: unsupported section type(%x)\n", __func__, type);
+               return -1;
+       }
+
+       return 0;
+}
+
+/*
+ * Loads an elf section into dmem
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                     ..., UTIL_ID)
+ * @param[in] data     pointer to the elf firmware
+ * @param[in] shdr     pointer to the elf section header
+ */
+static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+       u32 offset = be32_to_cpu(shdr->sh_offset);
+       u32 addr = be32_to_cpu(shdr->sh_addr);
+       u32 size = be32_to_cpu(shdr->sh_size);
+       u32 type = be32_to_cpu(shdr->sh_type);
+       u32 size32 = size >> 2;
+       int i;
+
+       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+               printf(
+                       "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+                       __func__, addr, (unsigned long)data + offset);
+
+               return -1;
+       }
+
+       if (addr & 0x3) {
+               printf("%s: load address(%x) is not 32bit aligned\n",
+                      __func__, addr);
+               return -1;
+       }
+
+       switch (type) {
+       case SHT_PROGBITS:
+               debug("dmem pe%d @%x len %d\n", id, addr, size);
+               pe_dmem_memcpy_to32(id, addr, data + offset, size);
+               break;
+
+       case SHT_NOBITS:
+               debug("dmem zero pe%d @%x len %d\n", id, addr, size);
+               for (i = 0; i < size32; i++, addr += 4)
+                       pe_dmem_write(id, 0, addr, 4);
+
+               if (size & 0x3)
+                       pe_dmem_write(id, 0, addr, size & 0x3);
+
+               break;
+
+       default:
+               printf("%s: unsupported section type(%x)\n", __func__, type);
+               return -1;
+       }
+
+       return 0;
+}
+
+/*
+ * Loads an elf section into DDR
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ *             initialized to 0
+ *
+ * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID,
+ *                     ..., UTIL_ID)
+ * @param[in] data     pointer to the elf firmware
+ * @param[in] shdr     pointer to the elf section header
+ */
+static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+       u32 offset = be32_to_cpu(shdr->sh_offset);
+       u32 addr = be32_to_cpu(shdr->sh_addr);
+       u32 size = be32_to_cpu(shdr->sh_size);
+       u32 type = be32_to_cpu(shdr->sh_type);
+       u32 flags = be32_to_cpu(shdr->sh_flags);
+
+       switch (type) {
+       case SHT_PROGBITS:
+               debug("ddr  pe%d @%x len %d\n", id, addr, size);
+               if (flags & SHF_EXECINSTR) {
+                       if (id <= CLASS_MAX_ID) {
+                               /* DO the loading only once in DDR */
+                               if (id == CLASS0_ID) {
+                                       debug(
+                                               "%s: load address(%x) and elf file address(%lx) rcvd\n"
+                                               , __func__, addr,
+                                               (unsigned long)data + offset);
+                                       if (((unsigned long)(data + offset)
+                                               & 0x3) != (addr & 0x3)) {
+                                               printf(
+                                                       "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+                                                       __func__, addr,
+                                                       (unsigned long)data +
+                                                       offset);
+
+                                               return -1;
+                                       }
+
+                                       if (addr & 0x1) {
+                                               printf(
+                                                       "%s: load address(%x) is not 16bit aligned\n"
+                                                       , __func__, addr);
+                                               return -1;
+                                       }
+
+                                       if (size & 0x1) {
+                                               printf(
+                                                       "%s: load length(%x) is not 16bit aligned\n"
+                                                       , __func__, size);
+                                               return -1;
+                                       }
+
+                                       memcpy((void *)DDR_PFE_TO_VIRT(addr),
+                                              data + offset, size);
+                               }
+                       } else {
+                               printf(
+                                       "%s: unsupported ddr section type(%x) for PE(%d)\n"
+                                       , __func__, type, id);
+                               return -1;
+                       }
+
+               } else {
+                       memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset,
+                              size);
+               }
+
+               break;
+
+       case SHT_NOBITS:
+               debug("ddr zero pe%d @%x len %d\n", id, addr, size);
+               memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
+
+               break;
+
+       default:
+               printf("%s: unsupported section type(%x)\n", __func__, type);
+               return -1;
+       }
+
+       return 0;
+}
+
+/*
+ * Loads an elf section into pe lmem
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id       PE identification (CLASS0_ID,..., CLASS5_ID)
+ * @param[in] data     pointer to the elf firmware
+ * @param[in] shdr     pointer to the elf section header
+ */
+static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+       u32 offset = be32_to_cpu(shdr->sh_offset);
+       u32 addr = be32_to_cpu(shdr->sh_addr);
+       u32 size = be32_to_cpu(shdr->sh_size);
+       u32 type = be32_to_cpu(shdr->sh_type);
+
+       if (id > CLASS_MAX_ID) {
+               printf("%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
+                      __func__, type, id);
+               return -1;
+       }
+
+       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+               printf(
+                       "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+                       __func__, addr, (unsigned long)data + offset);
+
+               return -1;
+       }
+
+       if (addr & 0x3) {
+               printf("%s: load address(%x) is not 32bit aligned\n",
+                      __func__, addr);
+               return -1;
+       }
+
+       debug("lmem  pe%d @%x len %d\n", id, addr, size);
+
+       switch (type) {
+       case SHT_PROGBITS:
+               class_pe_lmem_memcpy_to32(addr, data + offset, size);
+               break;
+
+       case SHT_NOBITS:
+               class_pe_lmem_memset(addr, 0, size);
+               break;
+
+       default:
+               printf("%s: unsupported section type(%x)\n", __func__, type);
+               return -1;
+       }
+
+       return 0;
+}
+
+/*
+ * Loads an elf section into a PE
+ * For now only supports loading a section to dmem (all PE's), pmem (class and
+ * tmu PE's), DDDR (util PE code)
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data     pointer to the elf firmware
+ * @param[in] shdr     pointer to the elf section header
+ */
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+       u32 addr = be32_to_cpu(shdr->sh_addr);
+       u32 size = be32_to_cpu(shdr->sh_size);
+
+       if (IS_DMEM(addr, size))
+               return pe_load_dmem_section(id, data, shdr);
+       else if (IS_PMEM(addr, size))
+               return pe_load_pmem_section(id, data, shdr);
+       else if (IS_PFE_LMEM(addr, size))
+               return 0;
+       else if (IS_PHYS_DDR(addr, size))
+               return pe_load_ddr_section(id, data, shdr);
+       else if (IS_PE_LMEM(addr, size))
+               return pe_load_pe_lmem_section(id, data, shdr);
+
+       printf("%s: unsupported memory range(%x)\n", __func__, addr);
+
+       return 0;
+}
+
+/**************************** BMU ***************************/
+/*
+ * Resets a BMU block.
+ * @param[in] base     BMU block base address
+ */
+static inline void bmu_reset(void *base)
+{
+       writel(CORE_SW_RESET, base + BMU_CTRL);
+
+       /* Wait for self clear */
+       while (readl(base + BMU_CTRL) & CORE_SW_RESET)
+               ;
+}
+
+/*
+ * Enabled a BMU block.
+ * @param[in] base     BMU block base address
+ */
+void bmu_enable(void *base)
+{
+       writel(CORE_ENABLE, base + BMU_CTRL);
+}
+
+/*
+ * Disables a BMU block.
+ * @param[in] base     BMU block base address
+ */
+static inline void bmu_disable(void *base)
+{
+       writel(CORE_DISABLE, base + BMU_CTRL);
+}
+
+/*
+ * Sets the configuration of a BMU block.
+ * @param[in] base     BMU block base address
+ * @param[in] cfg      BMU configuration
+ */
+static inline void bmu_set_config(void *base, struct bmu_cfg *cfg)
+{
+       writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
+       writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
+       writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
+
+       /* Interrupts are never used */
+       writel(0x0, base + BMU_INT_ENABLE);
+}
+
+/*
+ * Initializes a BMU block.
+ * @param[in] base     BMU block base address
+ * @param[in] cfg      BMU configuration
+ */
+void bmu_init(void *base, struct bmu_cfg *cfg)
+{
+       bmu_disable(base);
+
+       bmu_set_config(base, cfg);
+
+       bmu_reset(base);
+}
+
+/**************************** GPI ***************************/
+/*
+ * Resets a GPI block.
+ * @param[in] base     GPI base address
+ */
+static inline void gpi_reset(void *base)
+{
+       writel(CORE_SW_RESET, base + GPI_CTRL);
+}
+
+/*
+ * Enables a GPI block.
+ * @param[in] base     GPI base address
+ */
+void gpi_enable(void *base)
+{
+       writel(CORE_ENABLE, base + GPI_CTRL);
+}
+
+/*
+ * Disables a GPI block.
+ * @param[in] base     GPI base address
+ */
+void gpi_disable(void *base)
+{
+       writel(CORE_DISABLE, base + GPI_CTRL);
+}
+
+/*
+ * Sets the configuration of a GPI block.
+ * @param[in] base     GPI base address
+ * @param[in] cfg      GPI configuration
+ */
+static inline void gpi_set_config(void *base, struct gpi_cfg *cfg)
+{
+       writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base
+              + GPI_LMEM_ALLOC_ADDR);
+       writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base
+              + GPI_LMEM_FREE_ADDR);
+       writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base
+              + GPI_DDR_ALLOC_ADDR);
+       writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base
+              + GPI_DDR_FREE_ADDR);
+       writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
+       writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
+       writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
+       writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
+       writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
+       writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
+       writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
+
+       writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
+               GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
+       writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
+       writel(cfg->aseq_len, base + GPI_DTX_ASEQ);
+
+       /*Make GPI AXI transactions non-bufferable */
+       writel(0x1, base + GPI_AXI_CTRL);
+}
+
+/*
+ * Initializes a GPI block.
+ * @param[in] base     GPI base address
+ * @param[in] cfg      GPI configuration
+ */
+void gpi_init(void *base, struct gpi_cfg *cfg)
+{
+       gpi_reset(base);
+
+       gpi_disable(base);
+
+       gpi_set_config(base, cfg);
+}
+
+/**************************** CLASSIFIER ***************************/
+/*
+ * Resets CLASSIFIER block.
+ */
+static inline void class_reset(void)
+{
+       writel(CORE_SW_RESET, CLASS_TX_CTRL);
+}
+
+/*
+ * Enables all CLASS-PE's cores.
+ */
+void class_enable(void)
+{
+       writel(CORE_ENABLE, CLASS_TX_CTRL);
+}
+
+/*
+ * Disables all CLASS-PE's cores.
+ */
+void class_disable(void)
+{
+       writel(CORE_DISABLE, CLASS_TX_CTRL);
+}
+
+/*
+ * Sets the configuration of the CLASSIFIER block.
+ * @param[in] cfg      CLASSIFIER configuration
+ */
+static inline void class_set_config(struct class_cfg *cfg)
+{
+       if (PLL_CLK_EN == 0) {
+               /* Clock ratio: for 1:1 the value is 0 */
+               writel(0x0, CLASS_PE_SYS_CLK_RATIO);
+       } else {
+               /* Clock ratio: for 1:2 the value is 1 */
+               writel(0x1, CLASS_PE_SYS_CLK_RATIO);
+       }
+       writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
+       writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
+       writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
+               CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
+               CLASS_ROUTE_HASH_ENTRY_SIZE);
+       writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
+
+       writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);
+       memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0,
+              ROUTE_TABLE_SIZE);
+
+       writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
+       writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
+       writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
+       writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
+       writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
+
+       writel(23, CLASS_AFULL_THRES);
+       writel(23, CLASS_TSQ_FIFO_THRES);
+
+       writel(24, CLASS_MAX_BUF_CNT);
+       writel(24, CLASS_TSQ_MAX_CNT);
+
+       /*Make Class AXI transactions non-bufferable */
+       writel(0x1, CLASS_AXI_CTRL);
+
+       /*Make Util AXI transactions non-bufferable */
+       /*Util is disabled in U-boot, do it from here */
+       writel(0x1, UTIL_AXI_CTRL);
+}
+
+/*
+ * Initializes CLASSIFIER block.
+ * @param[in] cfg      CLASSIFIER configuration
+ */
+void class_init(struct class_cfg *cfg)
+{
+       class_reset();
+
+       class_disable();
+
+       class_set_config(cfg);
+}
+
+/**************************** TMU ***************************/
+/*
+ * Enables TMU-PE cores.
+ * @param[in] pe_mask  TMU PE mask
+ */
+void tmu_enable(u32 pe_mask)
+{
+       writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/*
+ * Disables TMU cores.
+ * @param[in] pe_mask  TMU PE mask
+ */
+void tmu_disable(u32 pe_mask)
+{
+       writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/*
+ * Initializes TMU block.
+ * @param[in] cfg      TMU configuration
+ */
+void tmu_init(struct tmu_cfg *cfg)
+{
+       int q, phyno;
+
+       /* keep in soft reset */
+       writel(SW_RESET, TMU_CTRL);
+
+       /*Make Class AXI transactions non-bufferable */
+       writel(0x1, TMU_AXI_CTRL);
+
+       /* enable EMAC PHY ports */
+       writel(0x3, TMU_SYS_GENERIC_CONTROL);
+
+       writel(750, TMU_INQ_WATERMARK);
+
+       writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR),
+              TMU_PHY0_INQ_ADDR);
+       writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR),
+              TMU_PHY1_INQ_ADDR);
+
+       writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR),
+              TMU_PHY3_INQ_ADDR);
+       writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
+       writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
+       writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
+              TMU_BMU_INQ_ADDR);
+
+       /* enabling all 10 schedulers [9:0] of each TDQ  */
+       writel(0x3FF, TMU_TDQ0_SCH_CTRL);
+       writel(0x3FF, TMU_TDQ1_SCH_CTRL);
+       writel(0x3FF, TMU_TDQ3_SCH_CTRL);
+
+       if (PLL_CLK_EN == 0) {
+               /* Clock ratio: for 1:1 the value is 0 */
+               writel(0x0, TMU_PE_SYS_CLK_RATIO);
+       } else {
+               /* Clock ratio: for 1:2 the value is 1 */
+               writel(0x1, TMU_PE_SYS_CLK_RATIO);
+       }
+
+       /* Extra packet pointers will be stored from this address onwards */
+       debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
+       writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR);
+
+       debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
+       writel(cfg->llm_queue_len,      TMU_LLM_QUE_LEN);
+
+       writel(5, TMU_TDQ_IIFG_CFG);
+       writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
+
+       writel(0x0, TMU_CTRL);
+
+       /* MEM init */
+       writel(MEM_INIT, TMU_CTRL);
+
+       while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
+               ;
+
+       /* LLM init */
+       writel(LLM_INIT, TMU_CTRL);
+
+       while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
+               ;
+
+       /* set up each queue for tail drop */
+       for (phyno = 0; phyno < 4; phyno++) {
+               if (phyno == 2)
+                       continue;
+               for (q = 0; q < 16; q++) {
+                       u32 qmax;
+
+                       writel((phyno << 8) | q, TMU_TEQ_CTRL);
+                       writel(BIT(22), TMU_TEQ_QCFG);
+
+                       if (phyno == 3)
+                               qmax = DEFAULT_TMU3_QDEPTH;
+                       else
+                               qmax = (q == 0) ? DEFAULT_Q0_QDEPTH :
+                                       DEFAULT_MAX_QDEPTH;
+
+                       writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
+                       writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
+               }
+       }
+       writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
+       writel(0, TMU_CTRL);
+}
+
+/**************************** HIF ***************************/
+/*
+ * Enable hif tx DMA and interrupt
+ */
+void hif_tx_enable(void)
+{
+       writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
+}
+
+/*
+ * Disable hif tx DMA and interrupt
+ */
+void hif_tx_disable(void)
+{
+       u32 hif_int;
+
+       writel(0, HIF_TX_CTRL);
+
+       hif_int = readl(HIF_INT_ENABLE);
+       hif_int &= HIF_TXPKT_INT_EN;
+       writel(hif_int, HIF_INT_ENABLE);
+}
+
+/*
+ * Enable hif rx DMA and interrupt
+ */
+void hif_rx_enable(void)
+{
+       writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+}
+
+/*
+ * Disable hif rx DMA and interrupt
+ */
+void hif_rx_disable(void)
+{
+       u32 hif_int;
+
+       writel(0, HIF_RX_CTRL);
+
+       hif_int = readl(HIF_INT_ENABLE);
+       hif_int &= HIF_RXPKT_INT_EN;
+       writel(hif_int, HIF_INT_ENABLE);
+}
+
+/*
+ * Initializes HIF copy block.
+ */
+void hif_init(void)
+{
+       /* Initialize HIF registers */
+       writel(HIF_RX_POLL_CTRL_CYCLE << 16 | HIF_TX_POLL_CTRL_CYCLE,
+              HIF_POLL_CTRL);
+       /* Make HIF AXI transactions non-bufferable */
+       writel(0x1, HIF_AXI_CTRL);
+}

diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
new file mode 100644 (file)
index 0000000..a78a4d6
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <net.h>
+#include <net/pfe_eth/pfe_eth.h>
+
+extern struct gemac_s gem_info[];
+#if defined(CONFIG_PHYLIB)
+
+#define MDIO_TIMEOUT    5000
+static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr,
+                         int reg_addr)
+{
+       void *reg_base = bus->priv;
+       u32 devadr;
+       u32 phy;
+       u32 reg_data;
+       int timeout = MDIO_TIMEOUT;
+
+       devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
+       phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+       reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
+
+       writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+       /*
+        * wait for the MII interrupt
+        */
+       while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+               if (timeout-- <= 0) {
+                       printf("Phy MDIO read/write timeout\n");
+                       return -1;
+               }
+       }
+
+       /*
+        * clear MII interrupt
+        */
+       writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+       return 0;
+}
+
+static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+                       int reg_addr)
+{
+       void *reg_base = bus->priv;
+       u32 reg;
+       u32 phy;
+       u32 reg_data;
+       u16 val;
+       int timeout = MDIO_TIMEOUT;
+
+       if (dev_addr == MDIO_DEVAD_NONE) {
+               reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
+                       EMAC_MII_DATA_RA_SHIFT);
+       } else {
+               pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
+               reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
+                      EMAC_MII_DATA_RA_SHIFT);
+       }
+
+       phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+       if (dev_addr == MDIO_DEVAD_NONE)
+               reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
+                           EMAC_MII_DATA_TA | phy | reg);
+       else
+               reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA |
+                           phy | reg);
+
+       writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+       /*
+        * wait for the MII interrupt
+        */
+       while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+               if (timeout-- <= 0) {
+                       printf("Phy MDIO read/write timeout\n");
+                       return -1;
+               }
+       }
+
+       /*
+        * clear MII interrupt
+        */
+       writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+       /*
+        * it's now safe to read the PHY's register
+        */
+       val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
+       debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
+             phy_addr, reg_addr, val);
+
+       return val;
+}
+
+static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+                        int reg_addr, u16 data)
+{
+       void *reg_base = bus->priv;
+       u32 reg;
+       u32 phy;
+       u32 reg_data;
+       int timeout = MDIO_TIMEOUT;
+       int val;
+
+       if (dev_addr == MDIO_DEVAD_NONE) {
+               reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
+                      EMAC_MII_DATA_RA_SHIFT);
+       } else {
+               pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
+               reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
+                      EMAC_MII_DATA_RA_SHIFT);
+       }
+
+       phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+       if (dev_addr == MDIO_DEVAD_NONE)
+               reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
+                           EMAC_MII_DATA_TA | phy | reg | data);
+       else
+               reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA |
+                           phy | reg | data);
+
+       writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+       /*
+        * wait for the MII interrupt
+        */
+       while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+               if (timeout-- <= 0) {
+                       printf("Phy MDIO read/write timeout\n");
+                       return -1;
+               }
+       }
+
+       /*
+        * clear MII interrupt
+        */
+       writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+       debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
+             reg_addr, data);
+
+       return val;
+}
+
+static void pfe_configure_serdes(struct pfe_eth_dev *priv)
+{
+       struct mii_dev bus;
+       int value, sgmii_2500 = 0;
+       struct gemac_s *gem = priv->gem;
+
+       if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
+               sgmii_2500 = 1;
+
+       printf("%s %d\n", __func__, priv->gemac_port);
+
+       /* PCS configuration done with corresponding GEMAC */
+       bus.priv = gem_info[priv->gemac_port].gemac_base;
+
+       pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
+       pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
+       pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
+       pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
+
+       /* Reset serdes */
+       pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
+
+       /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
+       value = PHY_SGMII_IF_MODE_SGMII;
+       if (!sgmii_2500)
+               value |= PHY_SGMII_IF_MODE_AN;
+       else
+               value |= PHY_SGMII_IF_MODE_SGMII_GBT;
+
+       pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+
+       /* Dev ability according to SGMII specification */
+       value = PHY_SGMII_DEV_ABILITY_SGMII;
+       pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+
+       /* These values taken from validation team */
+       if (!sgmii_2500) {
+               pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
+               pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
+       } else {
+               pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
+               pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
+       }
+
+       /* Restart AN */
+       value = PHY_SGMII_CR_DEF_VAL;
+       if (!sgmii_2500)
+               value |= PHY_SGMII_CR_RESET_AN;
+       /* Disable Auto neg for 2.5G SGMII as it doesn't support auto neg*/
+       if (sgmii_2500)
+               value &= ~PHY_SGMII_ENABLE_AN;
+       pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+}
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
+{
+       struct phy_device *phydev = NULL;
+       struct udevice *dev = priv->dev;
+       struct gemac_s *gem = priv->gem;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+       if (!gem->bus)
+               return -1;
+
+       /* Configure SGMII  PCS */
+       if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
+           gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
+               out_be32(&scfg->mdioselcr, 0x00000000);
+               pfe_configure_serdes(priv);
+       }
+
+       mdelay(100);
+
+       /* By this time on-chip SGMII initialization is done
+        * we can switch mdio interface to external PHYs
+        */
+       out_be32(&scfg->mdioselcr, 0x80000000);
+
+       phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
+       if (!phydev) {
+               printf("phy_connect failed\n");
+               return -ENODEV;
+       }
+
+       phy_config(phydev);
+
+       priv->phydev = phydev;
+
+       return 0;
+}
+#endif
+
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info)
+{
+       struct mii_dev *bus;
+       int ret;
+       u32 mdio_speed;
+       u32 pclk = 250000000;
+
+       bus = mdio_alloc();
+       if (!bus) {
+               printf("mdio_alloc failed\n");
+               return NULL;
+       }
+       bus->read = pfe_phy_read;
+       bus->write = pfe_phy_write;
+
+       /* MAC1 MDIO used to communicate with external PHYS */
+       bus->priv = mdio_info->reg_base;
+       sprintf(bus->name, mdio_info->name);
+
+       /* configure mdio speed */
+       mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
+       mdio_speed |= EMAC_HOLDTIME(0x5);
+       writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
+
+       ret = mdio_register(bus);
+       if (ret) {
+               printf("mdio_register failed\n");
+               free(bus);
+               return NULL;
+       }
+       return bus;
+}
+
+void pfe_set_mdio(int dev_id, struct mii_dev *bus)
+{
+       gem_info[dev_id].bus = bus;
+}
+
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
+{
+       gem_info[dev_id].phy_address = phy_id;
+       gem_info[dev_id].phy_mode  = phy_mode;
+}

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 25de3fb2266586bd2b234f81dda702fd68e95a2d..179e0418bca73f683929f1f5257e2e0ddc34bb2e 100644 (file)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -139,6 +139,16 @@ config PHY_NATSEMI
 config PHY_REALTEK
        bool "Realtek Ethernet PHYs support"
 
+config RTL8211E_PINE64_GIGABIT_FIX
+       bool "Fix gigabit throughput on some Pine64+ models"
+       depends on PHY_REALTEK
+       help
+         Configure the Realtek RTL8211E found on some Pine64+ models differently to
+         fix throughput on Gigabit links, turning off all internal delays in the
+         process. The settings that this touches are not documented in the CONFREG
+         section of the RTL8211E datasheet, but come from Realtek by way of the
+         Pine64 engineering team.
+
 config RTL8211X_PHY_FORCE_MASTER
        bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
        depends on PHY_REALTEK

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ad12f6d61fb27b0b132a307afc0f1606275f4893..6678147545699ba28a448f1b30c339b9af99ee3f 100644 (file)
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -7,6 +7,7 @@
  */
 #include <config.h>
 #include <common.h>
+#include <dm.h>
 #include <phy.h>
 
 #ifndef CONFIG_PHYLIB_10G

diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 637d89a1e1bcaa21509a25e6da996fac0d03ddb5..9cb3a52c208c72c652f00ad96d10af98c8252d28 100644 (file)
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:     GPL-2.0+
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  */
 
@@ -27,6 +28,7 @@
 #error The Cortina PHY needs 10G support
 #endif
 
+#ifndef CORTINA_NO_FW_UPLOAD
 struct cortina_reg_config cortina_reg_cfg[] = {
        /* CS4315_enable_sr_mode */
        {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@@ -215,12 +217,22 @@ void cs4340_upload_firmware(struct phy_device *phydev)
                phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
        }
 }
+#endif
 
 int cs4340_phy_init(struct phy_device *phydev)
 {
+#ifndef CORTINA_NO_FW_UPLOAD
        int timeout = 100;  /* 100ms */
+#endif
        int reg_value;
 
+       /*
+        * Cortina phy has provision to store
+        * phy firmware in attached dedicated EEPROM.
+        * Boards designed with EEPROM attached to Cortina
+        * does not require FW upload.
+        */
+#ifndef CORTINA_NO_FW_UPLOAD
        /* step1: BIST test */
        phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL,     0x0004);
        phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
@@ -241,6 +253,7 @@ int cs4340_phy_init(struct phy_device *phydev)
 
        /* setp2: upload ucode */
        cs4340_upload_firmware(phydev);
+#endif
        reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
        if (reg_value) {
                debug("%s checksum status failed.\n", __func__);
@@ -295,45 +308,33 @@ int phy_cortina_init(void)
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
        int phy_reg;
-       bool is_cortina_phy = false;
-
-       switch (addr) {
-#ifdef CORTINA_PHY_ADDR1
-       case CORTINA_PHY_ADDR1:
-#endif
-#ifdef CORTINA_PHY_ADDR2
-       case CORTINA_PHY_ADDR2:
-#endif
-#ifdef CORTINA_PHY_ADDR3
-       case CORTINA_PHY_ADDR3:
-#endif
-#ifdef CORTINA_PHY_ADDR4
-       case CORTINA_PHY_ADDR4:
-#endif
-               is_cortina_phy = true;
-               break;
-       default:
-               break;
-       }
 
        /* Cortina PHY has non-standard offset of PHY ID registers */
-       if (is_cortina_phy)
-               phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
-       else
-               phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+       phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
+       if (phy_reg < 0)
+               return -EIO;
+       *phy_id = (phy_reg & 0xffff) << 16;
 
+       phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
        if (phy_reg < 0)
                return -EIO;
+       *phy_id |= (phy_reg & 0xffff);
 
-       *phy_id = (phy_reg & 0xffff) << 16;
-       if (is_cortina_phy)
-               phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
-       else
-               phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+       if (*phy_id == PHY_UID_CS4340)
+               return 0;
 
+       /*
+        * If Cortina PHY not detected,
+        * try generic way to find PHY ID registers
+        */
+       phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
        if (phy_reg < 0)
                return -EIO;
+       *phy_id = (phy_reg & 0xffff) << 16;
 
+       phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+       if (phy_reg < 0)
+               return -EIO;
        *phy_id |= (phy_reg & 0xffff);
 
        return 0;

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 6d917f86f44d21537ffdd228316ec7e9ee86f9dc..d5c2a46c67e2b272644419cb96cfab8209a612c7 100644 (file)
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -13,6 +13,7 @@
 #include <phy.h>
 
 #define PHY_RTL8211x_FORCE_MASTER BIT(1)
+#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
 
 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
 
@@ -47,6 +48,13 @@
 #define MIIM_RTL8211F_PHYSTAT_SPDDONE  0x0800
 #define MIIM_RTL8211F_PHYSTAT_LINK     0x0004
 
+#define MIIM_RTL8211E_CONFREG           0x1c
+#define MIIM_RTL8211E_CONFREG_TXD              0x0002
+#define MIIM_RTL8211E_CONFREG_RXD              0x0004
+#define MIIM_RTL8211E_CONFREG_MAGIC            0xb400  /* Undocumented */
+
+#define MIIM_RTL8211E_EXT_PAGE_SELECT  0x1e
+
 #define MIIM_RTL8211F_PAGE_SELECT      0x1f
 #define MIIM_RTL8211F_TX_DELAY         0x100
 #define MIIM_RTL8211F_LCR              0x10
@@ -60,6 +68,15 @@ static int rtl8211b_probe(struct phy_device *phydev)
        return 0;
 }
 
+static int rtl8211e_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
+       phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
+#endif
+
+       return 0;
+}
+
 /* RealTek RTL8211x */
 static int rtl8211x_config(struct phy_device *phydev)
 {
@@ -81,6 +98,22 @@ static int rtl8211x_config(struct phy_device *phydev)
                reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
                phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
        }
+       if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
+               unsigned int reg;
+
+               phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
+                         7);
+               phy_write(phydev, MDIO_DEVAD_NONE,
+                         MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
+               reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
+               /* Ensure both internal delays are turned off */
+               reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
+               /* Flip the magic undocumented bits */
+               reg |= MIIM_RTL8211E_CONFREG_MAGIC;
+               phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
+               phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
+                         0);
+       }
        /* read interrupt status just to clear it */
        phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
 
@@ -279,6 +312,7 @@ static struct phy_driver RTL8211E_driver = {
        .uid = 0x1cc915,
        .mask = 0xffffff,
        .features = PHY_GBIT_FEATURES,
+       .probe = &rtl8211e_probe,
        .config = &rtl8211x_config,
        .startup = &rtl8211e_startup,
        .shutdown = &genphy_shutdown,

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 2cc49bca922a1f0896a9e6368813df77313b0661..1390c36c6141c610a47dfddd2e0e1164dad5888f 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -325,7 +325,8 @@ static int zynq_phy_init(struct udevice *dev)
        /* Enable only MDIO bus */
        writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-       if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+       if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
+           (priv->interface != PHY_INTERFACE_MODE_GMII)) {
                ret = phy_detection(dev);
                if (ret) {
                        printf("GEM PHY init failed\n");

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index da6421f35ccdf448b93fd188063cf17b2341253d..c20a0cc06077833a1db854f473ae32c206df9fe6 100644 (file)
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -26,6 +26,16 @@ config DM_PCI_COMPAT
          measure when porting a board to use driver model for PCI. Once the
          board is fully supported, this option should be disabled.
 
+config PCI_AARDVARK
+       bool "Enable Aardvark PCIe driver"
+       default n
+       depends on DM_PCI
+       depends on ARMADA_3700
+       help
+         Say Y here if you want to enable PCIe controller support on
+         Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
+         Aardvark hardware.
+
 config PCI_PNP
        bool "Enable Plug & Play support for PCI"
        depends on PCI || DM_PCI

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 8fbab462a4382cb11819bd14858ffa2bf598b49f..40ebc06f6dca15e6301e37c78314b652c9b178dd 100644 (file)
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_SH4_PCI) += pci_sh4.o
 obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
+obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o

diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
new file mode 100644 (file)
index 0000000..69a4d81
--- /dev/null
+++ b/drivers/pci/pci-aardvark.c
@@ -0,0 +1,690 @@
+/*
+ * ***************************************************************************
+ * Copyright (C) 2015 Marvell International Ltd.
+ * ***************************************************************************
+ * This program is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation, either version 2 of the License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * ***************************************************************************
+ */
+/* pcie_advk.c
+ *
+ * Ported from Linux driver - driver/pci/host/pci-aardvark.c
+ *
+ * Author: Victor Gu <xigu@marvell.com>
+ *         Hezi Shahmoon <hezi.shahmoon@marvell.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <linux/ioport.h>
+
+/* PCIe core registers */
+#define PCIE_CORE_CMD_STATUS_REG                               0x4
+#define     PCIE_CORE_CMD_IO_ACCESS_EN                         BIT(0)
+#define     PCIE_CORE_CMD_MEM_ACCESS_EN                                BIT(1)
+#define     PCIE_CORE_CMD_MEM_IO_REQ_EN                                BIT(2)
+#define PCIE_CORE_DEV_CTRL_STATS_REG                           0xc8
+#define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE       (0 << 4)
+#define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE             (0 << 11)
+#define PCIE_CORE_LINK_CTRL_STAT_REG                           0xd0
+#define     PCIE_CORE_LINK_TRAINING                            BIT(5)
+#define PCIE_CORE_ERR_CAPCTL_REG                               0x118
+#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX                   BIT(5)
+#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN                        BIT(6)
+#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHECK                    BIT(7)
+#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV                        BIT(8)
+
+/* PIO registers base address and register offsets */
+#define PIO_BASE_ADDR                          0x4000
+#define PIO_CTRL                               (PIO_BASE_ADDR + 0x0)
+#define   PIO_CTRL_TYPE_MASK                   GENMASK(3, 0)
+#define   PIO_CTRL_ADDR_WIN_DISABLE            BIT(24)
+#define PIO_STAT                               (PIO_BASE_ADDR + 0x4)
+#define   PIO_COMPLETION_STATUS_SHIFT          7
+#define   PIO_COMPLETION_STATUS_MASK           GENMASK(9, 7)
+#define   PIO_COMPLETION_STATUS_OK             0
+#define   PIO_COMPLETION_STATUS_UR             1
+#define   PIO_COMPLETION_STATUS_CRS            2
+#define   PIO_COMPLETION_STATUS_CA             4
+#define   PIO_NON_POSTED_REQ                   BIT(10)
+#define   PIO_ERR_STATUS                       BIT(11)
+#define PIO_ADDR_LS                            (PIO_BASE_ADDR + 0x8)
+#define PIO_ADDR_MS                            (PIO_BASE_ADDR + 0xc)
+#define PIO_WR_DATA                            (PIO_BASE_ADDR + 0x10)
+#define PIO_WR_DATA_STRB                       (PIO_BASE_ADDR + 0x14)
+#define PIO_RD_DATA                            (PIO_BASE_ADDR + 0x18)
+#define PIO_START                              (PIO_BASE_ADDR + 0x1c)
+#define PIO_ISR                                        (PIO_BASE_ADDR + 0x20)
+
+/* Aardvark Control registers */
+#define CONTROL_BASE_ADDR                      0x4800
+#define PCIE_CORE_CTRL0_REG                    (CONTROL_BASE_ADDR + 0x0)
+#define     PCIE_GEN_SEL_MSK                   0x3
+#define     PCIE_GEN_SEL_SHIFT                 0x0
+#define     SPEED_GEN_1                                0
+#define     SPEED_GEN_2                                1
+#define     SPEED_GEN_3                                2
+#define     IS_RC_MSK                          1
+#define     IS_RC_SHIFT                                2
+#define     LANE_CNT_MSK                       0x18
+#define     LANE_CNT_SHIFT                     0x3
+#define     LANE_COUNT_1                       (0 << LANE_CNT_SHIFT)
+#define     LANE_COUNT_2                       (1 << LANE_CNT_SHIFT)
+#define     LANE_COUNT_4                       (2 << LANE_CNT_SHIFT)
+#define     LANE_COUNT_8                       (3 << LANE_CNT_SHIFT)
+#define     LINK_TRAINING_EN                   BIT(6)
+#define PCIE_CORE_CTRL2_REG                    (CONTROL_BASE_ADDR + 0x8)
+#define     PCIE_CORE_CTRL2_RESERVED           0x7
+#define     PCIE_CORE_CTRL2_TD_ENABLE          BIT(4)
+#define     PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE        BIT(5)
+#define     PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
+
+/* LMI registers base address and register offsets */
+#define LMI_BASE_ADDR                          0x6000
+#define CFG_REG                                        (LMI_BASE_ADDR + 0x0)
+#define     LTSSM_SHIFT                                24
+#define     LTSSM_MASK                         0x3f
+#define     LTSSM_L0                           0x10
+
+/* PCIe core controller registers */
+#define CTRL_CORE_BASE_ADDR                    0x18000
+#define CTRL_CONFIG_REG                                (CTRL_CORE_BASE_ADDR + 0x0)
+#define     CTRL_MODE_SHIFT                    0x0
+#define     CTRL_MODE_MASK                     0x1
+#define     PCIE_CORE_MODE_DIRECT              0x0
+#define     PCIE_CORE_MODE_COMMAND             0x1
+
+/* Transaction types */
+#define PCIE_CONFIG_RD_TYPE0                   0x8
+#define PCIE_CONFIG_RD_TYPE1                   0x9
+#define PCIE_CONFIG_WR_TYPE0                   0xa
+#define PCIE_CONFIG_WR_TYPE1                   0xb
+
+/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
+#define PCIE_BDF(dev)                          (dev << 4)
+#define PCIE_CONF_BUS(bus)                     (((bus) & 0xff) << 20)
+#define PCIE_CONF_DEV(dev)                     (((dev) & 0x1f) << 15)
+#define PCIE_CONF_FUNC(fun)                    (((fun) & 0x7)  << 12)
+#define PCIE_CONF_REG(reg)                     ((reg) & 0xffc)
+#define PCIE_CONF_ADDR(bus, devfn, where)      \
+       (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
+        PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
+
+/* PCIe Retries & Timeout definitions */
+#define MAX_RETRIES                            10
+#define PIO_WAIT_TIMEOUT                       100
+#define LINK_WAIT_TIMEOUT                      100000
+
+#define CFG_RD_UR_VAL                  0xFFFFFFFF
+#define CFG_RD_CRS_VAL                 0xFFFF0001
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct pcie_advk - Advk PCIe controller state
+ *
+ * @reg_base:    The base address of the register space.
+ * @first_busno: This driver supports multiple PCIe controllers.
+ *               first_busno stores the bus number of the PCIe root-port
+ *               number which may vary depending on the PCIe setup
+ *               (PEX switches etc).
+ * @device:      The pointer to PCI uclass device.
+ */
+struct pcie_advk {
+       void           *base;
+       int            first_busno;
+       struct udevice *dev;
+};
+
+static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
+{
+       writel(val, pcie->base + reg);
+}
+
+static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
+{
+       return readl(pcie->base + reg);
+}
+
+/**
+ * pcie_advk_addr_valid() - Check for valid bus address
+ *
+ * @bdf: The PCI device to access
+ * @first_busno: Bus number of the PCIe controller root complex
+ *
+ * Return: 1 on valid, 0 on invalid
+ */
+static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
+{
+       /*
+        * In PCIE-E only a single device (0) can exist
+        * on the local bus. Beyound the local bus, there might be
+        * a Switch and everything is possible.
+        */
+       if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+               return 0;
+
+       return 1;
+}
+
+/**
+ * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
+ *
+ * @pcie: The PCI device to access
+ *
+ * Wait up to 1 micro second for PIO access to be accomplished.
+ *
+ * Return 1 (true) if PIO access is accomplished.
+ * Return 0 (false) if PIO access is timed out.
+ */
+static int pcie_advk_wait_pio(struct pcie_advk *pcie)
+{
+       uint start, isr;
+       uint count;
+
+       for (count = 0; count < MAX_RETRIES; count++) {
+               start = advk_readl(pcie, PIO_START);
+               isr = advk_readl(pcie, PIO_ISR);
+               if (!start && isr)
+                       return 1;
+               /*
+                * Do not check the PIO state too frequently,
+                * 100us delay is appropriate.
+                */
+               udelay(PIO_WAIT_TIMEOUT);
+       }
+
+       dev_err(pcie->dev, "config read/write timed out\n");
+       return 0;
+}
+
+/**
+ * pcie_advk_check_pio_status() - Validate PIO status and get the read result
+ *
+ * @pcie: Pointer to the PCI bus
+ * @read: Read from or write to configuration space - true(read) false(write)
+ * @read_val: Pointer to the read result, only valid when read is true
+ *
+ */
+static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
+                                     bool read,
+                                     uint *read_val)
+{
+       uint reg;
+       unsigned int status;
+       char *strcomp_status, *str_posted;
+
+       reg = advk_readl(pcie, PIO_STAT);
+       status = (reg & PIO_COMPLETION_STATUS_MASK) >>
+               PIO_COMPLETION_STATUS_SHIFT;
+
+       switch (status) {
+       case PIO_COMPLETION_STATUS_OK:
+               if (reg & PIO_ERR_STATUS) {
+                       strcomp_status = "COMP_ERR";
+                       break;
+               }
+               /* Get the read result */
+               if (read)
+                       *read_val = advk_readl(pcie, PIO_RD_DATA);
+               /* No error */
+               strcomp_status = NULL;
+               break;
+       case PIO_COMPLETION_STATUS_UR:
+               if (read) {
+                       /* For reading, UR is not an error status. */
+                       *read_val = CFG_RD_UR_VAL;
+                       strcomp_status = NULL;
+               } else {
+                       strcomp_status = "UR";
+               }
+               break;
+       case PIO_COMPLETION_STATUS_CRS:
+               if (read) {
+                       /* For reading, CRS is not an error status. */
+                       *read_val = CFG_RD_CRS_VAL;
+                       strcomp_status = NULL;
+               } else {
+                       strcomp_status = "CRS";
+               }
+               break;
+       case PIO_COMPLETION_STATUS_CA:
+               strcomp_status = "CA";
+               break;
+       default:
+               strcomp_status = "Unknown";
+               break;
+       }
+
+       if (!strcomp_status)
+               return 0;
+
+       if (reg & PIO_NON_POSTED_REQ)
+               str_posted = "Non-posted";
+       else
+               str_posted = "Posted";
+
+       dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
+               str_posted, strcomp_status, reg,
+               advk_readl(pcie, PIO_ADDR_LS));
+
+       return -EFAULT;
+}
+
+/**
+ * pcie_advk_read_config() - Read from configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_advk_read_config(struct udevice *bus, pci_dev_t bdf,
+                                uint offset, ulong *valuep,
+                                enum pci_size_t size)
+{
+       struct pcie_advk *pcie = dev_get_priv(bus);
+       uint reg;
+       int ret;
+
+       dev_dbg(pcie->dev, "PCIE CFG read:  (b,d,f)=(%2d,%2d,%2d) ",
+               PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+       if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+               dev_dbg(pcie->dev, "- out of range\n");
+               *valuep = pci_get_ff(size);
+               return 0;
+       }
+
+       /* Start PIO */
+       advk_writel(pcie, 0, PIO_START);
+       advk_writel(pcie, 1, PIO_ISR);
+
+       /* Program the control register */
+       reg = advk_readl(pcie, PIO_CTRL);
+       reg &= ~PIO_CTRL_TYPE_MASK;
+       if (PCI_BUS(bdf) == pcie->first_busno)
+               reg |= PCIE_CONFIG_RD_TYPE0;
+       else
+               reg |= PCIE_CONFIG_RD_TYPE1;
+       advk_writel(pcie, reg, PIO_CTRL);
+
+       /* Program the address registers */
+       reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+       advk_writel(pcie, reg, PIO_ADDR_LS);
+       advk_writel(pcie, 0, PIO_ADDR_MS);
+
+       /* Start the transfer */
+       advk_writel(pcie, 1, PIO_START);
+
+       if (!pcie_advk_wait_pio(pcie))
+               return -EINVAL;
+
+       /* Check PIO status and get the read result */
+       ret = pcie_advk_check_pio_status(pcie, true, &reg);
+       if (ret)
+               return ret;
+
+       dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
+               offset, size, reg);
+       *valuep = pci_conv_32_to_size(reg, offset, size);
+
+       return 0;
+}
+
+/**
+ * pcie_calc_datastrobe() - Calculate data strobe
+ *
+ * @offset: The offset into the device's configuration space
+ * @size: Indicates the size of access to perform
+ *
+ * Calculate data strobe according to offset and size
+ *
+ */
+static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
+{
+       uint bytes, data_strobe;
+
+       switch (size) {
+       case PCI_SIZE_8:
+               bytes = 1;
+               break;
+       case PCI_SIZE_16:
+               bytes = 2;
+               break;
+       default:
+               bytes = 4;
+       }
+
+       data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
+
+       return data_strobe;
+}
+
+/**
+ * pcie_advk_write_config() - Write to configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
+                                 uint offset, ulong value,
+                                 enum pci_size_t size)
+{
+       struct pcie_advk *pcie = dev_get_priv(bus);
+       uint reg;
+
+       dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+               PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+       dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
+               offset, size, value);
+
+       if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
+               dev_dbg(pcie->dev, "- out of range\n");
+               return 0;
+       }
+
+       /* Start PIO */
+       advk_writel(pcie, 0, PIO_START);
+       advk_writel(pcie, 1, PIO_ISR);
+
+       /* Program the control register */
+       reg = advk_readl(pcie, PIO_CTRL);
+       reg &= ~PIO_CTRL_TYPE_MASK;
+       if (PCI_BUS(bdf) == pcie->first_busno)
+               reg |= PCIE_CONFIG_WR_TYPE0;
+       else
+               reg |= PCIE_CONFIG_WR_TYPE1;
+       advk_writel(pcie, reg, PIO_CTRL);
+
+       /* Program the address registers */
+       reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
+       advk_writel(pcie, reg, PIO_ADDR_LS);
+       advk_writel(pcie, 0, PIO_ADDR_MS);
+       dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
+
+       /* Program the data register */
+       reg = pci_conv_size_to_32(0, value, offset, size);
+       advk_writel(pcie, reg, PIO_WR_DATA);
+       dev_dbg(pcie->dev, "\tPIO req. - val  = 0x%08x\n", reg);
+
+       /* Program the data strobe */
+       reg = pcie_calc_datastrobe(offset, size);
+       advk_writel(pcie, reg, PIO_WR_DATA_STRB);
+       dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
+
+       /* Start the transfer */
+       advk_writel(pcie, 1, PIO_START);
+
+       if (!pcie_advk_wait_pio(pcie)) {
+               dev_dbg(pcie->dev, "- wait pio timeout\n");
+               return -EINVAL;
+       }
+
+       /* Check PIO status */
+       pcie_advk_check_pio_status(pcie, false, &reg);
+
+       return 0;
+}
+
+/**
+ * pcie_advk_link_up() - Check if PCIe link is up or not
+ *
+ * @pcie: The PCI device to access
+ *
+ * Return 1 (true) on link up.
+ * Return 0 (false) on link down.
+ */
+static int pcie_advk_link_up(struct pcie_advk *pcie)
+{
+       u32 val, ltssm_state;
+
+       val = advk_readl(pcie, CFG_REG);
+       ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
+       return ltssm_state >= LTSSM_L0;
+}
+
+/**
+ * pcie_advk_wait_for_link() - Wait for link training to be accomplished
+ *
+ * @pcie: The PCI device to access
+ *
+ * Wait up to 1 second for link training to be accomplished.
+ *
+ * Return 1 (true) if link training ends up with link up success.
+ * Return 0 (false) if link training ends up with link up failure.
+ */
+static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
+{
+       int retries;
+
+       /* check if the link is up or not */
+       for (retries = 0; retries < MAX_RETRIES; retries++) {
+               if (pcie_advk_link_up(pcie)) {
+                       printf("PCIE-%d: Link up\n", pcie->first_busno);
+                       return 0;
+               }
+
+               udelay(LINK_WAIT_TIMEOUT);
+       }
+
+       printf("PCIE-%d: Link down\n", pcie->first_busno);
+
+       return -ETIMEDOUT;
+}
+
+/**
+ * pcie_advk_setup_hw() - PCIe initailzation
+ *
+ * @pcie: The PCI device to access
+ *
+ * Return: 0 on success
+ */
+static int pcie_advk_setup_hw(struct pcie_advk *pcie)
+{
+       u32 reg;
+
+       /* Set to Direct mode */
+       reg = advk_readl(pcie, CTRL_CONFIG_REG);
+       reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
+       reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
+       advk_writel(pcie, reg, CTRL_CONFIG_REG);
+
+       /* Set PCI global control register to RC mode */
+       reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+       reg |= (IS_RC_MSK << IS_RC_SHIFT);
+       advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+       /* Set Advanced Error Capabilities and Control PF0 register */
+       reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
+               PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
+               PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
+               PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
+       advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
+
+       /* Set PCIe Device Control and Status 1 PF0 register */
+       reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
+               PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
+       advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+
+       /* Program PCIe Control 2 to disable strict ordering */
+       reg = PCIE_CORE_CTRL2_RESERVED |
+               PCIE_CORE_CTRL2_TD_ENABLE;
+       advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+
+       /* Set GEN2 */
+       reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+       reg &= ~PCIE_GEN_SEL_MSK;
+       reg |= SPEED_GEN_2;
+       advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+       /* Set lane X1 */
+       reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+       reg &= ~LANE_CNT_MSK;
+       reg |= LANE_COUNT_1;
+       advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+       /* Enable link training */
+       reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+       reg |= LINK_TRAINING_EN;
+       advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+       /*
+        * Enable AXI address window location generation:
+        * When it is enabled, the default outbound window
+        * configurations (Default User Field: 0xD0074CFC)
+        * are used to transparent address translation for
+        * the outbound transactions. Thus, PCIe address
+        * windows are not required.
+        */
+       reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
+       reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
+       advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+
+       /*
+        * Bypass the address window mapping for PIO:
+        * Since PIO access already contains all required
+        * info over AXI interface by PIO registers, the
+        * address window is not required.
+        */
+       reg = advk_readl(pcie, PIO_CTRL);
+       reg |= PIO_CTRL_ADDR_WIN_DISABLE;
+       advk_writel(pcie, reg, PIO_CTRL);
+
+       /* Start link training */
+       reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
+       reg |= PCIE_CORE_LINK_TRAINING;
+       advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
+
+       /* Wait for PCIe link up */
+       if (pcie_advk_wait_for_link(pcie))
+               return -ENXIO;
+
+       reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
+       reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
+               PCIE_CORE_CMD_IO_ACCESS_EN |
+               PCIE_CORE_CMD_MEM_IO_REQ_EN;
+       advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
+
+       return 0;
+}
+
+/**
+ * pcie_advk_probe() - Probe the PCIe bus for active link
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Probe for an active link on the PCIe bus and configure the controller
+ * to enable this port.
+ *
+ * Return: 0 on success, else -ENODEV
+ */
+static int pcie_advk_probe(struct udevice *dev)
+{
+       struct pcie_advk *pcie = dev_get_priv(dev);
+
+#ifdef CONFIG_DM_GPIO
+       struct gpio_desc reset_gpio;
+
+       gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
+                            GPIOD_IS_OUT);
+       /*
+        * Issue reset to add-in card through the dedicated GPIO.
+        * Some boards are connecting the card reset pin to common system
+        * reset wire and others are using separate GPIO port.
+        * In the last case we have to release a reset of the addon card
+        * using this GPIO.
+        *
+        * FIX-ME:
+        *     The PCIe RESET signal is not supposed to be released along
+        *     with the SOC RESET signal. It should be lowered as early as
+        *     possible before PCIe PHY initialization. Moreover, the PCIe
+        *     clock should be gated as well.
+        */
+       if (dm_gpio_is_valid(&reset_gpio)) {
+               dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
+               dm_gpio_set_value(&reset_gpio, 0);
+               mdelay(200);
+               dm_gpio_set_value(&reset_gpio, 1);
+       }
+#else
+       dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
+#endif /* CONFIG_DM_GPIO */
+
+       pcie->first_busno = dev->seq;
+       pcie->dev = pci_get_controller(dev);
+
+       return pcie_advk_setup_hw(pcie);
+}
+
+/**
+ * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
+{
+       struct pcie_advk *pcie = dev_get_priv(dev);
+
+       /* Get the register base address */
+       pcie->base = (void *)dev_read_addr_index(dev, 0);
+       if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       return 0;
+}
+
+static const struct dm_pci_ops pcie_advk_ops = {
+       .read_config    = pcie_advk_read_config,
+       .write_config   = pcie_advk_write_config,
+};
+
+static const struct udevice_id pcie_advk_ids[] = {
+       { .compatible = "marvell,armada-37xx-pcie" },
+       { }
+};
+
+U_BOOT_DRIVER(pcie_advk) = {
+       .name                   = "pcie_advk",
+       .id                     = UCLASS_PCI,
+       .of_match               = pcie_advk_ids,
+       .ops                    = &pcie_advk_ops,
+       .ofdata_to_platdata     = pcie_advk_ofdata_to_platdata,
+       .probe                  = pcie_advk_probe,
+       .priv_auto_alloc_size   = sizeof(struct pcie_advk),
+};

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index ad43e8a27cc12404a0b198ece82e0dd8760ea75b..a2e829608a34f25c7d45673991a764ae523bc5ee 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -876,6 +876,9 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
 #ifdef CONFIG_NR_DRAM_BANKS
        bd_t *bd = gd->bd;
 
+       if (!bd)
+               return 0;
+
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
                if (bd->bi_dram[i].size) {
                        pci_set_region(hose->regions + hose->region_count++,
@@ -894,8 +897,9 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
 #endif
        if (gd->pci_ram_top && gd->pci_ram_top < base + size)
                size = gd->pci_ram_top - base;
-       pci_set_region(hose->regions + hose->region_count++, base, base,
-                      size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+       if (size)
+               pci_set_region(hose->regions + hose->region_count++, base,
+                       base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 #endif
 
        return 0;

diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index a19885501cab6a82d8f5e781e3b21d26041b7cf0..a0032b7b038d984e733c563631a58d1d3ec9bff0 100644 (file)
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -111,6 +111,10 @@ struct pcie_dw_mvebu {
        void *cfg_base;
        fdt_size_t cfg_size;
        int first_busno;
+
+       /* IO and MEM PCI regions */
+       struct pci_region io;
+       struct pci_region mem;
 };
 
 static int pcie_dw_get_link_speed(const void *regs_base)
@@ -125,6 +129,34 @@ static int pcie_dw_get_link_width(const void *regs_base)
                PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
 }
 
+/**
+ * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
+ *
+ * @pcie: Pointer to the PCI controller state
+ * @index: ATU region index
+ * @type: ATU accsess type
+ * @cpu_addr: the physical address for the translation entry
+ * @pci_addr: the pcie bus address for the translation entry
+ * @size: the size of the translation entry
+ */
+static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
+                                     int type, u64 cpu_addr, u64 pci_addr,
+                                     u32 size)
+{
+       writel(PCIE_ATU_REGION_OUTBOUND | index,
+              pcie->ctrl_base + PCIE_ATU_VIEWPORT);
+       writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
+       writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
+       writel(lower_32_bits(cpu_addr + size - 1),
+              pcie->ctrl_base + PCIE_ATU_LIMIT);
+       writel(lower_32_bits(pci_addr),
+              pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
+       writel(upper_32_bits(pci_addr),
+              pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
+       writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
+       writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
+}
+
 /**
  * set_cfg_address() - Configure the PCIe controller config space access
  *
@@ -143,27 +175,29 @@ static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
                                 pci_dev_t d, uint where)
 {
        uintptr_t va_address;
+       u32 atu_type;
 
        /*
         * Region #0 is used for Outbound CFG space access.
         * Direction = Outbound
         * Region Index = 0
         */
-       writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
 
        if (PCI_BUS(d) == (pcie->first_busno + 1))
                /* For local bus, change TLP Type field to 4. */
-               writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
+               atu_type = PCIE_ATU_TYPE_CFG0;
        else
                /* Otherwise, change TLP Type field to 5. */
-               writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1);
+               atu_type = PCIE_ATU_TYPE_CFG1;
 
        if (PCI_BUS(d) == pcie->first_busno) {
                /* Accessing root port configuration space. */
                va_address = (uintptr_t)pcie->ctrl_base;
        } else {
                d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
-               writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
+               pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+                                         atu_type, (u64)pcie->cfg_base,
+                                         d << 8, pcie->cfg_size);
                va_address = (uintptr_t)pcie->cfg_base;
        }
 
@@ -231,6 +265,10 @@ static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf,
        debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
        *valuep = pci_conv_32_to_size(value, offset, size);
 
+       pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+                                 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+                                 pcie->io.bus_start, pcie->io.size);
+
        return 0;
 }
 
@@ -272,6 +310,10 @@ static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
        value = pci_conv_size_to_32(old, value, offset, size);
        writel(value, va_address);
 
+       pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+                                 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+                                 pcie->io.bus_start, pcie->io.size);
+
        return 0;
 }
 
@@ -387,34 +429,6 @@ static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
        return 1;
 }
 
-/**
- * pcie_dw_regions_setup() - iATU region setup
- *
- * @pcie: Pointer to the PCI controller state
- *
- * Configure the iATU regions in the PCIe controller for outbound access.
- */
-static void pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie)
-{
-       /*
-        * Region #0 is used for Outbound CFG space access.
-        * Direction = Outbound
-        * Region Index = 0
-        */
-       writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
-
-       writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base
-              + PCIE_ATU_LOWER_BASE);
-       writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
-       writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size,
-              pcie->ctrl_base + PCIE_ATU_LIMIT);
-
-       writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
-       writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
-       writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
-       writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
-}
-
 /**
  * pcie_dw_set_host_bars() - Configure the host BARs
  *
@@ -495,7 +509,18 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
                       hose->first_busno);
        }
 
-       pcie_dw_regions_setup(pcie);
+       /* Store the IO and MEM windows settings for future use by the ATU */
+       pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
+       pcie->io.bus_start  = hose->regions[0].bus_start;  /* IO_bus_addr */
+       pcie->io.size       = hose->regions[0].size;       /* IO size */
+
+       pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
+       pcie->mem.bus_start  = hose->regions[1].bus_start;  /* MEM_bus_addr */
+       pcie->mem.size       = hose->regions[1].size;       /* MEM size */
+
+       pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
+                                 PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
+                                 pcie->mem.bus_start, pcie->mem.size);
 
        /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
        clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3b9a09ce181ab28faf947151e7e2e07708aab9ff..4e9d09910c32afdf34cf5810e100cdd8258f939d 100644 (file)
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -59,6 +59,31 @@ config SPL_NOP_PHY
          This is useful when a driver uses the PHY framework but no real PHY
          hardware exists.
 
+config BCM6318_USBH_PHY
+       bool "BCM6318 USBH PHY support"
+       depends on PHY && ARCH_BMIPS
+       select POWER_DOMAIN
+       help
+         Support for the Broadcom MIPS BCM6318 USBH PHY.
+
+config BCM6348_USBH_PHY
+       bool "BCM6348 USBH PHY support"
+       depends on PHY && ARCH_BMIPS
+       help
+         Support for the Broadcom MIPS BCM6348 USBH PHY.
+
+config BCM6358_USBH_PHY
+       bool "BCM6358 USBH PHY support"
+       depends on PHY && ARCH_BMIPS
+       help
+         Support for the Broadcom MIPS BCM6358 USBH PHY.
+
+config BCM6368_USBH_PHY
+       bool "BCM6368 USBH PHY support"
+       depends on PHY && ARCH_BMIPS
+       help
+         Support for the Broadcom MIPS BCM6368 USBH PHY.
+
 config PIPE3_PHY
        bool "Support omap's PIPE3 PHY"
        depends on PHY && ARCH_OMAP2PLUS

diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 668040b0bb764a87981e5f2e8cf18a5283cc686c..68087ae3b134d25304808172e7d20be9066dc004 100644 (file)
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,10 @@
 
 obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
 obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
+obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
+obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
+obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
+obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o

diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c
new file mode 100644 (file)
index 0000000..6d54214
--- /dev/null
+++ b/drivers/phy/bcm6318-usbh-phy.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ *     Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ *     Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH Setup register */
+#define USBH_SETUP_REG         0x00
+#define USBH_SETUP_IOC         BIT(4)
+
+/* USBH PLL Control register */
+#define USBH_PLL_REG           0x04
+#define USBH_PLL_SUSP_EN       BIT(27)
+#define USBH_PLL_IDDQ_PWRDN    BIT(31)
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG          0x0c
+#define USBH_SWAP_OHCI_DATA    BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN  BIT(1)
+#define USBH_SWAP_EHCI_DATA    BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN  BIT(4)
+
+/* USBH Sim Control register */
+#define USBH_SIM_REG           0x20
+#define USBH_SIM_LADDR         BIT(5)
+
+struct bcm6318_usbh_priv {
+       void __iomem *regs;
+};
+
+static int bcm6318_usbh_init(struct phy *phy)
+{
+       struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);
+
+       /* enable pll control susp */
+       setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);
+
+       /* configure to work in native cpu endian */
+       clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+                       USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+                       USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+       /* setup config */
+       setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
+
+       /* disable pll control pwrdn */
+       clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);
+
+       /* sim control config */
+       setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
+
+       return 0;
+}
+
+static struct phy_ops bcm6318_usbh_ops = {
+       .init = bcm6318_usbh_init,
+};
+
+static const struct udevice_id bcm6318_usbh_ids[] = {
+       { .compatible = "brcm,bcm6318-usbh" },
+       { /* sentinel */ }
+};
+
+static int bcm6318_usbh_probe(struct udevice *dev)
+{
+       struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
+       struct power_domain pwr_dom;
+       struct reset_ctl rst_ctl;
+       struct clk clk;
+       fdt_addr_t addr;
+       fdt_size_t size;
+       int ret;
+
+       addr = devfdt_get_addr_size_index(dev, 0, &size);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->regs = ioremap(addr, size);
+
+       /* enable usbh clock */
+       ret = clk_get_by_name(dev, "usbh", &clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_enable(&clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_free(&clk);
+       if (ret < 0)
+               return ret;
+
+       /* enable power domain */
+       ret = power_domain_get(dev, &pwr_dom);
+       if (ret < 0)
+               return ret;
+
+       ret = power_domain_on(&pwr_dom);
+       if (ret < 0)
+               return ret;
+
+       ret = power_domain_free(&pwr_dom);
+       if (ret < 0)
+               return ret;
+
+       /* perform reset */
+       ret = reset_get_by_index(dev, 0, &rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_deassert(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_free(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       mdelay(100);
+
+       return 0;
+}
+
+U_BOOT_DRIVER(bcm6318_usbh) = {
+       .name = "bcm6318-usbh",
+       .id = UCLASS_PHY,
+       .of_match = bcm6318_usbh_ids,
+       .ops = &bcm6318_usbh_ops,
+       .priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
+       .probe = bcm6318_usbh_probe,
+};

diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c
new file mode 100644 (file)
index 0000000..169ee0e
--- /dev/null
+++ b/drivers/phy/bcm6348-usbh-phy.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ *     Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ *     Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+#define USBH_SETUP_PORT1_EN    BIT(0)
+
+struct bcm6348_usbh_priv {
+       void __iomem *regs;
+};
+
+static int bcm6348_usbh_init(struct phy *phy)
+{
+       struct bcm6348_usbh_priv *priv = dev_get_priv(phy->dev);
+
+       writel_be(USBH_SETUP_PORT1_EN, priv->regs);
+
+       return 0;
+}
+
+static struct phy_ops bcm6348_usbh_ops = {
+       .init = bcm6348_usbh_init,
+};
+
+static const struct udevice_id bcm6348_usbh_ids[] = {
+       { .compatible = "brcm,bcm6348-usbh" },
+       { /* sentinel */ }
+};
+
+static int bcm6348_usbh_probe(struct udevice *dev)
+{
+       struct bcm6348_usbh_priv *priv = dev_get_priv(dev);
+       struct reset_ctl rst_ctl;
+       struct clk clk;
+       fdt_addr_t addr;
+       fdt_size_t size;
+       int ret;
+
+       addr = devfdt_get_addr_size_index(dev, 0, &size);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->regs = ioremap(addr, size);
+
+       /* enable usbh clock */
+       ret = clk_get_by_name(dev, "usbh", &clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_enable(&clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_free(&clk);
+       if (ret < 0)
+               return ret;
+
+       /* perform reset */
+       ret = reset_get_by_index(dev, 0, &rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_deassert(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_free(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
+
+U_BOOT_DRIVER(bcm6348_usbh) = {
+       .name = "bcm6348-usbh",
+       .id = UCLASS_PHY,
+       .of_match = bcm6348_usbh_ids,
+       .ops = &bcm6348_usbh_ops,
+       .priv_auto_alloc_size = sizeof(struct bcm6348_usbh_priv),
+       .probe = bcm6348_usbh_probe,
+};

diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c
new file mode 100644 (file)
index 0000000..e000316
--- /dev/null
+++ b/drivers/phy/bcm6358-usbh-phy.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ *     Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ *     Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG          0x00
+#define USBH_SWAP_OHCI_DATA    BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN  BIT(1)
+#define USBH_SWAP_EHCI_DATA    BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN  BIT(4)
+
+/* USBH Test register */
+#define USBH_TEST_REG          0x24
+#define USBH_TEST_PORT_CTL     0x1c0020
+
+struct bcm6358_usbh_priv {
+       void __iomem *regs;
+};
+
+static int bcm6358_usbh_init(struct phy *phy)
+{
+       struct bcm6358_usbh_priv *priv = dev_get_priv(phy->dev);
+
+       /* configure to work in native cpu endian */
+       clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+                       USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+                       USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+       /* test port control */
+       writel_be(USBH_TEST_PORT_CTL, priv->regs + USBH_TEST_REG);
+
+       return 0;
+}
+
+static struct phy_ops bcm6358_usbh_ops = {
+       .init = bcm6358_usbh_init,
+};
+
+static const struct udevice_id bcm6358_usbh_ids[] = {
+       { .compatible = "brcm,bcm6358-usbh" },
+       { /* sentinel */ }
+};
+
+static int bcm6358_usbh_probe(struct udevice *dev)
+{
+       struct bcm6358_usbh_priv *priv = dev_get_priv(dev);
+       struct reset_ctl rst_ctl;
+       fdt_addr_t addr;
+       fdt_size_t size;
+       int ret;
+
+       addr = devfdt_get_addr_size_index(dev, 0, &size);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->regs = ioremap(addr, size);
+
+       /* perform reset */
+       ret = reset_get_by_index(dev, 0, &rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_deassert(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_free(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
+
+U_BOOT_DRIVER(bcm6358_usbh) = {
+       .name = "bcm6358-usbh",
+       .id = UCLASS_PHY,
+       .of_match = bcm6358_usbh_ids,
+       .ops = &bcm6358_usbh_ops,
+       .priv_auto_alloc_size = sizeof(struct bcm6358_usbh_priv),
+       .probe = bcm6358_usbh_probe,
+};

diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c
new file mode 100644 (file)
index 0000000..71abc0f
--- /dev/null
+++ b/drivers/phy/bcm6368-usbh-phy.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ *     Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ *     Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH PLL Control register */
+#define USBH_PLL_REG           0x18
+#define USBH_PLL_IDDQ_PWRDN    BIT(9)
+#define USBH_PLL_PWRDN_DELAY   BIT(10)
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG          0x1c
+#define USBH_SWAP_OHCI_DATA    BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN  BIT(1)
+#define USBH_SWAP_EHCI_DATA    BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN  BIT(4)
+
+/* USBH Setup register */
+#define USBH_SETUP_REG         0x28
+#define USBH_SETUP_IOC         BIT(4)
+#define USBH_SETUP_IPP         BIT(5)
+
+struct bcm6368_usbh_hw {
+       uint32_t setup_clr;
+       uint32_t pll_clr;
+};
+
+struct bcm6368_usbh_priv {
+       const struct bcm6368_usbh_hw *hw;
+       void __iomem *regs;
+};
+
+static int bcm6368_usbh_init(struct phy *phy)
+{
+       struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
+       const struct bcm6368_usbh_hw *hw = priv->hw;
+
+       /* configure to work in native cpu endian */
+       clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+                       USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+                       USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+       /* setup config */
+       if (hw->setup_clr)
+               clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
+
+       setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
+
+       /* enable pll control */
+       if (hw->pll_clr)
+               clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
+
+       return 0;
+}
+
+static struct phy_ops bcm6368_usbh_ops = {
+       .init = bcm6368_usbh_init,
+};
+
+static const struct bcm6368_usbh_hw bcm6328_hw = {
+       .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
+       .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm6362_hw = {
+       .pll_clr = 0,
+       .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm6368_hw = {
+       .pll_clr = 0,
+       .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm63268_hw = {
+       .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
+       .setup_clr = USBH_SETUP_IPP,
+};
+
+static const struct udevice_id bcm6368_usbh_ids[] = {
+       {
+               .compatible = "brcm,bcm6328-usbh",
+               .data = (ulong)&bcm6328_hw,
+       }, {
+               .compatible = "brcm,bcm6362-usbh",
+               .data = (ulong)&bcm6362_hw,
+       }, {
+               .compatible = "brcm,bcm6368-usbh",
+               .data = (ulong)&bcm6368_hw,
+       }, {
+               .compatible = "brcm,bcm63268-usbh",
+               .data = (ulong)&bcm63268_hw,
+       }, { /* sentinel */ }
+};
+
+static int bcm6368_usbh_probe(struct udevice *dev)
+{
+       struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
+       const struct bcm6368_usbh_hw *hw =
+               (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
+#if defined(CONFIG_POWER_DOMAIN)
+       struct power_domain pwr_dom;
+#endif
+       struct reset_ctl rst_ctl;
+       struct clk clk;
+       fdt_addr_t addr;
+       fdt_size_t size;
+       int ret;
+
+       addr = devfdt_get_addr_size_index(dev, 0, &size);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->regs = ioremap(addr, size);
+       priv->hw = hw;
+
+       /* enable usbh clock */
+       ret = clk_get_by_name(dev, "usbh", &clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_enable(&clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_free(&clk);
+       if (ret < 0)
+               return ret;
+
+#if defined(CONFIG_POWER_DOMAIN)
+       /* enable power domain */
+       ret = power_domain_get(dev, &pwr_dom);
+       if (ret < 0)
+               return ret;
+
+       ret = power_domain_on(&pwr_dom);
+       if (ret < 0)
+               return ret;
+
+       ret = power_domain_free(&pwr_dom);
+       if (ret < 0)
+               return ret;
+#endif
+
+       /* perform reset */
+       ret = reset_get_by_index(dev, 0, &rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_deassert(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       ret = reset_free(&rst_ctl);
+       if (ret < 0)
+               return ret;
+
+       /* enable usb_ref clock */
+       ret = clk_get_by_name(dev, "usb_ref", &clk);
+       if (!ret) {
+               ret = clk_enable(&clk);
+               if (ret < 0)
+                       return ret;
+
+               ret = clk_free(&clk);
+               if (ret < 0)
+                       return ret;
+       }
+
+       mdelay(100);
+
+       return 0;
+}
+
+U_BOOT_DRIVER(bcm6368_usbh) = {
+       .name = "bcm6368-usbh",
+       .id = UCLASS_PHY,
+       .of_match = bcm6368_usbh_ids,
+       .ops = &bcm6368_usbh_ops,
+       .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
+       .probe = bcm6368_usbh_probe,
+};

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 2bf853eba13d237d3c6882daae08128fdb18e815..010eb203b7f517355f8c81bae62ab8806f376cc7 100644 (file)
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IRQ_STATUS     0x10
 #define IRQ_WKUP       0x18
 
-#define NB_FUNCS 2
+#define NB_FUNCS 3
 #define GPIO_PER_REG   32
 
 /**
@@ -128,6 +128,16 @@ struct armada_37xx_pinctrl {
                .funcs = {_func1, "gpio"}       \
        }
 
+#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
+       {                                       \
+               .name = _name,                  \
+               .start_pin = _start,            \
+               .npins = _nr,                   \
+               .reg_mask = _mask,              \
+               .val = {_v1, _v2, _v3}, \
+               .funcs = {_f1, _f2, "gpio"}     \
+       }
+
 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
                      _f1, _f2)                         \
        {                                               \
@@ -149,8 +159,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
        PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
        PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
        PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
-       PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
-       PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
+       PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
+       PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
        PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
        PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
        PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
@@ -172,13 +182,15 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
        PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
        PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
-       PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
-       PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
-       PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
-       PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
+       PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
+       PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
+       PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
+       PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
+       PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
        PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
        PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
-       PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
+       PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
+                      "mii", "mii_err"),
 };
 
 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
@@ -189,18 +201,18 @@ const struct armada_37xx_pin_data armada_37xx_pin_nb = {
 };
 
 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
-       .nr_pins = 29,
+       .nr_pins = 30,
        .name = "GPIO2",
        .groups = armada_37xx_sb_groups,
        .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
 };
 
 static inline void armada_37xx_update_reg(unsigned int *reg,
-                                         unsigned int offset)
+                                         unsigned int *offset)
 {
        /* We never have more than 2 registers */
-       if (offset >= GPIO_PER_REG) {
-               offset -= GPIO_PER_REG;
+       if (*offset >= GPIO_PER_REG) {
+               *offset -= GPIO_PER_REG;
                *reg += sizeof(u32);
        }
 }
@@ -210,7 +222,7 @@ static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
 {
        int f;
 
-       for (f = 0; f < NB_FUNCS; f++)
+       for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
                if (!strcmp(grp->funcs[f], func))
                        return f;
 
@@ -352,7 +364,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
                for (j = 0; j < grp->extra_npins; j++)
                        grp->pins[i+j] = grp->extra_pin + j;
 
-               for (f = 0; f < NB_FUNCS; f++) {
+               for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
                        int ret;
                        /* check for unique functions and count groups */
                        ret = armada_37xx_add_function(info->funcs, &funcsize,
@@ -404,7 +416,7 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
                        struct armada_37xx_pin_group *gp = &info->groups[g];
                        int f;
 
-                       for (f = 0; f < NB_FUNCS; f++) {
+                       for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
                                if (strcmp(gp->funcs[f], name) == 0) {
                                        *groups = gp->name;
                                        groups++;
@@ -421,7 +433,7 @@ static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
        unsigned int reg = INPUT_VAL;
        unsigned int val, mask;
 
-       armada_37xx_update_reg(&reg, offset);
+       armada_37xx_update_reg(&reg, &offset);
        mask = BIT(offset);
 
        val = readl(info->base + reg);
@@ -436,7 +448,7 @@ static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
        unsigned int reg = OUTPUT_VAL;
        unsigned int mask, val;
 
-       armada_37xx_update_reg(&reg, offset);
+       armada_37xx_update_reg(&reg, &offset);
        mask = BIT(offset);
        val = value ? mask : 0;
 
@@ -452,7 +464,7 @@ static int armada_37xx_gpio_get_direction(struct udevice *dev,
        unsigned int reg = OUTPUT_EN;
        unsigned int val, mask;
 
-       armada_37xx_update_reg(&reg, offset);
+       armada_37xx_update_reg(&reg, &offset);
        mask = BIT(offset);
        val = readl(info->base + reg);
 
@@ -469,7 +481,7 @@ static int armada_37xx_gpio_direction_input(struct udevice *dev,
        unsigned int reg = OUTPUT_EN;
        unsigned int mask;
 
-       armada_37xx_update_reg(&reg, offset);
+       armada_37xx_update_reg(&reg, &offset);
        mask = BIT(offset);
 
        clrbits_le32(info->base + reg, mask);
@@ -484,7 +496,7 @@ static int armada_37xx_gpio_direction_output(struct udevice *dev,
        unsigned int reg = OUTPUT_EN;
        unsigned int mask;
 
-       armada_37xx_update_reg(&reg, offset);
+       armada_37xx_update_reg(&reg, &offset);
        mask = BIT(offset);
 
        setbits_le32(info->base + reg, mask);

diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 6a73a0679b0a2caca9d675a73af5bebf669bbd99..a0a326a142f0aeb2ed06c5f8c61702e8b1927733 100644 (file)
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -12,6 +12,7 @@
 #include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <dm/util.h>
+#include <dm/of_access.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,16 +64,13 @@ static int pinctrl_config_one(struct udevice *config)
  */
 static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
 {
-       const void *fdt = gd->fdt_blob;
-       int node = dev_of_offset(dev);
        char propname[32]; /* long enough */
        const fdt32_t *list;
        uint32_t phandle;
-       int config_node;
        struct udevice *config;
        int state, size, i, ret;
 
-       state = fdt_stringlist_search(fdt, node, "pinctrl-names", statename);
+       state = dev_read_stringlist_search(dev, "pinctrl-names", statename);
        if (state < 0) {
                char *end;
                /*
@@ -85,22 +83,15 @@ static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
        }
 
        snprintf(propname, sizeof(propname), "pinctrl-%d", state);
-       list = fdt_getprop(fdt, node, propname, &size);
+       list = dev_read_prop(dev, propname, &size);
        if (!list)
                return -EINVAL;
 
        size /= sizeof(*list);
        for (i = 0; i < size; i++) {
                phandle = fdt32_to_cpu(*list++);
-
-               config_node = fdt_node_offset_by_phandle(fdt, phandle);
-               if (config_node < 0) {
-                       dev_err(dev, "prop %s index %d invalid phandle\n",
-                               propname, i);
-                       return -EINVAL;
-               }
-               ret = uclass_get_device_by_of_offset(UCLASS_PINCONFIG,
-                                                    config_node, &config);
+               ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG, phandle,
+                                                     &config);
                if (ret)
                        return ret;
 

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 2066e11cf13dd1b7e383d981fb855e97a6aa100e..31285cdd5784da2f915f52a5fd2fe4c41079d067 100644 (file)
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -41,9 +41,10 @@ static int stm32_gpio_config(struct gpio_desc *desc,
 
        return 0;
 }
+
 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
 {
-       gpio_dsc->port = (port_pin & 0xF000) >> 12;
+       gpio_dsc->port = (port_pin & 0x1F000) >> 12;
        gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
        debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
              gpio_dsc->pin);
@@ -115,11 +116,13 @@ static int stm32_pinctrl_config(int offset)
                        return -EINVAL;
                for (i = 0; i < len; i++) {
                        struct gpio_desc desc;
+
                        debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
                        prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
                        prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
                        rv = uclass_get_device_by_seq(UCLASS_GPIO,
-                                                     gpio_dsc.port, &desc.dev);
+                                                     gpio_dsc.port,
+                                                     &desc.dev);
                        if (rv)
                                return rv;
                        desc.offset = gpio_dsc.pin;
@@ -186,6 +189,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
        { .compatible = "st,stm32f469-pinctrl" },
        { .compatible = "st,stm32f746-pinctrl" },
        { .compatible = "st,stm32h743-pinctrl" },
+       { .compatible = "st,stm32mp157-pinctrl" },
+       { .compatible = "st,stm32mp157-z-pinctrl" },
        { }
 };
 

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 94f6d7ad403a33725a2540c8109288a1e41311f3..7e93d85dbb9d0673cced93cbc9ee9b5b4c49e61e 100644 (file)
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -18,6 +18,416 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* GRF_GPIO0A_IOMUX */
+enum {
+       GPIO0A3_SHIFT           = 6,
+       GPIO0A3_MASK            = 1 << GPIO0A3_SHIFT,
+       GPIO0A3_GPIO            = 0,
+       GPIO0A3_I2C1_SDA,
+
+       GPIO0A2_SHIFT           = 4,
+       GPIO0A2_MASK            = 1 << GPIO0A2_SHIFT,
+       GPIO0A2_GPIO            = 0,
+       GPIO0A2_I2C1_SCL,
+
+       GPIO0A1_SHIFT           = 2,
+       GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
+       GPIO0A1_GPIO            = 0,
+       GPIO0A1_I2C0_SDA,
+       GPIO0A1_PWM2,
+
+       GPIO0A0_SHIFT           = 0,
+       GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
+       GPIO0A0_GPIO            = 0,
+       GPIO0A0_I2C0_SCL,
+       GPIO0A0_PWM1,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+       GPIO0B6_SHIFT           = 12,
+       GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
+       GPIO0B6_GPIO            = 0,
+       GPIO0B6_MMC1_D3,
+       GPIO0B6_I2S1_SCLK,
+
+       GPIO0B5_SHIFT           = 10,
+       GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
+       GPIO0B5_GPIO            = 0,
+       GPIO0B5_MMC1_D2,
+       GPIO0B5_I2S1_SDI,
+
+       GPIO0B4_SHIFT           = 8,
+       GPIO0B4_MASK            = 3 << GPIO0B4_SHIFT,
+       GPIO0B4_GPIO            = 0,
+       GPIO0B4_MMC1_D1,
+       GPIO0B4_I2S1_LRCKTX,
+
+       GPIO0B3_SHIFT           = 6,
+       GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
+       GPIO0B3_GPIO            = 0,
+       GPIO0B3_MMC1_D0,
+       GPIO0B3_I2S1_LRCKRX,
+
+       GPIO0B1_SHIFT           = 2,
+       GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
+       GPIO0B1_GPIO            = 0,
+       GPIO0B1_MMC1_CLKOUT,
+       GPIO0B1_I2S1_MCLK,
+
+       GPIO0B0_SHIFT           = 0,
+       GPIO0B0_MASK            = 3,
+       GPIO0B0_GPIO            = 0,
+       GPIO0B0_MMC1_CMD,
+       GPIO0B0_I2S1_SDO,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+       GPIO0C4_SHIFT           = 8,
+       GPIO0C4_MASK            = 1 << GPIO0C4_SHIFT,
+       GPIO0C4_GPIO            = 0,
+       GPIO0C4_DRIVE_VBUS,
+
+       GPIO0C3_SHIFT           = 6,
+       GPIO0C3_MASK            = 1 << GPIO0C3_SHIFT,
+       GPIO0C3_GPIO            = 0,
+       GPIO0C3_UART0_CTSN,
+
+       GPIO0C2_SHIFT           = 4,
+       GPIO0C2_MASK            = 1 << GPIO0C2_SHIFT,
+       GPIO0C2_GPIO            = 0,
+       GPIO0C2_UART0_RTSN,
+
+       GPIO0C1_SHIFT           = 2,
+       GPIO0C1_MASK            = 1 << GPIO0C1_SHIFT,
+       GPIO0C1_GPIO            = 0,
+       GPIO0C1_UART0_SIN,
+
+
+       GPIO0C0_SHIFT           = 0,
+       GPIO0C0_MASK            = 1 << GPIO0C0_SHIFT,
+       GPIO0C0_GPIO            = 0,
+       GPIO0C0_UART0_SOUT,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+       GPIO0D4_SHIFT           = 8,
+       GPIO0D4_MASK            = 1 << GPIO0D4_SHIFT,
+       GPIO0D4_GPIO            = 0,
+       GPIO0D4_SPDIF,
+
+       GPIO0D3_SHIFT           = 6,
+       GPIO0D3_MASK            = 1 << GPIO0D3_SHIFT,
+       GPIO0D3_GPIO            = 0,
+       GPIO0D3_PWM3,
+
+       GPIO0D2_SHIFT           = 4,
+       GPIO0D2_MASK            = 1 << GPIO0D2_SHIFT,
+       GPIO0D2_GPIO            = 0,
+       GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+       GPIO1A5_SHIFT           = 10,
+       GPIO1A5_MASK            = 1 << GPIO1A5_SHIFT,
+       GPIO1A5_GPIO            = 0,
+       GPIO1A5_I2S_SDI,
+
+       GPIO1A4_SHIFT           = 8,
+       GPIO1A4_MASK            = 1 << GPIO1A4_SHIFT,
+       GPIO1A4_GPIO            = 0,
+       GPIO1A4_I2S_SD0,
+
+       GPIO1A3_SHIFT           = 6,
+       GPIO1A3_MASK            = 1 << GPIO1A3_SHIFT,
+       GPIO1A3_GPIO            = 0,
+       GPIO1A3_I2S_LRCKTX,
+
+       GPIO1A2_SHIFT           = 4,
+       GPIO1A2_MASK            = 3 << GPIO1A2_SHIFT,
+       GPIO1A2_GPIO            = 0,
+       GPIO1A2_I2S_LRCKRX,
+       GPIO1A2_PWM1_0,
+
+       GPIO1A1_SHIFT           = 2,
+       GPIO1A1_MASK            = 1 << GPIO1A1_SHIFT,
+       GPIO1A1_GPIO            = 0,
+       GPIO1A1_I2S_SCLK,
+
+       GPIO1A0_SHIFT           = 0,
+       GPIO1A0_MASK            = 1 << GPIO1A0_SHIFT,
+       GPIO1A0_GPIO            = 0,
+       GPIO1A0_I2S_MCLK,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+       GPIO1B7_SHIFT           = 14,
+       GPIO1B7_MASK            = 1 << GPIO1B7_SHIFT,
+       GPIO1B7_GPIO            = 0,
+       GPIO1B7_MMC0_CMD,
+
+       GPIO1B3_SHIFT           = 6,
+       GPIO1B3_MASK            = 1 << GPIO1B3_SHIFT,
+       GPIO1B3_GPIO            = 0,
+       GPIO1B3_HDMI_HPD,
+
+       GPIO1B2_SHIFT           = 4,
+       GPIO1B2_MASK            = 1 << GPIO1B2_SHIFT,
+       GPIO1B2_GPIO            = 0,
+       GPIO1B2_HDMI_SCL,
+
+       GPIO1B1_SHIFT           = 2,
+       GPIO1B1_MASK            = 1 << GPIO1B1_SHIFT,
+       GPIO1B1_GPIO            = 0,
+       GPIO1B1_HDMI_SDA,
+
+       GPIO1B0_SHIFT           = 0,
+       GPIO1B0_MASK            = 1 << GPIO1B0_SHIFT,
+       GPIO1B0_GPIO            = 0,
+       GPIO1B0_HDMI_CEC,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+       GPIO1C5_SHIFT           = 10,
+       GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
+       GPIO1C5_GPIO            = 0,
+       GPIO1C5_MMC0_D3,
+       GPIO1C5_JTAG_TMS,
+
+       GPIO1C4_SHIFT           = 8,
+       GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
+       GPIO1C4_GPIO            = 0,
+       GPIO1C4_MMC0_D2,
+       GPIO1C4_JTAG_TCK,
+
+       GPIO1C3_SHIFT           = 6,
+       GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
+       GPIO1C3_GPIO            = 0,
+       GPIO1C3_MMC0_D1,
+       GPIO1C3_UART2_SOUT,
+
+       GPIO1C2_SHIFT           = 4,
+       GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT ,
+       GPIO1C2_GPIO            = 0,
+       GPIO1C2_MMC0_D0,
+       GPIO1C2_UART2_SIN,
+
+       GPIO1C1_SHIFT           = 2,
+       GPIO1C1_MASK            = 1 << GPIO1C1_SHIFT,
+       GPIO1C1_GPIO            = 0,
+       GPIO1C1_MMC0_DETN,
+
+       GPIO1C0_SHIFT           = 0,
+       GPIO1C0_MASK            = 1 << GPIO1C0_SHIFT,
+       GPIO1C0_GPIO            = 0,
+       GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+       GPIO1D7_SHIFT           = 14,
+       GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
+       GPIO1D7_GPIO            = 0,
+       GPIO1D7_NAND_D7,
+       GPIO1D7_EMMC_D7,
+       GPIO1D7_SPI_CSN1,
+
+       GPIO1D6_SHIFT           = 12,
+       GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
+       GPIO1D6_GPIO            = 0,
+       GPIO1D6_NAND_D6,
+       GPIO1D6_EMMC_D6,
+       GPIO1D6_SPI_CSN0,
+
+       GPIO1D5_SHIFT           = 10,
+       GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
+       GPIO1D5_GPIO            = 0,
+       GPIO1D5_NAND_D5,
+       GPIO1D5_EMMC_D5,
+       GPIO1D5_SPI_TXD,
+
+       GPIO1D4_SHIFT           = 8,
+       GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
+       GPIO1D4_GPIO            = 0,
+       GPIO1D4_NAND_D4,
+       GPIO1D4_EMMC_D4,
+       GPIO1D4_SPI_RXD,
+
+       GPIO1D3_SHIFT           = 6,
+       GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
+       GPIO1D3_GPIO            = 0,
+       GPIO1D3_NAND_D3,
+       GPIO1D3_EMMC_D3,
+       GPIO1D3_SFC_SIO3,
+
+       GPIO1D2_SHIFT           = 4,
+       GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
+       GPIO1D2_GPIO            = 0,
+       GPIO1D2_NAND_D2,
+       GPIO1D2_EMMC_D2,
+       GPIO1D2_SFC_SIO2,
+
+       GPIO1D1_SHIFT           = 2,
+       GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
+       GPIO1D1_GPIO            = 0,
+       GPIO1D1_NAND_D1,
+       GPIO1D1_EMMC_D1,
+       GPIO1D1_SFC_SIO1,
+
+       GPIO1D0_SHIFT           = 0,
+       GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
+       GPIO1D0_GPIO            = 0,
+       GPIO1D0_NAND_D0,
+       GPIO1D0_EMMC_D0,
+       GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+       GPIO2A7_SHIFT           = 14,
+       GPIO2A7_MASK            = 1 << GPIO2A7_SHIFT,
+       GPIO2A7_GPIO            = 0,
+       GPIO2A7_TESTCLK_OUT,
+
+       GPIO2A6_SHIFT           = 12,
+       GPIO2A6_MASK            = 1 << GPIO2A6_SHIFT,
+       GPIO2A6_GPIO            = 0,
+       GPIO2A6_NAND_CS0,
+
+       GPIO2A4_SHIFT           = 8,
+       GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
+       GPIO2A4_GPIO            = 0,
+       GPIO2A4_NAND_RDY,
+       GPIO2A4_EMMC_CMD,
+       GPIO2A3_SFC_CLK,
+
+       GPIO2A3_SHIFT           = 6,
+       GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
+       GPIO2A3_GPIO            = 0,
+       GPIO2A3_NAND_RDN,
+       GPIO2A4_SFC_CSN1,
+
+       GPIO2A2_SHIFT           = 4,
+       GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
+       GPIO2A2_GPIO            = 0,
+       GPIO2A2_NAND_WRN,
+       GPIO2A4_SFC_CSN0,
+
+       GPIO2A1_SHIFT           = 2,
+       GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
+       GPIO2A1_GPIO            = 0,
+       GPIO2A1_NAND_CLE,
+       GPIO2A1_EMMC_CLKOUT,
+
+       GPIO2A0_SHIFT           = 0,
+       GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
+       GPIO2A0_GPIO            = 0,
+       GPIO2A0_NAND_ALE,
+       GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+       GPIO2B7_SHIFT           = 14,
+       GPIO2B7_MASK            = 1 << GPIO2B7_SHIFT,
+       GPIO2B7_GPIO            = 0,
+       GPIO2B7_MAC_RXER,
+
+       GPIO2B6_SHIFT           = 12,
+       GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
+       GPIO2B6_GPIO            = 0,
+       GPIO2B6_MAC_CLKOUT,
+       GPIO2B6_MAC_CLKIN,
+
+       GPIO2B5_SHIFT           = 10,
+       GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
+       GPIO2B5_GPIO            = 0,
+       GPIO2B5_MAC_TXEN,
+
+       GPIO2B4_SHIFT           = 8,
+       GPIO2B4_MASK            = 1 << GPIO2B4_SHIFT,
+       GPIO2B4_GPIO            = 0,
+       GPIO2B4_MAC_MDIO,
+
+       GPIO2B2_SHIFT           = 4,
+       GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
+       GPIO2B2_GPIO            = 0,
+       GPIO2B2_MAC_CRS,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+       GPIO2C7_SHIFT           = 14,
+       GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
+       GPIO2C7_GPIO            = 0,
+       GPIO2C7_UART1_SOUT,
+       GPIO2C7_TESTCLK_OUT1,
+
+       GPIO2C6_SHIFT           = 12,
+       GPIO2C6_MASK            = 1 << GPIO2C6_SHIFT,
+       GPIO2C6_GPIO            = 0,
+       GPIO2C6_UART1_SIN,
+
+       GPIO2C5_SHIFT           = 10,
+       GPIO2C5_MASK            = 1 << GPIO2C5_SHIFT,
+       GPIO2C5_GPIO            = 0,
+       GPIO2C5_I2C2_SCL,
+
+       GPIO2C4_SHIFT           = 8,
+       GPIO2C4_MASK            = 1 << GPIO2C4_SHIFT,
+       GPIO2C4_GPIO            = 0,
+       GPIO2C4_I2C2_SDA,
+
+       GPIO2C3_SHIFT           = 6,
+       GPIO2C3_MASK            = 1 << GPIO2C3_SHIFT,
+       GPIO2C3_GPIO            = 0,
+       GPIO2C3_MAC_TXD0,
+
+       GPIO2C2_SHIFT           = 4,
+       GPIO2C2_MASK            = 1 << GPIO2C2_SHIFT,
+       GPIO2C2_GPIO            = 0,
+       GPIO2C2_MAC_TXD1,
+
+       GPIO2C1_SHIFT           = 2,
+       GPIO2C1_MASK            = 1 << GPIO2C1_SHIFT,
+       GPIO2C1_GPIO            = 0,
+       GPIO2C1_MAC_RXD0,
+
+       GPIO2C0_SHIFT           = 0,
+       GPIO2C0_MASK            = 1 << GPIO2C0_SHIFT,
+       GPIO2C0_GPIO            = 0,
+       GPIO2C0_MAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+       GPIO2D6_SHIFT           = 12,
+       GPIO2D6_MASK            = 1 << GPIO2D6_SHIFT,
+       GPIO2D6_GPIO            = 0,
+       GPIO2D6_I2S_SDO1,
+
+       GPIO2D5_SHIFT           = 10,
+       GPIO2D5_MASK            = 1 << GPIO2D5_SHIFT,
+       GPIO2D5_GPIO            = 0,
+       GPIO2D5_I2S_SDO2,
+
+       GPIO2D4_SHIFT           = 8,
+       GPIO2D4_MASK            = 1 << GPIO2D4_SHIFT,
+       GPIO2D4_GPIO            = 0,
+       GPIO2D4_I2S_SDO3,
+
+       GPIO2D1_SHIFT           = 2,
+       GPIO2D1_MASK            = 1 << GPIO2D1_SHIFT,
+       GPIO2D1_GPIO            = 0,
+       GPIO2D1_MAC_MDC,
+};
+
 struct rk3036_pinctrl_priv {
        struct rk3036_grf *grf;
 };

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
index 692d8e298d02434b13ff820c431a7a33cde945bf..fdab836e5a984250140605bca1b74f6956be0fe2 100644 (file)
--- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
@@ -20,6 +20,386 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* GRF_GPIO0D_IOMUX */
+enum {
+       GPIO0D7_SHIFT           = 14,
+       GPIO0D7_MASK            = 1,
+       GPIO0D7_GPIO            = 0,
+       GPIO0D7_SPI1_CSN0,
+
+       GPIO0D6_SHIFT           = 12,
+       GPIO0D6_MASK            = 1,
+       GPIO0D6_GPIO            = 0,
+       GPIO0D6_SPI1_CLK,
+
+       GPIO0D5_SHIFT           = 10,
+       GPIO0D5_MASK            = 1,
+       GPIO0D5_GPIO            = 0,
+       GPIO0D5_SPI1_TXD,
+
+       GPIO0D4_SHIFT           = 8,
+       GPIO0D4_MASK            = 1,
+       GPIO0D4_GPIO            = 0,
+       GPIO0D4_SPI0_RXD,
+
+       GPIO0D3_SHIFT           = 6,
+       GPIO0D3_MASK            = 3,
+       GPIO0D3_GPIO            = 0,
+       GPIO0D3_FLASH_CSN3,
+       GPIO0D3_EMMC_RSTN_OUT,
+
+       GPIO0D2_SHIFT           = 4,
+       GPIO0D2_MASK            = 3,
+       GPIO0D2_GPIO            = 0,
+       GPIO0D2_FLASH_CSN2,
+       GPIO0D2_EMMC_CMD,
+
+       GPIO0D1_SHIFT           = 2,
+       GPIO0D1_MASK            = 1,
+       GPIO0D1_GPIO            = 0,
+       GPIO0D1_FLASH_CSN1,
+
+       GPIO0D0_SHIFT           = 0,
+       GPIO0D0_MASK            = 3,
+       GPIO0D0_GPIO            = 0,
+       GPIO0D0_FLASH_DQS,
+       GPIO0D0_EMMC_CLKOUT
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+       GPIO1A7_SHIFT           = 14,
+       GPIO1A7_MASK            = 3,
+       GPIO1A7_GPIO            = 0,
+       GPIO1A7_UART1_RTS_N,
+       GPIO1A7_SPI0_CSN0,
+
+       GPIO1A6_SHIFT           = 12,
+       GPIO1A6_MASK            = 3,
+       GPIO1A6_GPIO            = 0,
+       GPIO1A6_UART1_CTS_N,
+       GPIO1A6_SPI0_CLK,
+
+       GPIO1A5_SHIFT           = 10,
+       GPIO1A5_MASK            = 3,
+       GPIO1A5_GPIO            = 0,
+       GPIO1A5_UART1_SOUT,
+       GPIO1A5_SPI0_TXD,
+
+       GPIO1A4_SHIFT           = 8,
+       GPIO1A4_MASK            = 3,
+       GPIO1A4_GPIO            = 0,
+       GPIO1A4_UART1_SIN,
+       GPIO1A4_SPI0_RXD,
+
+       GPIO1A3_SHIFT           = 6,
+       GPIO1A3_MASK            = 1,
+       GPIO1A3_GPIO            = 0,
+       GPIO1A3_UART0_RTS_N,
+
+       GPIO1A2_SHIFT           = 4,
+       GPIO1A2_MASK            = 1,
+       GPIO1A2_GPIO            = 0,
+       GPIO1A2_UART0_CTS_N,
+
+       GPIO1A1_SHIFT           = 2,
+       GPIO1A1_MASK            = 1,
+       GPIO1A1_GPIO            = 0,
+       GPIO1A1_UART0_SOUT,
+
+       GPIO1A0_SHIFT           = 0,
+       GPIO1A0_MASK            = 1,
+       GPIO1A0_GPIO            = 0,
+       GPIO1A0_UART0_SIN,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+       GPIO1B7_SHIFT           = 14,
+       GPIO1B7_MASK            = 1,
+       GPIO1B7_GPIO            = 0,
+       GPIO1B7_SPI0_CSN1,
+
+       GPIO1B6_SHIFT           = 12,
+       GPIO1B6_MASK            = 3,
+       GPIO1B6_GPIO            = 0,
+       GPIO1B6_SPDIF_TX,
+       GPIO1B6_SPI1_CSN1,
+
+       GPIO1B5_SHIFT           = 10,
+       GPIO1B5_MASK            = 3,
+       GPIO1B5_GPIO            = 0,
+       GPIO1B5_UART3_RTS_N,
+       GPIO1B5_RESERVED,
+
+       GPIO1B4_SHIFT           = 8,
+       GPIO1B4_MASK            = 3,
+       GPIO1B4_GPIO            = 0,
+       GPIO1B4_UART3_CTS_N,
+       GPIO1B4_GPS_RFCLK,
+
+       GPIO1B3_SHIFT           = 6,
+       GPIO1B3_MASK            = 3,
+       GPIO1B3_GPIO            = 0,
+       GPIO1B3_UART3_SOUT,
+       GPIO1B3_GPS_SIG,
+
+       GPIO1B2_SHIFT           = 4,
+       GPIO1B2_MASK            = 3,
+       GPIO1B2_GPIO            = 0,
+       GPIO1B2_UART3_SIN,
+       GPIO1B2_GPS_MAG,
+
+       GPIO1B1_SHIFT           = 2,
+       GPIO1B1_MASK            = 3,
+       GPIO1B1_GPIO            = 0,
+       GPIO1B1_UART2_SOUT,
+       GPIO1B1_JTAG_TDO,
+
+       GPIO1B0_SHIFT           = 0,
+       GPIO1B0_MASK            = 3,
+       GPIO1B0_GPIO            = 0,
+       GPIO1B0_UART2_SIN,
+       GPIO1B0_JTAG_TDI,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+       GPIO1D7_SHIFT           = 14,
+       GPIO1D7_MASK            = 1,
+       GPIO1D7_GPIO            = 0,
+       GPIO1D7_I2C4_SCL,
+
+       GPIO1D6_SHIFT           = 12,
+       GPIO1D6_MASK            = 1,
+       GPIO1D6_GPIO            = 0,
+       GPIO1D6_I2C4_SDA,
+
+       GPIO1D5_SHIFT           = 10,
+       GPIO1D5_MASK            = 1,
+       GPIO1D5_GPIO            = 0,
+       GPIO1D5_I2C2_SCL,
+
+       GPIO1D4_SHIFT           = 8,
+       GPIO1D4_MASK            = 1,
+       GPIO1D4_GPIO            = 0,
+       GPIO1D4_I2C2_SDA,
+
+       GPIO1D3_SHIFT           = 6,
+       GPIO1D3_MASK            = 1,
+       GPIO1D3_GPIO            = 0,
+       GPIO1D3_I2C1_SCL,
+
+       GPIO1D2_SHIFT           = 4,
+       GPIO1D2_MASK            = 1,
+       GPIO1D2_GPIO            = 0,
+       GPIO1D2_I2C1_SDA,
+
+       GPIO1D1_SHIFT           = 2,
+       GPIO1D1_MASK            = 1,
+       GPIO1D1_GPIO            = 0,
+       GPIO1D1_I2C0_SCL,
+
+       GPIO1D0_SHIFT           = 0,
+       GPIO1D0_MASK            = 1,
+       GPIO1D0_GPIO            = 0,
+       GPIO1D0_I2C0_SDA,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+       GPIO3A7_SHIFT           = 14,
+       GPIO3A7_MASK            = 1,
+       GPIO3A7_GPIO            = 0,
+       GPIO3A7_SDMMC0_DATA3,
+
+       GPIO3A6_SHIFT           = 12,
+       GPIO3A6_MASK            = 1,
+       GPIO3A6_GPIO            = 0,
+       GPIO3A6_SDMMC0_DATA2,
+
+       GPIO3A5_SHIFT           = 10,
+       GPIO3A5_MASK            = 1,
+       GPIO3A5_GPIO            = 0,
+       GPIO3A5_SDMMC0_DATA1,
+
+       GPIO3A4_SHIFT           = 8,
+       GPIO3A4_MASK            = 1,
+       GPIO3A4_GPIO            = 0,
+       GPIO3A4_SDMMC0_DATA0,
+
+       GPIO3A3_SHIFT           = 6,
+       GPIO3A3_MASK            = 1,
+       GPIO3A3_GPIO            = 0,
+       GPIO3A3_SDMMC0_CMD,
+
+       GPIO3A2_SHIFT           = 4,
+       GPIO3A2_MASK            = 1,
+       GPIO3A2_GPIO            = 0,
+       GPIO3A2_SDMMC0_CLKOUT,
+
+       GPIO3A1_SHIFT           = 2,
+       GPIO3A1_MASK            = 1,
+       GPIO3A1_GPIO            = 0,
+       GPIO3A1_SDMMC0_PWREN,
+
+       GPIO3A0_SHIFT           = 0,
+       GPIO3A0_MASK            = 1,
+       GPIO3A0_GPIO            = 0,
+       GPIO3A0_SDMMC0_RSTN,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+       GPIO3B7_SHIFT           = 14,
+       GPIO3B7_MASK            = 3,
+       GPIO3B7_GPIO            = 0,
+       GPIO3B7_CIF_DATA11,
+       GPIO3B7_I2C3_SCL,
+
+       GPIO3B6_SHIFT           = 12,
+       GPIO3B6_MASK            = 3,
+       GPIO3B6_GPIO            = 0,
+       GPIO3B6_CIF_DATA10,
+       GPIO3B6_I2C3_SDA,
+
+       GPIO3B5_SHIFT           = 10,
+       GPIO3B5_MASK            = 3,
+       GPIO3B5_GPIO            = 0,
+       GPIO3B5_CIF_DATA1,
+       GPIO3B5_HSADC_DATA9,
+
+       GPIO3B4_SHIFT           = 8,
+       GPIO3B4_MASK            = 3,
+       GPIO3B4_GPIO            = 0,
+       GPIO3B4_CIF_DATA0,
+       GPIO3B4_HSADC_DATA8,
+
+       GPIO3B3_SHIFT           = 6,
+       GPIO3B3_MASK            = 1,
+       GPIO3B3_GPIO            = 0,
+       GPIO3B3_CIF_CLKOUT,
+
+       GPIO3B2_SHIFT           = 4,
+       GPIO3B2_MASK            = 1,
+       GPIO3B2_GPIO            = 0,
+       /* no muxes */
+
+       GPIO3B1_SHIFT           = 2,
+       GPIO3B1_MASK            = 1,
+       GPIO3B1_GPIO            = 0,
+       GPIO3B1_SDMMC0_WRITE_PRT,
+
+       GPIO3B0_SHIFT           = 0,
+       GPIO3B0_MASK            = 1,
+       GPIO3B0_GPIO            = 0,
+       GPIO3B0_SDMMC_DETECT_N,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+       GPIO3C7_SHIFT           = 14,
+       GPIO3C7_MASK            = 3,
+       GPIO3C7_GPIO            = 0,
+       GPIO3C7_SDMMC1_WRITE_PRT,
+       GPIO3C7_RMII_CRS_DVALID,
+       GPIO3C7_RESERVED,
+
+       GPIO3C6_SHIFT           = 12,
+       GPIO3C6_MASK            = 3,
+       GPIO3C6_GPIO            = 0,
+       GPIO3C6_SDMMC1_DECTN,
+       GPIO3C6_RMII_RX_ERR,
+       GPIO3C6_RESERVED,
+
+       GPIO3C5_SHIFT           = 10,
+       GPIO3C5_MASK            = 3,
+       GPIO3C5_GPIO            = 0,
+       GPIO3C5_SDMMC1_CLKOUT,
+       GPIO3C5_RMII_CLKOUT,
+       GPIO3C5_RMII_CLKIN,
+
+       GPIO3C4_SHIFT           = 8,
+       GPIO3C4_MASK            = 3,
+       GPIO3C4_GPIO            = 0,
+       GPIO3C4_SDMMC1_DATA3,
+       GPIO3C4_RMII_RXD1,
+       GPIO3C4_RESERVED,
+
+       GPIO3C3_SHIFT           = 6,
+       GPIO3C3_MASK            = 3,
+       GPIO3C3_GPIO            = 0,
+       GPIO3C3_SDMMC1_DATA2,
+       GPIO3C3_RMII_RXD0,
+       GPIO3C3_RESERVED,
+
+       GPIO3C2_SHIFT           = 4,
+       GPIO3C2_MASK            = 3,
+       GPIO3C2_GPIO            = 0,
+       GPIO3C2_SDMMC1_DATA1,
+       GPIO3C2_RMII_TXD0,
+       GPIO3C2_RESERVED,
+
+       GPIO3C1_SHIFT           = 2,
+       GPIO3C1_MASK            = 3,
+       GPIO3C1_GPIO            = 0,
+       GPIO3C1_SDMMC1_DATA0,
+       GPIO3C1_RMII_TXD1,
+       GPIO3C1_RESERVED,
+
+       GPIO3C0_SHIFT           = 0,
+       GPIO3C0_MASK            = 3,
+       GPIO3C0_GPIO            = 0,
+       GPIO3C0_SDMMC1_CMD,
+       GPIO3C0_RMII_TX_EN,
+       GPIO3C0_RESERVED,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+       GPIO3D6_SHIFT           = 12,
+       GPIO3D6_MASK            = 3,
+       GPIO3D6_GPIO            = 0,
+       GPIO3D6_PWM_3,
+       GPIO3D6_JTAG_TMS,
+       GPIO3D6_HOST_DRV_VBUS,
+
+       GPIO3D5_SHIFT           = 10,
+       GPIO3D5_MASK            = 3,
+       GPIO3D5_GPIO            = 0,
+       GPIO3D5_PWM_2,
+       GPIO3D5_JTAG_TCK,
+       GPIO3D5_OTG_DRV_VBUS,
+
+       GPIO3D4_SHIFT           = 8,
+       GPIO3D4_MASK            = 3,
+       GPIO3D4_GPIO            = 0,
+       GPIO3D4_PWM_1,
+       GPIO3D4_JTAG_TRSTN,
+
+       GPIO3D3_SHIFT           = 6,
+       GPIO3D3_MASK            = 3,
+       GPIO3D3_GPIO            = 0,
+       GPIO3D3_PWM_0,
+
+       GPIO3D2_SHIFT           = 4,
+       GPIO3D2_MASK            = 3,
+       GPIO3D2_GPIO            = 0,
+       GPIO3D2_SDMMC1_INT_N,
+
+       GPIO3D1_SHIFT           = 2,
+       GPIO3D1_MASK            = 3,
+       GPIO3D1_GPIO            = 0,
+       GPIO3D1_SDMMC1_BACKEND_PWR,
+       GPIO3D1_MII_MDCLK,
+
+       GPIO3D0_SHIFT           = 0,
+       GPIO3D0_MASK            = 3,
+       GPIO3D0_GPIO            = 0,
+       GPIO3D0_SDMMC1_PWR_EN,
+       GPIO3D0_MII_MD,
+};
+
 struct rk3188_pinctrl_priv {
        struct rk3188_grf *grf;
        struct rk3188_pmu *pmu;

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 19a741552203eb75924a587aa258291f47c9bc23..c7052257aa4abb3435cc746de8caa8418015862d 100644 (file)
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -70,6 +70,60 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
                             PMUGRF_GPIO1C0_SEL_MASK,
                             PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
                break;
+
+       case PERIPH_ID_I2C1:
+               rk_clrsetreg(&grf->gpio4a_iomux,
+                            GRF_GPIO4A1_SEL_MASK,
+                            GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
+               rk_clrsetreg(&grf->gpio4a_iomux,
+                            GRF_GPIO4A2_SEL_MASK,
+                            GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
+               break;
+
+       case PERIPH_ID_I2C2:
+               rk_clrsetreg(&grf->gpio2a_iomux,
+                            GRF_GPIO2A0_SEL_MASK,
+                            GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
+               rk_clrsetreg(&grf->gpio2a_iomux,
+                            GRF_GPIO2A1_SEL_MASK,
+                            GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
+               break;
+       case PERIPH_ID_I2C3:
+               rk_clrsetreg(&grf->gpio4c_iomux,
+                            GRF_GPIO4C0_SEL_MASK,
+                            GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
+               rk_clrsetreg(&grf->gpio4c_iomux,
+                            GRF_GPIO4C1_SEL_MASK,
+                            GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
+               break;
+
+       case PERIPH_ID_I2C4:
+               rk_clrsetreg(&pmugrf->gpio1b_iomux,
+                            PMUGRF_GPIO1B3_SEL_MASK,
+                            PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
+               rk_clrsetreg(&pmugrf->gpio1b_iomux,
+                            PMUGRF_GPIO1B4_SEL_MASK,
+                            PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
+               break;
+
+       case PERIPH_ID_I2C7:
+               rk_clrsetreg(&grf->gpio2a_iomux,
+                            GRF_GPIO2A7_SEL_MASK,
+                            GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
+               rk_clrsetreg(&grf->gpio2b_iomux,
+                            GRF_GPIO2B0_SEL_MASK,
+                            GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
+               break;
+
+       case PERIPH_ID_I2C6:
+               rk_clrsetreg(&grf->gpio2b_iomux,
+                            GRF_GPIO2B1_SEL_MASK,
+                            GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
+               rk_clrsetreg(&grf->gpio2b_iomux,
+                            GRF_GPIO2B2_SEL_MASK,
+                            GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
+               break;
+
        case PERIPH_ID_I2C8:
                rk_clrsetreg(&pmugrf->gpio1c_iomux,
                             PMUGRF_GPIO1C4_SEL_MASK,
@@ -78,13 +132,8 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
                             PMUGRF_GPIO1C5_SEL_MASK,
                             PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
                break;
-       case PERIPH_ID_I2C1:
-       case PERIPH_ID_I2C2:
-       case PERIPH_ID_I2C3:
-       case PERIPH_ID_I2C4:
+
        case PERIPH_ID_I2C5:
-       case PERIPH_ID_I2C6:
-       case PERIPH_ID_I2C7:
        default:
                debug("i2c id = %d iomux error!\n", i2c_id);
                break;

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 5d49c93f32a2915b897512aeb8308391bdf4946f..40ab9f7fa519802e1e98e7698afcc98edf35f6e9 100644 (file)
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -209,3 +209,11 @@ config DM_PMIC_TPS65910
        The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
        DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
        pmic children.
+
+config PMIC_STPMU1
+       bool "Enable support for STMicroelectronics STPMU1 PMIC"
+       depends on DM_PMIC && DM_I2C
+       ---help---
+       The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
+       It is accessed via an I2C interface. The device is used with STM32MP1
+       SoCs. This driver implements register read/write operations.

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index fc19fdc701c2f67409f1804e78a36b55fe42c7cc..ad32068b3ab054fd7eb03206bdd49606b72f196e 100644 (file)
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
 obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
 obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
 obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
+obj-$(CONFIG_PMIC_STPMU1) += stpmu1.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o

diff --git a/drivers/power/pmic/stpmu1.c b/drivers/power/pmic/stpmu1.c
new file mode 100644 (file)
index 0000000..4615365
--- /dev/null
+++ b/drivers/power/pmic/stpmu1.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#define STMPU1_NUM_OF_REGS 0x100
+
+static int stpmu1_reg_count(struct udevice *dev)
+{
+       return STMPU1_NUM_OF_REGS;
+}
+
+static int stpmu1_write(struct udevice *dev, uint reg, const uint8_t *buff,
+                       int len)
+{
+       int ret;
+
+       ret = dm_i2c_write(dev, reg, buff, len);
+       if (ret)
+               dev_err(dev, "%s: failed to write register %#x :%d",
+                       __func__, reg, ret);
+
+       return ret;
+}
+
+static int stpmu1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+       int ret;
+
+       ret = dm_i2c_read(dev, reg, buff, len);
+       if (ret)
+               dev_err(dev, "%s: failed to read register %#x : %d",
+                       __func__, reg, ret);
+
+       return ret;
+}
+
+static struct dm_pmic_ops stpmu1_ops = {
+       .reg_count = stpmu1_reg_count,
+       .read = stpmu1_read,
+       .write = stpmu1_write,
+};
+
+static const struct udevice_id stpmu1_ids[] = {
+       { .compatible = "st,stpmu1" },
+       { }
+};
+
+U_BOOT_DRIVER(pmic_stpmu1) = {
+       .name = "stpmu1_pmic",
+       .id = UCLASS_PMIC,
+       .of_match = stpmu1_ids,
+       .ops = &stpmu1_ops,
+};

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 47969f3f2815b1135318dba6ea036dff024b1735..496e2b793bdf380d757e4ce26921d92cfbb1d10b 100644 (file)
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -33,3 +33,5 @@ config STM32_SDRAM
          STM32F7 family devices support flexible memory controller(FMC) to
          support external memories like sdram, psram & nand.
          This driver is for the sdram memory interface with the FMC.
+
+source "drivers/ram/stm32mp1/Kconfig"

diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 51ae6be655083fedfbdf2dc1078772e33afda358..3820d03aa410c18fc6822d2662dd83e20ef6170a 100644 (file)
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -6,6 +6,7 @@
 #
 obj-$(CONFIG_RAM) += ram-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_ram.o
+obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
 obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
 obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
 

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 76c1fe80a7fb2c1c900f24a39496d56b91a0d068..5cb470c209f24a0bbc2ea490c6ec8319e4d9af1a 100644 (file)
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1015,6 +1015,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
        writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
        while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
                mdelay(10);
+               i++;
                if (i > 10) {
                        debug("index1 frequency done overtime\n");
                        return -ETIME;

diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig
new file mode 100644 (file)
index 0000000..b9c8166
--- /dev/null
+++ b/drivers/ram/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+
+config STM32MP1_DDR
+       bool "STM32MP1 DDR driver"
+       depends on DM && OF_CONTROL && ARCH_STM32MP
+       select RAM
+       select SPL_RAM if SPL
+       default y
+       help
+               activate STM32MP1 DDR controller driver for STM32MP1 soc
+               family: support for LPDDR2, LPDDR3 and DDR3
+               the SDRAM parameters for controleur and phy need to be provided
+               in device tree (computed by DDR tuning tools)

diff --git a/drivers/ram/stm32mp1/Makefile b/drivers/ram/stm32mp1/Makefile
new file mode 100644 (file)
index 0000000..9f05cd4
--- /dev/null
+++ b/drivers/ram/stm32mp1/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
+#
+
+obj-y += stm32mp1_ram.o
+obj-y += stm32mp1_ddr.o

diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
new file mode 100644 (file)
index 0000000..ffe50d9
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -0,0 +1,496 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <ram.h>
+#include <reset.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <linux/iopoll.h>
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_ddr_regs.h"
+
+#define RCC_DDRITFCR           0xD8
+
+#define RCC_DDRITFCR_DDRCAPBRST                (BIT(14))
+#define RCC_DDRITFCR_DDRCAXIRST                (BIT(15))
+#define RCC_DDRITFCR_DDRCORERST                (BIT(16))
+#define RCC_DDRITFCR_DPHYAPBRST                (BIT(17))
+#define RCC_DDRITFCR_DPHYRST           (BIT(18))
+#define RCC_DDRITFCR_DPHYCTLRST                (BIT(19))
+
+struct reg_desc {
+       const char *name;
+       u16 offset;     /* offset for base address */
+       u8 par_offset;  /* offset for parameter array */
+};
+
+#define INVALID_OFFSET 0xFF
+
+#define DDRCTL_REG(x, y) \
+       {#x,\
+        offsetof(struct stm32mp1_ddrctl, x),\
+        offsetof(struct y, x)}
+
+#define DDRPHY_REG(x, y) \
+       {#x,\
+        offsetof(struct stm32mp1_ddrphy, x),\
+        offsetof(struct y, x)}
+
+#define DDRCTL_REG_REG(x)      DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
+static const struct reg_desc ddr_reg[] = {
+       DDRCTL_REG_REG(mstr),
+       DDRCTL_REG_REG(mrctrl0),
+       DDRCTL_REG_REG(mrctrl1),
+       DDRCTL_REG_REG(derateen),
+       DDRCTL_REG_REG(derateint),
+       DDRCTL_REG_REG(pwrctl),
+       DDRCTL_REG_REG(pwrtmg),
+       DDRCTL_REG_REG(hwlpctl),
+       DDRCTL_REG_REG(rfshctl0),
+       DDRCTL_REG_REG(rfshctl3),
+       DDRCTL_REG_REG(crcparctl0),
+       DDRCTL_REG_REG(zqctl0),
+       DDRCTL_REG_REG(dfitmg0),
+       DDRCTL_REG_REG(dfitmg1),
+       DDRCTL_REG_REG(dfilpcfg0),
+       DDRCTL_REG_REG(dfiupd0),
+       DDRCTL_REG_REG(dfiupd1),
+       DDRCTL_REG_REG(dfiupd2),
+       DDRCTL_REG_REG(dfiphymstr),
+       DDRCTL_REG_REG(odtmap),
+       DDRCTL_REG_REG(dbg0),
+       DDRCTL_REG_REG(dbg1),
+       DDRCTL_REG_REG(dbgcmd),
+       DDRCTL_REG_REG(poisoncfg),
+       DDRCTL_REG_REG(pccfg),
+};
+
+#define DDRCTL_REG_TIMING(x)   DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
+static const struct reg_desc ddr_timing[] = {
+       DDRCTL_REG_TIMING(rfshtmg),
+       DDRCTL_REG_TIMING(dramtmg0),
+       DDRCTL_REG_TIMING(dramtmg1),
+       DDRCTL_REG_TIMING(dramtmg2),
+       DDRCTL_REG_TIMING(dramtmg3),
+       DDRCTL_REG_TIMING(dramtmg4),
+       DDRCTL_REG_TIMING(dramtmg5),
+       DDRCTL_REG_TIMING(dramtmg6),
+       DDRCTL_REG_TIMING(dramtmg7),
+       DDRCTL_REG_TIMING(dramtmg8),
+       DDRCTL_REG_TIMING(dramtmg14),
+       DDRCTL_REG_TIMING(odtcfg),
+};
+
+#define DDRCTL_REG_MAP(x)      DDRCTL_REG(x, stm32mp1_ddrctrl_map)
+static const struct reg_desc ddr_map[] = {
+       DDRCTL_REG_MAP(addrmap1),
+       DDRCTL_REG_MAP(addrmap2),
+       DDRCTL_REG_MAP(addrmap3),
+       DDRCTL_REG_MAP(addrmap4),
+       DDRCTL_REG_MAP(addrmap5),
+       DDRCTL_REG_MAP(addrmap6),
+       DDRCTL_REG_MAP(addrmap9),
+       DDRCTL_REG_MAP(addrmap10),
+       DDRCTL_REG_MAP(addrmap11),
+};
+
+#define DDRCTL_REG_PERF(x)     DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
+static const struct reg_desc ddr_perf[] = {
+       DDRCTL_REG_PERF(sched),
+       DDRCTL_REG_PERF(sched1),
+       DDRCTL_REG_PERF(perfhpr1),
+       DDRCTL_REG_PERF(perflpr1),
+       DDRCTL_REG_PERF(perfwr1),
+       DDRCTL_REG_PERF(pcfgr_0),
+       DDRCTL_REG_PERF(pcfgw_0),
+       DDRCTL_REG_PERF(pcfgqos0_0),
+       DDRCTL_REG_PERF(pcfgqos1_0),
+       DDRCTL_REG_PERF(pcfgwqos0_0),
+       DDRCTL_REG_PERF(pcfgwqos1_0),
+       DDRCTL_REG_PERF(pcfgr_1),
+       DDRCTL_REG_PERF(pcfgw_1),
+       DDRCTL_REG_PERF(pcfgqos0_1),
+       DDRCTL_REG_PERF(pcfgqos1_1),
+       DDRCTL_REG_PERF(pcfgwqos0_1),
+       DDRCTL_REG_PERF(pcfgwqos1_1),
+};
+
+#define DDRPHY_REG_REG(x)      DDRPHY_REG(x, stm32mp1_ddrphy_reg)
+static const struct reg_desc ddrphy_reg[] = {
+       DDRPHY_REG_REG(pgcr),
+       DDRPHY_REG_REG(aciocr),
+       DDRPHY_REG_REG(dxccr),
+       DDRPHY_REG_REG(dsgcr),
+       DDRPHY_REG_REG(dcr),
+       DDRPHY_REG_REG(odtcr),
+       DDRPHY_REG_REG(zq0cr1),
+       DDRPHY_REG_REG(dx0gcr),
+       DDRPHY_REG_REG(dx1gcr),
+       DDRPHY_REG_REG(dx2gcr),
+       DDRPHY_REG_REG(dx3gcr),
+};
+
+#define DDRPHY_REG_TIMING(x)   DDRPHY_REG(x, stm32mp1_ddrphy_timing)
+static const struct reg_desc ddrphy_timing[] = {
+       DDRPHY_REG_TIMING(ptr0),
+       DDRPHY_REG_TIMING(ptr1),
+       DDRPHY_REG_TIMING(ptr2),
+       DDRPHY_REG_TIMING(dtpr0),
+       DDRPHY_REG_TIMING(dtpr1),
+       DDRPHY_REG_TIMING(dtpr2),
+       DDRPHY_REG_TIMING(mr0),
+       DDRPHY_REG_TIMING(mr1),
+       DDRPHY_REG_TIMING(mr2),
+       DDRPHY_REG_TIMING(mr3),
+};
+
+#define DDRPHY_REG_CAL(x)      DDRPHY_REG(x, stm32mp1_ddrphy_cal)
+static const struct reg_desc ddrphy_cal[] = {
+       DDRPHY_REG_CAL(dx0dllcr),
+       DDRPHY_REG_CAL(dx0dqtr),
+       DDRPHY_REG_CAL(dx0dqstr),
+       DDRPHY_REG_CAL(dx1dllcr),
+       DDRPHY_REG_CAL(dx1dqtr),
+       DDRPHY_REG_CAL(dx1dqstr),
+       DDRPHY_REG_CAL(dx2dllcr),
+       DDRPHY_REG_CAL(dx2dqtr),
+       DDRPHY_REG_CAL(dx2dqstr),
+       DDRPHY_REG_CAL(dx3dllcr),
+       DDRPHY_REG_CAL(dx3dqtr),
+       DDRPHY_REG_CAL(dx3dqstr),
+};
+
+enum reg_type {
+       REG_REG,
+       REG_TIMING,
+       REG_PERF,
+       REG_MAP,
+       REGPHY_REG,
+       REGPHY_TIMING,
+       REGPHY_CAL,
+       REG_TYPE_NB
+};
+
+enum base_type {
+       DDR_BASE,
+       DDRPHY_BASE,
+       NONE_BASE
+};
+
+struct ddr_reg_info {
+       const char *name;
+       const struct reg_desc *desc;
+       u8 size;
+       enum base_type base;
+};
+
+#define DDRPHY_REG_CAL(x)      DDRPHY_REG(x, stm32mp1_ddrphy_cal)
+
+const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
+[REG_REG] = {
+       "static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
+[REG_TIMING] = {
+       "timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
+[REG_PERF] = {
+       "perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE},
+[REG_MAP] = {
+       "map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE},
+[REGPHY_REG] = {
+       "static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE},
+[REGPHY_TIMING] = {
+       "timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE},
+[REGPHY_CAL] = {
+       "cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE},
+};
+
+const char *base_name[] = {
+       [DDR_BASE] = "ctl",
+       [DDRPHY_BASE] = "phy",
+};
+
+static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
+{
+       if (base == DDRPHY_BASE)
+               return (u32)priv->phy;
+       else
+               return (u32)priv->ctl;
+}
+
+static void set_reg(const struct ddr_info *priv,
+                   enum reg_type type,
+                   const void *param)
+{
+       unsigned int i;
+       unsigned int *ptr, value;
+       enum base_type base = ddr_registers[type].base;
+       u32 base_addr = get_base_addr(priv, base);
+       const struct reg_desc *desc = ddr_registers[type].desc;
+
+       debug("init %s\n", ddr_registers[type].name);
+       for (i = 0; i < ddr_registers[type].size; i++) {
+               ptr = (unsigned int *)(base_addr + desc[i].offset);
+               if (desc[i].par_offset == INVALID_OFFSET) {
+                       pr_err("invalid parameter offset for %s", desc[i].name);
+               } else {
+                       value = *((u32 *)((u32)param +
+                                              desc[i].par_offset));
+                       writel(value, ptr);
+                       debug("[0x%x] %s= 0x%08x\n",
+                             (u32)ptr, desc[i].name, value);
+               }
+       }
+}
+
+static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
+{
+       u32 pgsr;
+       int ret;
+
+       ret = readl_poll_timeout(&phy->pgsr, pgsr,
+                                pgsr & (DDRPHYC_PGSR_IDONE |
+                                        DDRPHYC_PGSR_DTERR |
+                                        DDRPHYC_PGSR_DTIERR |
+                                        DDRPHYC_PGSR_DFTERR |
+                                        DDRPHYC_PGSR_RVERR |
+                                        DDRPHYC_PGSR_RVEIRR),
+                               1000000);
+       debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
+             (u32)&phy->pgsr, pgsr, ret);
+}
+
+void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
+{
+       pir |= DDRPHYC_PIR_INIT;
+       writel(pir, &phy->pir);
+       debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
+             (u32)&phy->pir, pir, readl(&phy->pir));
+
+       /* need to wait 10 configuration clock before start polling */
+       udelay(10);
+
+       /* Wait DRAM initialization and Gate Training Evaluation complete */
+       ddrphy_idone_wait(phy);
+}
+
+/* start quasi dynamic register update */
+static void start_sw_done(struct stm32mp1_ddrctl *ctl)
+{
+       clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+}
+
+/* wait quasi dynamic register update */
+static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
+{
+       int ret;
+       u32 swstat;
+
+       setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+
+       ret = readl_poll_timeout(&ctl->swstat, swstat,
+                                swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
+                                1000000);
+       if (ret)
+               panic("Timeout initialising DRAM : DDR->swstat = %x\n",
+                     swstat);
+
+       debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
+}
+
+/* wait quasi dynamic register update */
+static void wait_operating_mode(struct ddr_info *priv, int mode)
+{
+       u32 stat, val, mask, val2 = 0, mask2 = 0;
+       int ret;
+
+       mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
+       val = mode;
+       /* self-refresh due to software => check also STAT.selfref_type */
+       if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
+               mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
+               stat |= DDRCTRL_STAT_SELFREF_TYPE_SR;
+       } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
+               /* normal mode: handle also automatic self refresh */
+               mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
+                       DDRCTRL_STAT_SELFREF_TYPE_MASK;
+               val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
+                      DDRCTRL_STAT_SELFREF_TYPE_ASR;
+       }
+
+       ret = readl_poll_timeout(&priv->ctl->stat, stat,
+                                ((stat & mask) == val) ||
+                                (mask2 && ((stat & mask2) == val2)),
+                                1000000);
+
+       if (ret)
+               panic("Timeout DRAM : DDR->stat = %x\n", stat);
+
+       debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
+}
+
+void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
+{
+       start_sw_done(ctl);
+       /* quasi-dynamic register update*/
+       setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+       clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+       clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+       wait_sw_done_ack(ctl);
+}
+
+void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+                             u32 rfshctl3, u32 pwrctl)
+{
+       start_sw_done(ctl);
+       if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
+               clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+       if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
+               setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+       setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+       wait_sw_done_ack(ctl);
+}
+
+/* board-specific DDR power initializations. */
+__weak int board_ddr_power_init(void)
+{
+       return 0;
+}
+
+__maybe_unused
+void stm32mp1_ddr_init(struct ddr_info *priv,
+                      const struct stm32mp1_ddr_config *config)
+{
+       u32 pir;
+       int ret;
+
+       ret = board_ddr_power_init();
+
+       if (ret)
+               panic("ddr power init failed\n");
+
+       debug("name = %s\n", config->info.name);
+       debug("speed = %d MHz\n", config->info.speed);
+       debug("size  = 0x%x\n", config->info.size);
+/*
+ * 1. Program the DWC_ddr_umctl2 registers
+ * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
+ */
+       /* Assert All DDR part */
+       setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
+       setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
+       setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
+       setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
+       setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
+       setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
+
+/* 1.2. start CLOCK */
+       if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
+               panic("invalid DRAM clock : %d MHz\n",
+                     config->info.speed);
+
+/* 1.3. deassert reset */
+       /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
+       clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
+       clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
+       /* De-assert presetn once the clocks are active
+        * and stable via DDRCAPBRST bit
+        */
+       clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
+
+/* 1.4. wait 4 cycles for synchronization */
+       asm(" nop");
+       asm(" nop");
+       asm(" nop");
+       asm(" nop");
+
+/* 1.5. initialize registers ddr_umctl2 */
+       /* Stop uMCTL2 before PHY is ready */
+       clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+       debug("[0x%08x] dfimisc = 0x%08x\n",
+             (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
+
+       set_reg(priv, REG_REG, &config->c_reg);
+       set_reg(priv, REG_TIMING, &config->c_timing);
+       set_reg(priv, REG_MAP, &config->c_map);
+
+       /* skip CTRL init, SDRAM init is done by PHY PUBL */
+       clrsetbits_le32(&priv->ctl->init0,
+                       DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
+                       DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
+
+       set_reg(priv, REG_PERF, &config->c_perf);
+
+/*  2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
+       clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
+       clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
+       clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
+
+/*  3. start PHY init by accessing relevant PUBL registers
+ *    (DXGCR, DCR, PTR*, MR*, DTPR*)
+ */
+       set_reg(priv, REGPHY_REG, &config->p_reg);
+       set_reg(priv, REGPHY_TIMING, &config->p_timing);
+       set_reg(priv, REGPHY_CAL, &config->p_cal);
+
+/*  4. Monitor PHY init status by polling PUBL register PGSR.IDONE
+ *     Perform DDR PHY DRAM initialization and Gate Training Evaluation
+ */
+       ddrphy_idone_wait(priv->phy);
+
+/*  5. Indicate to PUBL that controller performs SDRAM initialization
+ *     by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
+ *     DRAM init is done by PHY, init0.skip_dram.init = 1
+ */
+       pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
+             DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
+
+       if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+               pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
+
+       stm32mp1_ddrphy_init(priv->phy, pir);
+
+/*  6. SET DFIMISC.dfi_init_complete_en to 1 */
+       /* Enable quasi-dynamic register programming*/
+       start_sw_done(priv->ctl);
+       setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+       wait_sw_done_ack(priv->ctl);
+
+/*  7. Wait for DWC_ddr_umctl2 to move to normal operation mode
+ *     by monitoring STAT.operating_mode signal
+ */
+       /* wait uMCTL2 ready */
+
+       wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
+
+       debug("DDR DQS training : ");
+/*  8. Disable Auto refresh and power down by setting
+ *    - RFSHCTL3.dis_au_refresh = 1
+ *    - PWRCTL.powerdown_en = 0
+ *    - DFIMISC.dfiinit_complete_en = 0
+ */
+       stm32mp1_refresh_disable(priv->ctl);
+
+/*  9. Program PUBL PGCR to enable refresh during training and rank to train
+ *     not done => keep the programed value in PGCR
+ */
+
+/* 10. configure PUBL PIR register to specify which training step to run */
+       /* warning : RVTRN  is not supported by this PUBL */
+       stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
+
+/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
+       ddrphy_idone_wait(priv->phy);
+
+/* 12. set back registers in step 8 to the orginal values if desidered */
+       stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
+                                config->c_reg.pwrctl);
+
+       /* enable uMCTL2 AXI port 0 and 1 */
+       setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
+       setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
+}

diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h
new file mode 100644 (file)
index 0000000..b77d823
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef _RAM_STM32MP1_DDR_H
+#define _RAM_STM32MP1_DDR_H
+
+enum stm32mp1_ddr_interact_step {
+       STEP_DDR_RESET,
+       STEP_CTL_INIT,
+       STEP_PHY_INIT,
+       STEP_DDR_READY,
+       STEP_RUN,
+};
+
+/* DDR CTL and DDR PHY REGISTERS */
+struct stm32mp1_ddrctl;
+struct stm32mp1_ddrphy;
+
+/**
+ * struct ddr_info
+ *
+ * @dev: pointer for the device
+ * @info: UCLASS RAM information
+ * @ctl: DDR controleur base address
+ * @clk: DDR clock
+ * @phy: DDR PHY base address
+ * @rcc: rcc base address
+ */
+struct ddr_info {
+       struct udevice *dev;
+       struct ram_info info;
+       struct clk clk;
+       struct stm32mp1_ddrctl *ctl;
+       struct stm32mp1_ddrphy *phy;
+       u32 rcc;
+};
+
+struct stm32mp1_ddrctrl_reg {
+       u32 mstr;
+       u32 mrctrl0;
+       u32 mrctrl1;
+       u32 derateen;
+       u32 derateint;
+       u32 pwrctl;
+       u32 pwrtmg;
+       u32 hwlpctl;
+       u32 rfshctl0;
+       u32 rfshctl3;
+       u32 crcparctl0;
+       u32 zqctl0;
+       u32 dfitmg0;
+       u32 dfitmg1;
+       u32 dfilpcfg0;
+       u32 dfiupd0;
+       u32 dfiupd1;
+       u32 dfiupd2;
+       u32 dfiphymstr;
+       u32 odtmap;
+       u32 dbg0;
+       u32 dbg1;
+       u32 dbgcmd;
+       u32 poisoncfg;
+       u32 pccfg;
+
+};
+
+struct stm32mp1_ddrctrl_timing {
+       u32 rfshtmg;
+       u32 dramtmg0;
+       u32 dramtmg1;
+       u32 dramtmg2;
+       u32 dramtmg3;
+       u32 dramtmg4;
+       u32 dramtmg5;
+       u32 dramtmg6;
+       u32 dramtmg7;
+       u32 dramtmg8;
+       u32 dramtmg14;
+       u32 odtcfg;
+};
+
+struct stm32mp1_ddrctrl_map {
+       u32 addrmap1;
+       u32 addrmap2;
+       u32 addrmap3;
+       u32 addrmap4;
+       u32 addrmap5;
+       u32 addrmap6;
+       u32 addrmap9;
+       u32 addrmap10;
+       u32 addrmap11;
+};
+
+struct stm32mp1_ddrctrl_perf {
+       u32 sched;
+       u32 sched1;
+       u32 perfhpr1;
+       u32 perflpr1;
+       u32 perfwr1;
+       u32 pcfgr_0;
+       u32 pcfgw_0;
+       u32 pcfgqos0_0;
+       u32 pcfgqos1_0;
+       u32 pcfgwqos0_0;
+       u32 pcfgwqos1_0;
+       u32 pcfgr_1;
+       u32 pcfgw_1;
+       u32 pcfgqos0_1;
+       u32 pcfgqos1_1;
+       u32 pcfgwqos0_1;
+       u32 pcfgwqos1_1;
+};
+
+struct stm32mp1_ddrphy_reg {
+       u32 pgcr;
+       u32 aciocr;
+       u32 dxccr;
+       u32 dsgcr;
+       u32 dcr;
+       u32 odtcr;
+       u32 zq0cr1;
+       u32 dx0gcr;
+       u32 dx1gcr;
+       u32 dx2gcr;
+       u32 dx3gcr;
+};
+
+struct stm32mp1_ddrphy_timing {
+       u32 ptr0;
+       u32 ptr1;
+       u32 ptr2;
+       u32 dtpr0;
+       u32 dtpr1;
+       u32 dtpr2;
+       u32 mr0;
+       u32 mr1;
+       u32 mr2;
+       u32 mr3;
+};
+
+struct stm32mp1_ddrphy_cal {
+       u32 dx0dllcr;
+       u32 dx0dqtr;
+       u32 dx0dqstr;
+       u32 dx1dllcr;
+       u32 dx1dqtr;
+       u32 dx1dqstr;
+       u32 dx2dllcr;
+       u32 dx2dqtr;
+       u32 dx2dqstr;
+       u32 dx3dllcr;
+       u32 dx3dqtr;
+       u32 dx3dqstr;
+};
+
+struct stm32mp1_ddr_info {
+       const char *name;
+       u16 speed; /* in MHZ */
+       u32 size;  /* memory size in byte = col * row * width */
+};
+
+struct stm32mp1_ddr_config {
+       struct stm32mp1_ddr_info info;
+       struct stm32mp1_ddrctrl_reg c_reg;
+       struct stm32mp1_ddrctrl_timing c_timing;
+       struct stm32mp1_ddrctrl_map c_map;
+       struct stm32mp1_ddrctrl_perf c_perf;
+       struct stm32mp1_ddrphy_reg p_reg;
+       struct stm32mp1_ddrphy_timing p_timing;
+       struct stm32mp1_ddrphy_cal p_cal;
+};
+
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed);
+void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
+void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
+void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+                             u32 rfshctl3,
+                             u32 pwrctl);
+
+void stm32mp1_ddr_init(
+       struct ddr_info *priv,
+       const struct stm32mp1_ddr_config *config);
+
+int stm32mp1_dump_reg(const struct ddr_info *priv,
+                     const char *name);
+
+void stm32mp1_edit_reg(const struct ddr_info *priv,
+                      char *name,
+                      char *string);
+
+int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
+                       const char *name);
+
+void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
+                        char *name,
+                        char *string);
+
+void stm32mp1_dump_info(
+       const struct ddr_info *priv,
+       const struct stm32mp1_ddr_config *config);
+
+bool stm32mp1_ddr_interactive(
+       void *priv,
+       enum stm32mp1_ddr_interact_step step,
+       const struct stm32mp1_ddr_config *config);
+
+#endif

diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
new file mode 100644 (file)
index 0000000..82c254b
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef _RAM_STM32MP1_DDR_REGS_H
+#define _RAM_STM32MP1_DDR_REGS_H
+
+/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
+struct stm32mp1_ddrctl {
+       u32 mstr ;              /* 0x0 Master*/
+       u32 stat;               /* 0x4 Operating Mode Status*/
+       u8 reserved008[0x10 - 0x8];
+       u32 mrctrl0;            /* 0x10 Control 0.*/
+       u32 mrctrl1;            /* 0x14 Control 1*/
+       u32 mrstat;             /* 0x18 Status*/
+       u32 reserved01c;        /* 0x1c */
+       u32 derateen;           /* 0x20 Temperature Derate Enable*/
+       u32 derateint;          /* 0x24 Temperature Derate Interval*/
+       u8 reserved028[0x30 - 0x28];
+       u32 pwrctl;             /* 0x30 Low Power Control*/
+       u32 pwrtmg;             /* 0x34 Low Power Timing*/
+       u32 hwlpctl;            /* 0x38 Hardware Low Power Control*/
+       u8 reserved03c[0x50 - 0x3C];
+       u32 rfshctl0;           /* 0x50 Refresh Control 0*/
+       u32 reserved054;        /* 0x54 Refresh Control 1*/
+       u32 reserved058;        /* 0x58 Refresh Control 2*/
+       u32 reserved05C;
+       u32 rfshctl3;           /* 0x60 Refresh Control 0*/
+       u32 rfshtmg;            /* 0x64 Refresh Timing*/
+       u8 reserved068[0xc0 - 0x68];
+       u32 crcparctl0;         /* 0xc0 CRC Parity Control0*/
+       u32 reserved0c4;        /* 0xc4 CRC Parity Control1*/
+       u32 reserved0c8;        /* 0xc8 CRC Parity Control2*/
+       u32 crcparstat;         /* 0xcc CRC Parity Status*/
+       u32 init0;              /* 0xd0 SDRAM Initialization 0*/
+       u32 init1;              /* 0xd4 SDRAM Initialization 1*/
+       u32 init2;              /* 0xd8 SDRAM Initialization 2*/
+       u32 init3;              /* 0xdc SDRAM Initialization 3*/
+       u32 init4;              /* 0xe0 SDRAM Initialization 4*/
+       u32 init5;              /* 0xe4 SDRAM Initialization 5*/
+       u32 reserved0e8;
+       u32 reserved0ec;
+       u32 dimmctl;            /* 0xf0 DIMM Control*/
+       u8 reserved0f4[0x100 - 0xf4];
+       u32 dramtmg0;           /* 0x100 SDRAM Timing 0*/
+       u32 dramtmg1;           /* 0x104 SDRAM Timing 1*/
+       u32 dramtmg2;           /* 0x108 SDRAM Timing 2*/
+       u32 dramtmg3;           /* 0x10c SDRAM Timing 3*/
+       u32 dramtmg4;           /* 0x110 SDRAM Timing 4*/
+       u32 dramtmg5;           /* 0x114 SDRAM Timing 5*/
+       u32 dramtmg6;           /* 0x118 SDRAM Timing 6*/
+       u32 dramtmg7;           /* 0x11c SDRAM Timing 7*/
+       u32 dramtmg8;           /* 0x120 SDRAM Timing 8*/
+       u8 reserved124[0x138 - 0x124];
+       u32 dramtmg14;          /* 0x138 SDRAM Timing 14*/
+       u32 dramtmg15;          /* 0x13C SDRAM Timing 15*/
+       u8 reserved140[0x180 - 0x140];
+       u32 zqctl0;             /* 0x180 ZQ Control 0*/
+       u32 zqctl1;             /* 0x184 ZQ Control 1*/
+       u32 zqctl2;             /* 0x188 ZQ Control 2*/
+       u32 zqstat;             /* 0x18c ZQ Status*/
+       u32 dfitmg0;            /* 0x190 DFI Timing 0*/
+       u32 dfitmg1;            /* 0x194 DFI Timing 1*/
+       u32 dfilpcfg0;          /* 0x198 DFI Low Power Configuration 0*/
+       u32 reserved19c;
+       u32 dfiupd0;            /* 0x1a0 DFI Update 0*/
+       u32 dfiupd1;            /* 0x1a4 DFI Update 1*/
+       u32 dfiupd2;            /* 0x1a8 DFI Update 2*/
+       u32 reserved1ac;
+       u32 dfimisc;            /* 0x1b0 DFI Miscellaneous Control*/
+       u8 reserved1b4[0x1bc - 0x1b4];
+       u32 dfistat;            /* 0x1bc DFI Miscellaneous Control*/
+       u8 reserved1c0[0x1c4 - 0x1c0];
+       u32 dfiphymstr;         /* 0x1c4 DFI PHY Master interface*/
+       u8 reserved1c8[0x204 - 0x1c8];
+       u32 addrmap1;           /* 0x204 Address Map 1*/
+       u32 addrmap2;           /* 0x208 Address Map 2*/
+       u32 addrmap3;           /* 0x20c Address Map 3*/
+       u32 addrmap4;           /* 0x210 Address Map 4*/
+       u32 addrmap5;           /* 0x214 Address Map 5*/
+       u32 addrmap6;           /* 0x218 Address Map 6*/
+       u8 reserved21c[0x224 - 0x21c];
+       u32 addrmap9;           /* 0x224 Address Map 9*/
+       u32 addrmap10;          /* 0x228 Address Map 10*/
+       u32 addrmap11;          /* 0x22C Address Map 11*/
+       u8 reserved230[0x240 - 0x230];
+       u32 odtcfg;             /* 0x240 ODT Configuration*/
+       u32 odtmap;             /* 0x244 ODT/Rank Map*/
+       u8 reserved248[0x250 - 0x248];
+       u32 sched;              /* 0x250 Scheduler Control*/
+       u32 sched1;             /* 0x254 Scheduler Control 1*/
+       u32 reserved258;
+       u32 perfhpr1;           /* 0x25c High Priority Read CAM 1*/
+       u32 reserved260;
+       u32 perflpr1;           /* 0x264 Low Priority Read CAM 1*/
+       u32 reserved268;
+       u32 perfwr1;            /* 0x26c Write CAM 1*/
+       u8 reserved27c[0x300 - 0x270];
+       u32 dbg0;               /* 0x300 Debug 0*/
+       u32 dbg1;               /* 0x304 Debug 1*/
+       u32 dbgcam;             /* 0x308 CAM Debug*/
+       u32 dbgcmd;             /* 0x30c Command Debug*/
+       u32 dbgstat;            /* 0x310 Status Debug*/
+       u8 reserved314[0x320 - 0x314];
+       u32 swctl;              /* 0x320 Software Programming Control Enable*/
+       u32 swstat;             /* 0x324 Software Programming Control Status*/
+       u8 reserved328[0x36c - 0x328];
+       u32 poisoncfg;          /* 0x36c AXI Poison Configuration Register*/
+       u32 poisonstat;         /* 0x370 AXI Poison Status Register*/
+       u8 reserved374[0x3fc - 0x374];
+
+       /* Multi Port registers */
+       u32 pstat;              /* 0x3fc Port Status*/
+       u32 pccfg;              /* 0x400 Port Common Configuration*/
+
+       /* PORT 0 */
+       u32 pcfgr_0;            /* 0x404 Configuration Read*/
+       u32 pcfgw_0;            /* 0x408 Configuration Write*/
+       u8 reserved40c[0x490 - 0x40c];
+       u32 pctrl_0;            /* 0x490 Port Control Register */
+       u32 pcfgqos0_0;         /* 0x494 Read QoS Configuration 0*/
+       u32 pcfgqos1_0;         /* 0x498 Read QoS Configuration 1*/
+       u32 pcfgwqos0_0;        /* 0x49c Write QoS Configuration 0*/
+       u32 pcfgwqos1_0;        /* 0x4a0 Write QoS Configuration 1*/
+       u8 reserved4a4[0x4b4 - 0x4a4];
+
+       /* PORT 1 */
+       u32 pcfgr_1;            /* 0x4b4 Configuration Read*/
+       u32 pcfgw_1;            /* 0x4b8 Configuration Write*/
+       u8 reserved4bc[0x540 - 0x4bc];
+       u32 pctrl_1;            /* 0x540 Port 2 Control Register */
+       u32 pcfgqos0_1;         /* 0x544 Read QoS Configuration 0*/
+       u32 pcfgqos1_1;         /* 0x548 Read QoS Configuration 1*/
+       u32 pcfgwqos0_1;        /* 0x54c Write QoS Configuration 0*/
+       u32 pcfgwqos1_1;        /* 0x550 Write QoS Configuration 1*/
+};
+
+/* DDR Physical Interface Control (DDRPHYC) registers*/
+struct stm32mp1_ddrphy {
+       u32 ridr;               /* 0x00 R Revision Identification*/
+       u32 pir;                /* 0x04 R/W PHY Initialization*/
+       u32 pgcr;               /* 0x08 R/W PHY General Configuration*/
+       u32 pgsr;               /* 0x0C PHY General Status*/
+       u32 dllgcr;             /* 0x10 R/W DLL General Control*/
+       u32 acdllcr;            /* 0x14 R/W AC DLL Control*/
+       u32 ptr0;               /* 0x18 R/W PHY Timing 0*/
+       u32 ptr1;               /* 0x1C R/W PHY Timing 1*/
+       u32 ptr2;               /* 0x20 R/W PHY Timing 2*/
+       u32 aciocr;             /* 0x24 AC I/O Configuration*/
+       u32 dxccr;              /* 0x28 DATX8 Common Configuration*/
+       u32 dsgcr;              /* 0x2C DDR System General Configuration*/
+       u32 dcr;                /* 0x30 DRAM Configuration*/
+       u32 dtpr0;              /* 0x34 DRAM Timing Parameters0*/
+       u32 dtpr1;              /* 0x38 DRAM Timing Parameters1*/
+       u32 dtpr2;              /* 0x3C DRAM Timing Parameters2*/
+       u32 mr0;                /* 0x40 Mode 0*/
+       u32 mr1;                /* 0x44 Mode 1*/
+       u32 mr2;                /* 0x48 Mode 2*/
+       u32 mr3;                /* 0x4C Mode 3*/
+       u32 odtcr;              /* 0x50 ODT Configuration*/
+       u32 dtar;               /* 0x54 data training address*/
+       u32 dtdr0;              /* 0x58 */
+       u32 dtdr1;              /* 0x5c */
+       u8 res1[0x0c0 - 0x060]; /* 0x60 */
+       u32 dcuar;              /* 0xc0 Address*/
+       u32 dcudr;              /* 0xc4 DCU Data*/
+       u32 dcurr;              /* 0xc8 DCU Run*/
+       u32 dculr;              /* 0xcc DCU Loop*/
+       u32 dcugcr;             /* 0xd0 DCU General Configuration*/
+       u32 dcutpr;             /* 0xd4 DCU Timing Parameters */
+       u32 dcusr0;             /* 0xd8 DCU Status 0*/
+       u32 dcusr1;             /* 0xdc DCU Status 1*/
+       u8 res2[0x100 - 0xe0];  /* 0xe0 */
+       u32 bistrr;             /* 0x100 BIST Run*/
+       u32 bistmskr0;          /* 0x104 BIST Mask 0*/
+       u32 bistmskr1;          /* 0x108 BIST Mask 0*/
+       u32 bistwcr;            /* 0x10c BIST Word Count*/
+       u32 bistlsr;            /* 0x110 BIST LFSR Seed*/
+       u32 bistar0;            /* 0x114 BIST Address 0*/
+       u32 bistar1;            /* 0x118 BIST Address 1*/
+       u32 bistar2;            /* 0x11c BIST Address 2*/
+       u32 bistupdr;           /* 0x120 BIST User Data Pattern*/
+       u32 bistgsr;            /* 0x124 BIST General Status*/
+       u32 bistwer;            /* 0x128 BIST Word Error*/
+       u32 bistber0;           /* 0x12c BIST Bit Error 0*/
+       u32 bistber1;           /* 0x130 BIST Bit Error 1*/
+       u32 bistber2;           /* 0x134 BIST Bit Error 2*/
+       u32 bistwcsr;           /* 0x138 BIST Word Count Status*/
+       u32 bistfwr0;           /* 0x13c BIST Fail Word 0*/
+       u32 bistfwr1;           /* 0x140 BIST Fail Word 1*/
+       u8 res3[0x178 - 0x144]; /* 0x144 */
+       u32 gpr0;               /* 0x178 General Purpose 0 (GPR0)*/
+       u32 gpr1;               /* 0x17C General Purpose 1 (GPR1)*/
+       u32 zq0cr0;             /* 0x180 zq 0 control 0 */
+       u32 zq0cr1;             /* 0x184 zq 0 control 1 */
+       u32 zq0sr0;             /* 0x188 zq 0 status 0 */
+       u32 zq0sr1;             /* 0x18C zq 0 status 1 */
+       u8 res4[0x1C0 - 0x190]; /* 0x190 */
+       u32 dx0gcr;             /* 0x1c0 Byte lane 0 General Configuration*/
+       u32 dx0gsr0;            /* 0x1c4 Byte lane 0 General Status 0*/
+       u32 dx0gsr1;            /* 0x1c8 Byte lane 0 General Status 1*/
+       u32 dx0dllcr;           /* 0x1cc Byte lane 0 DLL Control*/
+       u32 dx0dqtr;            /* 0x1d0 Byte lane 0 DQ Timing*/
+       u32 dx0dqstr;           /* 0x1d4 Byte lane 0 DQS Timing*/
+       u8 res5[0x200 - 0x1d8]; /* 0x1d8 */
+       u32 dx1gcr;             /* 0x200 Byte lane 1 General Configuration*/
+       u32 dx1gsr0;            /* 0x204 Byte lane 1 General Status 0*/
+       u32 dx1gsr1;            /* 0x208 Byte lane 1 General Status 1*/
+       u32 dx1dllcr;           /* 0x20c Byte lane 1 DLL Control*/
+       u32 dx1dqtr;            /* 0x210 Byte lane 1 DQ Timing*/
+       u32 dx1dqstr;           /* 0x214 Byte lane 1 QS Timing*/
+       u8 res6[0x240 - 0x218]; /* 0x218 */
+       u32 dx2gcr;             /* 0x240 Byte lane 2 General Configuration*/
+       u32 dx2gsr0;            /* 0x244 Byte lane 2 General Status 0*/
+       u32 dx2gsr1;            /* 0x248 Byte lane 2 General Status 1*/
+       u32 dx2dllcr;           /* 0x24c Byte lane 2 DLL Control*/
+       u32 dx2dqtr;            /* 0x250 Byte lane 2 DQ Timing*/
+       u32 dx2dqstr;           /* 0x254 Byte lane 2 QS Timing*/
+       u8 res7[0x280 - 0x258]; /* 0x258 */
+       u32 dx3gcr;             /* 0x280 Byte lane 3 General Configuration*/
+       u32 dx3gsr0;            /* 0x284 Byte lane 3 General Status 0*/
+       u32 dx3gsr1;            /* 0x288 Byte lane 3 General Status 1*/
+       u32 dx3dllcr;           /* 0x28c Byte lane 3 DLL Control*/
+       u32 dx3dqtr;            /* 0x290 Byte lane 3 DQ Timing*/
+       u32 dx3dqstr;           /* 0x294 Byte lane 3 QS Timing*/
+};
+
+#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40))
+#define DXNGCR(phy, byte)      DXN(phy, 0x1c0, byte)
+#define DXNDLLCR(phy, byte)    DXN(phy, 0x1cc, byte)
+#define DXNDQTR(phy, byte)     DXN(phy, 0x1d0, byte)
+#define DXNDQSTR(phy, byte)    DXN(phy, 0x1d4, byte)
+
+/* DDRCTRL REGISTERS */
+#define DDRCTRL_MSTR_DDR3                      BIT(0)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK       GENMASK(13, 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL       (0 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF       (1 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER    (2 << 12)
+#define DDRCTRL_MSTR_DLL_OFF_MODE              BIT(15)
+
+#define DDRCTRL_STAT_OPERATING_MODE_MASK       GENMASK(2, 0)
+#define DDRCTRL_STAT_OPERATING_MODE_NORMAL     1
+#define DDRCTRL_STAT_OPERATING_MODE_SR         3
+#define DDRCTRL_STAT_SELFREF_TYPE_MASK         GENMASK(5, 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_ASR          (3 << 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_SR           (2 << 4)
+
+#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE          0
+/* only one rank supported */
+#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT          4
+#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
+               (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT          12
+#define DDRCTRL_MRCTRL0_MR_ADDR_MASK           GENMASK(15, 12)
+#define DDRCTRL_MRCTRL0_MR_WR                  BIT(31)
+
+#define DDRCTRL_MRSTAT_MR_WR_BUSY              BIT(0)
+
+#define DDRCTRL_PWRCTL_POWERDOWN_EN            BIT(1)
+#define DDRCTRL_PWRCTL_SELFREF_SW              BIT(5)
+
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH      BIT(0)
+
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK  GENMASK(27, 16)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
+
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK      (0xC0000000)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL    (BIT(30))
+
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN   BIT(0)
+
+#define DDRCTRL_DBG1_DIS_HIF                   BIT(1)
+
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY  BIT(29)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY  BIT(28)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY          BIT(26)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH         GENMASK(12, 8)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH         GENMASK(4, 0)
+#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
+               (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
+                DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
+#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
+               (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
+                DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
+                DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
+
+#define DDRCTRL_DBGCMD_RANK0_REFRESH           BIT(0)
+
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY     BIT(0)
+
+#define DDRCTRL_SWCTL_SW_DONE                  BIT(0)
+
+#define DDRCTRL_SWSTAT_SW_DONE_ACK             BIT(0)
+
+#define DDRCTRL_PCTRL_N_PORT_EN                        BIT(0)
+
+/* DDRPHYC registers */
+#define DDRPHYC_PIR_INIT                       BIT(0)
+#define DDRPHYC_PIR_DLLSRST                    BIT(1)
+#define DDRPHYC_PIR_DLLLOCK                    BIT(2)
+#define DDRPHYC_PIR_ZCAL                       BIT(3)
+#define DDRPHYC_PIR_ITMSRST                    BIT(4)
+#define DDRPHYC_PIR_DRAMRST                    BIT(5)
+#define DDRPHYC_PIR_DRAMINIT                   BIT(6)
+#define DDRPHYC_PIR_QSTRN                      BIT(7)
+#define DDRPHYC_PIR_ICPC                       BIT(16)
+#define DDRPHYC_PIR_ZCALBYP                    BIT(30)
+#define DDRPHYC_PIR_INITSTEPS_MASK             GENMASK(31, 7)
+
+#define DDRPHYC_PGCR_DFTCMP                    BIT(2)
+#define DDRPHYC_PGCR_PDDISDX                   BIT(24)
+#define DDRPHYC_PGCR_RFSHDT_MASK               GENMASK(28, 25)
+
+#define DDRPHYC_PGSR_IDONE                     BIT(0)
+#define DDRPHYC_PGSR_DTERR                     BIT(5)
+#define DDRPHYC_PGSR_DTIERR                    BIT(6)
+#define DDRPHYC_PGSR_DFTERR                    BIT(7)
+#define DDRPHYC_PGSR_RVERR                     BIT(8)
+#define DDRPHYC_PGSR_RVEIRR                    BIT(9)
+
+#define DDRPHYC_DLLGCR_BPS200                  BIT(23)
+
+#define DDRPHYC_ACDLLCR_DLLDIS                 BIT(31)
+
+#define DDRPHYC_ZQ0CRN_ZDATA_MASK              GENMASK(27, 0)
+#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT             0
+#define DDRPHYC_ZQ0CRN_ZDEN                    BIT(28)
+
+#define DDRPHYC_DXNGCR_DXEN                    BIT(0)
+
+#define DDRPHYC_DXNDLLCR_DLLDIS                        BIT(31)
+#define DDRPHYC_DXNDLLCR_SDPHASE_MASK          GENMASK(17, 14)
+#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT         14
+
+#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)       (4 * (bit))
+#define DDRPHYC_DXNDQTR_DQDLY_MASK             GENMASK(3, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK         GENMASK(1, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK                GENMASK(3, 2)
+
+#define DDRPHYC_DXNDQSTR_DQSDLY_MASK           GENMASK(22, 20)
+#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT          20
+#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK          GENMASK(25, 23)
+#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT         23
+#define DDRPHYC_DXNDQSTR_R0DGSL_MASK           GENMASK(2, 0)
+#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT          0
+#define DDRPHYC_DXNDQSTR_R0DGPS_MASK           GENMASK(13, 12)
+#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT          12
+
+#define DDRPHYC_BISTRR_BDXSEL_MASK             GENMASK(22, 19)
+#define DDRPHYC_BISTRR_BDXSEL_SHIFT            19
+
+#define DDRPHYC_BISTGSR_BDDONE                 BIT(0)
+#define DDRPHYC_BISTGSR_BDXERR                 BIT(2)
+
+#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT          16
+
+/* PWR registers */
+#define PWR_CR3                                        0x00C
+#define PWR_CR3_DDRSRDIS                       BIT(11)
+#define PWR_CR3_DDRRETEN                       BIT(12)
+
+#endif

diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
new file mode 100644 (file)
index 0000000..9599444
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include "stm32mp1_ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *const clkname[] = {
+       "ddrc1",
+       "ddrc2",
+       "ddrcapb",
+       "ddrphycapb",
+       "ddrphyc" /* LAST clock => used for get_rate() */
+};
+
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
+{
+       unsigned long ddrphy_clk;
+       unsigned long ddr_clk;
+       struct clk clk;
+       int ret;
+       int idx;
+
+       for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
+               ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
+
+               if (!ret)
+                       ret = clk_enable(&clk);
+
+               if (ret) {
+                       printf("error for %s : %d\n", clkname[idx], ret);
+                       return ret;
+               }
+       }
+
+       priv->clk = clk;
+       ddrphy_clk = clk_get_rate(&priv->clk);
+
+       debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
+             mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+       /* max 10% frequency delta */
+       ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000);
+       if (ddr_clk > (mem_speed * 1000 * 100)) {
+               pr_err("DDR expected freq %d MHz, current is %d MHz\n",
+                      mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
+{
+       struct ddr_info *priv = dev_get_priv(dev);
+       int ret, idx;
+       struct clk axidcg;
+       struct stm32mp1_ddr_config config;
+
+#define PARAM(x, y) \
+       { x,\
+         offsetof(struct stm32mp1_ddr_config, y),\
+         sizeof(config.y) / sizeof(u32)}
+
+#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
+#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
+
+       const struct {
+               const char *name; /* name in DT */
+               const u32 offset; /* offset in config struct */
+               const u32 size;   /* size of parameters */
+       } param[] = {
+               CTL_PARAM(reg),
+               CTL_PARAM(timing),
+               CTL_PARAM(map),
+               CTL_PARAM(perf),
+               PHY_PARAM(reg),
+               PHY_PARAM(timing),
+               PHY_PARAM(cal)
+       };
+
+       config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
+       config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+       config.info.name = dev_read_string(dev, "st,mem-name");
+       if (!config.info.name) {
+               debug("%s: no st,mem-name\n", __func__);
+               return -EINVAL;
+       }
+       printf("RAM: %s\n", config.info.name);
+
+       for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
+               ret = dev_read_u32_array(dev, param[idx].name,
+                                        (void *)((u32)&config +
+                                                 param[idx].offset),
+                                        param[idx].size);
+               debug("%s: %s[0x%x] = %d\n", __func__,
+                     param[idx].name, param[idx].size, ret);
+               if (ret) {
+                       pr_err("%s: Cannot read %s\n",
+                              __func__, param[idx].name);
+                       return -EINVAL;
+               }
+       }
+
+       ret = clk_get_by_name(dev, "axidcg", &axidcg);
+       if (ret) {
+               debug("%s: Cannot found axidcg\n", __func__);
+               return -EINVAL;
+       }
+       clk_disable(&axidcg); /* disable clock gating during init */
+
+       stm32mp1_ddr_init(priv, &config);
+
+       clk_enable(&axidcg); /* enable clock gating */
+
+       /* check size */
+       debug("%s : get_ram_size(%x, %x)\n", __func__,
+             (u32)priv->info.base, (u32)STM32_DDR_SIZE);
+
+       priv->info.size = get_ram_size((long *)priv->info.base,
+                                      STM32_DDR_SIZE);
+
+       debug("%s : %x\n", __func__, (u32)priv->info.size);
+
+       /* check memory access for all memory */
+       if (config.info.size != priv->info.size) {
+               printf("DDR invalid size : 0x%x, expected 0x%x\n",
+                      priv->info.size, config.info.size);
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static int stm32mp1_ddr_probe(struct udevice *dev)
+{
+       struct ddr_info *priv = dev_get_priv(dev);
+       struct regmap *map;
+       int ret;
+
+       debug("STM32MP1 DDR probe\n");
+       priv->dev = dev;
+
+       ret = regmap_init_mem(dev, &map);
+       if (ret)
+               return ret;
+
+       priv->ctl = regmap_get_range(map, 0);
+       priv->phy = regmap_get_range(map, 1);
+
+       priv->rcc = STM32_RCC_BASE;
+
+       priv->info.base = STM32_DDR_BASE;
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       priv->info.size = 0;
+       return stm32mp1_ddr_setup(dev);
+#else
+       priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+       return 0;
+#endif
+}
+
+static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+       struct ddr_info *priv = dev_get_priv(dev);
+
+       *info = priv->info;
+
+       return 0;
+}
+
+static struct ram_ops stm32mp1_ddr_ops = {
+       .get_info = stm32mp1_ddr_get_info,
+};
+
+static const struct udevice_id stm32mp1_ddr_ids[] = {
+       { .compatible = "st,stm32mp1-ddr" },
+       { }
+};
+
+U_BOOT_DRIVER(ddr_stm32mp1) = {
+       .name = "stm32mp1_ddr",
+       .id = UCLASS_RAM,
+       .of_match = stm32mp1_ddr_ids,
+       .ops = &stm32mp1_ddr_ops,
+       .probe = stm32mp1_ddr_probe,
+       .priv_auto_alloc_size = sizeof(struct ddr_info),
+};

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3964b9eb6e18b208c689e731e23edb42c96b4b22..71a786bab51ad8809f6f057e9a81566f9c8c45ad 100644 (file)
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -30,7 +30,7 @@ config STI_RESET
 
 config STM32_RESET
        bool "Enable the STM32 reset"
-       depends on STM32
+       depends on STM32 || ARCH_STM32MP
        help
          Support for reset controllers on STMicroelectronics STM32 family SoCs.
          This resset driver is compatible with STM32 F4/F7 and H7 SoCs.

diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index b266f46263c55db31fa1c3b0821bb0495ca63e4b..e98f34b0370ec36cb842cc26b59f17897de541fb 100644 (file)
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -11,7 +11,13 @@
 #include <reset-uclass.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+/* reset clear offset for STM32MP RCC */
+#define RCC_CL 0x4
+
+enum rcc_type {
+       RCC_STM32 = 0,
+       RCC_STM32MP,
+};
 
 struct stm32_reset_priv {
        fdt_addr_t base;
@@ -35,7 +41,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
        debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
              reset_ctl->id, bank, offset);
 
-       setbits_le32(priv->base + bank, BIT(offset));
+       if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+               /* reset assert is done in rcc set register */
+               writel(BIT(offset), priv->base + bank);
+       else
+               setbits_le32(priv->base + bank, BIT(offset));
 
        return 0;
 }
@@ -48,7 +58,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
        debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
              reset_ctl->id, bank, offset);
 
-       clrbits_le32(priv->base + bank, BIT(offset));
+       if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+               /* reset deassert is done in rcc clr register */
+               writel(BIT(offset), priv->base + bank + RCC_CL);
+       else
+               clrbits_le32(priv->base + bank, BIT(offset));
 
        return 0;
 }
@@ -64,16 +78,26 @@ static int stm32_reset_probe(struct udevice *dev)
 {
        struct stm32_reset_priv *priv = dev_get_priv(dev);
 
-       priv->base = devfdt_get_addr(dev);
-       if (priv->base == FDT_ADDR_T_NONE)
-               return -EINVAL;
+       priv->base = dev_read_addr(dev);
+       if (priv->base == FDT_ADDR_T_NONE) {
+               /* for MFD, get address of parent */
+               priv->base = dev_read_addr(dev->parent);
+               if (priv->base == FDT_ADDR_T_NONE)
+                       return -EINVAL;
+       }
 
        return 0;
 }
 
+static const struct udevice_id stm32_reset_ids[] = {
+       { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
+       { }
+};
+
 U_BOOT_DRIVER(stm32_rcc_reset) = {
        .name                   = "stm32_rcc_reset",
        .id                     = UCLASS_RESET,
+       .of_match               = stm32_reset_ids,
        .probe                  = stm32_reset_probe,
        .priv_auto_alloc_size   = sizeof(struct stm32_reset_priv),
        .ops                    = &stm32_reset_ops,

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 76d5e99647149abd4e1b915f14458062e95174c2..eb718a650faae04915a9796594020e92e3014b22 100644 (file)
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -609,10 +609,10 @@ config STI_ASC_SERIAL
 
 config STM32_SERIAL
        bool "STMicroelectronics STM32 SoCs on-chip UART"
-       depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
+       depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7 || ARCH_STM32MP)
        help
-         If you have a machine based on a STM32 F4, F7 or H7 SoC you can
-         enable its onboard serial ports, say Y to this option.
+         If you have a machine based on a STM32 F4, F7, H7 or MP1 SOC
+         you can enable its onboard serial ports, say Y to this option.
          If unsure, say N.
 
 config ZYNQ_SERIAL

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index c501aeea166e2cae4fdb13f7a1f9d569ebcda20e..0e93b62eee1ed6ec9bde0d338572f4aa073015c5 100644 (file)
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -10,6 +10,7 @@
  * SPDX-License-Identifier:    GPL-2.0
  */
 
+#include <asm-generic/gpio.h>
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
@@ -18,6 +19,7 @@
 #include <spi.h>
 #include <fdtdec.h>
 #include <linux/compat.h>
+#include <linux/iopoll.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -97,6 +99,8 @@ struct dw_spi_priv {
        struct clk clk;
        unsigned long bus_clk_rate;
 
+       struct gpio_desc cs_gpio;       /* External chip-select gpio */
+
        int bits_per_word;
        u8 cs;                  /* chip select pin */
        u8 tmode;               /* TR/TO/RO/EEPROM */
@@ -110,24 +114,40 @@ struct dw_spi_priv {
        void *rx_end;
 };
 
-static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
+static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
 {
        return __raw_readl(priv->regs + offset);
 }
 
-static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val)
+static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
 {
        __raw_writel(val, priv->regs + offset);
 }
 
-static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset)
+static int request_gpio_cs(struct udevice *bus)
 {
-       return __raw_readw(priv->regs + offset);
-}
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+       struct dw_spi_priv *priv = dev_get_priv(bus);
+       int ret;
 
-static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val)
-{
-       __raw_writew(val, priv->regs + offset);
+       /* External chip select gpio line is optional */
+       ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
+       if (ret == -ENOENT)
+               return 0;
+
+       if (ret < 0) {
+               printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
+               return ret;
+       }
+
+       if (dm_gpio_is_valid(&priv->cs_gpio)) {
+               dm_gpio_set_dir_flags(&priv->cs_gpio,
+                                     GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+       }
+
+       debug("%s: used external gpio for CS management\n", __func__);
+#endif
+       return 0;
 }
 
 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
@@ -144,19 +164,19 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
        debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
              plat->frequency);
 
-       return 0;
+       return request_gpio_cs(bus);
 }
 
 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
 {
-       dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
+       dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
 }
 
 /* Restart the controller, disable all interrupts, clean rx fifo */
 static void spi_hw_init(struct dw_spi_priv *priv)
 {
        spi_enable_chip(priv, 0);
-       dw_writel(priv, DW_SPI_IMR, 0xff);
+       dw_write(priv, DW_SPI_IMR, 0xff);
        spi_enable_chip(priv, 1);
 
        /*
@@ -167,13 +187,13 @@ static void spi_hw_init(struct dw_spi_priv *priv)
                u32 fifo;
 
                for (fifo = 1; fifo < 256; fifo++) {
-                       dw_writew(priv, DW_SPI_TXFLTR, fifo);
-                       if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
+                       dw_write(priv, DW_SPI_TXFLTR, fifo);
+                       if (fifo != dw_read(priv, DW_SPI_TXFLTR))
                                break;
                }
 
                priv->fifo_len = (fifo == 1) ? 0 : fifo;
-               dw_writew(priv, DW_SPI_TXFLTR, 0);
+               dw_write(priv, DW_SPI_TXFLTR, 0);
        }
        debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
 }
@@ -242,7 +262,7 @@ static inline u32 tx_max(struct dw_spi_priv *priv)
        u32 tx_left, tx_room, rxtx_gap;
 
        tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
-       tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR);
+       tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
 
        /*
         * Another concern is about the tx/rx mismatch, we
@@ -263,7 +283,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv)
 {
        u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
 
-       return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR));
+       return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
 }
 
 static void dw_writer(struct dw_spi_priv *priv)
@@ -279,34 +299,22 @@ static void dw_writer(struct dw_spi_priv *priv)
                        else
                                txw = *(u16 *)(priv->tx);
                }
-               dw_writew(priv, DW_SPI_DR, txw);
+               dw_write(priv, DW_SPI_DR, txw);
                debug("%s: tx=0x%02x\n", __func__, txw);
                priv->tx += priv->bits_per_word >> 3;
        }
 }
 
-static int dw_reader(struct dw_spi_priv *priv)
+static void dw_reader(struct dw_spi_priv *priv)
 {
-       unsigned start = get_timer(0);
-       u32 max;
+       u32 max = rx_max(priv);
        u16 rxw;
 
-       /* Wait for rx data to be ready */
-       while (rx_max(priv) == 0) {
-               if (get_timer(start) > RX_TIMEOUT)
-                       return -ETIMEDOUT;
-       }
-
-       max = rx_max(priv);
-
        while (max--) {
-               rxw = dw_readw(priv, DW_SPI_DR);
+               rxw = dw_read(priv, DW_SPI_DR);
                debug("%s: rx=0x%02x\n", __func__, rxw);
 
-               /*
-                * Care about rx only if the transfer's original "rx" is
-                * not null
-                */
+               /* Care about rx if the transfer's original "rx" is not null */
                if (priv->rx_end - priv->len) {
                        if (priv->bits_per_word == 8)
                                *(u8 *)(priv->rx) = rxw;
@@ -315,24 +323,30 @@ static int dw_reader(struct dw_spi_priv *priv)
                }
                priv->rx += priv->bits_per_word >> 3;
        }
-
-       return 0;
 }
 
 static int poll_transfer(struct dw_spi_priv *priv)
 {
-       int ret;
-
        do {
                dw_writer(priv);
-               ret = dw_reader(priv);
-               if (ret < 0)
-                       return ret;
+               dw_reader(priv);
        } while (priv->rx_end > priv->rx);
 
        return 0;
 }
 
+static void external_cs_manage(struct udevice *dev, bool on)
+{
+#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+       struct dw_spi_priv *priv = dev_get_priv(dev->parent);
+
+       if (!dm_gpio_is_valid(&priv->cs_gpio))
+               return;
+
+       dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
+#endif
+}
+
 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
                       const void *dout, void *din, unsigned long flags)
 {
@@ -342,6 +356,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
        u8 *rx = din;
        int ret = 0;
        u32 cr0 = 0;
+       u32 val;
        u32 cs;
 
        /* spi core configured to do 8 bit transfers */
@@ -350,6 +365,10 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
                return -1;
        }
 
+       /* Start the transaction if necessary. */
+       if (flags & SPI_XFER_BEGIN)
+               external_cs_manage(dev, false);
+
        cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
                (priv->mode << SPI_MODE_OFFSET) |
                (priv->tmode << SPI_TMOD_OFFSET);
@@ -359,7 +378,11 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
        else if (rx)
                priv->tmode = SPI_TMOD_RO;
        else
-               priv->tmode = SPI_TMOD_TO;
+               /*
+                * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
+                * any data which breaks our logic in poll_transfer() above.
+                */
+               priv->tmode = SPI_TMOD_TR;
 
        cr0 &= ~SPI_TMOD_MASK;
        cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
@@ -377,8 +400,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
        debug("%s: cr0=%08x\n", __func__, cr0);
        /* Reprogram cr0 only if changed */
-       if (dw_readw(priv, DW_SPI_CTRL0) != cr0)
-               dw_writew(priv, DW_SPI_CTRL0, cr0);
+       if (dw_read(priv, DW_SPI_CTRL0) != cr0)
+               dw_write(priv, DW_SPI_CTRL0, cr0);
 
        /*
         * Configure the desired SS (slave select 0...3) in the controller
@@ -386,7 +409,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
         * automatically. So no cs_activate() etc is needed in this driver.
         */
        cs = spi_chip_select(dev);
-       dw_writel(priv, DW_SPI_SER, 1 << cs);
+       dw_write(priv, DW_SPI_SER, 1 << cs);
 
        /* Enable controller after writing control registers */
        spi_enable_chip(priv, 1);
@@ -394,6 +417,23 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
        /* Start transfer in a polling loop */
        ret = poll_transfer(priv);
 
+       /*
+        * Wait for current transmit operation to complete.
+        * Otherwise if some data still exists in Tx FIFO it can be
+        * silently flushed, i.e. dropped on disabling of the controller,
+        * which happens when writing 0 to DW_SPI_SSIENR which happens
+        * in the beginning of new transfer.
+        */
+       if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
+                              !(val & SR_TF_EMPT) || (val & SR_BUSY),
+                              RX_TIMEOUT * 1000)) {
+               ret = -ETIMEDOUT;
+       }
+
+       /* Stop the transaction if necessary */
+       if (flags & SPI_XFER_END)
+               external_cs_manage(dev, true);
+
        return ret;
 }
 
@@ -412,7 +452,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
        /* clk_div doesn't support odd number */
        clk_div = priv->bus_clk_rate / speed;
        clk_div = (clk_div + 1) & 0xfffe;
-       dw_writel(priv, DW_SPI_BAUDR, clk_div);
+       dw_write(priv, DW_SPI_BAUDR, clk_div);
 
        /* Enable controller after writing control registers */
        spi_enable_chip(priv, 1);

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 053a67bbe0f2d2a470a6916950c75f746bae8171..1ac691a68e7a2404dcaa7a6c2cbbda68bf3dd30f 100644 (file)
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -630,8 +630,10 @@ static int omap3_spi_probe(struct udevice *dev)
                (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
 
        priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
-       priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
-                                           MCSPI_PINDIR_D0_IN_D1_OUT);
+       if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
+               priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+       else
+               priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
        priv->wordlen = SPI_DEFAULT_WORDLEN;
        return 0;
 }

diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig
index 496a6d1933e78f3233aeeed5dc5aec37db96b529..2f6bfa8e71b80a0f79df3820d77bb956a9453d85 100644 (file)
--- a/drivers/usb/eth/Kconfig
+++ b/drivers/usb/eth/Kconfig
@@ -23,6 +23,7 @@ config USB_ETHER_ASIX88179
 config USB_ETHER_LAN75XX
        bool "Microchip LAN75XX support"
        depends on USB_HOST_ETHER
+       depends on PHYLIB
        ---help---
          Say Y here if you would like to support Microchip LAN75XX Hi-Speed
          USB 2.0 to 10/100/1000 Gigabit Ethernet controller.
@@ -32,6 +33,7 @@ config USB_ETHER_LAN75XX
 config USB_ETHER_LAN78XX
        bool "Microchip LAN78XX support"
        depends on USB_HOST_ETHER
+       depends on PHYLIB
        ---help---
          Say Y here if you would like to support Microchip LAN78XX USB 3.1
          Gen 1 to 10/100/1000 Gigabit Ethernet controller.

diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c
index d5a10f19042730d6fb60cb4b16a76beeb3b128cb..ad3ae91e6de4db6073306ac788c84c2ce476b521 100644 (file)
--- a/drivers/usb/gadget/f_rockusb.c
+++ b/drivers/usb/gadget/f_rockusb.c
@@ -552,7 +552,6 @@ static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
                                 sizeof(struct fsg_bulk_cb_wrap));
        struct f_rockusb *f_rkusb = get_rkusb();
 
-       f_rkusb->reboot_flag = 0;
        memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
        f_rkusb->reboot_flag = cbw->CDB[1];
        rockusb_func->in_req->complete = compl_do_reset;

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 90b2f78ec7d938dd8e3e2cd38fd4dee4c6b15e3e..a7249b7511f4552a74ac8431d6ffd41b0666c598 100644 (file)
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -245,3 +245,15 @@ config USB_DWC2
          Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
          operation is compliant to the controller Supplement. If you want to
          enable this controller in host mode, say Y.
+
+if USB_DWC2
+config USB_DWC2_BUFFER_SIZE
+       int "Data buffer size in kB"
+       default 64
+       ---help---
+         By default 64 kB buffer is used but if amount of RAM avaialble on
+         the target is not enough to accommodate allocation of buffer of
+         that size it is possible to shrink it. Smaller sizes should be fine
+         because larger transactions could be split in smaller ones.
+
+endif # USB_DWC2

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7f9ba24cfe753263d8d8de7aed0b3b1ee8b7374a..98194893b9d668fa5d81c680449f00da7ac12dfc 100644 (file)
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
 obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
 obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o
 obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
-obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 0efe645044c547dbd538bcaf34edc5994ec31bd9..4862ab0e7db541b2c1b90d972dfea0fcadd3f38d 100644 (file)
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DWC2_HC_CHANNEL                        0
 
 #define DWC2_STATUS_BUF_SIZE           64
-#define DWC2_DATA_BUF_SIZE             (64 * 1024)
+#define DWC2_DATA_BUF_SIZE             (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
 
 #define MAX_DEVICE                     16
 #define MAX_ENDPOINT                   16
@@ -34,6 +34,9 @@ struct dwc2_priv {
 #ifdef CONFIG_DM_USB
        uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
        uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
+#ifdef CONFIG_DM_REGULATOR
+       struct udevice *vbus_supply;
+#endif
 #else
        uint8_t *aligned_buffer;
        uint8_t *status_buffer;
@@ -111,7 +114,7 @@ static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
        ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
                                false, 1000, false);
        if (ret)
-               printf("%s: Timeout!\n", __func__);
+               dev_info(dev, "%s: Timeout!\n", __func__);
 
        /* Wait for 3 PHY Clocks */
        udelay(1);
@@ -130,7 +133,7 @@ static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
        ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
                                false, 1000, false);
        if (ret)
-               printf("%s: Timeout!\n", __func__);
+               dev_info(dev, "%s: Timeout!\n", __func__);
 
        /* Wait for 3 PHY Clocks */
        udelay(1);
@@ -148,14 +151,14 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
        ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
                                true, 1000, false);
        if (ret)
-               printf("%s: Timeout!\n", __func__);
+               dev_info(dev, "%s: Timeout!\n", __func__);
 
        /* Core Soft Reset */
        writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
        ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
                                false, 1000, false);
        if (ret)
-               printf("%s: Timeout!\n", __func__);
+               dev_info(dev, "%s: Timeout!\n", __func__);
 
        /*
         * Wait for core to come out of reset.
@@ -168,28 +171,52 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
 static int dwc_vbus_supply_init(struct udevice *dev)
 {
-       struct udevice *vbus_supply;
+       struct dwc2_priv *priv = dev_get_priv(dev);
        int ret;
 
-       ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
+       ret = device_get_supply_regulator(dev, "vbus-supply",
+                                         &priv->vbus_supply);
        if (ret) {
                debug("%s: No vbus supply\n", dev->name);
                return 0;
        }
 
-       ret = regulator_set_enable(vbus_supply, true);
+       ret = regulator_set_enable(priv->vbus_supply, true);
        if (ret) {
-               pr_err("Error enabling vbus supply\n");
+               dev_err(dev, "Error enabling vbus supply\n");
                return ret;
        }
 
        return 0;
 }
+
+static int dwc_vbus_supply_exit(struct udevice *dev)
+{
+       struct dwc2_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       if (priv->vbus_supply) {
+               ret = regulator_set_enable(priv->vbus_supply, false);
+               if (ret) {
+                       dev_err(dev, "Error disabling vbus supply\n");
+                       return ret;
+               }
+       }
+
+       return 0;
+}
 #else
 static int dwc_vbus_supply_init(struct udevice *dev)
 {
        return 0;
 }
+
+#if defined(CONFIG_DM_USB)
+static int dwc_vbus_supply_exit(struct udevice *dev)
+{
+       return 0;
+}
+#endif
 #endif
 
 /*
@@ -270,7 +297,7 @@ static void dwc_otg_core_host_init(struct udevice *dev,
                ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
                                        DWC2_HCCHAR_CHEN, false, 1000, false);
                if (ret)
-                       printf("%s: Timeout!\n", __func__);
+                       dev_info("%s: Timeout!\n", __func__);
        }
 
        /* Turn on the vbus power. */
@@ -784,7 +811,7 @@ int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
        uint32_t hcint, hctsiz;
 
        ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
-                               1000, false);
+                               2000, false);
        if (ret)
                return ret;
 
@@ -1091,7 +1118,7 @@ int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
        timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
        for (;;) {
                if (get_timer(0) > timeout) {
-                       printf("Timeout poll on interrupt endpoint\n");
+                       dev_err(dev, "Timeout poll on interrupt endpoint\n");
                        return -ETIMEDOUT;
                }
                ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
@@ -1107,11 +1134,13 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
        int i, j;
 
        snpsid = readl(&regs->gsnpsid);
-       printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
+       dev_info(dev, "Core Release: %x.%03x\n",
+                snpsid >> 12 & 0xf, snpsid & 0xfff);
 
        if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
            (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
-               printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
+               dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
+                        snpsid);
                return -ENODEV;
        }
 
@@ -1269,6 +1298,11 @@ static int dwc2_usb_probe(struct udevice *dev)
 static int dwc2_usb_remove(struct udevice *dev)
 {
        struct dwc2_priv *priv = dev_get_priv(dev);
+       int ret;
+
+       ret = dwc_vbus_supply_exit(dev);
+       if (ret)
+               return ret;
 
        dwc2_uninit_common(priv->regs);
 

diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 1cb92c033870887939ee40915ce8af4562f8847b..b012d8651f1239c2a4048d3d5369c3eb08e23d4d 100644 (file)
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -27,6 +27,56 @@ struct generic_ehci {
        int reset_count;
 };
 
+static int ehci_setup_phy(struct udevice *dev, int index)
+{
+       struct generic_ehci *priv = dev_get_priv(dev);
+       int ret;
+
+       ret = generic_phy_get_by_index(dev, index, &priv->phy);
+       if (ret) {
+               if (ret != -ENOENT) {
+                       dev_err(dev, "failed to get usb phy\n");
+                       return ret;
+               }
+       } else {
+               ret = generic_phy_init(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to init usb phy\n");
+                       return ret;
+               }
+
+               ret = generic_phy_power_on(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to power on usb phy\n");
+                       return generic_phy_exit(&priv->phy);
+               }
+       }
+
+       return 0;
+}
+
+static int ehci_shutdown_phy(struct udevice *dev)
+{
+       struct generic_ehci *priv = dev_get_priv(dev);
+       int ret = 0;
+
+       if (generic_phy_valid(&priv->phy)) {
+               ret = generic_phy_power_off(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to power off usb phy\n");
+                       return ret;
+               }
+
+               ret = generic_phy_exit(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to power off usb phy\n");
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
 static int ehci_usb_probe(struct udevice *dev)
 {
        struct generic_ehci *priv = dev_get_priv(dev);
@@ -51,7 +101,7 @@ static int ehci_usb_probe(struct udevice *dev)
                                break;
                        err = clk_enable(&priv->clocks[i]);
                        if (err) {
-                               pr_err("failed to enable clock %d\n", i);
+                               dev_err(dev, "failed to enable clock %d\n", i);
                                clk_free(&priv->clocks[i]);
                                goto clk_err;
                        }
@@ -59,7 +109,8 @@ static int ehci_usb_probe(struct udevice *dev)
                }
        } else {
                if (clock_nb != -ENOENT) {
-                       pr_err("failed to get clock phandle(%d)\n", clock_nb);
+                       dev_err(dev, "failed to get clock phandle(%d)\n",
+                               clock_nb);
                        return clock_nb;
                }
        }
@@ -80,7 +131,8 @@ static int ehci_usb_probe(struct udevice *dev)
                                break;
 
                        if (reset_deassert(&priv->resets[i])) {
-                               pr_err("failed to deassert reset %d\n", i);
+                               dev_err(dev, "failed to deassert reset %d\n",
+                                       i);
                                reset_free(&priv->resets[i]);
                                goto reset_err;
                        }
@@ -88,25 +140,15 @@ static int ehci_usb_probe(struct udevice *dev)
                }
        } else {
                if (reset_nb != -ENOENT) {
-                       pr_err("failed to get reset phandle(%d)\n", reset_nb);
+                       dev_err(dev, "failed to get reset phandle(%d)\n",
+                               reset_nb);
                        goto clk_err;
                }
        }
 
-       err = generic_phy_get_by_index(dev, 0, &priv->phy);
-       if (err) {
-               if (err != -ENOENT) {
-                       pr_err("failed to get usb phy\n");
-                       goto reset_err;
-               }
-       } else {
-
-               err = generic_phy_init(&priv->phy);
-               if (err) {
-                       pr_err("failed to init usb phy\n");
-                       goto reset_err;
-               }
-       }
+       err = ehci_setup_phy(dev, 0);
+       if (err)
+               goto reset_err;
 
        hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
        hcor = (struct ehci_hcor *)((uintptr_t)hccr +
@@ -119,20 +161,18 @@ static int ehci_usb_probe(struct udevice *dev)
        return 0;
 
 phy_err:
-       if (generic_phy_valid(&priv->phy)) {
-               ret = generic_phy_exit(&priv->phy);
-               if (ret)
-                       pr_err("failed to release phy\n");
-       }
+       ret = ehci_shutdown_phy(dev);
+       if (ret)
+               dev_err(dev, "failed to shutdown usb phy\n");
 
 reset_err:
        ret = reset_release_all(priv->resets, priv->reset_count);
        if (ret)
-               pr_err("failed to assert all resets\n");
+               dev_err(dev, "failed to assert all resets\n");
 clk_err:
        ret = clk_release_all(priv->clocks, priv->clock_count);
        if (ret)
-               pr_err("failed to disable all clocks\n");
+               dev_err(dev, "failed to disable all clocks\n");
 
        return err;
 }
@@ -146,11 +186,9 @@ static int ehci_usb_remove(struct udevice *dev)
        if (ret)
                return ret;
 
-       if (generic_phy_valid(&priv->phy)) {
-               ret = generic_phy_exit(&priv->phy);
-               if (ret)
-                       return ret;
-       }
+       ret = ehci_shutdown_phy(dev);
+       if (ret)
+               return ret;
 
        ret =  reset_release_all(priv->resets, priv->reset_count);
        if (ret)

diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
deleted file mode 100644 (file)
index 9d23577..0000000
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2010, Chris Zhang <chris@seamicro.com>
- *
- * Author: Chris Zhang <chris@seamicro.com>
- * This code is based on ehci freescale driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#include <common.h>
-#include <usb.h>
-#include <asm/io.h>
-
-#include "ehci.h"
-
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
-               struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-       *hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
-       *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-               HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-       return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-       return 0;
-}

diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index bf55a71d66c22fb09ea5bd7ac5a15664d51b5b57..5bdd7995b9051f789b25267b273f6d816945312c 100644 (file)
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -25,6 +25,56 @@ struct generic_ohci {
        int reset_count;        /* number of reset in reset list */
 };
 
+static int ohci_setup_phy(struct udevice *dev, int index)
+{
+       struct generic_ohci *priv = dev_get_priv(dev);
+       int ret;
+
+       ret = generic_phy_get_by_index(dev, index, &priv->phy);
+       if (ret) {
+               if (ret != -ENOENT) {
+                       dev_err(dev, "failed to get usb phy\n");
+                       return ret;
+               }
+       } else {
+               ret = generic_phy_init(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to init usb phy\n");
+                       return ret;
+               }
+
+               ret = generic_phy_power_on(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to power on usb phy\n");
+                       return generic_phy_exit(&priv->phy);
+               }
+       }
+
+       return 0;
+}
+
+static int ohci_shutdown_phy(struct udevice *dev)
+{
+       struct generic_ohci *priv = dev_get_priv(dev);
+       int ret = 0;
+
+       if (generic_phy_valid(&priv->phy)) {
+               ret = generic_phy_power_off(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to power off usb phy\n");
+                       return ret;
+               }
+
+               ret = generic_phy_exit(&priv->phy);
+               if (ret) {
+                       dev_err(dev, "failed to power off usb phy\n");
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
 static int ohci_usb_probe(struct udevice *dev)
 {
        struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
@@ -47,14 +97,14 @@ static int ohci_usb_probe(struct udevice *dev)
 
                        err = clk_enable(&priv->clocks[i]);
                        if (err) {
-                               pr_err("failed to enable clock %d\n", i);
+                               dev_err(dev, "failed to enable clock %d\n", i);
                                clk_free(&priv->clocks[i]);
                                goto clk_err;
                        }
                        priv->clock_count++;
                }
        } else if (clock_nb != -ENOENT) {
-               pr_err("failed to get clock phandle(%d)\n", clock_nb);
+               dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb);
                return clock_nb;
        }
 
@@ -74,31 +124,20 @@ static int ohci_usb_probe(struct udevice *dev)
 
                        err = reset_deassert(&priv->resets[i]);
                        if (err) {
-                               pr_err("failed to deassert reset %d\n", i);
+                               dev_err(dev, "failed to deassert reset %d\n", i);
                                reset_free(&priv->resets[i]);
                                goto reset_err;
                        }
                        priv->reset_count++;
                }
        } else if (reset_nb != -ENOENT) {
-               pr_err("failed to get reset phandle(%d)\n", reset_nb);
+               dev_err(dev, "failed to get reset phandle(%d)\n", reset_nb);
                goto clk_err;
        }
 
-       err = generic_phy_get_by_index(dev, 0, &priv->phy);
-       if (err) {
-               if (err != -ENOENT) {
-                       pr_err("failed to get usb phy\n");
-                       goto reset_err;
-               }
-       } else {
-
-               err = generic_phy_init(&priv->phy);
-               if (err) {
-                       pr_err("failed to init usb phy\n");
-                       goto reset_err;
-               }
-       }
+       err = ohci_setup_phy(dev, 0);
+       if (err)
+               goto reset_err;
 
        err = ohci_register(dev, regs);
        if (err)
@@ -107,20 +146,18 @@ static int ohci_usb_probe(struct udevice *dev)
        return 0;
 
 phy_err:
-       if (generic_phy_valid(&priv->phy)) {
-               ret = generic_phy_exit(&priv->phy);
-               if (ret)
-                       pr_err("failed to release phy\n");
-       }
+       ret = ohci_shutdown_phy(dev);
+       if (ret)
+               dev_err(dev, "failed to shutdown usb phy\n");
 
 reset_err:
        ret = reset_release_all(priv->resets, priv->reset_count);
        if (ret)
-               pr_err("failed to assert all resets\n");
+               dev_err(dev, "failed to assert all resets\n");
 clk_err:
        ret = clk_release_all(priv->clocks, priv->clock_count);
        if (ret)
-               pr_err("failed to disable all clocks\n");
+               dev_err(dev, "failed to disable all clocks\n");
 
        return err;
 }
@@ -134,11 +171,9 @@ static int ohci_usb_remove(struct udevice *dev)
        if (ret)
                return ret;
 
-       if (generic_phy_valid(&priv->phy)) {
-               ret = generic_phy_exit(&priv->phy);
-               if (ret)
-                       return ret;
-       }
+       ret = ohci_shutdown_phy(dev);
+       if (ret)
+               return ret;
 
        ret = reset_release_all(priv->resets, priv->reset_count);
        if (ret)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 258d1cd00a085adaa9cf1c613947eaf43c3767aa..1022dd5512418fe90b5a399ad6ea5735202789cb 100644 (file)
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct xhci_dwc3_platdata {
        struct phy usb_phy;
+       struct phy usb3_phy;
 };
 
 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
@@ -112,6 +113,50 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 }
 
 #ifdef CONFIG_DM_USB
+static int xhci_dwc3_setup_phy(struct udevice *dev, int index, struct phy *phy)
+{
+       int ret = 0;
+
+       ret = generic_phy_get_by_index(dev, index, phy);
+       if (ret) {
+               if (ret != -ENOENT) {
+                       pr_err("Failed to get USB PHY for %s\n", dev->name);
+                       return ret;
+               }
+       } else {
+               ret = generic_phy_init(phy);
+               if (ret) {
+                       pr_err("Can't init USB PHY for %s\n", dev->name);
+                       return ret;
+               }
+               ret = generic_phy_power_on(phy);
+               if (ret) {
+                       pr_err("Can't power on USB PHY for %s\n", dev->name);
+                       generic_phy_exit(phy);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+static int xhci_dwc3_shutdown_phy(struct phy *phy)
+{
+       int ret = 0;
+
+       if (generic_phy_valid(phy)) {
+               ret = generic_phy_power_off(phy);
+               if (ret)
+                       return ret;
+
+               ret = generic_phy_exit(phy);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
 static int xhci_dwc3_probe(struct udevice *dev)
 {
        struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
@@ -125,18 +170,17 @@ static int xhci_dwc3_probe(struct udevice *dev)
        hcor = (struct xhci_hcor *)((uintptr_t)hccr +
                        HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 
-       ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
+       ret = xhci_dwc3_setup_phy(dev, 0, &plat->usb_phy);
        if (ret) {
-               if (ret != -ENOENT) {
-                       pr_err("Failed to get USB PHY for %s\n", dev->name);
-                       return ret;
-               }
-       } else {
-               ret = generic_phy_init(&plat->usb_phy);
-               if (ret) {
-                       pr_err("Can't init USB PHY for %s\n", dev->name);
-                       return ret;
-               }
+               pr_err("Failed to setup USB PHY for %s\n", dev->name);
+               return ret;
+       }
+
+       ret = xhci_dwc3_setup_phy(dev, 1, &plat->usb3_phy);
+       if (ret) {
+               pr_err("Failed to setup USB3 PHY for %s\n", dev->name);
+               xhci_dwc3_shutdown_phy(&plat->usb_phy);
+               return ret;
        }
 
        dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
@@ -158,13 +202,13 @@ static int xhci_dwc3_remove(struct udevice *dev)
        struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
        int ret;
 
-       if (generic_phy_valid(&plat->usb_phy)) {
-               ret = generic_phy_exit(&plat->usb_phy);
-               if (ret) {
-                       pr_err("Can't deinit USB PHY for %s\n", dev->name);
-                       return ret;
-               }
-       }
+       ret = xhci_dwc3_shutdown_phy(&plat->usb_phy);
+       if (ret)
+               pr_err("Can't shutdown USB PHY for %s\n", dev->name);
+
+       ret = xhci_dwc3_shutdown_phy(&plat->usb3_phy);
+       if (ret)
+               pr_err("Can't shutdown USB3 PHY for %s\n", dev->name);
 
        return xhci_deregister(dev);
 }

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 0b2589706201ccfd525437e24967f5a612b07e5f..5b7795dd44d81b5ef60ac81d7adc4dbfde430591 100644 (file)
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -768,7 +768,7 @@ static void parse_putc(const char c)
                break;
 
        case '\n':              /* next line */
-               if (console_col || (!console_col && nl))
+               if (console_col || nl)
                        console_newline(1);
                nl = 1;
                break;

diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 6ec4f89e346d357892b31492e72645670a55004b..26db73b13883e51742f4f1a547bab62e2383288c 100644 (file)
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -853,9 +853,10 @@ static u32 wait_for_event(u32 event)
        do {
                ret = lcdc_irq_handler();
                udelay(1000);
-       } while (!(ret & event));
+               --timeout;
+       } while (!(ret & event) && timeout);
 
-       if (timeout <= 0) {
+       if (!(ret & event)) {
                printf("%s: event %d not hit\n", __func__, event);
                return -1;
        }

diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 30e4020686a830b4369731b1e1203c86ed1b04b4..3a6ef62890c09cbd8319043f825c5a5215ee1380 100644 (file)
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -321,7 +321,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
 
 static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
 {
-       unsigned int ret = EXYNOS_DP_SUCCESS;
+       unsigned int ret;
 
        exynos_dp_set_training_pattern(regs, DP_NONE);
 
@@ -339,7 +339,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
                struct exynos_dp *regs, unsigned char enable)
 {
        unsigned char data;
-       unsigned int ret = EXYNOS_DP_SUCCESS;
+       unsigned int ret;
 
        ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
                                            &data);
@@ -366,7 +366,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
                                                unsigned char enhance_mode)
 {
-       unsigned int ret = EXYNOS_DP_SUCCESS;
+       unsigned int ret;
 
        ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
        if (ret != EXYNOS_DP_SUCCESS) {
@@ -416,7 +416,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
 static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
                unsigned char lane_num, unsigned char *sw, unsigned char *em)
 {
-       unsigned int ret = EXYNOS_DP_SUCCESS;
+       unsigned int ret;
        unsigned char buf;
        unsigned int dpcd_addr;
        unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
@@ -484,7 +484,7 @@ static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
                                        struct exynos_dp_priv *priv)
 {
-       unsigned int ret = EXYNOS_DP_SUCCESS;
+       unsigned int ret;
        unsigned char lane_stat;
        unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
        unsigned int i;
@@ -594,7 +594,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
 static unsigned int exynos_dp_process_equalizer_training(
                struct exynos_dp *regs, struct exynos_dp_priv *priv)
 {
-       unsigned int ret = EXYNOS_DP_SUCCESS;
+       unsigned int ret;
        unsigned char lane_stat, adj_req_sw, adj_req_em, i;
        unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
        unsigned char interlane_aligned = 0;

diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index 953b47fb8c8e5cc2b11e7f83922ca8e04a7ea870..a7fa9c5110eb982e26cfa8eb5757518cec171f0c 100644 (file)
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -136,7 +136,7 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
        struct rk_mipi_priv *priv = dev_get_priv(dev);
 
        priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-       if (IS_ERR(priv->grf)) {
+       if (IS_ERR_OR_NULL(priv->grf)) {
                debug("%s: Get syscon grf failed (ret=%p)\n",
                      __func__, priv->grf);
                return  -ENXIO;

diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index 9ef202bf090e2d827732ba519c993494c66e8623..b936fcec9ba882892735c83e66cea625beb3c336 100644 (file)
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -128,7 +128,7 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
        struct rk_mipi_priv *priv = dev_get_priv(dev);
 
        priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-       if (priv->grf <= 0) {
+       if (IS_ERR_OR_NULL(priv->grf)) {
                debug("%s: Get syscon grf failed (ret=%p)\n",
                      __func__, priv->grf);
                return  -ENXIO;

diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h
index 26e483cf566ac8a20898e52ebc25e972f480d178..5d00bff9fd02be58391ef7deec706fbb1fcc1dbb 100644 (file)
--- a/drivers/video/stb_truetype.h
+++ b/drivers/video/stb_truetype.h
@@ -1993,7 +1993,7 @@ static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill,
 
                STBTT_assert(fabs(area) <= 1.01f);
 
-               scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing);
+               scanline[x2] += area + sign * (1-(x_bottom-x2)/2) * (sy1-y_crossing);
 
                scanline_fill[x2] += sign * (sy1-sy0);
             }

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index b417ac260a58cffaa2ba11aa0f739216c58245ba..e160c77e075cdeca6e2addcfcfcd2a2687bc1711 100644 (file)
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -1,8 +1,7 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- *
- * Authors: Philippe Cornu <philippe.cornu@st.com>
- *          Yannick Fertre <yannick.fertre@st.com>
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *           Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -11,6 +10,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <panel.h>
+#include <reset.h>
 #include <video.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
@@ -138,7 +138,9 @@ struct stm32_ltdc_priv {
 #define LXCFBLNR_CFBLN GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 
 #define BF1_PAXCA      0x600           /* Pixel Alpha x Constant Alpha */
+#define BF1_CA         0x400           /* Constant Alpha */
 #define BF2_1PAXCA     0x007           /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA                0x005           /* 1 - Constant Alpha */
 
 enum stm32_ltdc_pix_fmt {
        PF_ARGB8888 = 0,
@@ -161,11 +163,17 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
                pf = PF_RGB565;
                break;
 
+       case VIDEO_BPP32:
+               pf = PF_ARGB8888;
+               break;
+
+       case VIDEO_BPP8:
+               pf = PF_L8;
+               break;
+
        case VIDEO_BPP1:
        case VIDEO_BPP2:
        case VIDEO_BPP4:
-       case VIDEO_BPP8:
-       case VIDEO_BPP32:
        default:
                debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
                      __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
@@ -178,6 +186,23 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
        return (u32)pf;
 }
 
+static bool has_alpha(u32 fmt)
+{
+       switch (fmt) {
+       case PF_ARGB8888:
+       case PF_ARGB1555:
+       case PF_ARGB4444:
+       case PF_AL44:
+       case PF_AL88:
+               return true;
+       case PF_RGB888:
+       case PF_RGB565:
+       case PF_L8:
+       default:
+               return false;
+       }
+}
+
 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
 {
        /* Reload configuration immediately & enable LTDC */
@@ -219,6 +244,8 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
        val = (total_w << 16) | total_h;
        clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 
+       setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
        /* Signal polarities */
        val = 0;
        debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
@@ -245,6 +272,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
        u32 line_length;
        u32 bus_width;
        u32 val, tmp, bpp;
+       u32 format;
 
        x0 = priv->crop_x;
        x1 = priv->crop_x + priv->crop_w - 1;
@@ -275,15 +303,18 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
        clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
 
        /* Pixel format */
-       val = stm32_ltdc_get_pixel_format(priv->l2bpp);
-       clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
+       format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+       clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
 
        /* Constant alpha value */
        clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
 
+       /* Specifies the blending factors : with or without pixel alpha */
+       /* Manage hw-specific capabilities */
+       val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
        /* Blending factors */
-       clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
-                       BF1_PAXCA | BF2_1PAXCA);
+       clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
 
        /* Frame buffer line number */
        clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
@@ -301,8 +332,9 @@ static int stm32_ltdc_probe(struct udevice *dev)
        struct video_priv *uc_priv = dev_get_uclass_priv(dev);
        struct stm32_ltdc_priv *priv = dev_get_priv(dev);
        struct udevice *panel;
-       struct clk pclk, pxclk;
-       int ret;
+       struct clk pclk;
+       struct reset_ctl rst;
+       int rate, ret;
 
        priv->regs = (void *)dev_read_addr(dev);
        if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
@@ -310,45 +342,60 @@ static int stm32_ltdc_probe(struct udevice *dev)
                return -EINVAL;
        }
 
-       ret = uclass_first_device(UCLASS_PANEL, &panel);
+       ret = clk_get_by_index(dev, 0, &pclk);
        if (ret) {
-               debug("%s: panel device error %d\n", __func__, ret);
+               debug("%s: peripheral clock get error %d\n", __func__, ret);
                return ret;
        }
 
-       ret = panel_enable_backlight(panel);
+       ret = clk_enable(&pclk);
        if (ret) {
-               debug("%s: panel %s enable backlight error %d\n",
-                     __func__, panel->name, ret);
+               debug("%s: peripheral clock enable error %d\n",
+                     __func__, ret);
                return ret;
        }
 
-       ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
-                                          0, &priv->timing);
+       ret = reset_get_by_index(dev, 0, &rst);
        if (ret) {
-               debug("%s: decode display timing error %d\n", __func__, ret);
-               return -EINVAL;
+               debug("%s: missing ltdc hardware reset\n", __func__);
+               return -ENODEV;
        }
 
-       ret = clk_get_by_name(dev, "pclk", &pclk);
+       /* Reset */
+       reset_deassert(&rst);
+
+       ret = uclass_first_device(UCLASS_PANEL, &panel);
        if (ret) {
-               debug("%s: peripheral clock get error %d\n", __func__, ret);
+               debug("%s: panel device error %d\n", __func__, ret);
                return ret;
        }
 
-       ret = clk_enable(&pclk);
+       ret = panel_enable_backlight(panel);
        if (ret) {
-               debug("%s: peripheral clock enable error %d\n", __func__, ret);
+               debug("%s: panel %s enable backlight error %d\n",
+                     __func__, panel->name, ret);
                return ret;
        }
 
-       /* Verify pixel clock value if any & inform user accordingly */
-       ret = clk_get_by_name(dev, "pxclk", &pxclk);
-       if (!ret) {
-               if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
-                       printf("Warning: please adjust ltdc pixel clock\n");
+       ret = fdtdec_decode_display_timing(gd->fdt_blob,
+                                          dev_of_offset(dev), 0,
+                                          &priv->timing);
+       if (ret) {
+               debug("%s: decode display timing error %d\n",
+                     __func__, ret);
+               return -EINVAL;
+       }
+
+       rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
+       if (rate < 0) {
+               debug("%s: fail to set pixel clock %d hz %d hz\n",
+                     __func__, priv->timing.pixelclock.typ, rate);
+               return rate;
        }
 
+       debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+             priv->timing.pixelclock.typ, rate);
+
        /* TODO Below parameters are hard-coded for the moment... */
        priv->l2bpp = VIDEO_BPP16;
        priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
@@ -397,10 +444,10 @@ static const struct udevice_id stm32_ltdc_ids[] = {
 };
 
 U_BOOT_DRIVER(stm32_ltdc) = {
-       .name   = "stm32_ltdc",
-       .id     = UCLASS_VIDEO,
-       .of_match = stm32_ltdc_ids,
-       .probe  = stm32_ltdc_probe,
-       .bind   = stm32_ltdc_bind,
+       .name                   = "stm32_display",
+       .id                     = UCLASS_VIDEO,
+       .of_match               = stm32_ltdc_ids,
+       .probe                  = stm32_ltdc_probe,
+       .bind                   = stm32_ltdc_bind,
        .priv_auto_alloc_size   = sizeof(struct stm32_ltdc_priv),
 };

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index fc46b6774d57a0ab983676f3af6721457ceb8606..8a66e479ab8401f781f943d4a81f5f37f63f216b 100644 (file)
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1,5 +1,13 @@
 menu "Watchdog Timer Support"
 
+config WATCHDOG
+       bool "Enable U-Boot watchdog reset"
+       help
+         This option enables U-Boot watchdog support where U-Boot is using
+         watchdog_reset function to service watchdog device in U-Boot. Enable
+         this option if you want to service enabled watchdog by U-Boot. Disable
+         this option if you want U-Boot to start watchdog but never service it.
+
 config HW_WATCHDOG
        bool
 
@@ -78,4 +86,12 @@ config WDT_ORION
           Select this to enable Orion watchdog timer, which can be found on some
           Marvell Armada chips.
 
+config WDT_CDNS
+       bool "Cadence watchdog timer support"
+       depends on WDT
+       imply WATCHDOG
+       help
+          Select this to enable Cadence watchdog timer, which can be found on some
+          Xilinx Microzed Platform.
+
 endmenu

diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index ab6a6b79e1d7c15630dc6025bef8c2b63a56eab8..4b97df3ab67b88afecc4c5a1162832542e7bf61a 100644 (file)
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
 obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
 obj-$(CONFIG_BCM2835_WDT)       += bcm2835_wdt.o
 obj-$(CONFIG_WDT_ORION) += orion_wdt.o
+obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o

diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c
new file mode 100644 (file)
index 0000000..71733cf
--- /dev/null
+++ b/drivers/watchdog/cdns_wdt.c
@@ -0,0 +1,276 @@
+/*
+ * Cadence WDT driver - Used by Xilinx Zynq
+ * Reference: Linux kernel Cadence watchdog driver.
+ *
+ * Author(s):  Shreenidhi Shedi <yesshedi@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <clk.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cdns_regs {
+       u32 zmr;        /* WD Zero mode register, offset - 0x0 */
+       u32 ccr;        /* Counter Control Register offset - 0x4 */
+       u32 restart;    /* Restart key register, offset - 0x8 */
+       u32 status;     /* Status Register, offset - 0xC */
+};
+
+struct cdns_wdt_priv {
+       bool rst;
+       u32 timeout;
+       void __iomem *reg;
+       struct cdns_regs *regs;
+};
+
+#define CDNS_WDT_DEFAULT_TIMEOUT       10
+
+/* Supports 1 - 516 sec */
+#define CDNS_WDT_MIN_TIMEOUT           1
+#define CDNS_WDT_MAX_TIMEOUT           516
+
+/* Restart key */
+#define CDNS_WDT_RESTART_KEY           0x00001999
+
+/* Counter register access key */
+#define CDNS_WDT_REGISTER_ACCESS_KEY   0x00920000
+
+/* Counter value divisor */
+#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000
+
+/* Clock prescaler value and selection */
+#define CDNS_WDT_PRESCALE_64           64
+#define CDNS_WDT_PRESCALE_512          512
+#define CDNS_WDT_PRESCALE_4096         4096
+#define CDNS_WDT_PRESCALE_SELECT_64    1
+#define CDNS_WDT_PRESCALE_SELECT_512   2
+#define CDNS_WDT_PRESCALE_SELECT_4096  3
+
+/* Input clock frequency */
+#define CDNS_WDT_CLK_75MHZ     75000000
+
+/* Counter maximum value */
+#define CDNS_WDT_COUNTER_MAX   0xFFF
+
+/*********************    Register Map    **********************************/
+
+/*
+ * Zero Mode Register - This register controls how the time out is indicated
+ * and also contains the access code to allow writes to the register (0xABC).
+ */
+#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
+#define CDNS_WDT_ZMR_RSTEN_MASK        0x00000002 /* Enable the reset output */
+#define CDNS_WDT_ZMR_IRQEN_MASK        0x00000004 /* Enable IRQ output */
+#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
+#define CDNS_WDT_ZMR_ZKEY_VAL  0x00ABC000 /* Access key, 0xABC << 12 */
+
+/*
+ * Counter Control register - This register controls how fast the timer runs
+ * and the reset value and also contains the access code to allow writes to
+ * the register.
+ */
+#define CDNS_WDT_CCR_CRV_MASK  0x00003FFC /* Counter reset value */
+
+/* Write access to Registers */
+static inline void cdns_wdt_writereg(u32 *addr, u32 val)
+{
+       writel(val, addr);
+}
+
+/**
+ * cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog).
+ *
+ * @dev: Watchdog device
+ *
+ * Write the restart key value (0x00001999) to the restart register.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_reset(struct udevice *dev)
+{
+       struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+       debug("%s\n", __func__);
+
+       cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+       return 0;
+}
+
+/**
+ * cdns_wdt_start - Enable and start the watchdog.
+ *
+ * @dev: Watchdog device
+ * @timeout: Timeout value
+ * @flags: Driver flags
+ *
+ * The counter value is calculated according to the formula:
+ *             count = (timeout * clock) / prescaler + 1.
+ *
+ * The calculated count is divided by 0x1000 to obtain the field value
+ * to write to counter control register.
+ *
+ * Clears the contents of prescaler and counter reset value. Sets the
+ * prescaler to 4096 and the calculated count and access key
+ * to write to CCR Register.
+ *
+ * Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
+ * or Interrupt signal(IRQEN) with a specified cycles and the access
+ * key to write to ZMR Register.
+ *
+ * Return: Upon success 0, failure -1.
+ */
+static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+       ulong clk_f;
+       u32 count, prescaler, ctrl_clksel, data = 0;
+       struct clk clock;
+       struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+       if (clk_get_by_index(dev, 0, &clock) < 0) {
+               dev_err(dev, "failed to get clock\n");
+               return -1;
+       }
+
+       clk_f = clk_get_rate(&clock);
+       if (IS_ERR_VALUE(clk_f)) {
+               dev_err(dev, "failed to get rate\n");
+               return -1;
+       }
+
+       debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout);
+
+       if ((timeout < CDNS_WDT_MIN_TIMEOUT) ||
+           (timeout > CDNS_WDT_MAX_TIMEOUT)) {
+               timeout = priv->timeout;
+       }
+
+       if (clk_f <= CDNS_WDT_CLK_75MHZ) {
+               prescaler = CDNS_WDT_PRESCALE_512;
+               ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;
+       } else {
+               prescaler = CDNS_WDT_PRESCALE_4096;
+               ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;
+       }
+
+       /*
+        * Counter value divisor to obtain the value of
+        * counter reset to be written to control register.
+        */
+       count = (timeout * (clk_f / prescaler)) /
+               CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;
+
+       if (count > CDNS_WDT_COUNTER_MAX)
+               count = CDNS_WDT_COUNTER_MAX;
+
+       cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL);
+
+       count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
+
+       /* Write counter access key first to be able write to register */
+       data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel;
+       cdns_wdt_writereg(&priv->regs->ccr, data);
+
+       data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
+               CDNS_WDT_ZMR_ZKEY_VAL;
+
+       /* Reset on timeout if specified in device tree. */
+       if (priv->rst) {
+               data |= CDNS_WDT_ZMR_RSTEN_MASK;
+               data &= ~CDNS_WDT_ZMR_IRQEN_MASK;
+       } else {
+               data &= ~CDNS_WDT_ZMR_RSTEN_MASK;
+               data |= CDNS_WDT_ZMR_IRQEN_MASK;
+       }
+
+       cdns_wdt_writereg(&priv->regs->zmr, data);
+       cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
+
+       return 0;
+}
+
+/**
+ * cdns_wdt_stop - Stop the watchdog.
+ *
+ * @dev: Watchdog device
+ *
+ * Read the contents of the ZMR register, clear the WDEN bit in the register
+ * and set the access key for successful write.
+ *
+ * Return: Always 0
+ */
+static int cdns_wdt_stop(struct udevice *dev)
+{
+       struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+       cdns_wdt_writereg(&priv->regs->zmr,
+                         CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK));
+
+       return 0;
+}
+
+/**
+ * cdns_wdt_probe - Probe call for the device.
+ *
+ * @dev: Handle to the udevice structure.
+ *
+ * Return: Always 0.
+ */
+static int cdns_wdt_probe(struct udevice *dev)
+{
+       struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+       debug("%s: Probing wdt%u\n", __func__, dev->seq);
+
+       priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs));
+
+       cdns_wdt_stop(dev);
+
+       return 0;
+}
+
+static int cdns_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+       int node = dev_of_offset(dev);
+       struct cdns_wdt_priv *priv = dev_get_priv(dev);
+
+       priv->regs = devfdt_get_addr_ptr(dev);
+       if (IS_ERR(priv->regs))
+               return PTR_ERR(priv->regs);
+
+       priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec",
+                                      CDNS_WDT_DEFAULT_TIMEOUT);
+
+       priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout");
+
+       debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst);
+
+       return 0;
+}
+
+static const struct wdt_ops cdns_wdt_ops = {
+       .start = cdns_wdt_start,
+       .reset = cdns_wdt_reset,
+       .stop = cdns_wdt_stop,
+};
+
+static const struct udevice_id cdns_wdt_ids[] = {
+       { .compatible = "cdns,wdt-r1p2" },
+       {}
+};
+
+U_BOOT_DRIVER(cdns_wdt) = {
+       .name = "cdns_wdt",
+       .id = UCLASS_WDT,
+       .of_match = cdns_wdt_ids,
+       .probe = cdns_wdt_probe,
+       .priv_auto_alloc_size = sizeof(struct cdns_wdt_priv),
+       .ofdata_to_platdata = cdns_wdt_ofdata_to_platdata,
+       .ops = &cdns_wdt_ops,
+};

diff --git a/env/Kconfig b/env/Kconfig
index 0c1e928f136cf10756e9925950f95286fb2fb321..3bc1a35f658b0db7c1d2d18f7ec8d2c1bcbd78ef 100644 (file)
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -359,12 +359,6 @@ config ENV_IS_IN_UBI
          the environment in.  This will enable redundant environments in UBI.
          It is assumed that both volumes are in the same MTD partition.
 
-         - CONFIG_UBI_SILENCE_MSG
-         - CONFIG_UBIFS_SILENCE_MSG
-
-         You will probably want to define these to avoid a really noisy system
-         when storing the env in UBI.
-
 config ENV_FAT_INTERFACE
        string "Name of the block device for the environment"
        depends on ENV_IS_IN_FAT

diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index 6e1107d751bc63b7c0603bda218234c41d8cd03d..46da8f134fa77aecf9e48f7a5921186cdcd5bfe5 100644 (file)
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -168,9 +168,9 @@ static int file_cbfs_load_header(uintptr_t end_of_rom,
                                 struct cbfs_header *header)
 {
        struct cbfs_header *header_in_rom;
+       int32_t offset = *(u32 *)(end_of_rom - 3);
 
-       header_in_rom = (struct cbfs_header *)(uintptr_t)
-                       *(u32 *)(end_of_rom - 3);
+       header_in_rom = (struct cbfs_header *)(end_of_rom + offset + 1);
        swap_header(header, header_in_rom);
 
        if (header->magic != good_magic || header->offset >

diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9da35b8a3794a44f6f57fc7301cc230330ebb82d 100644 (file)
--- a/fs/ubifs/Kconfig
+++ b/fs/ubifs/Kconfig
@@ -0,0 +1,6 @@
+config UBIFS_SILENCE_MSG
+       bool "UBIFS silence verbose messages"
+       default ENV_IS_IN_UBI
+       help
+         Make the verbose messages from UBIFS stop printing. This leaves
+         warnings and errors enabled.

diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index effa8d933fe9d0db7d7b91085e39e826f3b4f804..2c478cba963914af65c8c9c6c9d5f49fcaf47c15 100644 (file)
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1334,7 +1334,10 @@ static int check_free_space(struct ubifs_info *c)
 static int mount_ubifs(struct ubifs_info *c)
 {
        int err;
-       long long x, y;
+       long long x;
+#ifndef CONFIG_UBIFS_SILENCE_MSG
+       long long y;
+#endif
        size_t sz;
 
        c->ro_mount = !!(c->vfs_sb->s_flags & MS_RDONLY);
@@ -1613,7 +1616,9 @@ static int mount_ubifs(struct ubifs_info *c)
                  c->vi.ubi_num, c->vi.vol_id, c->vi.name,
                  c->ro_mount ? ", R/O mode" : "");
        x = (long long)c->main_lebs * c->leb_size;
+#ifndef CONFIG_UBIFS_SILENCE_MSG
        y = (long long)c->log_lebs * c->leb_size + c->max_bud_bytes;
+#endif
        ubifs_msg(c, "LEB size: %d bytes (%d KiB), min./max. I/O unit sizes: %d bytes/%d bytes",
                  c->leb_size, c->leb_size >> 10, c->min_io_size,
                  c->max_write_size);

diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 1d894652059acf80a793fb02259e5bdf7ce7b709..b4ce706a8e6af65bc48c23dadb4d688480576094 100644 (file)
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -618,9 +618,13 @@ static inline ino_t parent_ino(struct dentry *dentry)
 #define UBIFS_VERSION 1
 
 /* Normal UBIFS messages */
+#ifdef CONFIG_UBIFS_SILENCE_MSG
+#define ubifs_msg(c, fmt, ...)
+#else
 #define ubifs_msg(c, fmt, ...)                                      \
        pr_notice("UBIFS (ubi%d:%d): " fmt "\n",                    \
                  (c)->vi.ubi_num, (c)->vi.vol_id, ##__VA_ARGS__)
+#endif
 /* UBIFS error messages */
 #ifndef __UBOOT__
 #define ubifs_err(c, fmt, ...)                                      \

diff --git a/include/command.h b/include/command.h
index 767cabb3df09752e36d46987b32b774a716061e1..56499b8ad5ca17bc61a4422f82afe9e72f3b2aad 100644 (file)
--- a/include/command.h
+++ b/include/command.h
@@ -111,6 +111,8 @@ extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
 extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 
+extern unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+                               char * const argv[]);
 /*
  * Error codes that commands return to cmd_process(). We use the standard 0
  * and 1 for success and failure, but add one more case - failure with a

diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h
index f5a8dec24a3f0fa49a26e3708e818f8771260661..1ebbc4c9e254ae450541650acd99d92b02fe1a22 100644 (file)
--- a/include/configs/adp-ae3xx.h
+++ b/include/configs/adp-ae3xx.h
@@ -80,12 +80,6 @@
 #endif
 #define CONFIG_SYS_NS16550_CLK         ((18432000 * 20) / 25)  /* AG101P */
 
-/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER         1
-#define CONFIG_FTSDC010_SDIO
-
 /*
  * Miscellaneous configurable options
  */

diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 6ae6fb454509af6c38e811a0804564c0a1cc8981..ff365c464e52c8f02445026e08eceeb518db6f70 100644 (file)
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -82,12 +82,6 @@
 #endif
 #define CONFIG_SYS_NS16550_CLK         ((18432000 * 20) / 25)  /* AG101P */
 
-/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER         1
-#define CONFIG_FTSDC010_SDIO
-
 /*
  * Miscellaneous configurable options
  */

diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 50fd46a589e0ddfa28f3cbd3e7361947ffceaa9f..fe3f838598fdb562d6d788e02f42c23afa2fd0dc 100644 (file)
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -22,10 +22,6 @@
 
 #define CONFIG_ENV_SIZE                        (96 << 10)      /*  96 KiB */
 
-/* Make the verbose messages from UBI stop printing */
-#define CONFIG_UBI_SILENCE_MSG
-#define CONFIG_UBIFS_SILENCE_MSG
-
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 #ifndef CONFIG_SPL_BUILD

diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index 454a7b7f7bafdaefdd3657af91e4a359f28b1fe5..5541cc5cf6a543450f0ce3780c16392908e41592 100644 (file)
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h
@@ -14,6 +14,13 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 

diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index ac0a6700f7c18f08272803909234f3d1fe586829..042479b5159ba09b0ee6f8bebba98d7100504100 100644 (file)
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h
@@ -14,6 +14,13 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 

diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index 41c7838a232eba79eb138704fe49e72490988b42..2cb9b5540eb020d16b351336af38f9b15d2edaf2 100644 (file)
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -14,6 +14,13 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 

diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index e9f53d6811784b907e582df95ffb3b58bd9a7d29..6c9c33b822fa8e8f163e05c4d7b9c8d1a01bd5b3 100644 (file)
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h
@@ -14,6 +14,11 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 

diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index 5d018a348140f0ffad71def1406d34625f961030..e3113ee309ce6d80ecbfc42d8e542e69b1f2f561 100644 (file)
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h
@@ -14,6 +14,13 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 

diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
new file mode 100644 (file)
index 0000000..2f92ac1
--- /dev/null
+++ b/include/configs/bmips_bcm6362.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6362_H
+#define __CONFIG_BMIPS_BCM6362_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ     200000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET      0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6362_H */

diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index ce35fae6a0f5917878f03bb9c6838437182a517b..ad8877b7d3a4bb855ff88470decf9d257bcdc5c6 100644 (file)
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h
@@ -14,6 +14,13 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 

diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
index fb4829ab4688bd69e5abd7f7621c7b3439607e79..ac86f3114255055c847a7079beb59f1793968e01 100644 (file)
--- a/include/configs/hsdk.h
+++ b/include/configs/hsdk.h
@@ -12,6 +12,7 @@
 /*
  *  CPU configuration
  */
+#define NR_CPUS                                4
 #define ARC_PERIPHERAL_BASE            0xF0000000
 #define ARC_DWMMC_BASE                 (ARC_PERIPHERAL_BASE + 0xA000)
 #define ARC_DWGMAC_BASE                        (ARC_PERIPHERAL_BASE + 0x18000)
@@ -61,6 +62,50 @@
  */
 #define CONFIG_ENV_SIZE                        SZ_16K
 
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "core_dccm_0=0x10\0" \
+       "core_dccm_1=0x6\0" \
+       "core_dccm_2=0x10\0" \
+       "core_dccm_3=0x6\0" \
+       "core_iccm_0=0x10\0" \
+       "core_iccm_1=0x6\0" \
+       "core_iccm_2=0x10\0" \
+       "core_iccm_3=0x6\0" \
+       "core_mask=0xF\0" \
+       "dcache_ena=0x1\0" \
+       "icache_ena=0x1\0" \
+       "non_volatile_limit=0xE\0" \
+       "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
+       "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+       "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+       "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
+       "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
+setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
+
 /*
  * Environment configuration
  */
@@ -68,12 +113,17 @@
 #define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 
 /*
- * Console configuration
+ * Misc utility configuration
  */
+#define CONFIG_BOUNCE_BUFFER
+
+/* Cli configuration */
+#define CONFIG_SYS_CBSIZE              SZ_2K
 
 /*
- * Misc utility configuration
+ * Callback configuration
  */
-#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
 
 #endif /* _CONFIG_HSDK_H_ */

diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 25df103983bc19e93e3c104186c337233ab8fcd9..dbb0fcc62b5ad19a7be848ada1d8552428ed7bef 100644 (file)
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -9,15 +9,6 @@
 
 #include "ls1012a_common.h"
 
-/* PFE Ethernet */
-#ifdef CONFIG_FSL_PFE
-#define EMAC1_PHY_ADDR          0x2
-#define EMAC2_PHY_ADDR          0x1
-#define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_AQUANTIA
-#endif
-
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
@@ -110,7 +101,7 @@
 
 #undef CONFIG_BOOTCOMMAND
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
                           "env exists secureboot && esbc_halt;"
 #endif
 

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index a58b867c1440c8c1c05b6e8dfd3dcd40b574cbab..0f8033f5b42012e921e0d88f4b60e0fb0f8ed7d2 100644 (file)
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -112,9 +112,9 @@
        "kernel_size=0x2800000\0"               \
 
 #undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND             "sf probe 0:0; sf read $kernel_load "\
-                                       "$kernel_start $kernel_size && "\
-                                       "bootm $kernel_load"
+#define CONFIG_BOOTCOMMAND     "pfe stop; sf probe 0:0; sf read $kernel_load "\
+                               "$kernel_start $kernel_size && "\
+                               "bootm $kernel_load"
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */

diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 297c057292273f9e9b74290d17cc86c162e1a37e..7c080a0cd38fe18809ddd1a6cd79da0e962b2b1b 100644 (file)
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -68,7 +68,7 @@
                "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
 
 #undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
 
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MEMTEST

diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 97ed9092e0abb4339101ee15412df4d8635d6d49..442c95eb1416243c3f9f69d86a562d7746bc558c 100644 (file)
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -25,6 +25,7 @@
  */
 
 #define I2C_MUX_IO_ADDR                0x24
+#define I2C_MUX_IO2_ADDR       0x25
 #define I2C_MUX_IO_0           0
 #define I2C_MUX_IO_1           1
 #define SW_BOOT_MASK           0x03
@@ -39,6 +40,9 @@
 #define SW_REV_C2              0xD8
 #define SW_REV_D               0xD0
 #define SW_REV_E               0xC8
+#define __PHY_MASK             0xF9
+#define __PHY_ETH2_MASK                0xFB
+#define __PHY_ETH1_MASK                0xFD
 
 /*  MMC  */
 #ifdef CONFIG_MMC
@@ -113,7 +117,7 @@
                "bootm $load_addr#$board\0"
 
 #undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "    \
+#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
                           "env exists secureboot && esbc_halt;"
 
 #include <asm/fsl_secure_boot.h>

diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 897a0497bb7eb3f657b94e858e6407e3f57f5ff8..34f991caa55b9be3a11b477ae39f4eb1d5ca1f4c 100644 (file)
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -27,7 +27,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_MMC_ENV_DEV         0
 #define CONFIG_ENV_SIZE                        0x2000
 #else
-#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define CONFIG_ENV_SIZE                        0x20000
@@ -41,6 +40,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CLK_FREQ            100000000
 #define CONFIG_DDR_CLK_FREQ            100000000
 #else
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
 #define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ            get_board_ddr_clk()
 #endif
@@ -89,13 +90,14 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NOR_CSOR    CSOR_NOR_ADM_SHIFT(12)
 #define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \
                                FTIM0_NOR_TEADC(0x5) | \
+                               FTIM0_NOR_TAVDS(0x6) | \
                                FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x35) | \
-                               FTIM1_NOR_TRAD_NOR(0x1a) |\
+                               FTIM1_NOR_TRAD_NOR(0x1a) | \
                                FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
-                               FTIM2_NOR_TCH(0x4) | \
-                               FTIM2_NOR_TWPH(0x0E) | \
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x8) | \
+                               FTIM2_NOR_TCH(0x8) | \
+                               FTIM2_NOR_TWPH(0xe) | \
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x04000000
 #define CONFIG_SYS_IFC_CCR     0x01000000
@@ -197,7 +199,7 @@ unsigned long get_board_ddr_clk(void);
                                        | CSPR_MSEL_GPCM \
                                        | CSPR_V)
 
-#define CONFIG_SYS_FPGA_AMASK          IFC_AMASK(64*1024)
+#define SYS_FPGA_AMASK         IFC_AMASK(64 * 1024)
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_FPGA_CSOR           CSOR_GPCM_ADM_SHIFT(0)
 #else
@@ -226,7 +228,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR2               CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_CSPR2_FINAL         SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_AMASK2              SYS_FPGA_AMASK
 #define CONFIG_SYS_CSOR2               CONFIG_SYS_FPGA_CSOR
 #define CONFIG_SYS_CS2_FTIM0           SYS_FPGA_CS_FTIM0
 #define CONFIG_SYS_CS2_FTIM1           SYS_FPGA_CS_FTIM1
@@ -262,13 +264,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT           CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3               CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL         CONFIG_SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSPR3_FINAL         SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3              SYS_FPGA_AMASK
 #define CONFIG_SYS_CSOR3               CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0           CONFIG_SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_CS_FTIM3
+#define CONFIG_SYS_CS3_FTIM0           SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1           SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2           SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3           SYS_FPGA_CS_FTIM3
 #endif
 
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 692f64275a8465270e986b572f731283c3a24ca6..5033008ca72df096b502a204440e61da3a0f9235 100644 (file)
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -369,7 +369,7 @@ unsigned long get_board_sys_clk(void);
        "fdt_high=0xa0000000\0"                 \
        "initrd_high=0xffffffffffffffff\0"      \
        "fdt_addr=0x64f00000\0"                 \
-       "kernel_addr=0x65000000\0"              \
+       "kernel_addr=0x581000000\0"             \
        "kernel_start=0x1000000\0"              \
        "kernelheader_start=0x800000\0"         \
        "scriptaddr=0x80000000\0"               \
@@ -439,8 +439,8 @@ unsigned long get_board_sys_clk(void);
                        "&& esbc_validate 0x20780000; "                 \
                        "env exists mcinitcmd && "                      \
                        "fsl_mc lazyapply dpl 0x20d00000; "             \
-                       "run distro_bootcmd;env exists secureboot "     \
-                       " && esbc_halt;run qspi_bootcmd; "
+                       "run distro_bootcmd;run qspi_bootcmd; "         \
+                       "env exists secureboot && esbc_halt;"
 #elif defined(CONFIG_SD_BOOT)
 /* Try to boot an on-SD kernel first, then do normal distro boot */
 #define CONFIG_BOOTCOMMAND                                             \
@@ -450,16 +450,16 @@ unsigned long get_board_sys_clk(void);
                        "env exists mcinitcmd && run mcinitcmd "        \
                        "&& mmc read 0x88000000 0x6800 0x800 "          \
                        "&& fsl_mc lazyapply dpl 0x88000000; "          \
-                       "run distro_bootcmd;env exists secureboot "     \
-                       "&& esbc_halt;run sd_bootcmd;"
+                       "run distro_bootcmd;run sd_bootcmd; "           \
+                       "env exists secureboot && esbc_halt;"
 #else
 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 #define CONFIG_BOOTCOMMAND                                             \
                        "env exists mcinitcmd && env exists secureboot "\
                        "&& esbc_validate 0x580780000; env exists mcinitcmd "\
                        "&& fsl_mc lazyapply dpl 0x580d00000;"          \
-                       "run distro_bootcmd; env exists secureboot "    \
-                       "&& esbc_halt; run nor_bootcmd;"
+                       "run distro_bootcmd;run nor_bootcmd; "          \
+                       "env exists secureboot && esbc_halt;"
 #endif
 
 /* MAC/PHY configuration */

diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index f288cf5b17ad94042d7f0f9f8b88480f4224ede1..1cd0fa93d345b76f879de269990b84a4dfd337fe 100644 (file)
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -106,4 +106,23 @@
 #define CONFIG_E1000
 #endif
 
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 1) \
+       func(MMC, mmc, 0) \
+       func(USB, usb, 0) \
+       func(SCSI, scsi, 0) \
+       func(PXE, pxe, na) \
+       func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS      \
+       "scriptaddr=0x4d00000\0"        \
+       "pxefile_addr_r=0x4e00000\0"    \
+       "fdt_addr_r=0x4f00000\0"        \
+       "kernel_addr_r=0x5000000\0"     \
+       "ramdisk_addr_r=0x8000000\0"    \
+       "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+       BOOTENV
+
 #endif /* _CONFIG_MVEBU_ARMADA_8K_H */

diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h
new file mode 100644 (file)
index 0000000..0c3823b
--- /dev/null
+++ b/include/configs/netgear_dgnd3700v2.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6362.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+

diff --git a/include/configs/nx25-ae250.h b/include/configs/nx25-ae250.h
index 73c3c33ffa5a181cf6d8cb5100b3a2c01ecb0b89..0e4c431cabf7cb88b5c22d152521b35db5c2418f 100644 (file)
--- a/include/configs/nx25-ae250.h
+++ b/include/configs/nx25-ae250.h
@@ -11,18 +11,9 @@
 /*
  * CPU and Board Configuration Options
  */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_SERVERIP
 
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_SEPARATE
-#define CONFIG_OF_EMBED
-#endif
-#endif
-
 /*
  * Miscellaneous configurable options
  */
@@ -50,6 +41,9 @@
  */
 #define CONFIG_SYS_MALLOC_LEN   (512 << 10)
 
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE            0x000f0000
+
 /*
  * Physical Memory Map
  */
@@ -70,12 +64,6 @@
 #endif
 #define CONFIG_SYS_NS16550_CLK         19660800
 
-/*
- * SD (MMC) controller
- */
-#define CONFIG_FTSDC010_NUMBER         1
-#define CONFIG_FTSDC010_SDIO
-
 /* Init Stack Pointer */
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
                                        GENERATED_GBL_DATA_SIZE)

diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 76d8e13d52c107d1d5bc79bb062d4d241d894627..e2a7f63e4fa2b9dc160f2c11833b85d106bcf85e 100644 (file)
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -136,8 +136,6 @@
 #define CONFIG_ENV_UBI_PART            "UBI"
 #define CONFIG_ENV_UBI_VOLUME          "config"
 #define CONFIG_ENV_UBI_VOLUME_REDUND   "config_r"
-#define CONFIG_UBI_SILENCE_MSG         1
-#define CONFIG_UBIFS_SILENCE_MSG       1
 #define CONFIG_ENV_SIZE                        (32*1024)
 
 #endif /* __IGEP00X0_H */

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 12b266e51532b0e89986e5e00c1d5667fe74c4ab..77b89bc7a03c6c2a0f526fb22ebddc6664de6b49 100644 (file)
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -19,6 +19,14 @@
 #undef CONFIG_SYS_USE_NOR
 #define        CONFIG_USE_NAND
 
+/*
+* Disable DM_* for SPL build and can be re-enabled after adding
+* DM support in SPL
+*/
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_I2C
+#undef CONFIG_DM_I2C_COMPAT
+#endif
 /*
  * SoC Configuration
  */
@@ -57,7 +65,8 @@
  * PLL configuration
  */
 
-#define CONFIG_SYS_DA850_PLL0_PLLM     37
+/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
+#define CONFIG_SYS_DA850_PLL0_PLLM     18
 #define CONFIG_SYS_DA850_PLL1_PLLM     21
 
 /*
@@ -104,11 +113,14 @@
 /*
  * Serial Driver info
  */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#if !defined(CONFIG_DM_SERIAL)
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    -4      /* NS16550 register size */
 #define CONFIG_SYS_NS16550_COM1        DAVINCI_UART2_BASE /* Base address of UART2 */
 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#endif
 
 #define CONFIG_SPI
 #define CONFIG_SYS_SPI_BASE            DAVINCI_SPI1_BASE
@@ -125,7 +137,6 @@
 /*
  * I2C Configuration
  */
-#define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_DAVINCI
 #define CONFIG_SYS_DAVINCI_I2C_SPEED   25000
 #define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 8582252dc306b85477ec71187c5088441703ec67..f0e550d8aae781c4fde4eaa75288b41c176520a2 100644 (file)
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -59,6 +59,7 @@
 #include <config_distro_bootcmd.h>
 #define CONFIG_EXTRA_ENV_SETTINGS \
        ENV_MEM_LAYOUT_SETTINGS \
+       "fdtfile=rockchip/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
        "partitions=" PARTS_DEFAULT \
        BOOTENV
 

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 801980ea3388d2d1742f9392ebf585ec284360e9..8b8a73d0f9ee79a43343c6f1b9e56562ba712418 100644 (file)
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -79,4 +79,14 @@
 #endif
 /* For SPL ends */
 
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
 #endif /* __CONFIG_H */

diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
new file mode 100644 (file)
index 0000000..aae2cb8
--- /dev/null
+++ b/include/configs/stm32mp1.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP15x CPU
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+#define CONFIG_PREBOOT
+
+/*
+ * Number of clock ticks in 1 sec
+ */
+#define CONFIG_SYS_HZ                          1000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK                    64000000
+
+/*
+ * malloc() pool size
+ */
+#define CONFIG_SYS_MALLOC_LEN                  SZ_32M
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE                  STM32_DDR_BASE
+#define CONFIG_SYS_INIT_SP_ADDR                        CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_NR_DRAM_BANKS   1
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE                      SZ_1K
+
+/*
+ * Needed by "loadb"
+ */
+#define CONFIG_SYS_LOAD_ADDR                   STM32_DDR_BASE
+
+/*
+ * Env parameters
+ */
+#define CONFIG_ENV_SIZE                                SZ_4K
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* SPL support */
+#ifdef CONFIG_SPL
+/* BOOTROM load address */
+#define CONFIG_SPL_TEXT_BASE           0x2FFC2500
+/* SPL use DDR */
+#define CONFIG_SPL_BSS_START_ADDR      0xC0200000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START    0xC0300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
+
+/* limit SYSRAM usage to first 128 KB */
+#define CONFIG_SPL_MAX_SIZE            0x00020000
+#define CONFIG_SPL_STACK               (STM32_SYSRAM_BASE + \
+                                        STM32_SYSRAM_SIZE)
+#endif /* #ifdef CONFIG_SPL */
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE      3
+
+#if !defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD)
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 1) \
+       func(MMC, mmc, 0) \
+       func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "scriptaddr=0xC0000000\0" \
+       "pxefile_addr_r=0xC0000000\0" \
+       "kernel_addr_r=0xC1000000\0" \
+       "fdt_addr_r=0xC4000000\0" \
+       "ramdisk_addr_r=0xC4100000\0" \
+       "fdt_high=0xffffffff\0" \
+       "initrd_high=0xffffffff\0" \
+       BOOTENV
+
+#endif /* ifndef CONFIG_SPL_BUILD */
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index e23b0f2adb7da8a6af123fc447611c6f7b3cf2eb..8c0b5d9c06aec18b4be416e38c4aebf41dfea1e0 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -21,7 +21,9 @@
 #define GICC_BASE      0xF9020000
 
 #define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
+#ifndef CONFIG_SYS_MEMTEST_SCRATCH
+# define CONFIG_SYS_MEMTEST_SCRATCH    0x10800000
+#endif
 
 #ifndef CONFIG_NR_DRAM_BANKS
 # define CONFIG_NR_DRAM_BANKS          2

diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
deleted file mode 100644 (file)
index a26377a..0000000
--- a/include/configs/xilinx_zynqmp_ep.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Configuration for Xilinx ZynqMP emulation platforms
- *
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- *
- * Based on Configuration for Versatile Express
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQMP_EP_H
-#define __CONFIG_ZYNQMP_EP_H
-
-#define CONFIG_ZYNQ_EEPROM
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
-                                ZYNQMP_USB1_XHCI_BASEADDR}
-
-#define COUNTER_FREQUENCY      4000000
-
-#include <configs/xilinx_zynqmp.h>
-
-#endif /* __CONFIG_ZYNQMP_EP_H */

diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
index 00f4c1c087b067f63b7c2228d1fb6b0674c468d0..4fbf85a9edc39a0d96175ae9b2610eabc38357aa 100644 (file)
--- a/include/configs/xilinx_zynqmp_mini.h
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -11,6 +11,8 @@
 #ifndef __CONFIG_ZYNQMP_MINI_H
 #define __CONFIG_ZYNQMP_MINI_H
 
+#define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
+
 #include <configs/xilinx_zynqmp.h>
 
 /* Undef unneeded configs */

diff --git a/include/dm/platform_data/pfe_dm_eth.h b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644 (file)
index 0000000..7943c67
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include <net.h>
+
+struct pfe_ddr_address {
+       void *ddr_pfe_baseaddr;
+       unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+       struct eth_pdata pfe_eth_pdata_mac;
+       struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */

diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 07fabc3ce6cf67d0dc45c85ef598ecd6247c41d7..d28fb3e23f01f78e746c13c17c25bb11df33d448 100644 (file)
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -19,6 +19,7 @@ enum uclass_id {
        UCLASS_TEST_FDT,
        UCLASS_TEST_BUS,
        UCLASS_TEST_PROBE,
+       UCLASS_TEST_DUMMY,
        UCLASS_SPI_EMUL,        /* sandbox SPI device emulator */
        UCLASS_I2C_EMUL,        /* sandbox I2C device emulator */
        UCLASS_PCI_EMUL,        /* sandbox PCI device emulator */

diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 3a01abc239ea9d48d869361c871939634cf24fa3..a5bf3eb831868b7f5e3efd75e2d505da4078df37 100644 (file)
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -210,6 +210,22 @@ int uclass_get_device_by_of_offset(enum uclass_id id, int node,
 int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node,
                                struct udevice **devp);
 
+/**
+ * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id
+ *
+ * This searches the devices in the uclass for one with the given phandle id.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: uclass ID to look up
+ * @phandle_id: the phandle id to look up
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ENODEV if there is no device match the phandle, other
+ *     -ve on error
+ */
+int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
+                                   struct udevice **devp);
+
 /**
  * uclass_get_device_by_phandle() - Get a uclass device by phandle
  *

diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h
new file mode 100644 (file)
index 0000000..6b11a9f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6362-clock.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
+#define __DT_BINDINGS_CLOCK_BCM6362_H
+
+#define BCM6362_CLK_GLESS      0
+#define BCM6362_CLK_ADSL_QPROC 1
+#define BCM6362_CLK_ADSL_AFE   2
+#define BCM6362_CLK_ADSL       3
+#define BCM6362_CLK_MIPS       4
+#define BCM6362_CLK_WLAN_OCP   5
+#define BCM6362_CLK_SWPKT_USB  7
+#define BCM6362_CLK_SWPKT_SAR  8
+#define BCM6362_CLK_SAR                9
+#define BCM6362_CLK_ROBOSW     10
+#define BCM6362_CLK_PCM                11
+#define BCM6362_CLK_USBD       12
+#define BCM6362_CLK_USBH       13
+#define BCM6362_CLK_IPSEC      14
+#define BCM6362_CLK_SPI                15
+#define BCM6362_CLK_HSSPI      16
+#define BCM6362_CLK_PCIE       17
+#define BCM6362_CLK_FAP                18
+#define BCM6362_CLK_PHYMIPS    19
+#define BCM6362_CLK_NAND       20
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644 (file)
index 0000000..1643158
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+/* OSCILLATOR clocks */
+#define CK_HSE 0
+#define CK_CSI 1
+#define CK_LSI 2
+#define CK_LSE 3
+#define CK_HSI 4
+#define CK_HSE_DIV2 5
+
+/* Bus clocks */
+#define TIM2 6
+#define TIM3 7
+#define TIM4 8
+#define TIM5 9
+#define TIM6 10
+#define TIM7 11
+#define TIM12 12
+#define TIM13 13
+#define TIM14 14
+#define LPTIM1 15
+#define SPI2 16
+#define SPI3 17
+#define USART2 18
+#define USART3 19
+#define UART4 20
+#define UART5 21
+#define UART7 22
+#define UART8 23
+#define I2C1 24
+#define I2C2 25
+#define I2C3 26
+#define I2C5 27
+#define SPDIF 28
+#define CEC 29
+#define DAC12 30
+#define MDIO 31
+#define TIM1 32
+#define TIM8 33
+#define TIM15 34
+#define TIM16 35
+#define TIM17 36
+#define SPI1 37
+#define SPI4 38
+#define SPI5 39
+#define USART6 40
+#define SAI1 41
+#define SAI2 42
+#define SAI3 43
+#define DFSDM 44
+#define FDCAN 45
+#define LPTIM2 46
+#define LPTIM3 47
+#define LPTIM4 48
+#define LPTIM5 49
+#define SAI4 50
+#define SYSCFG 51
+#define VREF 52
+#define TMPSENS 53
+#define PMBCTRL 54
+#define HDP 55
+#define LTDC 56
+#define DSI 57
+#define IWDG2 58
+#define USBPHY 59
+#define STGENRO 60
+#define SPI6 61
+#define I2C4 62
+#define I2C6 63
+#define USART1 64
+#define RTCAPB 65
+#define TZC 66
+#define TZPC 67
+#define IWDG1 68
+#define BSEC 69
+#define STGEN 70
+#define DMA1 71
+#define DMA2 72
+#define DMAMUX 73
+#define ADC12 74
+#define USBO 75
+#define SDMMC3 76
+#define DCMI 77
+#define CRYP2 78
+#define HASH2 79
+#define RNG2 80
+#define CRC2 81
+#define HSEM 82
+#define IPCC 83
+#define GPIOA 84
+#define GPIOB 85
+#define GPIOC 86
+#define GPIOD 87
+#define GPIOE 88
+#define GPIOF 89
+#define GPIOG 90
+#define GPIOH 91
+#define GPIOI 92
+#define GPIOJ 93
+#define GPIOK 94
+#define GPIOZ 95
+#define CRYP1 96
+#define HASH1 97
+#define RNG1 98
+#define BKPSRAM 99
+#define MDMA 100
+#define DMA2D 101
+#define GPU 102
+#define ETHCK 103
+#define ETHTX 104
+#define ETHRX 105
+#define ETHMAC 106
+#define FMC 107
+#define QSPI 108
+#define SDMMC1 109
+#define SDMMC2 110
+#define CRC1 111
+#define USBH 112
+#define ETHSTP 113
+
+/* Kernel clocks */
+#define SDMMC1_K 114
+#define SDMMC2_K 115
+#define SDMMC3_K 116
+#define FMC_K 117
+#define QSPI_K 118
+#define ETHMAC_K 119
+#define RNG1_K 120
+#define RNG2_K 121
+#define GPU_K 122
+#define USBPHY_K 123
+#define STGEN_K 124
+#define SPDIF_K 125
+#define SPI1_K 126
+#define SPI2_K 127
+#define SPI3_K 128
+#define SPI4_K 129
+#define SPI5_K 130
+#define SPI6_K 131
+#define CEC_K 132
+#define I2C1_K 133
+#define I2C2_K 134
+#define I2C3_K 135
+#define I2C4_K 136
+#define I2C5_K 137
+#define I2C6_K 138
+#define LPTIM1_K 139
+#define LPTIM2_K 140
+#define LPTIM3_K 141
+#define LPTIM4_K 142
+#define LPTIM5_K 143
+#define USART1_K 144
+#define USART2_K 145
+#define USART3_K 146
+#define UART4_K 147
+#define UART5_K 148
+#define USART6_K 149
+#define UART7_K 150
+#define UART8_K 151
+#define DFSDM_K 152
+#define FDCAN_K 153
+#define SAI1_K 154
+#define SAI2_K 155
+#define SAI3_K 156
+#define SAI4_K 157
+#define ADC12_K 158
+#define DSI_K 159
+#define ADFSDM_K 160
+#define USBO_K 161
+#define LTDC_K 162
+
+/* PLL */
+#define PLL1 163
+#define PLL2 164
+#define PLL3 165
+#define PLL4 166
+
+/* ODF */
+#define PLL1_P 167
+#define PLL1_Q 168
+#define PLL1_R 169
+#define PLL2_P 170
+#define PLL2_Q 171
+#define PLL2_R 172
+#define PLL3_P 173
+#define PLL3_Q 174
+#define PLL3_R 175
+#define PLL4_P 176
+#define PLL4_Q 177
+#define PLL4_R 178
+
+/* AUX */
+#define RTC 179
+
+/* MCLK */
+#define CK_PER 180
+#define CK_MPU 181
+#define CK_AXI 182
+#define CK_MCU 183
+
+/* Time base */
+#define TIM2_K 184
+#define TIM3_K 185
+#define TIM4_K 186
+#define TIM5_K 187
+#define TIM6_K 188
+#define TIM7_K 189
+#define TIM12_K 190
+#define TIM13_K 191
+#define TIM14_K 192
+#define TIM1_K 193
+#define TIM8_K 194
+#define TIM15_K 195
+#define TIM16_K 196
+#define TIM17_K 197
+
+/* MCO clocks */
+#define CK_MCO1 198
+#define CK_MCO2 199
+
+/* TRACE & DEBUG clocks */
+#define DBG 200
+#define CK_DBG 201
+#define CK_TRACE 202
+
+/* DDR */
+#define DDRC1 203
+#define DDRC1LP 204
+#define DDRC2 205
+#define DDRC2LP 206
+#define DDRPHYC 207
+#define DDRPHYCLP 208
+#define DDRCAPB 209
+#define DDRCAPBLP 210
+#define AXIDCG 211
+#define DDRPHYCAPB 212
+#define DDRPHYCAPBLP 213
+#define DDRPERFM 214
+
+#define STM32MP1_LAST_CLK 215

diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h
new file mode 100644 (file)
index 0000000..19fd959
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clksrc.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+
+/* PLL output is enable when x=1, with x=p,q or r */
+#define PQR(p, q, r)   (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
+
+/* st,clksrc: mandatory clock source */
+
+#define CLK_MPU_HSI            0x00000200
+#define CLK_MPU_HSE            0x00000201
+#define CLK_MPU_PLL1P          0x00000202
+#define CLK_MPU_PLL1P_DIV      0x00000203
+
+#define CLK_AXI_HSI            0x00000240
+#define CLK_AXI_HSE            0x00000241
+#define CLK_AXI_PLL2P          0x00000242
+
+#define CLK_MCU_HSI            0x00000480
+#define CLK_MCU_HSE            0x00000481
+#define CLK_MCU_CSI            0x00000482
+#define CLK_MCU_PLL3P          0x00000483
+
+#define CLK_PLL12_HSI          0x00000280
+#define CLK_PLL12_HSE          0x00000281
+
+#define CLK_PLL3_HSI           0x00008200
+#define CLK_PLL3_HSE           0x00008201
+#define CLK_PLL3_CSI           0x00008202
+
+#define CLK_PLL4_HSI           0x00008240
+#define CLK_PLL4_HSE           0x00008241
+#define CLK_PLL4_CSI           0x00008242
+#define CLK_PLL4_I2SCKIN       0x00008243
+
+#define CLK_RTC_DISABLED       0x00001400
+#define CLK_RTC_LSE            0x00001401
+#define CLK_RTC_LSI            0x00001402
+#define CLK_RTC_HSE            0x00001403
+
+#define CLK_MCO1_HSI           0x00008000
+#define CLK_MCO1_HSE           0x00008001
+#define CLK_MCO1_CSI           0x00008002
+#define CLK_MCO1_LSI           0x00008003
+#define CLK_MCO1_LSE           0x00008004
+#define CLK_MCO1_DISABLED      0x0000800F
+
+#define CLK_MCO2_MPU           0x00008040
+#define CLK_MCO2_AXI           0x00008041
+#define CLK_MCO2_MCU           0x00008042
+#define CLK_MCO2_PLL4P         0x00008043
+#define CLK_MCO2_HSE           0x00008044
+#define CLK_MCO2_HSI           0x00008045
+#define CLK_MCO2_DISABLED      0x0000804F
+
+/* st,pkcs: peripheral kernel clock source */
+
+#define CLK_I2C12_PCLK1                0x00008C00
+#define CLK_I2C12_PLL4R                0x00008C01
+#define CLK_I2C12_HSI          0x00008C02
+#define CLK_I2C12_CSI          0x00008C03
+#define CLK_I2C12_DISABLED     0x00008C07
+
+#define CLK_I2C35_PCLK1                0x00008C40
+#define CLK_I2C35_PLL4R                0x00008C41
+#define CLK_I2C35_HSI          0x00008C42
+#define CLK_I2C35_CSI          0x00008C43
+#define CLK_I2C35_DISABLED     0x00008C47
+
+#define CLK_I2C46_PCLK5                0x00000C00
+#define CLK_I2C46_PLL3Q                0x00000C01
+#define CLK_I2C46_HSI          0x00000C02
+#define CLK_I2C46_CSI          0x00000C03
+#define CLK_I2C46_DISABLED     0x00000C07
+
+#define CLK_SAI1_PLL4Q         0x00008C80
+#define CLK_SAI1_PLL3Q         0x00008C81
+#define CLK_SAI1_I2SCKIN       0x00008C82
+#define CLK_SAI1_CKPER         0x00008C83
+#define CLK_SAI1_PLL3R         0x00008C84
+#define CLK_SAI1_DISABLED      0x00008C87
+
+#define CLK_SAI2_PLL4Q         0x00008CC0
+#define CLK_SAI2_PLL3Q         0x00008CC1
+#define CLK_SAI2_I2SCKIN       0x00008CC2
+#define CLK_SAI2_CKPER         0x00008CC3
+#define CLK_SAI2_SPDIF         0x00008CC4
+#define CLK_SAI2_PLL3R         0x00008CC5
+#define CLK_SAI2_DISABLED      0x00008CC7
+
+#define CLK_SAI3_PLL4Q         0x00008D00
+#define CLK_SAI3_PLL3Q         0x00008D01
+#define CLK_SAI3_I2SCKIN       0x00008D02
+#define CLK_SAI3_CKPER         0x00008D03
+#define CLK_SAI3_PLL3R         0x00008D04
+#define CLK_SAI3_DISABLED      0x00008D07
+
+#define CLK_SAI4_PLL4Q         0x00008D40
+#define CLK_SAI4_PLL3Q         0x00008D41
+#define CLK_SAI4_I2SCKIN       0x00008D42
+#define CLK_SAI4_CKPER         0x00008D43
+#define CLK_SAI4_PLL3R         0x00008D44
+#define CLK_SAI4_DISABLED      0x00008D47
+
+#define CLK_SPI2S1_PLL4P       0x00008D80
+#define CLK_SPI2S1_PLL3Q       0x00008D81
+#define CLK_SPI2S1_I2SCKIN     0x00008D82
+#define CLK_SPI2S1_CKPER       0x00008D83
+#define CLK_SPI2S1_PLL3R       0x00008D84
+#define CLK_SPI2S1_DISABLED    0x00008D87
+
+#define CLK_SPI2S23_PLL4P      0x00008DC0
+#define CLK_SPI2S23_PLL3Q      0x00008DC1
+#define CLK_SPI2S23_I2SCKIN    0x00008DC2
+#define CLK_SPI2S23_CKPER      0x00008DC3
+#define CLK_SPI2S23_PLL3R      0x00008DC4
+#define CLK_SPI2S23_DISABLED   0x00008DC7
+
+#define CLK_SPI45_PCLK2                0x00008E00
+#define CLK_SPI45_PLL4Q                0x00008E01
+#define CLK_SPI45_HSI          0x00008E02
+#define CLK_SPI45_CSI          0x00008E03
+#define CLK_SPI45_HSE          0x00008E04
+#define CLK_SPI45_DISABLED     0x00008E07
+
+#define CLK_SPI6_PCLK5         0x00000C40
+#define CLK_SPI6_PLL4Q         0x00000C41
+#define CLK_SPI6_HSI           0x00000C42
+#define CLK_SPI6_CSI           0x00000C43
+#define CLK_SPI6_HSE           0x00000C44
+#define CLK_SPI6_PLL3Q         0x00000C45
+#define CLK_SPI6_DISABLED      0x00000C47
+
+#define CLK_UART6_PCLK2                0x00008E40
+#define CLK_UART6_PLL4Q                0x00008E41
+#define CLK_UART6_HSI          0x00008E42
+#define CLK_UART6_CSI          0x00008E43
+#define CLK_UART6_HSE          0x00008E44
+#define CLK_UART6_DISABLED     0x00008E47
+
+#define CLK_UART24_PCLK1       0x00008E80
+#define CLK_UART24_PLL4Q       0x00008E81
+#define CLK_UART24_HSI         0x00008E82
+#define CLK_UART24_CSI         0x00008E83
+#define CLK_UART24_HSE         0x00008E84
+#define CLK_UART24_DISABLED    0x00008E87
+
+#define CLK_UART35_PCLK1       0x00008EC0
+#define CLK_UART35_PLL4Q       0x00008EC1
+#define CLK_UART35_HSI         0x00008EC2
+#define CLK_UART35_CSI         0x00008EC3
+#define CLK_UART35_HSE         0x00008EC4
+#define CLK_UART35_DISABLED    0x00008EC7
+
+#define CLK_UART78_PCLK1       0x00008F00
+#define CLK_UART78_PLL4Q       0x00008F01
+#define CLK_UART78_HSI         0x00008F02
+#define CLK_UART78_CSI         0x00008F03
+#define CLK_UART78_HSE         0x00008F04
+#define CLK_UART78_DISABLED    0x00008F07
+
+#define CLK_UART1_PCLK5                0x00000C80
+#define CLK_UART1_PLL3Q                0x00000C81
+#define CLK_UART1_HSI          0x00000C82
+#define CLK_UART1_CSI          0x00000C83
+#define CLK_UART1_PLL4Q                0x00000C84
+#define CLK_UART1_HSE          0x00000C85
+#define CLK_UART1_DISABLED     0x00000C87
+
+#define CLK_SDMMC12_HCLK6      0x00008F40
+#define CLK_SDMMC12_PLL3R      0x00008F41
+#define CLK_SDMMC12_PLL4P      0x00008F42
+#define CLK_SDMMC12_HSI                0x00008F43
+#define CLK_SDMMC12_DISABLED   0x00008F47
+
+#define CLK_SDMMC3_HCLK2       0x00008F80
+#define CLK_SDMMC3_PLL3R       0x00008F81
+#define CLK_SDMMC3_PLL4P       0x00008F82
+#define CLK_SDMMC3_HSI         0x00008F83
+#define CLK_SDMMC3_DISABLED    0x00008F87
+
+#define CLK_ETH_PLL4P          0x00008FC0
+#define CLK_ETH_PLL3Q          0x00008FC1
+#define CLK_ETH_DISABLED       0x00008FC3
+
+#define CLK_QSPI_ACLK          0x00009000
+#define CLK_QSPI_PLL3R         0x00009001
+#define CLK_QSPI_PLL4P         0x00009002
+#define CLK_QSPI_CKPER         0x00009003
+
+#define CLK_FMC_ACLK           0x00009040
+#define CLK_FMC_PLL3R          0x00009041
+#define CLK_FMC_PLL4P          0x00009042
+#define CLK_FMC_CKPER          0x00009043
+
+#define CLK_FDCAN_HSE          0x000090C0
+#define CLK_FDCAN_PLL3Q                0x000090C1
+#define CLK_FDCAN_PLL4Q                0x000090C2
+#define CLK_FDCAN_PLL4R                0x000090C3
+
+#define CLK_SPDIF_PLL4P                0x00009140
+#define CLK_SPDIF_PLL3Q                0x00009141
+#define CLK_SPDIF_HSI          0x00009142
+#define CLK_SPDIF_DISABLED     0x00009143
+
+#define CLK_CEC_LSE            0x00009180
+#define CLK_CEC_LSI            0x00009181
+#define CLK_CEC_CSI_DIV122     0x00009182
+#define CLK_CEC_DISABLED       0x00009183
+
+#define CLK_USBPHY_HSE         0x000091C0
+#define CLK_USBPHY_PLL4R       0x000091C1
+#define CLK_USBPHY_HSE_DIV2    0x000091C2
+#define CLK_USBPHY_DISABLED    0x000091C3
+
+#define CLK_USBO_PLL4R         0x800091C0
+#define CLK_USBO_USBPHY                0x800091C1
+
+#define CLK_RNG1_CSI           0x00000CC0
+#define CLK_RNG1_PLL4R         0x00000CC1
+#define CLK_RNG1_LSE           0x00000CC2
+#define CLK_RNG1_LSI           0x00000CC3
+
+#define CLK_RNG2_CSI           0x00009200
+#define CLK_RNG2_PLL4R         0x00009201
+#define CLK_RNG2_LSE           0x00009202
+#define CLK_RNG2_LSI           0x00009203
+
+#define CLK_CKPER_HSI          0x00000D00
+#define CLK_CKPER_CSI          0x00000D01
+#define CLK_CKPER_HSE          0x00000D02
+#define CLK_CKPER_DISABLED     0x00000D03
+
+#define CLK_STGEN_HSI          0x00000D40
+#define CLK_STGEN_HSE          0x00000D41
+#define CLK_STGEN_DISABLED     0x00000D43
+
+#define CLK_DSI_DSIPLL         0x00009240
+#define CLK_DSI_PLL4P          0x00009241
+
+#define CLK_ADC_PLL4R          0x00009280
+#define CLK_ADC_CKPER          0x00009281
+#define CLK_ADC_PLL3Q          0x00009282
+#define CLK_ADC_DISABLED       0x00009283
+
+#define CLK_LPTIM45_PCLK3      0x000092C0
+#define CLK_LPTIM45_PLL4P      0x000092C1
+#define CLK_LPTIM45_PLL3Q      0x000092C2
+#define CLK_LPTIM45_LSE                0x000092C3
+#define CLK_LPTIM45_LSI                0x000092C4
+#define CLK_LPTIM45_CKPER      0x000092C5
+#define CLK_LPTIM45_DISABLED   0x000092C7
+
+#define CLK_LPTIM23_PCLK3      0x00009300
+#define CLK_LPTIM23_PLL4Q      0x00009301
+#define CLK_LPTIM23_CKPER      0x00009302
+#define CLK_LPTIM23_LSE                0x00009303
+#define CLK_LPTIM23_LSI                0x00009304
+#define CLK_LPTIM23_DISABLED   0x00009307
+
+#define CLK_LPTIM1_PCLK1       0x00009340
+#define CLK_LPTIM1_PLL4P       0x00009341
+#define CLK_LPTIM1_PLL3Q       0x00009342
+#define CLK_LPTIM1_LSE         0x00009343
+#define CLK_LPTIM1_LSI         0x00009344
+#define CLK_LPTIM1_CKPER       0x00009345
+#define CLK_LPTIM1_DISABLED    0x00009347
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD        0
+#define SSCG_MODE_DOWN_SPREAD  1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST          0
+#define LSEDRV_MEDIUM_LOW      1
+#define LSEDRV_MEDIUM_HIGH     2
+#define LSEDRV_HIGHEST         3
+
+#endif

diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h
new file mode 100644 (file)
index 0000000..3178b00
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+
+#define BCM6362_PWR_SAR                0
+#define BCM6362_PWR_IPSEC      1
+#define BCM6362_PWR_MIPS       2
+#define BCM6362_PWR_DECT       3
+#define BCM6362_PWR_USBH       4
+#define BCM6362_PWR_USBD       5
+#define BCM6362_PWR_ROBOSW     6
+#define BCM6362_PWR_PCM                7
+#define BCM6362_PWR_PERIPH     8
+#define BCM6362_PWR_ADSL_PHY   9
+#define BCM6362_PWR_GMII_PADS  10
+#define BCM6362_PWR_FAP                11
+#define BCM6362_PWR_PCIE       12
+#define BCM6362_PWR_WLAN_PADS  13
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */

diff --git a/include/dt-bindings/reset-controller/stm32mp1-resets.h b/include/dt-bindings/reset-controller/stm32mp1-resets.h
new file mode 100644 (file)
index 0000000..f279f8f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stm32mp1-resets.h
@@ -0,0 +1,97 @@
+#define        LTDC_R          3072
+#define        DSI_R           3076
+#define DDRPERFM_R     3080
+#define        USBPHY_R        3088
+#define        SPI6_R          3136
+#define        I2C4_R          3138
+#define        I2C6_R          3139
+#define        USART1_R        3140
+#define        STGEN_R         3156
+#define        GPIOZ_R         3200
+#define        CRYP1_R         3204
+#define        HASH1_R         3205
+#define        RNG1_R          3206
+#define AXIM_R         3216
+#define        GPU_R           3269
+#define        ETHMAC_R        3274
+#define        FMC_R           3276
+#define        QSPI_R          3278
+#define        SDMMC1_R        3280
+#define        SDMMC2_R        3281
+#define        CRC1_R          3284
+#define        USBH_R          3288
+#define        MDMA_R          3328
+#define MCU_R          8225
+#define        TIM2_R          19456
+#define        TIM3_R          19457
+#define        TIM4_R          19458
+#define        TIM5_R          19459
+#define        TIM6_R          19460
+#define        TIM7_R          19461
+#define        TIM12_R         16462
+#define        TIM13_R         16463
+#define        TIM14_R         16464
+#define        LPTIM1_R        19465
+#define        SPI2_R          19467
+#define        SPI3_R          19468
+#define        USART2_R        19470
+#define        USART3_R        19471
+#define        UART4_R         19472
+#define        UART5_R         19473
+#define        UART7_R         19474
+#define        UART8_R         19475
+#define        I2C1_R          19477
+#define        I2C2_R          19478
+#define        I2C3_R          19479
+#define        I2C5_R          19480
+#define        SPDIF_R         19482
+#define        CEC_R           19483
+#define        DAC12_R         19485
+#define        MDIO_R          19847
+#define        TIM1_R          19520
+#define        TIM8_R          19521
+#define        TIM15_R         19522
+#define        TIM16_R         19523
+#define        TIM17_R         19524
+#define        SPI1_R          19528
+#define        SPI4_R          19529
+#define        SPI5_R          19530
+#define        USART6_R        19533
+#define        SAI1_R          19536
+#define        SAI2_R          19537
+#define        SAI3_R          19538
+#define        DFSDM_R         19540
+#define        FDCAN_R         19544
+#define        LPTIM2_R        19584
+#define        LPTIM3_R        19585
+#define        LPTIM4_R        19586
+#define        LPTIM5_R        19587
+#define        SAI4_R          19592
+#define        SYSCFG_R        19595
+#define        VREF_R          19597
+#define        TMPSENS_R       19600
+#define        PMBCTRL_R       19601
+#define        DMA1_R          19648
+#define        DMA2_R          19649
+#define        DMAMUX_R        19650
+#define        ADC12_R         19653
+#define        USBO_R          19656
+#define        SDMMC3_R        19664
+#define        CAMITF_R        19712
+#define        CRYP2_R         19716
+#define        HASH2_R         19717
+#define        RNG2_R          19718
+#define        CRC2_R          19719
+#define        HSEM_R          19723
+#define        MBOX_R          19724
+#define        GPIOA_R         19776
+#define        GPIOB_R         19777
+#define        GPIOC_R         19778
+#define        GPIOD_R         19779
+#define        GPIOE_R         19780
+#define        GPIOF_R         19781
+#define        GPIOG_R         19782
+#define        GPIOH_R         19783
+#define        GPIOI_R         19784
+#define        GPIOJ_R         19785
+#define        GPIOK_R         19786

diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h
new file mode 100644 (file)
index 0000000..ffa46a6
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6362-reset.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Ã\81lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6362_H
+#define __DT_BINDINGS_RESET_BCM6362_H
+
+#define BCM6362_RST_SPI                0
+#define BCM6362_RST_IPSEC      1
+#define BCM6362_RST_EPHY       2
+#define BCM6362_RST_SAR                3
+#define BCM6362_RST_ENETSW     4
+#define BCM6362_RST_USBD       5
+#define BCM6362_RST_USBH       6
+#define BCM6362_RST_PCM                7
+#define BCM6362_RST_PCIE_CORE  8
+#define BCM6362_RST_PCIE       9
+#define BCM6362_RST_PCIE_EXT   10
+#define BCM6362_RST_WLAN_SHIM  11
+#define BCM6362_RST_DDR_PHY    12
+#define BCM6362_RST_FAP                13
+#define BCM6362_RST_WLAN_UBUS  14
+
+#endif /* __DT_BINDINGS_RESET_BCM6362_H */

diff --git a/include/image.h b/include/image.h
index dbdaecbfdd3dc924274442594663c5b3d608eec4..a6f82aebfee024366e3ea11c90d7ed9c8d6c0893 100644 (file)
--- a/include/image.h
+++ b/include/image.h
@@ -21,6 +21,7 @@
 
 /* Define this to avoid #ifdefs later on */
 struct lmb;
+struct fdt_region;
 
 #ifdef USE_HOSTCC
 #include <sys/types.h>
@@ -153,6 +154,7 @@ enum {
        IH_OS_PLAN9,                    /* Plan 9       */
        IH_OS_OPENRTOS,         /* OpenRTOS     */
        IH_OS_ARM_TRUSTED_FIRMWARE,     /* ARM Trusted Firmware */
+       IH_OS_TEE,                      /* Trusted Execution Environment */
 
        IH_OS_COUNT,
 };
@@ -272,6 +274,7 @@ enum {
        IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
        IH_TYPE_FIRMWARE_IVT,           /* Firmware Image with HABv4 IVT */
        IH_TYPE_PMMC,            /* TI Power Management Micro-Controller Firmware */
+       IH_TYPE_STM32IMAGE,             /* STMicroelectronics STM32 Image */
 
        IH_TYPE_COUNT,                  /* Number of image types */
 };
@@ -1013,6 +1016,8 @@ int fit_add_verification_data(const char *keydir, void *keydest, void *fit,
                              const char *comment, int require_keys,
                              const char *engine_id);
 
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+                              const void *data, size_t size);
 int fit_image_verify(const void *fit, int noffset);
 int fit_config_verify(const void *fit, int conf_noffset);
 int fit_all_image_verify(const void *fit);

diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h
index 9e6eeadc400f86a66b19fc557a3194c641f8ce3c..eeb2344971f3ff9489ae454647bb4f951bf170df 100644 (file)
--- a/include/linux/libfdt.h
+++ b/include/linux/libfdt.h
@@ -309,7 +309,4 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
 
 extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
 
-/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
-#define FDT_RAMDISK_OVERHEAD   0x80
-
 #endif /* _INCLUDE_LIBFDT_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus.h b/include/net/pfe_eth/pfe/cbus.h
new file mode 100644 (file)
index 0000000..002041c
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR         ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR                (CBUS_BASE_ADDR + 0x200000)
+#define EGPI1_BASE_ADDR                (CBUS_BASE_ADDR + 0x210000)
+#define EMAC2_BASE_ADDR                (CBUS_BASE_ADDR + 0x220000)
+#define EGPI2_BASE_ADDR                (CBUS_BASE_ADDR + 0x230000)
+#define BMU1_BASE_ADDR         (CBUS_BASE_ADDR + 0x240000)
+#define BMU2_BASE_ADDR         (CBUS_BASE_ADDR + 0x250000)
+#define ARB_BASE_ADDR          (CBUS_BASE_ADDR + 0x260000)
+#define DDR_CONFIG_BASE_ADDR   (CBUS_BASE_ADDR + 0x270000)
+#define HIF_BASE_ADDR          (CBUS_BASE_ADDR + 0x280000)
+#define HGPI_BASE_ADDR         (CBUS_BASE_ADDR + 0x290000)
+#define LMEM_BASE_ADDR         (CBUS_BASE_ADDR + 0x300000)
+#define LMEM_SIZE              0x10000
+#define LMEM_END               (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR      (CBUS_BASE_ADDR + 0x310000)
+#define CLASS_CSR_BASE_ADDR    (CBUS_BASE_ADDR + 0x320000)
+#define HIF_NOCPY_BASE_ADDR    (CBUS_BASE_ADDR + 0x350000)
+#define UTIL_CSR_BASE_ADDR     (CBUS_BASE_ADDR + 0x360000)
+#define CBUS_GPT_BASE_ADDR     (CBUS_BASE_ADDR + 0x370000)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+/* Internal Memory Write. */
+#define PE_MEM_ACCESS_WRITE            BIT(31)
+/* Internal Memory Read. */
+#define PE_MEM_ACCESS_READ             (0 << 31)
+
+#define PE_MEM_ACCESS_IMEM             BIT(15)
+#define PE_MEM_ACCESS_DMEM             BIT(16)
+
+/* Byte Enables of the Internal memory access. These are interpred in BE */
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)        (((((1 << (size)) - 1) << (4 \
+                                                       - (offset) - (size)))\
+                                                       & 0xf) << 24)
+
+/* PFE cores states */
+#define CORE_DISABLE   0x00000000
+#define CORE_ENABLE    0x00000001
+#define CORE_SW_RESET  0x00000002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE          0x0010
+#define LMEM_BUF_SIZE_LN2      0x7
+#define LMEM_BUF_SIZE          BIT(LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE           0x0100
+#define DDR_BUF_SIZE_LN2       0xb
+#define DDR_BUF_SIZE           BIT(DDR_BUF_SIZE_LN2)
+
+/* Clock generation through PLL */
+#define PLL_CLK_EN     1
+
+#endif /* _CBUS_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/bmu.h b/include/net/pfe_eth/pfe/cbus/bmu.h
new file mode 100644 (file)
index 0000000..f707cc3
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/bmu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _BMU_H_
+#define _BMU_H_
+
+#define BMU_VERSION            0x000
+#define BMU_CTRL               0x004
+#define BMU_UCAST_CONFIG       0x008
+#define BMU_UCAST_BASE_ADDR    0x00c
+#define BMU_BUF_SIZE           0x010
+#define BMU_BUF_CNT            0x014
+#define BMU_THRES              0x018
+#define BMU_INT_SRC            0x020
+#define BMU_INT_ENABLE         0x024
+#define BMU_ALLOC_CTRL         0x030
+#define BMU_FREE_CTRL          0x034
+#define BMU_FREE_ERR_ADDR      0x038
+#define BMU_CURR_BUF_CNT       0x03c
+#define BMU_MCAST_CNT          0x040
+#define BMU_MCAST_ALLOC_CTRL   0x044
+#define BMU_REM_BUF_CNT                0x048
+#define BMU_LOW_WATERMARK      0x050
+#define BMU_HIGH_WATERMARK     0x054
+#define BMU_INT_MEM_ACCESS     0x100
+
+struct bmu_cfg {
+       u32 baseaddr;
+       u32 count;
+       u32 size;
+};
+
+#define BMU1_BUF_SIZE  LMEM_BUF_SIZE_LN2
+#define BMU2_BUF_SIZE  DDR_BUF_SIZE_LN2
+
+#endif /* _BMU_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/class_csr.h b/include/net/pfe_eth/pfe/cbus/class_csr.h
new file mode 100644 (file)
index 0000000..eeca751
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/class_csr.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CLASS_CSR_H_
+#define _CLASS_CSR_H_
+
+/*
+ * @file class_csr.h.
+ * class_csr - block containing all the classifier control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define CLASS_VERSION                  (CLASS_CSR_BASE_ADDR + 0x000)
+#define CLASS_TX_CTRL                  (CLASS_CSR_BASE_ADDR + 0x004)
+#define CLASS_INQ_PKTPTR               (CLASS_CSR_BASE_ADDR + 0x010)
+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
+#define CLASS_HDR_SIZE                 (CLASS_CSR_BASE_ADDR + 0x014)
+/* LMEM header size for the Classifier block.
+ * Data in the LMEM is written from this offset.
+ */
+#define CLASS_HDR_SIZE_LMEM(off)       ((off) & 0x3f)
+/* DDR header size for the Classifier block.
+ * Data in the DDR is written from this offset.
+ */
+#define CLASS_HDR_SIZE_DDR(off)                (((off) & 0x1ff) << 16)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR0          (CLASS_CSR_BASE_ADDR + 0x020)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR1          (CLASS_CSR_BASE_ADDR + 0x024)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR0          (CLASS_CSR_BASE_ADDR + 0x060)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR1          (CLASS_CSR_BASE_ADDR + 0x064)
+
+/*
+ * @name Class PE memory access. Allows external PE's and HOST to
+ * read/write PMEM/DMEM memory ranges for each classifier PE.
+ */
+#define CLASS_MEM_ACCESS_ADDR          (CLASS_CSR_BASE_ADDR + 0x100)
+/* Internal Memory Access Write Data [31:0] */
+#define CLASS_MEM_ACCESS_WDATA         (CLASS_CSR_BASE_ADDR + 0x104)
+/* Internal Memory Access Read Data [31:0] */
+#define CLASS_MEM_ACCESS_RDATA         (CLASS_CSR_BASE_ADDR + 0x108)
+#define CLASS_TM_INQ_ADDR              (CLASS_CSR_BASE_ADDR + 0x114)
+#define CLASS_PE_STATUS                        (CLASS_CSR_BASE_ADDR + 0x118)
+
+#define CLASS_PE_SYS_CLK_RATIO         (CLASS_CSR_BASE_ADDR + 0x200)
+#define CLASS_AFULL_THRES              (CLASS_CSR_BASE_ADDR + 0x204)
+#define CLASS_GAP_BETWEEN_READS                (CLASS_CSR_BASE_ADDR + 0x208)
+#define CLASS_MAX_BUF_CNT              (CLASS_CSR_BASE_ADDR + 0x20c)
+#define CLASS_TSQ_FIFO_THRES           (CLASS_CSR_BASE_ADDR + 0x210)
+#define CLASS_TSQ_MAX_CNT              (CLASS_CSR_BASE_ADDR + 0x214)
+#define CLASS_IRAM_DATA_0              (CLASS_CSR_BASE_ADDR + 0x218)
+#define CLASS_IRAM_DATA_1              (CLASS_CSR_BASE_ADDR + 0x21c)
+#define CLASS_IRAM_DATA_2              (CLASS_CSR_BASE_ADDR + 0x220)
+#define CLASS_IRAM_DATA_3              (CLASS_CSR_BASE_ADDR + 0x224)
+
+#define CLASS_BUS_ACCESS_ADDR          (CLASS_CSR_BASE_ADDR + 0x228)
+/* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
+#define CLASS_BUS_ACCESS_ADDR_MASK     (0x0001FFFF)
+
+#define CLASS_BUS_ACCESS_WDATA         (CLASS_CSR_BASE_ADDR + 0x22c)
+#define CLASS_BUS_ACCESS_RDATA         (CLASS_CSR_BASE_ADDR + 0x230)
+
+/*
+ * (route_entry_size[9:0], route_hash_size[23:16]
+ * (this is actually ln2(size)))
+ */
+#define CLASS_ROUTE_HASH_ENTRY_SIZE    (CLASS_CSR_BASE_ADDR + 0x234)
+#define CLASS_ROUTE_ENTRY_SIZE(size)    ((size) & 0x1ff)
+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
+
+#define CLASS_ROUTE_TABLE_BASE         (CLASS_CSR_BASE_ADDR + 0x238)
+#define CLASS_ROUTE_MULTI              (CLASS_CSR_BASE_ADDR + 0x23c)
+#define CLASS_SMEM_OFFSET              (CLASS_CSR_BASE_ADDR + 0x240)
+#define CLASS_LMEM_BUF_SIZE            (CLASS_CSR_BASE_ADDR + 0x244)
+#define CLASS_VLAN_ID                  (CLASS_CSR_BASE_ADDR + 0x248)
+#define CLASS_BMU1_BUF_FREE            (CLASS_CSR_BASE_ADDR + 0x24c)
+#define CLASS_USE_TMU_INQ              (CLASS_CSR_BASE_ADDR + 0x250)
+#define CLASS_VLAN_ID1                 (CLASS_CSR_BASE_ADDR + 0x254)
+
+#define CLASS_BUS_ACCESS_BASE          (CLASS_CSR_BASE_ADDR + 0x258)
+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
+#define CLASS_BUS_ACCESS_BASE_MASK     (0xFF000000)
+
+#define CLASS_HIF_PARSE                        (CLASS_CSR_BASE_ADDR + 0x25c)
+
+#define CLASS_HOST_PE0_GP              (CLASS_CSR_BASE_ADDR + 0x260)
+#define CLASS_PE0_GP                   (CLASS_CSR_BASE_ADDR + 0x264)
+#define CLASS_HOST_PE1_GP              (CLASS_CSR_BASE_ADDR + 0x268)
+#define CLASS_PE1_GP                   (CLASS_CSR_BASE_ADDR + 0x26c)
+#define CLASS_HOST_PE2_GP              (CLASS_CSR_BASE_ADDR + 0x270)
+#define CLASS_PE2_GP                   (CLASS_CSR_BASE_ADDR + 0x274)
+#define CLASS_HOST_PE3_GP              (CLASS_CSR_BASE_ADDR + 0x278)
+#define CLASS_PE3_GP                   (CLASS_CSR_BASE_ADDR + 0x27c)
+#define CLASS_HOST_PE4_GP              (CLASS_CSR_BASE_ADDR + 0x280)
+#define CLASS_PE4_GP                   (CLASS_CSR_BASE_ADDR + 0x284)
+#define CLASS_HOST_PE5_GP              (CLASS_CSR_BASE_ADDR + 0x288)
+#define CLASS_PE5_GP                   (CLASS_CSR_BASE_ADDR + 0x28c)
+
+#define CLASS_PE_INT_SRC               (CLASS_CSR_BASE_ADDR + 0x290)
+#define CLASS_PE_INT_ENABLE            (CLASS_CSR_BASE_ADDR + 0x294)
+
+#define CLASS_TPID0_TPID1              (CLASS_CSR_BASE_ADDR + 0x298)
+#define CLASS_TPID2                    (CLASS_CSR_BASE_ADDR + 0x29c)
+
+#define CLASS_L4_CHKSUM_ADDR           (CLASS_CSR_BASE_ADDR + 0x2a0)
+
+#define CLASS_PE0_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2a4)
+#define CLASS_PE1_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2a8)
+#define CLASS_PE2_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2ac)
+#define CLASS_PE3_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2b0)
+#define CLASS_PE4_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2b4)
+#define CLASS_PE5_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2b8)
+
+#define CLASS_STATE                    (CLASS_CSR_BASE_ADDR + 0x2bc)
+#define CLASS_AXI_CTRL                 (CLASS_CSR_BASE_ADDR + 0x2d0)
+
+/* CLASS defines */
+#define CLASS_PBUF_SIZE                        0x100   /* Fixed by hardware */
+#define CLASS_PBUF_HEADER_OFFSET       0x80    /* Can be configured */
+
+#define CLASS_PBUF0_BASE_ADDR          0x000   /* Can be configured */
+/* Can be configured */
+#define CLASS_PBUF1_BASE_ADDR  (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF2_BASE_ADDR  (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF3_BASE_ADDR  (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
+
+#define CLASS_PBUF0_HEADER_BASE_ADDR   (CLASS_PBUF0_BASE_ADDR +\
+                                               CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF1_HEADER_BASE_ADDR   (CLASS_PBUF1_BASE_ADDR +\
+                                               CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF2_HEADER_BASE_ADDR   (CLASS_PBUF2_BASE_ADDR +\
+                                               CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF3_HEADER_BASE_ADDR   (CLASS_PBUF3_BASE_ADDR +\
+                                               CLASS_PBUF_HEADER_OFFSET)
+
+#define CLASS_PE0_RO_DM_ADDR0_VAL      ((CLASS_PBUF1_BASE_ADDR << 16) |\
+                                               CLASS_PBUF0_BASE_ADDR)
+#define CLASS_PE0_RO_DM_ADDR1_VAL      ((CLASS_PBUF3_BASE_ADDR << 16) |\
+                                               CLASS_PBUF2_BASE_ADDR)
+
+#define CLASS_PE0_QB_DM_ADDR0_VAL      ((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
+                                               | CLASS_PBUF0_HEADER_BASE_ADDR)
+#define CLASS_PE0_QB_DM_ADDR1_VAL      ((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
+                                               | CLASS_PBUF2_HEADER_BASE_ADDR)
+
+#define CLASS_ROUTE_SIZE               128
+#define CLASS_ROUTE_HASH_BITS          20
+#define CLASS_ROUTE_HASH_MASK          (BIT(CLASS_ROUTE_HASH_BITS) - 1)
+
+#define TWO_LEVEL_ROUTE                BIT(0)
+#define PHYNO_IN_HASH          BIT(1)
+#define HW_ROUTE_FETCH         BIT(3)
+#define HW_BRIDGE_FETCH                BIT(5)
+#define IP_ALIGNED             BIT(6)
+#define ARC_HIT_CHECK_EN       BIT(7)
+#define CLASS_TOE              BIT(11)
+#define HASH_CRC_PORT          BIT(12)
+#define HASH_CRC_IP            BIT(13)
+#define HASH_CRC_PORT_IP       GENMASK(13, 12)
+#define QB2BUS_LE              BIT(15)
+
+#define        TCP_CHKSUM_DROP         BIT(0)
+#define        UDP_CHKSUM_DROP         BIT(1)
+#define        IPV4_CHKSUM_DROP        BIT(9)
+
+struct class_cfg {
+       u32 route_table_baseaddr;
+       u32 route_table_hash_bits;
+};
+
+#endif /* _CLASS_CSR_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/emac.h b/include/net/pfe_eth/pfe/cbus/emac.h
new file mode 100644 (file)
index 0000000..f74bd96
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/emac.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+#define EMAC_IEVENT_REG                0x004
+#define EMAC_IMASK_REG         0x008
+#define EMAC_R_DES_ACTIVE_REG  0x010
+#define EMAC_X_DES_ACTIVE_REG  0x014
+#define EMAC_ECNTRL_REG                0x024
+#define EMAC_MII_DATA_REG      0x040
+#define EMAC_MII_CTRL_REG      0x044
+#define EMAC_MIB_CTRL_STS_REG  0x064
+#define EMAC_RCNTRL_REG                0x084
+#define EMAC_TCNTRL_REG                0x0C4
+#define EMAC_PHY_ADDR_LOW      0x0E4
+#define EMAC_PHY_ADDR_HIGH     0x0E8
+#define EMAC_TFWR_STR_FWD      0x144
+#define EMAC_RX_SECTIOM_FULL   0x190
+#define EMAC_TX_SECTION_EMPTY  0x1A0
+#define EMAC_TRUNC_FL          0x1B0
+
+/* GEMAC definitions and settings */
+#define EMAC_PORT_0                    0
+#define EMAC_PORT_1                    1
+
+/* GEMAC Bit definitions */
+#define EMAC_IEVENT_HBERR                BIT(31)
+#define EMAC_IEVENT_BABR                 BIT(30)
+#define EMAC_IEVENT_BABT                 BIT(29)
+#define EMAC_IEVENT_GRA                  BIT(28)
+#define EMAC_IEVENT_TXF                  BIT(27)
+#define EMAC_IEVENT_TXB                  BIT(26)
+#define EMAC_IEVENT_RXF                  BIT(25)
+#define EMAC_IEVENT_RXB                  BIT(24)
+#define EMAC_IEVENT_MII                  BIT(23)
+#define EMAC_IEVENT_EBERR                BIT(22)
+#define EMAC_IEVENT_LC                   BIT(21)
+#define EMAC_IEVENT_RL                   BIT(20)
+#define EMAC_IEVENT_UN                   BIT(19)
+
+#define EMAC_IMASK_HBERR                 BIT(31)
+#define EMAC_IMASK_BABR                  BIT(30)
+#define EMAC_IMASKT_BABT                 BIT(29)
+#define EMAC_IMASK_GRA                   BIT(28)
+#define EMAC_IMASKT_TXF                  BIT(27)
+#define EMAC_IMASK_TXB                   BIT(26)
+#define EMAC_IMASKT_RXF                  BIT(25)
+#define EMAC_IMASK_RXB                   BIT(24)
+#define EMAC_IMASK_MII                   BIT(23)
+#define EMAC_IMASK_EBERR                 BIT(22)
+#define EMAC_IMASK_LC                    BIT(21)
+#define EMAC_IMASKT_RL                   BIT(20)
+#define EMAC_IMASK_UN                    BIT(19)
+
+#define EMAC_RCNTRL_MAX_FL_SHIFT         16
+#define EMAC_RCNTRL_LOOP                 BIT(0)
+#define EMAC_RCNTRL_DRT                  BIT(1)
+#define EMAC_RCNTRL_MII_MODE             BIT(2)
+#define EMAC_RCNTRL_PROM                 BIT(3)
+#define EMAC_RCNTRL_BC_REJ               BIT(4)
+#define EMAC_RCNTRL_FCE                  BIT(5)
+#define EMAC_RCNTRL_RGMII                BIT(6)
+#define EMAC_RCNTRL_SGMII                BIT(7)
+#define EMAC_RCNTRL_RMII                 BIT(8)
+#define EMAC_RCNTRL_RMII_10T             BIT(9)
+#define EMAC_RCNTRL_CRC_FWD             BIT(10)
+
+#define EMAC_TCNTRL_GTS                  BIT(0)
+#define EMAC_TCNTRL_HBC                  BIT(1)
+#define EMAC_TCNTRL_FDEN                 BIT(2)
+#define EMAC_TCNTRL_TFC_PAUSE            BIT(3)
+#define EMAC_TCNTRL_RFC_PAUSE            BIT(4)
+
+#define EMAC_ECNTRL_RESET                BIT(0)      /* reset the EMAC */
+#define EMAC_ECNTRL_ETHER_EN             BIT(1)      /* enable the EMAC */
+#define EMAC_ECNTRL_SPEED                BIT(5)
+#define EMAC_ECNTRL_DBSWAP               BIT(8)
+
+#define EMAC_X_WMRK_STRFWD               BIT(8)
+
+#define EMAC_X_DES_ACTIVE_TDAR           BIT(24)
+#define EMAC_R_DES_ACTIVE_RDAR           BIT(24)
+
+#define EMAC_TFWR                      (0x4)
+#define EMAC_RX_SECTION_FULL_32                (0x5)
+#define EMAC_TRUNC_FL_16K              (0x3FFF)
+#define EMAC_TX_SECTION_EMPTY_30       (0x30)
+#define EMAC_MIBC_NO_CLR_NO_DIS                (0x0)
+
+/*
+ * The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M,
+               PFE_MAC_SPEED_1000M_PCS};
+
+/* MII-related definitios */
+#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
+#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */
+#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */
+#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
+#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
+#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */
+#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
+
+#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
+#define EMAC_MII_DATA_RA_MASK   0x1F      /* MII Register address mask */
+#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
+#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */
+
+#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+                               EMAC_MII_DATA_RA_SHIFT)
+#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+                               EMAC_MII_DATA_PA_SHIFT)
+#define EMAC_MII_DATA(v)    (v & 0xffff)
+
+#define EMAC_MII_SPEED_SHIFT   1
+#define EMAC_HOLDTIME_SHIFT    8
+#define EMAC_HOLDTIME_MASK     0x7
+#define EMAC_HOLDTIME(v)    ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET      0x8000
+#define PHY_SGMII_CR_RESET_AN       0x0200
+#define PHY_SGMII_CR_DEF_VAL        0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN        0x0002
+#define PHY_SGMII_IF_MODE_SGMII     0x0001
+#define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008
+#define PHY_SGMII_ENABLE_AN         0x1000
+
+#endif /* _EMAC_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/gpi.h b/include/net/pfe_eth/pfe/cbus/gpi.h
new file mode 100644 (file)
index 0000000..f86f3f9
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/gpi.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _GPI_H_
+#define _GPI_H_
+
+#define GPI_VERSION                    0x00
+#define GPI_CTRL                       0x04
+#define GPI_RX_CONFIG                  0x08
+#define GPI_HDR_SIZE                   0x0c
+#define GPI_BUF_SIZE                   0x10
+#define GPI_LMEM_ALLOC_ADDR            0x14
+#define GPI_LMEM_FREE_ADDR             0x18
+#define GPI_DDR_ALLOC_ADDR             0x1c
+#define GPI_DDR_FREE_ADDR              0x20
+#define GPI_CLASS_ADDR                 0x24
+#define GPI_DRX_FIFO                   0x28
+#define GPI_TRX_FIFO                   0x2c
+#define GPI_INQ_PKTPTR                 0x30
+#define GPI_DDR_DATA_OFFSET            0x34
+#define GPI_LMEM_DATA_OFFSET           0x38
+#define GPI_TMLF_TX                    0x4c
+#define GPI_DTX_ASEQ                   0x50
+#define GPI_FIFO_STATUS                        0x54
+#define GPI_FIFO_DEBUG                 0x58
+#define GPI_TX_PAUSE_TIME              0x5c
+#define GPI_LMEM_SEC_BUF_DATA_OFFSET   0x60
+#define GPI_DDR_SEC_BUF_DATA_OFFSET    0x64
+#define GPI_TOE_CHKSUM_EN              0x68
+#define GPI_OVERRUN_DROPCNT            0x6c
+#define GPI_AXI_CTRL                   0x70
+
+struct gpi_cfg {
+       u32 lmem_rtry_cnt;
+       u32 tmlf_txthres;
+       u32 aseq_len;
+};
+
+/* GPI commons defines */
+#define GPI_LMEM_BUF_EN                0x1
+#define GPI_DDR_BUF_EN         0x1
+
+/* EGPI 1 defines */
+#define EGPI1_LMEM_RTRY_CNT    0x40
+#define EGPI1_TMLF_TXTHRES     0xBC
+#define EGPI1_ASEQ_LEN         0x50
+
+/* EGPI 2 defines */
+#define EGPI2_LMEM_RTRY_CNT    0x40
+#define EGPI2_TMLF_TXTHRES     0xBC
+#define EGPI2_ASEQ_LEN         0x40
+
+/* HGPI defines */
+#define HGPI_LMEM_RTRY_CNT     0x40
+#define HGPI_TMLF_TXTHRES      0xBC
+#define HGPI_ASEQ_LEN          0x40
+
+#endif /* _GPI_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/hif.h b/include/net/pfe_eth/pfe/cbus/hif.h
new file mode 100644 (file)
index 0000000..4b5cb3c
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/hif.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _HIF_H_
+#define _HIF_H_
+
+/*
+ * @file hif.h.
+ * hif - PFE hif block control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define HIF_VERSION            (HIF_BASE_ADDR + 0x00)
+#define HIF_TX_CTRL            (HIF_BASE_ADDR + 0x04)
+#define HIF_TX_CURR_BD_ADDR    (HIF_BASE_ADDR + 0x08)
+#define HIF_TX_ALLOC           (HIF_BASE_ADDR + 0x0c)
+#define HIF_TX_BDP_ADDR                (HIF_BASE_ADDR + 0x10)
+#define HIF_TX_STATUS          (HIF_BASE_ADDR + 0x14)
+#define HIF_RX_CTRL            (HIF_BASE_ADDR + 0x20)
+#define HIF_RX_BDP_ADDR                (HIF_BASE_ADDR + 0x24)
+#define HIF_RX_STATUS          (HIF_BASE_ADDR + 0x30)
+#define HIF_INT_SRC            (HIF_BASE_ADDR + 0x34)
+#define HIF_INT_ENABLE         (HIF_BASE_ADDR + 0x38)
+#define HIF_POLL_CTRL          (HIF_BASE_ADDR + 0x3c)
+#define HIF_RX_CURR_BD_ADDR    (HIF_BASE_ADDR + 0x40)
+#define HIF_RX_ALLOC           (HIF_BASE_ADDR + 0x44)
+#define HIF_TX_DMA_STATUS      (HIF_BASE_ADDR + 0x48)
+#define HIF_RX_DMA_STATUS      (HIF_BASE_ADDR + 0x4c)
+#define HIF_INT_COAL           (HIF_BASE_ADDR + 0x50)
+#define HIF_AXI_CTRL           (HIF_BASE_ADDR + 0x54)
+
+/* HIF_TX_CTRL bits */
+#define HIF_CTRL_DMA_EN                        BIT(0)
+#define HIF_CTRL_BDP_POLL_CTRL_EN      BIT(1)
+#define HIF_CTRL_BDP_CH_START_WSTB     BIT(2)
+
+/* HIF_RX_STATUS bits */
+#define BDP_CSR_RX_DMA_ACTV    BIT(16)
+
+/* HIF_INT_ENABLE bits */
+#define HIF_INT_EN             BIT(0)
+#define HIF_RXBD_INT_EN                BIT(1)
+#define HIF_RXPKT_INT_EN       BIT(2)
+#define HIF_TXBD_INT_EN                BIT(3)
+#define HIF_TXPKT_INT_EN       BIT(4)
+
+/* HIF_POLL_CTRL bits*/
+#define HIF_RX_POLL_CTRL_CYCLE 0x0400
+#define HIF_TX_POLL_CTRL_CYCLE 0x0400
+
+/* Buffer descriptor control bits */
+#define BD_CTRL_BUFLEN_MASK    (0xffff)
+#define BD_BUF_LEN(x)  (x & BD_CTRL_BUFLEN_MASK)
+#define BD_CTRL_CBD_INT_EN     BIT(16)
+#define BD_CTRL_PKT_INT_EN     BIT(17)
+#define BD_CTRL_LIFM           BIT(18)
+#define BD_CTRL_LAST_BD                BIT(19)
+#define BD_CTRL_DIR            BIT(20)
+#define BD_CTRL_PKT_XFER       BIT(24)
+#define BD_CTRL_DESC_EN                BIT(31)
+#define BD_CTRL_PARSE_DISABLE  BIT(25)
+#define BD_CTRL_BRFETCH_DISABLE        BIT(26)
+#define BD_CTRL_RTFETCH_DISABLE        BIT(27)
+
+#endif /* _HIF_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/hif_nocpy.h b/include/net/pfe_eth/pfe/cbus/hif_nocpy.h
new file mode 100644 (file)
index 0000000..c2d6f6d
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/hif_nocpy.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _HIF_NOCPY_H_
+#define _HIF_NOCPY_H_
+
+#define HIF_NOCPY_VERSION              (HIF_NOCPY_BASE_ADDR + 0x00)
+#define HIF_NOCPY_TX_CTRL              (HIF_NOCPY_BASE_ADDR + 0x04)
+#define HIF_NOCPY_TX_CURR_BD_ADDR      (HIF_NOCPY_BASE_ADDR + 0x08)
+#define HIF_NOCPY_TX_ALLOC             (HIF_NOCPY_BASE_ADDR + 0x0c)
+#define HIF_NOCPY_TX_BDP_ADDR          (HIF_NOCPY_BASE_ADDR + 0x10)
+#define HIF_NOCPY_TX_STATUS            (HIF_NOCPY_BASE_ADDR + 0x14)
+#define HIF_NOCPY_RX_CTRL              (HIF_NOCPY_BASE_ADDR + 0x20)
+#define HIF_NOCPY_RX_BDP_ADDR          (HIF_NOCPY_BASE_ADDR + 0x24)
+#define HIF_NOCPY_RX_STATUS            (HIF_NOCPY_BASE_ADDR + 0x30)
+#define HIF_NOCPY_INT_SRC              (HIF_NOCPY_BASE_ADDR + 0x34)
+#define HIF_NOCPY_INT_ENABLE           (HIF_NOCPY_BASE_ADDR + 0x38)
+#define HIF_NOCPY_POLL_CTRL            (HIF_NOCPY_BASE_ADDR + 0x3c)
+#define HIF_NOCPY_RX_CURR_BD_ADDR      (HIF_NOCPY_BASE_ADDR + 0x40)
+#define HIF_NOCPY_RX_ALLOC             (HIF_NOCPY_BASE_ADDR + 0x44)
+#define HIF_NOCPY_TX_DMA_STATUS                (HIF_NOCPY_BASE_ADDR + 0x48)
+#define HIF_NOCPY_RX_DMA_STATUS                (HIF_NOCPY_BASE_ADDR + 0x4c)
+#define HIF_NOCPY_RX_INQ0_PKTPTR       (HIF_NOCPY_BASE_ADDR + 0x50)
+#define HIF_NOCPY_RX_INQ1_PKTPTR       (HIF_NOCPY_BASE_ADDR + 0x54)
+#define HIF_NOCPY_TX_PORT_NO           (HIF_NOCPY_BASE_ADDR + 0x60)
+#define HIF_NOCPY_LMEM_ALLOC_ADDR      (HIF_NOCPY_BASE_ADDR + 0x64)
+#define HIF_NOCPY_CLASS_ADDR           (HIF_NOCPY_BASE_ADDR + 0x68)
+#define HIF_NOCPY_TMU_PORT0_ADDR       (HIF_NOCPY_BASE_ADDR + 0x70)
+#define HIF_NOCPY_TMU_PORT1_ADDR       (HIF_NOCPY_BASE_ADDR + 0x74)
+#define HIF_NOCPY_TMU_PORT2_ADDR       (HIF_NOCPY_BASE_ADDR + 0x7c)
+#define HIF_NOCPY_TMU_PORT3_ADDR       (HIF_NOCPY_BASE_ADDR + 0x80)
+#define HIF_NOCPY_TMU_PORT4_ADDR       (HIF_NOCPY_BASE_ADDR + 0x84)
+#define HIF_NOCPY_INT_COAL             (HIF_NOCPY_BASE_ADDR + 0x90)
+#define HIF_NOCPY_AXI_CTRL             (HIF_NOCPY_BASE_ADDR + 0x94)
+
+#endif /* _HIF_NOCPY_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/tmu_csr.h b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
new file mode 100644 (file)
index 0000000..e810b79
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _TMU_CSR_H_
+#define _TMU_CSR_H_
+
+#define TMU_VERSION                    (TMU_CSR_BASE_ADDR + 0x000)
+#define TMU_INQ_WATERMARK              (TMU_CSR_BASE_ADDR + 0x004)
+#define TMU_PHY_INQ_PKTPTR             (TMU_CSR_BASE_ADDR + 0x008)
+#define TMU_PHY_INQ_PKTINFO            (TMU_CSR_BASE_ADDR + 0x00c)
+#define TMU_PHY_INQ_FIFO_CNT           (TMU_CSR_BASE_ADDR + 0x010)
+#define TMU_SYS_GENERIC_CONTROL                (TMU_CSR_BASE_ADDR + 0x014)
+#define TMU_SYS_GENERIC_STATUS         (TMU_CSR_BASE_ADDR + 0x018)
+#define TMU_SYS_GEN_CON0               (TMU_CSR_BASE_ADDR + 0x01c)
+#define TMU_SYS_GEN_CON1               (TMU_CSR_BASE_ADDR + 0x020)
+#define TMU_SYS_GEN_CON2               (TMU_CSR_BASE_ADDR + 0x024)
+#define TMU_SYS_GEN_CON3               (TMU_CSR_BASE_ADDR + 0x028)
+#define TMU_SYS_GEN_CON4               (TMU_CSR_BASE_ADDR + 0x02c)
+#define TMU_TEQ_DISABLE_DROPCHK                (TMU_CSR_BASE_ADDR + 0x030)
+#define TMU_TEQ_CTRL                   (TMU_CSR_BASE_ADDR + 0x034)
+#define TMU_TEQ_QCFG                   (TMU_CSR_BASE_ADDR + 0x038)
+#define TMU_TEQ_DROP_STAT              (TMU_CSR_BASE_ADDR + 0x03c)
+#define TMU_TEQ_QAVG                   (TMU_CSR_BASE_ADDR + 0x040)
+#define TMU_TEQ_WREG_PROB              (TMU_CSR_BASE_ADDR + 0x044)
+#define TMU_TEQ_TRANS_STAT             (TMU_CSR_BASE_ADDR + 0x048)
+#define TMU_TEQ_HW_PROB_CFG0           (TMU_CSR_BASE_ADDR + 0x04c)
+#define TMU_TEQ_HW_PROB_CFG1           (TMU_CSR_BASE_ADDR + 0x050)
+#define TMU_TEQ_HW_PROB_CFG2           (TMU_CSR_BASE_ADDR + 0x054)
+#define TMU_TEQ_HW_PROB_CFG3           (TMU_CSR_BASE_ADDR + 0x058)
+#define TMU_TEQ_HW_PROB_CFG4           (TMU_CSR_BASE_ADDR + 0x05c)
+#define TMU_TEQ_HW_PROB_CFG5           (TMU_CSR_BASE_ADDR + 0x060)
+#define TMU_TEQ_HW_PROB_CFG6           (TMU_CSR_BASE_ADDR + 0x064)
+#define TMU_TEQ_HW_PROB_CFG7           (TMU_CSR_BASE_ADDR + 0x068)
+#define TMU_TEQ_HW_PROB_CFG8           (TMU_CSR_BASE_ADDR + 0x06c)
+#define TMU_TEQ_HW_PROB_CFG9           (TMU_CSR_BASE_ADDR + 0x070)
+#define TMU_TEQ_HW_PROB_CFG10          (TMU_CSR_BASE_ADDR + 0x074)
+#define TMU_TEQ_HW_PROB_CFG11          (TMU_CSR_BASE_ADDR + 0x078)
+#define TMU_TEQ_HW_PROB_CFG12          (TMU_CSR_BASE_ADDR + 0x07c)
+#define TMU_TEQ_HW_PROB_CFG13          (TMU_CSR_BASE_ADDR + 0x080)
+#define TMU_TEQ_HW_PROB_CFG14          (TMU_CSR_BASE_ADDR + 0x084)
+#define TMU_TEQ_HW_PROB_CFG15          (TMU_CSR_BASE_ADDR + 0x088)
+#define TMU_TEQ_HW_PROB_CFG16          (TMU_CSR_BASE_ADDR + 0x08c)
+#define TMU_TEQ_HW_PROB_CFG17          (TMU_CSR_BASE_ADDR + 0x090)
+#define TMU_TEQ_HW_PROB_CFG18          (TMU_CSR_BASE_ADDR + 0x094)
+#define TMU_TEQ_HW_PROB_CFG19          (TMU_CSR_BASE_ADDR + 0x098)
+#define TMU_TEQ_HW_PROB_CFG20          (TMU_CSR_BASE_ADDR + 0x09c)
+#define TMU_TEQ_HW_PROB_CFG21          (TMU_CSR_BASE_ADDR + 0x0a0)
+#define TMU_TEQ_HW_PROB_CFG22          (TMU_CSR_BASE_ADDR + 0x0a4)
+#define TMU_TEQ_HW_PROB_CFG23          (TMU_CSR_BASE_ADDR + 0x0a8)
+#define TMU_TEQ_HW_PROB_CFG24          (TMU_CSR_BASE_ADDR + 0x0ac)
+#define TMU_TEQ_HW_PROB_CFG25          (TMU_CSR_BASE_ADDR + 0x0b0)
+#define TMU_TDQ_IIFG_CFG               (TMU_CSR_BASE_ADDR + 0x0b4)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY0
+ */
+#define TMU_TDQ0_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x0b8)
+#define TMU_LLM_CTRL                   (TMU_CSR_BASE_ADDR + 0x0bc)
+#define TMU_LLM_BASE_ADDR              (TMU_CSR_BASE_ADDR + 0x0c0)
+#define TMU_LLM_QUE_LEN                        (TMU_CSR_BASE_ADDR + 0x0c4)
+#define TMU_LLM_QUE_HEADPTR            (TMU_CSR_BASE_ADDR + 0x0c8)
+#define TMU_LLM_QUE_TAILPTR            (TMU_CSR_BASE_ADDR + 0x0cc)
+#define TMU_LLM_QUE_DROPCNT            (TMU_CSR_BASE_ADDR + 0x0d0)
+#define TMU_INT_EN                     (TMU_CSR_BASE_ADDR + 0x0d4)
+#define TMU_INT_SRC                    (TMU_CSR_BASE_ADDR + 0x0d8)
+#define TMU_INQ_STAT                   (TMU_CSR_BASE_ADDR + 0x0dc)
+#define TMU_CTRL                       (TMU_CSR_BASE_ADDR + 0x0e0)
+
+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal
+ * memory Write [27:24] Byte Enables of the Internal memory access [23:0]
+ * Address of the internal memory. This address is used to access both the
+ * PM and DM of all the PE's
+ */
+#define TMU_MEM_ACCESS_ADDR            (TMU_CSR_BASE_ADDR + 0x0e4)
+
+/* Internal Memory Access Write Data */
+#define TMU_MEM_ACCESS_WDATA           (TMU_CSR_BASE_ADDR + 0x0e8)
+/* Internal Memory Access Read Data. The commands are blocked at the
+ * mem_access only
+ */
+#define TMU_MEM_ACCESS_RDATA           (TMU_CSR_BASE_ADDR + 0x0ec)
+
+/* [31:0] PHY0 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY0_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0f0)
+/* [31:0] PHY1 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY1_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0f4)
+/* [31:0] PHY3 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY3_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0fc)
+#define TMU_BMU_INQ_ADDR               (TMU_CSR_BASE_ADDR + 0x100)
+#define TMU_TX_CTRL                    (TMU_CSR_BASE_ADDR + 0x104)
+
+#define TMU_PE_SYS_CLK_RATIO           (TMU_CSR_BASE_ADDR + 0x114)
+#define TMU_PE_STATUS                  (TMU_CSR_BASE_ADDR + 0x118)
+#define TMU_TEQ_MAX_THRESHOLD          (TMU_CSR_BASE_ADDR + 0x11c)
+
+/* [31:0] PHY4 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY4_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x134)
+
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY1
+ */
+#define TMU_TDQ1_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x138)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY3
+ */
+#define TMU_TDQ3_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x140)
+
+#define TMU_BMU_BUF_SIZE               (TMU_CSR_BASE_ADDR + 0x144)
+/* [31:0] PHY5 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY5_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x148)
+
+#define TMU_AXI_CTRL                   (TMU_CSR_BASE_ADDR + 0x17c)
+
+#define SW_RESET               BIT(0) /* Global software reset */
+#define INQ_RESET              BIT(2)
+#define TEQ_RESET              BIT(3)
+#define TDQ_RESET              BIT(4)
+#define PE_RESET               BIT(5)
+#define MEM_INIT               BIT(6)
+#define MEM_INIT_DONE          BIT(7)
+#define LLM_INIT               BIT(8)
+#define LLM_INIT_DONE          BIT(9)
+#define ECC_MEM_INIT_DONE      BIT(10)
+
+struct tmu_cfg {
+       u32 llm_base_addr;
+       u32 llm_queue_len;
+};
+
+/* Not HW related for pfe_ctrl/pfe common defines */
+#define DEFAULT_MAX_QDEPTH     80
+#define DEFAULT_Q0_QDEPTH      511 /* We keep 1 large queue for host tx qos */
+#define DEFAULT_TMU3_QDEPTH    127
+
+#endif /* _TMU_CSR_H_ */

diff --git a/include/net/pfe_eth/pfe/cbus/util_csr.h b/include/net/pfe_eth/pfe/cbus/util_csr.h
new file mode 100644 (file)
index 0000000..bac4114
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/util_csr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _UTIL_CSR_H_
+#define _UTIL_CSR_H_
+
+#define UTIL_VERSION                   (UTIL_CSR_BASE_ADDR + 0x000)
+#define UTIL_TX_CTRL                   (UTIL_CSR_BASE_ADDR + 0x004)
+#define UTIL_INQ_PKTPTR                        (UTIL_CSR_BASE_ADDR + 0x010)
+
+#define UTIL_HDR_SIZE                  (UTIL_CSR_BASE_ADDR + 0x014)
+
+#define UTIL_PE0_QB_DM_ADDR0           (UTIL_CSR_BASE_ADDR + 0x020)
+#define UTIL_PE0_QB_DM_ADDR1           (UTIL_CSR_BASE_ADDR + 0x024)
+#define UTIL_PE0_RO_DM_ADDR0           (UTIL_CSR_BASE_ADDR + 0x060)
+#define UTIL_PE0_RO_DM_ADDR1           (UTIL_CSR_BASE_ADDR + 0x064)
+
+#define UTIL_MEM_ACCESS_ADDR           (UTIL_CSR_BASE_ADDR + 0x100)
+#define UTIL_MEM_ACCESS_WDATA          (UTIL_CSR_BASE_ADDR + 0x104)
+#define UTIL_MEM_ACCESS_RDATA          (UTIL_CSR_BASE_ADDR + 0x108)
+
+#define UTIL_TM_INQ_ADDR               (UTIL_CSR_BASE_ADDR + 0x114)
+#define UTIL_PE_STATUS                 (UTIL_CSR_BASE_ADDR + 0x118)
+
+#define UTIL_PE_SYS_CLK_RATIO          (UTIL_CSR_BASE_ADDR + 0x200)
+#define UTIL_AFULL_THRES               (UTIL_CSR_BASE_ADDR + 0x204)
+#define UTIL_GAP_BETWEEN_READS         (UTIL_CSR_BASE_ADDR + 0x208)
+#define UTIL_MAX_BUF_CNT               (UTIL_CSR_BASE_ADDR + 0x20c)
+#define UTIL_TSQ_FIFO_THRES            (UTIL_CSR_BASE_ADDR + 0x210)
+#define UTIL_TSQ_MAX_CNT               (UTIL_CSR_BASE_ADDR + 0x214)
+#define UTIL_IRAM_DATA_0               (UTIL_CSR_BASE_ADDR + 0x218)
+#define UTIL_IRAM_DATA_1               (UTIL_CSR_BASE_ADDR + 0x21c)
+#define UTIL_IRAM_DATA_2               (UTIL_CSR_BASE_ADDR + 0x220)
+#define UTIL_IRAM_DATA_3               (UTIL_CSR_BASE_ADDR + 0x224)
+
+#define UTIL_BUS_ACCESS_ADDR           (UTIL_CSR_BASE_ADDR + 0x228)
+#define UTIL_BUS_ACCESS_WDATA          (UTIL_CSR_BASE_ADDR + 0x22c)
+#define UTIL_BUS_ACCESS_RDATA          (UTIL_CSR_BASE_ADDR + 0x230)
+
+#define UTIL_INQ_AFULL_THRES           (UTIL_CSR_BASE_ADDR + 0x234)
+#define UTIL_AXI_CTRL                  (UTIL_CSR_BASE_ADDR + 0x240)
+
+#endif /* _UTIL_CSR_H_ */

diff --git a/include/net/pfe_eth/pfe/pfe_hw.h b/include/net/pfe_eth/pfe/pfe_hw.h
new file mode 100644 (file)
index 0000000..992454f
--- /dev/null
+++ b/include/net/pfe_eth/pfe/pfe_hw.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _PFE_H_
+#define _PFE_H_
+
+#include <elf.h>
+#include "cbus.h"
+
+#define PFE_RESET_WA
+
+#define CLASS_DMEM_BASE_ADDR(i)        (0x00000000 | ((i) << 20))
+/* Only valid for mem access register interface */
+#define CLASS_IMEM_BASE_ADDR(i)        (0x00000000 | ((i) << 20))
+#define CLASS_DMEM_SIZE                0x00002000
+#define CLASS_IMEM_SIZE                0x00008000
+
+#define TMU_DMEM_BASE_ADDR(i)  (0x00000000 + ((i) << 20))
+/* Only valid for mem access register interface */
+#define TMU_IMEM_BASE_ADDR(i)  (0x00000000 + ((i) << 20))
+#define TMU_DMEM_SIZE          0x00000800
+#define TMU_IMEM_SIZE          0x00002000
+
+#define UTIL_DMEM_BASE_ADDR    0x00000000
+#define UTIL_DMEM_SIZE         0x00002000
+
+#define PE_LMEM_BASE_ADDR      0xc3010000
+#define PE_LMEM_SIZE           0x8000
+#define PE_LMEM_END            (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+
+#define DMEM_BASE_ADDR         0x00000000
+#define DMEM_SIZE              0x2000          /* TMU has less... */
+#define DMEM_END               (DMEM_BASE_ADDR + DMEM_SIZE)
+
+#define PMEM_BASE_ADDR         0x00010000
+#define PMEM_SIZE              0x8000          /* TMU has less... */
+#define PMEM_END               (PMEM_BASE_ADDR + PMEM_SIZE)
+
+/* Memory ranges check from PE point of view/memory map */
+#define IS_DMEM(addr, len)     (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
+                                       (((unsigned long)(addr) +\
+                                       (len)) <= DMEM_END))
+#define IS_PMEM(addr, len)     (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
+                                       (((unsigned long)(addr) +\
+                                       (len)) <= PMEM_END))
+#define IS_PE_LMEM(addr, len)  (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
+                                       ) && (((unsigned long)(addr)\
+                                       + (len)) <= PE_LMEM_END))
+
+#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
+                                       CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
+                                       (((unsigned long)(addr) + (len)) <=\
+                                       CBUS_VIRT_TO_PFE(LMEM_END)))
+#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
+                                       PFE_DDR_PHYS_BASE_ADDR) &&\
+                                       (((unsigned long)(addr) + (len)) <=\
+                                       PFE_DDR_PHYS_END))
+
+/* Host View Address */
+extern void *ddr_pfe_base_addr;
+
+/* PFE View Address */
+/* DDR physical base address as seen by PE's. */
+#define PFE_DDR_PHYS_BASE_ADDR 0x03800000
+#define PFE_DDR_PHYS_SIZE      0xC000000
+#define PFE_DDR_PHYS_END       (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
+/* CBUS physical base address as seen by PE's. */
+#define PFE_CBUS_PHYS_BASE_ADDR        0xc0000000
+
+/* Host<->PFE Mapping */
+#define DDR_PFE_TO_VIRT(p)     ((unsigned long int)((p) + 0x80000000))
+#define CBUS_VIRT_TO_PFE(v)    (((v) - CBUS_BASE_ADDR) +\
+                                       PFE_CBUS_PHYS_BASE_ADDR)
+#define CBUS_PFE_TO_VIRT(p)    (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
+                                       CBUS_BASE_ADDR)
+
+enum {
+       CLASS0_ID = 0,
+       CLASS1_ID,
+       CLASS2_ID,
+       CLASS3_ID,
+       CLASS4_ID,
+       CLASS5_ID,
+
+       TMU0_ID,
+       TMU1_ID,
+       TMU2_ID,
+       TMU3_ID,
+       MAX_PE
+};
+
+#define CLASS_MASK     (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
+                               | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
+                               BIT(CLASS5_ID))
+#define CLASS_MAX_ID   CLASS5_ID
+
+#define TMU_MASK       (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
+#define TMU_MAX_ID     TMU3_ID
+
+/*
+ * PE information.
+ * Structure containing PE's specific information. It is used to create
+ * generic C functions common to all PEs.
+ * Before using the library functions this structure needs to be
+ * initialized with the different registers virtual addresses
+ * (according to the ARM MMU mmaping). The default initialization supports a
+ * virtual == physical mapping.
+ *
+ */
+struct pe_info {
+       u32 dmem_base_addr;             /* PE's dmem base address */
+       u32 pmem_base_addr;             /* PE's pmem base address */
+       u32 pmem_size;                  /* PE's pmem size */
+
+       void *mem_access_wdata;        /* PE's _MEM_ACCESS_WDATA
+                                       * register address
+                                       */
+       void *mem_access_addr;         /* PE's _MEM_ACCESS_ADDR
+                                       * register address
+                                       */
+       void *mem_access_rdata;        /* PE's _MEM_ACCESS_RDATA
+                                       * register address
+                                       */
+};
+
+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
+void pe_lmem_write(u32 *src, u32 len, u32 offset);
+
+u32 pe_pmem_read(int id, u32 addr, u8 size);
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
+u32 pe_dmem_read(int id, u32 addr, u8 size);
+
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
+
+void pfe_lib_init(void);
+
+void bmu_init(void *base, struct bmu_cfg *cfg);
+void bmu_enable(void *base);
+
+void gpi_init(void *base, struct gpi_cfg *cfg);
+void gpi_enable(void *base);
+void gpi_disable(void *base);
+
+void class_init(struct class_cfg *cfg);
+void class_enable(void);
+void class_disable(void);
+
+void tmu_init(struct tmu_cfg *cfg);
+void tmu_enable(u32 pe_mask);
+void tmu_disable(u32 pe_mask);
+
+void hif_init(void);
+void hif_tx_enable(void);
+void hif_tx_disable(void);
+void hif_rx_enable(void);
+void hif_rx_disable(void);
+void hif_rx_desc_disable(void);
+
+#endif /* _PFE_H_ */

diff --git a/include/net/pfe_eth/pfe_driver.h b/include/net/pfe_eth/pfe_driver.h
new file mode 100644 (file)
index 0000000..da7d247
--- /dev/null
+++ b/include/net/pfe_eth/pfe_driver.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __PFE_DRIVER_H__
+#define __PFE_DRIVER_H__
+
+#include <net/pfe_eth/pfe/pfe_hw.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define HIF_RX_DESC_NT         64
+#define        HIF_TX_DESC_NT          64
+
+#define RX_BD_BASEADDR         (HIF_DESC_BASEADDR)
+#define TX_BD_BASEADDR         (HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
+
+#define MIN_PKT_SIZE           56
+#define MAX_FRAME_SIZE         2048
+
+struct __packed hif_header_s {
+       u8      port_no; /* Carries input port no for host rx packets and
+                         * output port no for tx pkts
+                         */
+       u8 reserved0;
+       u32 reserved2;
+};
+
+struct __packed buf_desc {
+       u32 ctrl;
+       u32 status;
+       u32 data;
+       u32 next;
+};
+
+struct rx_desc_s {
+       struct buf_desc *rx_base;
+       unsigned int rx_base_pa;
+       int rx_to_read;
+       int rx_ring_size;
+};
+
+struct tx_desc_s {
+       struct buf_desc *tx_base;
+       unsigned int tx_base_pa;
+       int tx_to_send;
+       int tx_ring_size;
+};
+
+int pfe_send(int phy_port, void *data, int length);
+int pfe_recv(uchar **pkt_ptr, int *phy_port);
+int pfe_tx_done(void);
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length);
+int pfe_drv_init(struct pfe_ddr_address  *pfe_addr);
+int pfe_eth_remove(struct udevice *dev);
+
+#endif

diff --git a/include/net/pfe_eth/pfe_eth.h b/include/net/pfe_eth/pfe_eth.h
new file mode 100644 (file)
index 0000000..f319365
--- /dev/null
+++ b/include/net/pfe_eth/pfe_eth.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __PFE_ETH_H__
+#define __PFE_ETH_H__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include "pfe_driver.h"
+
+#define BMU2_DDR_BASEADDR      0
+#define BMU2_BUF_COUNT         (3 * SZ_1K)
+#define BMU2_DDR_SIZE          (DDR_BUF_SIZE * BMU2_BUF_COUNT)
+
+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define HIF_RX_PKT_DDR_SIZE     (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+#define HIF_TX_PKT_DDR_SIZE     (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+
+#define HIF_DESC_BASEADDR       (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+#define HIF_RX_DESC_SIZE        (16 * HIF_RX_DESC_NT)
+#define HIF_TX_DESC_SIZE        (16 * HIF_TX_DESC_NT)
+
+#define UTIL_CODE_BASEADDR     0x780000
+#define UTIL_CODE_SIZE         (128 * SZ_1K)
+
+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE     (64 * SZ_1K)
+
+#define CLASS_DDR_DATA_BASEADDR        (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE    (32 * SZ_1K)
+
+#define TMU_DDR_DATA_BASEADDR  (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE      (32 * SZ_1K)
+
+#define TMU_LLM_BASEADDR       (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define TMU_LLM_QUEUE_LEN      (16 * 256)
+       /* Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE           (4 * 16 * TMU_LLM_QUEUE_LEN)
+       /* (4 TMU's x 16 queues x queue_len) */
+
+#define ROUTE_TABLE_BASEADDR   0x800000
+#define ROUTE_TABLE_HASH_BITS_MAX      15 /* 32K entries */
+#define ROUTE_TABLE_HASH_BITS          8  /* 256 entries */
+#define ROUTE_TABLE_SIZE       (BIT(ROUTE_TABLE_HASH_BITS_MAX) \
+                               * CLASS_ROUTE_SIZE)
+
+#define        PFE_TOTAL_DATA_SIZE     (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+
+#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
+#error DDR mapping above 12MiB
+#endif
+
+/* LMEM Mapping */
+#define BMU1_LMEM_BASEADDR     0
+#define BMU1_BUF_COUNT         256
+#define BMU1_LMEM_SIZE         (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+
+struct gemac_s {
+       void *gemac_base;
+       void *egpi_base;
+
+       /* GEMAC config */
+       int gemac_mode;
+       int gemac_speed;
+       int gemac_duplex;
+       int flags;
+       /* phy iface */
+       int phy_address;
+       int phy_mode;
+       struct mii_dev *bus;
+
+};
+
+struct pfe_mdio_info {
+       void *reg_base;
+       char *name;
+};
+
+struct pfe_eth_dev {
+       int gemac_port;
+       struct gemac_s *gem;
+       struct pfe_ddr_address pfe_addr;
+       struct udevice *dev;
+#ifdef CONFIG_PHYLIB
+       struct phy_device *phydev;
+#endif
+};
+
+int pfe_remove(struct pfe_ddr_address *pfe_addr);
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info);
+void pfe_set_mdio(int dev_id, struct mii_dev *bus);
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
+int gemac_initialize(bd_t *bis, int dev_id, char *devname);
+int pfe_init(struct pfe_ddr_address *pfe_addr);
+int pfe_eth_board_init(struct udevice *dev);
+
+#endif /* __PFE_ETH_H__ */

diff --git a/include/net/pfe_eth/pfe_firmware.h b/include/net/pfe_eth/pfe_firmware.h
new file mode 100644 (file)
index 0000000..588b2ae
--- /dev/null
+++ b/include/net/pfe_eth/pfe_firmware.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/** @file
+ *  Contains all the defines to handle parsing and loading of PE firmware files.
+ */
+#ifndef __PFE_FIRMWARE_H__
+#define __PFE_FIRMWARE_H__
+
+int pfe_firmware_init(void);
+void pfe_firmware_exit(void);
+
+#endif

diff --git a/include/net/pfe_eth/pfe_mdio.h b/include/net/pfe_eth/pfe_mdio.h
new file mode 100644 (file)
index 0000000..ab27ec3
--- /dev/null
+++ b/include/net/pfe_eth/pfe_mdio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _PFE_MDIO_H_
+#define _PFE_MDIO_H_
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id);
+
+#endif /* _PFE_MDIO_H_ */

diff --git a/include/netdev.h b/include/netdev.h
index 3958a4cd32dd23653fcac286d4be8555989a1fdd..86d28ade14b6d5c14c9013428f923d2ce41629ad 100644 (file)
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -39,8 +39,6 @@ int dm9000_initialize(bd_t *bis);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
 int eepro100_initialize(bd_t *bis);
-int enc28j60_initialize(unsigned int bus, unsigned int cs,
-       unsigned int max_hz, unsigned int mode);
 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
 int eth_3com_initialize (bd_t * bis);
 int ethoc_initialize(u8 dev_num, int base_addr);

diff --git a/include/pci.h b/include/pci.h
index 7adc04301c06a90f582622d26bb17f770781a699..31dc7608a739658206dd47ea3e57f9360be99a07 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -585,8 +585,6 @@ struct pci_controller {
        /* Used by auto config */
        struct pci_region *pci_mem, *pci_io, *pci_prefetch;
 
-       /* Used by ppc405 autoconfig*/
-       struct pci_region *pci_fb;
 #ifndef CONFIG_DM_PCI
        int current_busno;
 

diff --git a/include/power/stpmu1.h b/include/power/stpmu1.h
new file mode 100644 (file)
index 0000000..697e245
--- /dev/null
+++ b/include/power/stpmu1.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#ifndef __PMIC_STPMU1_H_
+#define __PMIC_STPMU1_H_
+
+#define STPMU1_MASK_RESET_BUCK         0x18
+#define STPMU1_BUCKX_CTRL_REG(buck)    (0x20 + (buck))
+#define STPMU1_VREF_CTRL_REG           0x24
+#define STPMU1_LDOX_CTRL_REG(ldo)      (0x25 + (ldo))
+#define STPMU1_USB_CTRL_REG            0x40
+#define STPMU1_NVM_USER_STATUS_REG     0xb8
+#define STPMU1_NVM_USER_CONTROL_REG    0xb9
+
+#define STPMU1_MASK_RESET_BUCK3                BIT(2)
+
+#define STPMU1_BUCK_EN                 BIT(0)
+#define STPMU1_BUCK_MODE               BIT(1)
+#define STPMU1_BUCK_OUTPUT_MASK                GENMASK(7, 2)
+#define STPMU1_BUCK_OUTPUT_SHIFT       2
+#define STPMU1_BUCK2_1200000V          (24 << STPMU1_BUCK_OUTPUT_SHIFT)
+#define STPMU1_BUCK2_1350000V          (30 << STPMU1_BUCK_OUTPUT_SHIFT)
+#define STPMU1_BUCK3_1800000V          (39 << STPMU1_BUCK_OUTPUT_SHIFT)
+
+#define STPMU1_VREF_EN                 BIT(0)
+
+#define STPMU1_LDO_EN                  BIT(0)
+#define STPMU1_LDO12356_OUTPUT_MASK    GENMASK(6, 2)
+#define STPMU1_LDO12356_OUTPUT_SHIFT   2
+#define STPMU1_LDO3_MODE               BIT(7)
+#define STPMU1_LDO3_DDR_SEL            31
+#define STPMU1_LDO3_1800000            (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
+#define STPMU1_LDO4_UV                 3300000
+
+#define STPMU1_USB_BOOST_EN            BIT(0)
+#define STPMU1_USB_PWR_SW_EN           GENMASK(2, 1)
+
+#define STPMU1_NVM_USER_CONTROL_PROGRAM        BIT(0)
+#define STPMU1_NVM_USER_CONTROL_READ   BIT(1)
+
+#define STPMU1_NVM_USER_STATUS_BUSY    BIT(0)
+#define STPMU1_NVM_USER_STATUS_ERROR   BIT(1)
+
+#define STPMU1_DEFAULT_START_UP_DELAY_MS       1
+#define STPMU1_USB_BOOST_START_UP_DELAY_MS     10
+
+enum {
+       STPMU1_BUCK1,
+       STPMU1_BUCK2,
+       STPMU1_BUCK3,
+       STPMU1_BUCK4,
+       STPMU1_MAX_BUCK,
+};
+
+enum {
+       STPMU1_BUCK_MODE_HP,
+       STPMU1_BUCK_MODE_LP,
+};
+
+enum {
+       STPMU1_LDO1,
+       STPMU1_LDO2,
+       STPMU1_LDO3,
+       STPMU1_LDO4,
+       STPMU1_LDO5,
+       STPMU1_LDO6,
+       STPMU1_MAX_LDO,
+};
+
+enum {
+       STPMU1_LDO_MODE_NORMAL,
+       STPMU1_LDO_MODE_BYPASS,
+       STPMU1_LDO_MODE_SINK_SOURCE,
+};
+
+enum {
+       STPMU1_PWR_SW1,
+       STPMU1_PWR_SW2,
+       STPMU1_MAX_PWR_SW,
+};
+
+#endif

diff --git a/include/st_logo_data.h b/include/st_logo_data.h
new file mode 100644 (file)
index 0000000..4d3a26e
--- /dev/null
+++ b/include/st_logo_data.h
@@ -0,0 +1,3267 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ *           Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * file generated from picture
+ * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
+ */
+
+unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
+0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
+0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
+0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
+0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xae, 0x82, 0x3a, 0x00, 0xa5, 0x7b,
+0x37, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0xac, 0x80, 0x39, 0x00, 0x4e, 0x1b,
+0x02, 0x00, 0xb7, 0x88, 0x3b, 0x00, 0x4f, 0x1c, 0x02, 0x00, 0xb3, 0x85,
+0x3a, 0x00, 0xe1, 0xaa, 0x35, 0x00, 0x86, 0x62, 0x1f, 0x00, 0x65, 0x4a,
+0x13, 0x00, 0xa9, 0x7e, 0x38, 0x00, 0xff, 0xfe, 0xff, 0x00, 0x77, 0x55,
+0x13, 0x00, 0xbe, 0x91, 0x47, 0x00, 0xbc, 0x8d, 0x3d, 0x00, 0xfe, 0xfd,
+0xfd, 0x00, 0xa3, 0x7a, 0x38, 0x00, 0xbd, 0x8e, 0x42, 0x00, 0xa7, 0x7d,
+0x39, 0x00, 0x72, 0x52, 0x14, 0x00, 0xbc, 0x8d, 0x40, 0x00, 0x84, 0x60,
+0x1e, 0x00, 0xba, 0x8a, 0x3c, 0x00, 0x75, 0x53, 0x13, 0x00, 0x87, 0x62,
+0x11, 0x00, 0x85, 0x60, 0x10, 0x00, 0x7e, 0x5b, 0x12, 0x00, 0xb4, 0x86,
+0x3a, 0x00, 0x8c, 0x6a, 0x35, 0x00, 0xb1, 0x84, 0x3b, 0x00, 0xaa, 0x7f,
+0x3a, 0x00, 0xbc, 0x8c, 0x3c, 0x00, 0x85, 0x64, 0x34, 0x00, 0xb9, 0x89,
+0x3b, 0x00, 0x93, 0x69, 0x0e, 0x00, 0x8d, 0x65, 0x0e, 0x00, 0xfd, 0xfd,
+0xfc, 0x00, 0xa0, 0x78, 0x37, 0x00, 0x81, 0x5d, 0x12, 0x00, 0x9e, 0x76,
+0x36, 0x00, 0xbe, 0x90, 0x45, 0x00, 0x94, 0x6a, 0x0b, 0x00, 0x8b, 0x64,
+0x10, 0x00, 0x68, 0x4c, 0x14, 0x00, 0x8b, 0x69, 0x35, 0x00, 0x82, 0x5e,
+0x11, 0x00, 0x90, 0x6c, 0x35, 0x00, 0x89, 0x63, 0x0f, 0x00, 0xaf, 0x83,
+0x39, 0x00, 0xa2, 0x75, 0x06, 0x00, 0x96, 0x6b, 0x0d, 0x00, 0x7b, 0x59,
+0x12, 0x00, 0x9c, 0x70, 0x08, 0x00, 0x99, 0x73, 0x37, 0x00, 0xb0, 0x83,
+0x39, 0x00, 0x84, 0x60, 0x11, 0x00, 0x80, 0x5c, 0x14, 0x00, 0x91, 0x68,
+0x0c, 0x00, 0x6a, 0x4d, 0x14, 0x00, 0xc3, 0x99, 0x54, 0x00, 0x92, 0x6e,
+0x36, 0x00, 0x9a, 0x6e, 0x0b, 0x00, 0x8a, 0x68, 0x34, 0x00, 0xc0, 0x94,
+0x4b, 0x00, 0x98, 0x6c, 0x09, 0x00, 0x8f, 0x67, 0x0f, 0x00, 0x82, 0x62,
+0x34, 0x00, 0x7d, 0x5a, 0x15, 0x00, 0xc5, 0x9f, 0x5f, 0x00, 0xbb, 0x8b,
+0x3b, 0x00, 0xc8, 0xa7, 0x6a, 0x00, 0xc0, 0x95, 0x4e, 0x00, 0x87, 0x66,
+0x34, 0x00, 0x9f, 0x72, 0x06, 0x00, 0xbf, 0x93, 0x49, 0x00, 0xfd, 0xfb,
+0xfc, 0x00, 0xc7, 0xa4, 0x66, 0x00, 0x7a, 0x57, 0x13, 0x00, 0xc4, 0x9d,
+0x5a, 0x00, 0x83, 0x5f, 0x13, 0x00, 0x9c, 0x75, 0x36, 0x00, 0x7f, 0x60,
+0x32, 0x00, 0xb5, 0x87, 0x3c, 0x00, 0xc3, 0x9b, 0x57, 0x00, 0xc8, 0xa5,
+0x69, 0x00, 0x72, 0x55, 0x25, 0x00, 0xb9, 0x8a, 0x3a, 0x00, 0x94, 0x70,
+0x36, 0x00, 0xa2, 0x79, 0x36, 0x00, 0x7f, 0x5c, 0x12, 0x00, 0x97, 0x72,
+0x37, 0x00, 0x6c, 0x4e, 0x14, 0x00, 0xc5, 0x9e, 0x5d, 0x00, 0xca, 0xa9,
+0x6c, 0x00, 0xc5, 0xa3, 0x64, 0x00, 0x9e, 0x72, 0x0b, 0x00, 0xad, 0x81,
+0x3a, 0x00, 0x8e, 0x6b, 0x36, 0x00, 0xc6, 0xa1, 0x62, 0x00, 0x7c, 0x5f,
+0x31, 0x00, 0x6f, 0x50, 0x14, 0x00, 0xc1, 0x96, 0x50, 0x00, 0xd9, 0xc4,
+0x9f, 0x00, 0xcd, 0xbe, 0xa9, 0x00, 0xaa, 0x98, 0x7f, 0x00, 0xf6, 0xf3,
+0xf1, 0x00, 0xb9, 0x9b, 0x62, 0x00, 0x6a, 0x4c, 0x19, 0x00, 0x76, 0x59,
+0x29, 0x00, 0x79, 0x57, 0x15, 0x00, 0x6e, 0x4f, 0x13, 0x00, 0xfb, 0xf9,
+0xf9, 0x00, 0xae, 0x8d, 0x53, 0x00, 0x78, 0x5c, 0x2e, 0x00, 0xb2, 0x91,
+0x55, 0x00, 0xe8, 0xe1, 0xdc, 0x00, 0x8b, 0x69, 0x2e, 0x00, 0xc0, 0x9f,
+0x62, 0x00, 0xc1, 0x97, 0x52, 0x00, 0x52, 0x20, 0x06, 0x00, 0xbe, 0x9c,
+0x60, 0x00, 0xa1, 0x79, 0x38, 0x00, 0xed, 0xe8, 0xe5, 0x00, 0xdc, 0xc8,
+0xa6, 0x00, 0xd6, 0xca, 0xb9, 0x00, 0x80, 0x5e, 0x1d, 0x00, 0xb6, 0x95,
+0x58, 0x00, 0xb5, 0x97, 0x60, 0x00, 0x92, 0x75, 0x41, 0x00, 0x6f, 0x51,
+0x1d, 0x00, 0xc9, 0xba, 0xb2, 0x00, 0xa2, 0x88, 0x7b, 0x00, 0x82, 0x5e,
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+0x01, 0x62, 0x04, 0x01, 0x03, 0x38, 0x01, 0x1f, 0x04, 0x08, 0x01, 0x1d,
+0x01, 0x1d, 0x03, 0x54, 0x03, 0x06, 0x01, 0x23, 0x03, 0x18, 0x01, 0x47,
+0x01, 0x18, 0x05, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x06, 0x13,
+0x01, 0x2a, 0x01, 0x2a, 0x07, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41,
+0x04, 0x49, 0x03, 0x67, 0x04, 0x78, 0x05, 0x3d, 0x05, 0x55, 0x05, 0x50,
+0x05, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x01, 0x60, 0x05, 0x4e,
+0x05, 0x56, 0x07, 0x48, 0x05, 0x5f, 0x00, 0x03, 0x48, 0x5f, 0x5f, 0x00,
+0x07, 0x48, 0x04, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x60, 0x04, 0x64,
+0x07, 0x46, 0x04, 0x5e, 0x01, 0x50, 0x01, 0x5e, 0x04, 0x50, 0x05, 0x55,
+0x05, 0x3d, 0x03, 0x78, 0x04, 0x67, 0x05, 0x49, 0x03, 0x41, 0x04, 0x4c,
+0x01, 0x0f, 0x01, 0x4c, 0x03, 0x0f, 0x04, 0x2a, 0x05, 0x13, 0x00, 0x04,
+0x16, 0x16, 0x10, 0x10, 0x04, 0x21, 0x01, 0x47, 0x05, 0x18, 0x00, 0x04,
+0x23, 0x23, 0x06, 0x06, 0x04, 0x54, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x05,
+0x1f, 0x1f, 0x38, 0x38, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62,
+0x03, 0x04, 0x01, 0x20, 0x01, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x07,
+0x02, 0xaf, 0x88, 0x88, 0x72, 0x6c, 0xad, 0x00, 0x2b, 0x00, 0x00, 0x00,
+0x82, 0x00, 0x00, 0x05, 0xb1, 0xd4, 0x82, 0x82, 0xb8, 0x00, 0x03, 0xbb,
+0x01, 0xb4, 0x01, 0x52, 0x04, 0x29, 0x04, 0x27, 0x00, 0x05, 0x7b, 0x5a,
+0x5a, 0x12, 0x12, 0x00, 0x05, 0x02, 0x05, 0x14, 0x00, 0x04, 0x0c, 0x0c,
+0x20, 0x20, 0x04, 0x04, 0x01, 0x62, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x1f, 0x1f, 0x00, 0x04, 0x08, 0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54,
+0x04, 0x06, 0x01, 0x23, 0x04, 0x18, 0x00, 0x06, 0x47, 0x21, 0x21, 0x47,
+0x21, 0x21, 0x04, 0x16, 0x04, 0x13, 0x05, 0x2a, 0x06, 0x0f, 0x03, 0x4c,
+0x04, 0x41, 0x04, 0x49, 0x01, 0x67, 0x01, 0x67, 0x05, 0x78, 0x05, 0x3d,
+0x06, 0x55, 0x05, 0x50, 0x04, 0x5e, 0x05, 0x46, 0x01, 0x64, 0x01, 0x46,
+0x04, 0x64, 0x03, 0x60, 0x04, 0x4e, 0x05, 0x56, 0x07, 0x48, 0x01, 0x5f,
+0x01, 0x48, 0x04, 0x5f, 0x09, 0x48, 0x04, 0x56, 0x06, 0x4e, 0x06, 0x64,
+0x07, 0x46, 0x04, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x05, 0x3d, 0x05, 0x78,
+0x03, 0x67, 0x05, 0x49, 0x01, 0x41, 0x01, 0x41, 0x04, 0x4c, 0x05, 0x0f,
+0x04, 0x2a, 0x04, 0x13, 0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21,
+0x01, 0x47, 0x05, 0x18, 0x00, 0x04, 0x23, 0x23, 0x06, 0x06, 0x03, 0x54,
+0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32,
+0x32, 0x00, 0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x01, 0x20,
+0x01, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x07, 0x02, 0xaa, 0x74, 0x81,
+0x88, 0x74, 0x90, 0x00, 0x2b, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x05,
+0x6b, 0x8b, 0xf4, 0xa6, 0xb4, 0x00, 0x04, 0xb8, 0x00, 0x0b, 0xb4, 0x7b,
+0x27, 0x29, 0x29, 0x27, 0x7b, 0x27, 0x7b, 0x12, 0x5a, 0x00, 0x03, 0x12,
+0x05, 0x02, 0x03, 0x14, 0x03, 0x0c, 0x01, 0x20, 0x01, 0x20, 0x03, 0x04,
+0x04, 0x62, 0x00, 0x04, 0x01, 0x01, 0x32, 0x38, 0x03, 0x1f, 0x03, 0x08,
+0x00, 0x04, 0x1d, 0x1d, 0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23,
+0x04, 0x18, 0x03, 0x47, 0x01, 0x21, 0x01, 0x21, 0x03, 0x10, 0x03, 0x16,
+0x04, 0x13, 0x04, 0x2a, 0x05, 0x0f, 0x04, 0x4c, 0x04, 0x41, 0x04, 0x49,
+0x01, 0x67, 0x01, 0x67, 0x04, 0x78, 0x07, 0x3d, 0x05, 0x55, 0x06, 0x50,
+0x04, 0x5e, 0x05, 0x46, 0x06, 0x64, 0x01, 0x60, 0x01, 0x60, 0x05, 0x4e,
+0x05, 0x56, 0x14, 0x48, 0x05, 0x56, 0x06, 0x4e, 0x06, 0x64, 0x06, 0x46,
+0x05, 0x5e, 0x06, 0x50, 0x05, 0x55, 0x06, 0x3d, 0x03, 0x78, 0x03, 0x67,
+0x05, 0x49, 0x03, 0x41, 0x04, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x05, 0x13,
+0x03, 0x16, 0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x00, 0x07, 0x47, 0x47,
+0x18, 0x18, 0x58, 0x23, 0x23, 0x00, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d,
+0x01, 0x1d, 0x04, 0x08, 0x00, 0x05, 0x1f, 0x1f, 0x38, 0x32, 0x32, 0x00,
+0x03, 0x01, 0x01, 0x62, 0x01, 0x62, 0x03, 0x04, 0x01, 0x20, 0x01, 0x20,
+0x03, 0x0c, 0x04, 0x14, 0x00, 0x08, 0x02, 0x02, 0xc1, 0x6c, 0x6c, 0x74,
+0xa7, 0x6b, 0x2a, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x05, 0xad, 0xea,
+0xb8, 0x37, 0xb4, 0x00, 0x04, 0xb8, 0x00, 0x04, 0xaf, 0xb4, 0xb4, 0x7b,
+0x04, 0x27, 0x01, 0x5a, 0x03, 0x12, 0x06, 0x02, 0x03, 0x14, 0x00, 0x04,
+0x0c, 0x0c, 0x20, 0x20, 0x03, 0x04, 0x03, 0x62, 0x00, 0x05, 0x01, 0x01,
+0x32, 0x32, 0x38, 0x00, 0x04, 0x1f, 0x00, 0x06, 0x08, 0x08, 0x1d, 0x1d,
+0x54, 0x54, 0x03, 0x06, 0x01, 0x23, 0x01, 0x23, 0x04, 0x18, 0x00, 0x04,
+0x47, 0x47, 0x21, 0x47, 0x03, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16,
+0x04, 0x13, 0x04, 0x2a, 0x06, 0x0f, 0x03, 0x4c, 0x03, 0x41, 0x03, 0x49,
+0x01, 0x67, 0x01, 0x49, 0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x06, 0x55,
+0x04, 0x50, 0x05, 0x5e, 0x05, 0x46, 0x04, 0x64, 0x01, 0x60, 0x03, 0x64,
+0x06, 0x4e, 0x05, 0x56, 0x12, 0x48, 0x06, 0x56, 0x05, 0x4e, 0x07, 0x64,
+0x06, 0x46, 0x04, 0x5e, 0x07, 0x50, 0x05, 0x55, 0x03, 0x3d, 0x00, 0x03,
+0x78, 0x3d, 0x3d, 0x00, 0x03, 0x78, 0x03, 0x67, 0x04, 0x49, 0x05, 0x41,
+0x01, 0x4c, 0x01, 0x4c, 0x06, 0x0f, 0x03, 0x2a, 0x05, 0x13, 0x03, 0x16,
+0x01, 0x10, 0x01, 0x10, 0x04, 0x21, 0x01, 0x47, 0x04, 0x18, 0x01, 0x23,
+0x01, 0x23, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08,
+0x00, 0x05, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62,
+0x03, 0x04, 0x03, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x0a, 0x02, 0x5a,
+0xaa, 0x91, 0x6c, 0x6c, 0x81, 0xd9, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00,
+0x87, 0x00, 0x00, 0x05, 0xb2, 0xea, 0xa8, 0xb4, 0xb4, 0x00, 0x03, 0xaf,
+0x01, 0xa8, 0x03, 0xaf, 0x00, 0x04, 0xb4, 0xb4, 0x12, 0x7b, 0x03, 0x5a,
+0x01, 0x02, 0x01, 0x12, 0x04, 0x02, 0x01, 0x14, 0x01, 0x14, 0x04, 0x0c,
+0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x00, 0x03, 0x1d, 0x54, 0x1d, 0x00,
+0x03, 0x06, 0x03, 0x23, 0x01, 0x18, 0x01, 0x18, 0x03, 0x47, 0x01, 0x21,
+0x01, 0x47, 0x04, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x04, 0x13,
+0x04, 0x2a, 0x05, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41, 0x04, 0x49,
+0x04, 0x67, 0x01, 0x78, 0x01, 0x78, 0x08, 0x3d, 0x05, 0x55, 0x05, 0x50,
+0x04, 0x5e, 0x07, 0x46, 0x04, 0x64, 0x08, 0x4e, 0x03, 0x56, 0x13, 0x48,
+0x06, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x4e, 0x04, 0x64, 0x07, 0x46,
+0x05, 0x5e, 0x04, 0x50, 0x04, 0x55, 0x01, 0x3d, 0x01, 0x55, 0x03, 0x3d,
+0x06, 0x78, 0x04, 0x67, 0x01, 0x49, 0x01, 0x49, 0x05, 0x41, 0x03, 0x4c,
+0x05, 0x0f, 0x04, 0x2a, 0x03, 0x13, 0x04, 0x16, 0x00, 0x04, 0x10, 0x10,
+0x21, 0x21, 0x05, 0x47, 0x01, 0x58, 0x01, 0x58, 0x03, 0x23, 0x04, 0x06,
+0x04, 0x1d, 0x04, 0x08, 0x03, 0x38, 0x00, 0x03, 0x32, 0x01, 0x01, 0x00,
+0x05, 0x04, 0x06, 0x0c, 0x07, 0x02, 0x00, 0x08, 0x5a, 0x5a, 0x74, 0x8f,
+0x8f, 0x80, 0xd0, 0x4d, 0x29, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x07,
+0x03, 0x00, 0x00, 0x0d, 0x75, 0x8b, 0x88, 0x00, 0x04, 0xaf, 0x06, 0xa8,
+0x03, 0xaf, 0x03, 0xaa, 0x03, 0x14, 0x0c, 0xaa, 0x01, 0x62, 0x06, 0x01,
+0x07, 0x1f, 0x06, 0x54, 0x01, 0x06, 0x04, 0xb7, 0x03, 0x18, 0x03, 0x16,
+0x01, 0x10, 0x03, 0x16, 0x04, 0xf3, 0x00, 0x04, 0x13, 0xf3, 0xf3, 0x2a,
+0x08, 0x0f, 0x00, 0x05, 0x4c, 0x4c, 0xfb, 0xfb, 0x41, 0x00, 0x06, 0x49,
+0x01, 0x67, 0x01, 0x67, 0x09, 0x78, 0x03, 0x3d, 0x07, 0x55, 0x05, 0x50,
+0x06, 0x5e, 0x06, 0x46, 0x03, 0x64, 0x05, 0x60, 0x07, 0x4e, 0x10, 0x56,
+0x04, 0x4e, 0x00, 0x04, 0x60, 0x60, 0x4e, 0x4e, 0x04, 0x60, 0x04, 0x64,
+0x0a, 0x46, 0x01, 0x5e, 0x01, 0x5e, 0x05, 0x50, 0x07, 0x55, 0x03, 0x3d,
+0x00, 0x03, 0x78, 0x3d, 0x3d, 0x00, 0x07, 0x78, 0x01, 0x67, 0x01, 0x67,
+0x06, 0x49, 0x01, 0x41, 0x07, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x06, 0x13,
+0x06, 0x16, 0x00, 0x03, 0xb7, 0xb7, 0x16, 0x00, 0x08, 0xb7, 0x06, 0x54,
+0x08, 0x1f, 0x04, 0x01, 0x00, 0x04, 0x62, 0xaa, 0x62, 0xaa, 0x03, 0x20,
+0x03, 0xaa, 0x00, 0x0b, 0x14, 0x14, 0x02, 0xf8, 0x8f, 0xcc, 0x8f, 0xcc,
+0xe7, 0x00, 0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x86, 0x00, 0x01, 0x0d,
+0x01, 0x11, 0x03, 0x00, 0x00, 0x05, 0x6b, 0x7e, 0xcf, 0x88, 0xa8, 0x00,
+0x03, 0xaf, 0x03, 0xa8, 0x03, 0x72, 0x06, 0xa8, 0x00, 0x06, 0x72, 0xa8,
+0xa8, 0x72, 0x72, 0xa8, 0x23, 0x72, 0x1d, 0x74, 0x13, 0x80, 0x00, 0x04,
+0x81, 0x80, 0x80, 0x81, 0x04, 0x80, 0x1b, 0x81, 0x00, 0x04, 0x91, 0x91,
+0x81, 0x91, 0x34, 0x6c, 0x03, 0x7a, 0x01, 0x6c, 0x22, 0x7a, 0x03, 0x77,
+0x00, 0x03, 0x7a, 0x7a, 0x77, 0x00, 0x03, 0x7a, 0x05, 0x77, 0x01, 0x7a,
+0x2a, 0x77, 0x03, 0xcc, 0x00, 0x04, 0x91, 0xd9, 0x00, 0x03, 0x27, 0x00,
+0x00, 0x00, 0x8e, 0x00, 0x00, 0x0b, 0x8e, 0x7e, 0xea, 0x8f, 0x88, 0xa8,
+0xaf, 0xaf, 0xa8, 0x72, 0x72, 0x00, 0x3d, 0x88, 0x2c, 0x81, 0x01, 0x6c,
+0x09, 0x81, 0x01, 0x6c, 0x03, 0x81, 0x2e, 0x6c, 0x28, 0x8f, 0x1c, 0xcc,
+0x01, 0xa7, 0x03, 0xcc, 0x00, 0x05, 0xa7, 0xcc, 0xa7, 0xa7, 0xcc, 0x00,
+0x14, 0xa7, 0x13, 0x9d, 0x00, 0x07, 0xa7, 0x9d, 0x9d, 0x77, 0xec, 0x00,
+0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x08, 0x6b, 0xb2,
+0x7d, 0xd0, 0xea, 0xcc, 0x81, 0x88, 0x12, 0xc1, 0x00, 0x03, 0x72, 0x72,
+0xc1, 0x00, 0x24, 0x72, 0x01, 0x74, 0x03, 0x72, 0x01, 0x74, 0x01, 0x72,
+0x27, 0x74, 0x2c, 0x80, 0x01, 0x91, 0x01, 0x80, 0x23, 0x91, 0x05, 0x7a,
+0x01, 0x91, 0x18, 0x7a, 0x04, 0x77, 0x01, 0x7a, 0x1b, 0x77, 0x01, 0x60,
+0x01, 0x64, 0x24, 0x60, 0x00, 0x05, 0x77, 0xfa, 0x6b, 0x00, 0x0d, 0x00,
+0x27, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x08, 0x71, 0x7c, 0xe7, 0xec,
+0x7e, 0x7d, 0x68, 0x90, 0x45, 0x8b, 0x00, 0x03, 0x90, 0x90, 0x8b, 0x00,
+0x2b, 0x90, 0x01, 0x68, 0x04, 0x90, 0x4d, 0x68, 0x00, 0x03, 0x7d, 0x7d,
+0x68, 0x00, 0x4f, 0x7d, 0x00, 0x04, 0xd9, 0x8e, 0x00, 0x0d, 0x28, 0x00,
+0x00, 0x00, 0x9d, 0x00, 0xff, 0x0d, 0x18, 0x0d, 0x2c, 0x00, 0x00, 0x00,
+0x95, 0x00, 0x01, 0x0d, 0x03, 0x03, 0x00, 0x03, 0x11, 0x11, 0x0d, 0x00,
+0xff, 0x00, 0x1a, 0x00, 0x01, 0x0d, 0x2a, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x01
+};
+

diff --git a/include/tee/optee.h b/include/tee/optee.h
index 9ab0d08634f2b9b9cc6c30953aa5f2217be10c35..4b9e94c1754430a412d7ca0aeb8140256c85f79c 100644 (file)
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -10,6 +10,8 @@
 #ifndef        _OPTEE_H
 #define _OPTEE_H
 
+#include <linux/errno.h>
+
 #define OPTEE_MAGIC             0x4554504f
 #define OPTEE_VERSION           1
 #define OPTEE_ARCH_ARM32        0
@@ -27,4 +29,43 @@ struct optee_header {
        uint32_t paged_size;
 };
 
+static inline uint32_t optee_image_get_entry_point(const image_header_t *hdr)
+{
+       struct optee_header *optee_hdr = (struct optee_header *)(hdr + 1);
+
+       return optee_hdr->init_load_addr_lo;
+}
+
+static inline uint32_t optee_image_get_load_addr(const image_header_t *hdr)
+{
+       return optee_image_get_entry_point(hdr) - sizeof(struct optee_header);
+}
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+                      unsigned long tzdram_len, unsigned long image_len);
+#else
+static inline int optee_verify_image(struct optee_header *hdr,
+                                    unsigned long tzdram_start,
+                                    unsigned long tzdram_len,
+                                    unsigned long image_len)
+{
+       return -EPERM;
+}
+
+#endif
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_bootm_image(unsigned long image_addr,
+                            unsigned long image_load_addr,
+                            unsigned long image_len);
+#else
+static inline int optee_verify_bootm_image(unsigned long image_addr,
+                                          unsigned long image_load_addr,
+                                          unsigned long image_len)
+{
+       return -EPERM;
+}
+#endif
+
 #endif /* _OPTEE_H */

diff --git a/lib/Kconfig b/lib/Kconfig
index ab581f172f5922cbcbd3ba153c9e3ccef0991a18..436b90fa85cb8c9304b6c9439a5e22856f29c9e2 100644 (file)
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -309,5 +309,6 @@ endmenu
 
 source lib/efi/Kconfig
 source lib/efi_loader/Kconfig
+source lib/optee/Kconfig
 
 endmenu

diff --git a/lib/Makefile b/lib/Makefile
index 0db41c19f379f1209a5eaf622d8f1867e5655e5b..35da5705a4b3be8729973beb7d84b9d8033b2896 100644 (file)
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FIT) += libfdt/
 obj-$(CONFIG_OF_LIVE) += of_live.o
 obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
 obj-$(CONFIG_ARCH_AT91) += at91/
+obj-$(CONFIG_OPTEE) += optee/
 
 obj-$(CONFIG_AES) += aes.o
 obj-y += charset.o

diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c
index 2e8d409d31af1ea99f90932dfe6c292a13ef7ce0..205aa1994726d24e8119ce323c07975190df225f 100644 (file)
--- a/lib/efi/efi_stub.c
+++ b/lib/efi/efi_stub.c
@@ -182,7 +182,7 @@ static int get_codeseg32(void)
                                << 16;
                base <<= 12;    /* 4KB granularity */
                limit <<= 12;
-               if ((desc & GDT_PRESENT) && (desc && GDT_NOTSYS) &&
+               if ((desc & GDT_PRESENT) && (desc & GDT_NOTSYS) &&
                    !(desc & GDT_LONG) && (desc & GDT_4KB) &&
                    (desc & GDT_32BIT) && (desc & GDT_CODE) &&
                    CONFIG_SYS_TEXT_BASE > base &&

diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c
index 70914a4e9b6039e9b0fc308cbbd8232379b8bf5b..054c4b302f44a5facfeb51e6b2065051bdd07e38 100644 (file)
--- a/lib/libfdt/fdt_region.c
+++ b/lib/libfdt/fdt_region.c
@@ -14,8 +14,6 @@
 #include "fdt_host.h"
 #endif
 
-#include "libfdt_internal.h"
-
 #define FDT_MAX_DEPTH  32
 
 static int str_in_list(const char *str, char * const list[], int count)

diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
new file mode 100644 (file)
index 0000000..1e5ab45
--- /dev/null
+++ b/lib/optee/Kconfig
@@ -0,0 +1,39 @@
+config OPTEE
+       bool "Support OPTEE images"
+       help
+         U-Boot can be configured to boot OPTEE images.
+         Selecting this option will enable shared OPTEE library code and
+          enable an OPTEE specific bootm command that will perform additional
+          OPTEE specific checks before booting an OPTEE image created with
+          mkimage.
+
+config OPTEE_LOAD_ADDR
+       hex "OPTEE load address"
+       default 0x00000000
+       help
+         The load address of the bootable OPTEE binary.
+
+config OPTEE_TZDRAM_SIZE
+       hex "Amount of Trust-Zone RAM for the OPTEE image"
+       depends on OPTEE
+       default 0x3000000
+       help
+         The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
+         runtime.
+
+config OPTEE_TZDRAM_BASE
+       hex "Base address of Trust-Zone RAM for the OPTEE image"
+       depends on OPTEE
+       default 0x9d000000
+       help
+         The base address of pre-allocated Trust Zone DRAM for
+         the OPTEE runtime.
+
+config BOOTM_OPTEE
+       bool "Support OPTEE bootm command"
+       select BOOTM_LINUX
+       default n
+       help
+         Select this command to enable chain-loading of a Linux kernel
+         via an OPTEE firmware.
+         The bootflow is BootROM -> u-boot -> OPTEE -> Linux in this case.

diff --git a/lib/optee/Makefile b/lib/optee/Makefile
new file mode 100644 (file)
index 0000000..03e832f
--- /dev/null
+++ b/lib/optee/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Linaro
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-$(CONFIG_OPTEE) += optee.o

diff --git a/lib/optee/optee.c b/lib/optee/optee.c
new file mode 100644 (file)
index 0000000..78a15e8
--- /dev/null
+++ b/lib/optee/optee.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2017 Linaro
+ * Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <tee/optee.h>
+
+#define optee_hdr_err_msg \
+       "OPTEE verification error:" \
+       "\n\thdr=%p image=0x%08lx magic=0x%08x tzdram 0x%08lx-0x%08lx " \
+       "\n\theader lo=0x%08x hi=0x%08x size=0x%08lx arch=0x%08x" \
+       "\n\tuimage params 0x%08lx-0x%08lx\n"
+
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+                      unsigned long tzdram_len, unsigned long image_len)
+{
+       unsigned long tzdram_end = tzdram_start + tzdram_len;
+       uint32_t tee_file_size;
+
+       tee_file_size = hdr->init_size + hdr->paged_size +
+                       sizeof(struct optee_header);
+
+       if (hdr->magic != OPTEE_MAGIC ||
+           hdr->version != OPTEE_VERSION ||
+           hdr->init_load_addr_hi > tzdram_end ||
+           hdr->init_load_addr_lo < tzdram_start ||
+           tee_file_size > tzdram_len ||
+           tee_file_size != image_len ||
+           (hdr->init_load_addr_lo + tee_file_size) > tzdram_end) {
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+int optee_verify_bootm_image(unsigned long image_addr,
+                            unsigned long image_load_addr,
+                            unsigned long image_len)
+{
+       struct optee_header *hdr = (struct optee_header *)image_addr;
+       unsigned long tzdram_start = CONFIG_OPTEE_TZDRAM_BASE;
+       unsigned long tzdram_len = CONFIG_OPTEE_TZDRAM_SIZE;
+
+       int ret;
+
+       ret = optee_verify_image(hdr, tzdram_start, tzdram_len, image_len);
+       if (ret)
+               goto error;
+
+       if (image_load_addr + sizeof(*hdr) != hdr->init_load_addr_lo) {
+               ret = -EINVAL;
+               goto error;
+       }
+
+       return ret;
+error:
+       printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic, tzdram_start,
+              tzdram_start + tzdram_len, hdr->init_load_addr_lo,
+              hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr,
+              image_load_addr + image_len);
+
+       return ret;
+}

diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index d30b04ba862a8b90d370b97116a7683c1d752f36..240b5965345543ff679ae925a2401f9c254b6e8b 100644 (file)
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -336,7 +336,7 @@ int eth_send(void *packet, int length)
        if (!current)
                return -ENODEV;
 
-       if (!device_active(current))
+       if (!eth_is_active(current))
                return -EINVAL;
 
        ret = eth_get_ops(current)->send(current, packet, length);
@@ -359,7 +359,7 @@ int eth_rx(void)
        if (!current)
                return -ENODEV;
 
-       if (!device_active(current))
+       if (!eth_is_active(current))
                return -EINVAL;
 
        /* Process up to 32 packets at one time */

diff --git a/net/net.c b/net/net.c
index 4259c9e321d6905efef6ca5abe441e89943eab9f..8a9b69c6b0b098743609c6141040a1c1fb7a0850 100644 (file)
--- a/net/net.c
+++ b/net/net.c
@@ -683,7 +683,7 @@ int net_start_again(void)
                retry_forever = 0;
        }
 
-       if ((!retry_forever) && (net_try_count >= retrycnt)) {
+       if ((!retry_forever) && (net_try_count > retrycnt)) {
                eth_halt();
                net_set_state(NETLOOP_FAIL);
                /*

diff --git a/scripts/check-config.sh b/scripts/check-config.sh
index 267758498b3d435d1708e2ac4e10e85b69b2f067..4848ca6e25a59f6b6602166d6f3d329ec9b2b4d6 100755 (executable)
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
@@ -14,6 +14,9 @@
 # For example:
 #   scripts/check-config.sh b/chromebook_link/u-boot.cfg kconfig_whitelist.txt .
 
+set -e
+set -u
+
 path="$1"
 whitelist="$2"
 srctree="$3"

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b0958d7a802eee9186abb6aec18253fb2472b819..2c26d34ce4f000a8f6d56c615aaa901c84bdf82f 100644 (file)
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -741,10 +741,6 @@ CONFIG_FTPWM010_BASE
 CONFIG_FTRTC010_BASE
 CONFIG_FTRTC010_EXTCLK
 CONFIG_FTRTC010_PCLK
-CONFIG_FTSDC010_BASE
-CONFIG_FTSDC010_BASE_LIST
-CONFIG_FTSDC010_NUMBER
-CONFIG_FTSDC010_SDIO
 CONFIG_FTSDMC021
 CONFIG_FTSDMC021_BASE
 CONFIG_FTSMC020
@@ -1335,7 +1331,6 @@ CONFIG_MSHC_FREQ
 CONFIG_MTD_CONCAT
 CONFIG_MTD_DEVICE
 CONFIG_MTD_ECC_SOFT
-CONFIG_MTD_NAND_ECC_SMC
 CONFIG_MTD_NAND_MUSEUM_IDS
 CONFIG_MTD_NAND_VERIFY_WRITE
 CONFIG_MTD_ONENAND_VERIFY_WRITE
@@ -1416,7 +1411,6 @@ CONFIG_NAND_LPC32XX_MLC
 CONFIG_NAND_LPC32XX_SLC
 CONFIG_NAND_MODE_REG
 CONFIG_NAND_MXC_V1_1
-CONFIG_NAND_NDFC
 CONFIG_NAND_OMAP_ECCSCHEME
 CONFIG_NAND_OMAP_GPMC_WSCFG
 CONFIG_NAND_SECBOOT
@@ -4629,10 +4623,8 @@ CONFIG_T_SH7706LSR
 CONFIG_UART_BR_PRELIM
 CONFIG_UART_OR_PRELIM
 CONFIG_UBIBLOCK
-CONFIG_UBIFS_SILENCE_MSG
 CONFIG_UBIFS_VOLUME
 CONFIG_UBI_PART
-CONFIG_UBI_SILENCE_MSG
 CONFIG_UBI_SIZE
 CONFIG_UBOOT1_ENV_ADDR
 CONFIG_UBOOT2_ENV_ADDR

diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 920ccbf016dc291e93c2bf5ea2c1a4123d60381c..0d11bfdb2f97dd19fc021573a734c054a6c43b04 100644 (file)
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -419,3 +419,46 @@ static int dm_test_first_next_ok_device(struct unit_test_state *uts)
        return 0;
 }
 DM_TEST(dm_test_first_next_ok_device, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static const struct udevice_id fdt_dummy_ids[] = {
+       { .compatible = "denx,u-boot-fdt-dummy", },
+       { }
+};
+
+UCLASS_DRIVER(fdt_dummy) = {
+       .name           = "fdt_dummy",
+       .id             = UCLASS_TEST_DUMMY,
+       .flags          = DM_UC_FLAG_SEQ_ALIAS,
+};
+
+U_BOOT_DRIVER(fdt_dummy_drv) = {
+       .name   = "fdt_dummy_drv",
+       .of_match       = fdt_dummy_ids,
+       .id     = UCLASS_TEST_DUMMY,
+};
+
+static int dm_test_fdt_translation(struct unit_test_state *uts)
+{
+       struct udevice *dev;
+
+       /* Some simple translations */
+       ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
+       ut_asserteq_str("dev@0,0", dev->name);
+       ut_asserteq(0x8000, dev_read_addr(dev));
+
+       ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 1, true, &dev));
+       ut_asserteq_str("dev@1,100", dev->name);
+       ut_asserteq(0x9000, dev_read_addr(dev));
+
+       ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 2, true, &dev));
+       ut_asserteq_str("dev@2,200", dev->name);
+       ut_asserteq(0xA000, dev_read_addr(dev));
+
+       /* No translation for busses with #size-cells == 0 */
+       ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 3, true, &dev));
+       ut_asserteq_str("dev@42", dev->name);
+       ut_asserteq(0x42, dev_read_addr(dev));
+
+       return 0;
+}
+DM_TEST(dm_test_fdt_translation, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

diff --git a/test/py/README.md b/test/py/README.md
index eefac377567a813572ac6912cc7db467c4620601..aed2fd063a81025c3bbd659a1db925d65586aed6 100644 (file)
--- a/test/py/README.md
+++ b/test/py/README.md
@@ -150,7 +150,7 @@ processing.
   option takes a single argument which is used to filter test names. Simple
   logical operators are supported. For example:
   - `'ums'` runs only tests with "ums" in their name.
-  - ``ut_dm'` runs only tests with "ut_dm" in their name. Note that in this
+  - `'ut_dm'` runs only tests with "ut_dm" in their name. Note that in this
     case, "ut_dm" is a parameter to a test rather than the test name. The full
     test name is e.g. "test_ut[ut_dm_leak]".
   - `'not reset'` runs everything except tests with "reset" in their name.
@@ -320,7 +320,7 @@ If U-Boot has already been built:
 
 ```bash
 PATH=$HOME/ubtest/bin:$PATH \
-    PYTHONPATH=${HOME}/ubtest/py:${PYTHONPATH} \
+    PYTHONPATH=${HOME}/ubtest/py/${HOSTNAME}:${PYTHONPATH} \
     ./test/py/test.py --bd seaboard
 ```
 
@@ -331,7 +331,7 @@ follow:
 ```bash
 CROSS_COMPILE=arm-none-eabi- \
     PATH=$HOME/ubtest/bin:$PATH \
-    PYTHONPATH=${HOME}/ubtest/py:${PYTHONPATH} \
+    PYTHONPATH=${HOME}/ubtest/py/${HOSTNAME}:${PYTHONPATH} \
     ./test/py/test.py --bd seaboard --build
 ```
 

diff --git a/test/py/tests/test_sf.py b/test/py/tests/test_sf.py
new file mode 100644 (file)
index 0000000..95a7564
--- /dev/null
+++ b/test/py/tests/test_sf.py
@@ -0,0 +1,218 @@
+# Copyright (c) 2016, Xilinx Inc. Michal Simek
+# Copyright (c) 2017, Xiphos Systems Corp. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+import re
+import pytest
+import random
+import u_boot_utils
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+which SPI Flash areas are available for testing.  Without this, this test will
+be automatically skipped.
+For example:
+
+# A list of sections of Flash memory to be tested.
+env__sf_configs = (
+    {
+        # Where in SPI Flash should the test operate.
+        'offset': 0x00000000,
+        # This value is optional.
+        #   If present, specifies the [[bus:]cs] argument used in `sf probe`
+        #   If missing, defaults to 0.
+        'id': '0:1',
+        # This value is optional.
+        #   If set as a number, specifies the speed of the SPI Flash.
+        #   If set as an array of 2, specifies a range for a random speed.
+        #   If missing, defaults to 0.
+        'speed': 1000000,
+        # This value is optional.
+        #   If present, specifies the size to use for read/write operations.
+        #   If missing, the SPI Flash page size is used as a default (based on
+        #   the `sf probe` output).
+        'len': 0x10000,
+        # This value is optional.
+        #   If present, specifies if the test can write to Flash offset
+        #   If missing, defaults to False.
+        'writeable': False,
+        # This value is optional.
+        #   If present, specifies the expected CRC32 value of the flash area.
+        #   If missing, extra check is ignored.
+        'crc32': 0xCAFECAFE,
+    },
+)
+"""
+
+def sf_prepare(u_boot_console, env__sf_config):
+    """Check global state of the SPI Flash before running any test.
+
+   Args:
+        u_boot_console: A U-Boot console connection.
+        env__sf_config: The single SPI Flash device configuration on which to
+            run the tests.
+
+    Returns:
+        sf_params: a dictionary of SPI Flash parameters.
+    """
+
+    sf_params = {}
+    sf_params['ram_base'] = u_boot_utils.find_ram_base(u_boot_console)
+
+    probe_id = env__sf_config.get('id', 0)
+    speed = env__sf_config.get('speed', 0)
+    if isinstance(speed, int):
+        sf_params['speed'] = speed
+    else:
+        assert len(speed) == 2, "If speed is a list, it must have 2 entries"
+        sf_params['speed'] = random.randint(speed[0], speed[1])
+
+    cmd = 'sf probe %d %d' % (probe_id, sf_params['speed'])
+
+    output = u_boot_console.run_command(cmd)
+    assert 'SF: Detected' in output, 'No Flash device available'
+
+    m = re.search('page size (.+?) Bytes', output)
+    assert m, 'SPI Flash page size not recognized'
+    sf_params['page_size'] = int(m.group(1))
+
+    m = re.search('erase size (.+?) KiB', output)
+    assert m, 'SPI Flash erase size not recognized'
+    sf_params['erase_size'] = int(m.group(1))
+    sf_params['erase_size'] *= 1024
+
+    m = re.search('total (.+?) MiB', output)
+    assert m, 'SPI Flash total size not recognized'
+    sf_params['total_size'] = int(m.group(1))
+    sf_params['total_size'] *= 1024 * 1024
+
+    assert 'offset' in env__sf_config, \
+        '\'offset\' is required for this test.'
+    sf_params['len'] = env__sf_config.get('len', sf_params['erase_size'])
+
+    assert not env__sf_config['offset'] % sf_params['erase_size'], \
+        'offset not multiple of erase size.'
+    assert not sf_params['len'] % sf_params['erase_size'], \
+        'erase length not multiple of erase size.'
+
+    assert not (env__sf_config.get('writeable', False) and
+                'crc32' in env__sf_config), \
+        'Cannot check crc32 on writeable sections'
+
+    return sf_params
+
+def sf_read(u_boot_console, env__sf_config, sf_params):
+    """Helper function used to read and compute the CRC32 value of a section of
+    SPI Flash memory.
+
+    Args:
+        u_boot_console: A U-Boot console connection.
+        env__sf_config: The single SPI Flash device configuration on which to
+            run the tests.
+        sf_params: SPI Flash parameters.
+
+    Returns:
+        CRC32 value of SPI Flash section
+    """
+
+    addr = sf_params['ram_base']
+    offset = env__sf_config['offset']
+    count = sf_params['len']
+    pattern = random.randint(0, 0xFF)
+    crc_expected = env__sf_config.get('crc32', None)
+
+    cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
+    u_boot_console.run_command(cmd)
+    crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+    if crc_expected:
+        assert crc_pattern != crc_expected
+
+    cmd = 'sf read %08x %08x %x' % (addr, offset, count)
+    response = u_boot_console.run_command(cmd)
+    assert 'Read: OK' in response, 'Read operation failed'
+    crc_readback = u_boot_utils.crc32(u_boot_console, addr, count)
+    assert crc_pattern != crc_readback, 'sf read did not update RAM content.'
+    if crc_expected:
+        assert crc_readback == crc_expected
+
+    return crc_readback
+
+def sf_update(u_boot_console, env__sf_config, sf_params):
+    """Helper function used to update a section of SPI Flash memory.
+
+   Args:
+        u_boot_console: A U-Boot console connection.
+        env__sf_config: The single SPI Flash device configuration on which to
+           run the tests.
+
+    Returns:
+        CRC32 value of SPI Flash section
+    """
+
+    addr = sf_params['ram_base']
+    offset = env__sf_config['offset']
+    count = sf_params['len']
+    pattern = int(random.random() * 0xFF)
+
+    cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
+    u_boot_console.run_command(cmd)
+    crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+
+    cmd = 'sf update %08x %08x %x' % (addr, offset, count)
+    u_boot_console.run_command(cmd)
+    crc_readback = sf_read(u_boot_console, env__sf_config, sf_params)
+
+    assert crc_readback == crc_pattern
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_read(u_boot_console, env__sf_config):
+    sf_params = sf_prepare(u_boot_console, env__sf_config)
+    sf_read(u_boot_console, env__sf_config, sf_params)
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_read_twice(u_boot_console, env__sf_config):
+    sf_params = sf_prepare(u_boot_console, env__sf_config)
+
+    crc1 = sf_read(u_boot_console, env__sf_config, sf_params)
+    sf_params['ram_base'] += 0x100
+    crc2 = sf_read(u_boot_console, env__sf_config, sf_params)
+
+    assert crc1 == crc2, 'CRC32 of two successive read operation do not match'
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_erase(u_boot_console, env__sf_config):
+    if not env__sf_config.get('writeable', False):
+        pytest.skip('Flash config is tagged as not writeable')
+
+    sf_params = sf_prepare(u_boot_console, env__sf_config)
+    addr = sf_params['ram_base']
+    offset = env__sf_config['offset']
+    count = sf_params['len']
+
+    cmd = 'sf erase %08x %x' % (offset, count)
+    output = u_boot_console.run_command(cmd)
+    assert 'Erased: OK' in output, 'Erase operation failed'
+
+    cmd = 'mw.b %08x ff %x' % (addr, count)
+    u_boot_console.run_command(cmd)
+    crc_ffs = u_boot_utils.crc32(u_boot_console, addr, count)
+
+    crc_read = sf_read(u_boot_console, env__sf_config, sf_params)
+    assert crc_ffs == crc_read, 'Unexpected CRC32 after erase operation.'
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_crc32')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_sf_update(u_boot_console, env__sf_config):
+    if not env__sf_config.get('writeable', False):
+        pytest.skip('Flash config is tagged as not writeable')
+
+    sf_params = sf_prepare(u_boot_console, env__sf_config)
+    sf_update(u_boot_console, env__sf_config, sf_params)

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 9acb92ddc448c5241842e86eb4fb4b278c49f3c1..de9ee2643f51f1b9a10b840eba5e9e7de910cc96 100644 (file)
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -11,7 +11,7 @@ import os.path
 import pytest
 import sys
 import time
-import pytest
+import re
 
 def md5sum_data(data):
     """Calculate the MD5 hash of some data.
@@ -311,3 +311,25 @@ def persistent_file_helper(u_boot_log, filename):
     """
 
     return PersistentFileHelperCtxMgr(u_boot_log, filename)
+
+def crc32(u_boot_console, address, count):
+    """Helper function used to compute the CRC32 value of a section of RAM.
+
+    Args:
+        u_boot_console: A U-Boot console connection.
+        address: Address where data starts.
+        count: Amount of data to use for calculation.
+
+    Returns:
+        CRC32 value
+    """
+
+    bcfg = u_boot_console.config.buildconfig
+    has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
+    assert has_cmd_crc32, 'Cannot compute crc32 without CONFIG_CMD_CRC32.'
+    output = u_boot_console.run_command('crc32 %08x %x' % (address, count))
+
+    m = re.search('==> ([0-9a-fA-F]{8})$', output)
+    assert m, 'CRC32 operation failed.'
+
+    return m.group(1)

diff --git a/tools/Makefile b/tools/Makefile
index f38f68ee47dce4192b7ad39cd0a2cf99db93fadd..8143c25666018c056d187e0ea1f27b643e0eb434 100644 (file)
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -7,6 +7,7 @@
 
 # Enable all the config-independent tools
 ifneq ($(HOST_TOOLS_ALL),)
+CONFIG_KIRKWOOD = y
 CONFIG_LCD_LOGO = y
 CONFIG_CMD_LOADS = y
 CONFIG_CMD_NET = y
@@ -103,6 +104,7 @@ dumpimage-mkimage-objs := aisimage.o \
                        pblimage.o \
                        pbl_crc32.o \
                        vybridimage.o \
+                       stm32image.o \
                        $(ROCKCHIP_OBS) \
                        socfpgaimage.o \
                        lib/sha1.o \

diff --git a/tools/default_image.c b/tools/default_image.c
index 4e5568e06a496fc6b43e865aee7d4093ce111c77..c67f66b2552eadf6dd6692a029884aeb7682f823 100644 (file)
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -18,6 +18,7 @@
 #include "mkimage.h"
 
 #include <image.h>
+#include <tee/optee.h>
 #include <u-boot/crc.h>
 
 static image_header_t header;
@@ -90,6 +91,8 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd,
        uint32_t checksum;
        time_t time;
        uint32_t imagesize;
+       uint32_t ep;
+       uint32_t addr;
 
        image_header_t * hdr = (image_header_t *)ptr;
 
@@ -99,18 +102,26 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd,
                        sbuf->st_size - sizeof(image_header_t));
 
        time = imagetool_get_source_date(params, sbuf->st_mtime);
+       ep = params->ep;
+       addr = params->addr;
+
        if (params->type == IH_TYPE_FIRMWARE_IVT)
                /* Add size of CSF minus IVT */
                imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0;
        else
                imagesize = sbuf->st_size - sizeof(image_header_t);
 
+       if (params->os == IH_OS_TEE) {
+               addr = optee_image_get_load_addr(hdr);
+               ep = optee_image_get_entry_point(hdr);
+       }
+
        /* Build new header */
        image_set_magic(hdr, IH_MAGIC);
        image_set_time(hdr, time);
        image_set_size(hdr, imagesize);
-       image_set_load(hdr, params->addr);
-       image_set_ep(hdr, params->ep);
+       image_set_load(hdr, addr);
+       image_set_ep(hdr, ep);
        image_set_dcrc(hdr, checksum);
        image_set_os(hdr, params->os);
        image_set_arch(hdr, params->arch);

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 0e3e34321f6467b9889295aaf9b46b3bee158e57..77eac3d6c1736eabc97fe5eadb138fb2e08d90a4 100644 (file)
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -14,6 +14,7 @@
 #include <errno.h>
 #include <env_flags.h>
 #include <fcntl.h>
+#include <libgen.h>
 #include <linux/fs.h>
 #include <linux/stringify.h>
 #include <ctype.h>
@@ -64,14 +65,14 @@ struct envdev_s {
        int is_ubi;                     /* set if we use UBI volume */
 };
 
-static struct envdev_s envdevices[2] =
-{
+static struct envdev_s envdevices[2] = {
        {
                .mtd_type = MTD_ABSENT,
        }, {
                .mtd_type = MTD_ABSENT,
        },
 };
+
 static int dev_current;
 
 #define DEVNAME(i)    envdevices[(i)].devname
@@ -88,14 +89,14 @@ static unsigned long usable_envsize;
 #define ENV_SIZE      usable_envsize
 
 struct env_image_single {
-       uint32_t        crc;    /* CRC32 over data bytes    */
-       char            data[];
+       uint32_t crc;           /* CRC32 over data bytes    */
+       char data[];
 };
 
 struct env_image_redundant {
-       uint32_t        crc;    /* CRC32 over data bytes    */
-       unsigned char   flags;  /* active or obsolete */
-       char            data[];
+       uint32_t crc;           /* CRC32 over data bytes    */
+       unsigned char flags;    /* active or obsolete */
+       char data[];
 };
 
 enum flag_scheme {
@@ -105,18 +106,18 @@ enum flag_scheme {
 };
 
 struct environment {
-       void                    *image;
-       uint32_t                *crc;
-       unsigned char           *flags;
-       char                    *data;
-       enum flag_scheme        flag_scheme;
+       void *image;
+       uint32_t *crc;
+       unsigned char *flags;
+       char *data;
+       enum flag_scheme flag_scheme;
 };
 
 static struct environment environment = {
        .flag_scheme = FLAG_NONE,
 };
 
-static int HaveRedundEnv = 0;
+static int have_redund_env;
 
 static unsigned char active_flag = 1;
 /* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */
@@ -347,11 +348,11 @@ static int ubi_write(int fd, const void *buf, size_t count)
        return 0;
 }
 
-static int flash_io (int mode);
+static int flash_io(int mode);
 static int parse_config(struct env_opts *opts);
 
 #if defined(CONFIG_FILE)
-static int get_config (char *);
+static int get_config(char *);
 #endif
 
 static char *skip_chars(char *s)
@@ -394,7 +395,7 @@ static char *envmatch(char *s1, char *s2)
  * Search the environment for a variable.
  * Return the value, if found, or NULL, if not found.
  */
-char *fw_getenv (char *name)
+char *fw_getenv(char *name)
 {
        char *env, *nxt;
 
@@ -403,12 +404,12 @@ char *fw_getenv (char *name)
 
                for (nxt = env; *nxt; ++nxt) {
                        if (nxt >= &environment.data[ENV_SIZE]) {
-                               fprintf (stderr, "## Error: "
+                               fprintf(stderr, "## Error: "
                                        "environment not terminated\n");
                                return NULL;
                        }
                }
-               val = envmatch (name, env);
+               val = envmatch(name, env);
                if (!val)
                        continue;
                return val;
@@ -462,18 +463,18 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
        if (fw_env_open(opts))
                return -1;
 
-       if (argc == 0) {                /* Print all env variables  */
+       if (argc == 0) {        /* Print all env variables  */
                char *env, *nxt;
                for (env = environment.data; *env; env = nxt + 1) {
                        for (nxt = env; *nxt; ++nxt) {
                                if (nxt >= &environment.data[ENV_SIZE]) {
-                                       fprintf (stderr, "## Error: "
+                                       fprintf(stderr, "## Error: "
                                                "environment not terminated\n");
                                        return -1;
                                }
                        }
 
-                       printf ("%s\n", env);
+                       printf("%s\n", env);
                }
                fw_env_close(opts);
                return 0;
@@ -485,7 +486,7 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 
                val = fw_getenv(name);
                if (!val) {
-                       fprintf (stderr, "## Error: \"%s\" not defined\n", name);
+                       fprintf(stderr, "## Error: \"%s\" not defined\n", name);
                        rc = -1;
                        continue;
                }
@@ -515,15 +516,13 @@ int fw_env_flush(struct env_opts *opts)
 
        /* write environment back to flash */
        if (flash_io(O_RDWR)) {
-               fprintf(stderr,
-                       "Error: can't write fw_env to flash\n");
-                       return -1;
+               fprintf(stderr, "Error: can't write fw_env to flash\n");
+               return -1;
        }
 
        return 0;
 }
 
-
 /*
  * Set/Clear a single variable in the environment.
  * This is called in sequence to update the environment
@@ -548,7 +547,8 @@ int fw_env_write(char *name, char *value)
                                return -1;
                        }
                }
-               if ((oldval = envmatch (name, env)) != NULL)
+               oldval = envmatch(name, env);
+               if (oldval)
                        break;
        }
 
@@ -571,7 +571,7 @@ int fw_env_write(char *name, char *value)
                        errno = EROFS;
                        return -1;
                } else if (env_flags_validate_varaccess(name,
-                   ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR)) {
+                          ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR)) {
                        const char *defval = fw_getdefenv(name);
 
                        if (defval == NULL)
@@ -615,21 +615,21 @@ int fw_env_write(char *name, char *value)
        /*
         * Append new definition at the end
         */
-       for (env = environment.data; *env || *(env + 1); ++env);
+       for (env = environment.data; *env || *(env + 1); ++env)
+               ;
        if (env > environment.data)
                ++env;
        /*
         * Overflow when:
         * "name" + "=" + "val" +"\0\0"  > CUR_ENVSIZE - (env-environment)
         */
-       len = strlen (name) + 2;
+       len = strlen(name) + 2;
        /* add '=' for first arg, ' ' for all others */
        len += strlen(value) + 1;
 
        if (len > (&environment.data[ENV_SIZE] - env)) {
-               fprintf (stderr,
-                       "Error: environment overflow, \"%s\" deleted\n",
-                       name);
+               fprintf(stderr,
+                       "Error: environment overflow, \"%s\" deleted\n", name);
                return -1;
        }
 
@@ -759,7 +759,7 @@ int fw_parse_script(char *fname, struct env_opts *opts)
                fp = fopen(fname, "r");
                if (fp == NULL) {
                        fprintf(stderr, "I cannot open %s for reading\n",
-                                fname);
+                               fname);
                        return -1;
                }
        }
@@ -774,7 +774,7 @@ int fw_parse_script(char *fname, struct env_opts *opts)
                 */
                if (dump[len - 1] != '\n') {
                        fprintf(stderr,
-                       "Line %d not corrected terminated or too long\n",
+                               "Line %d not corrected terminated or too long\n",
                                lineno);
                        ret = -1;
                        break;
@@ -807,7 +807,6 @@ int fw_parse_script(char *fname, struct env_opts *opts)
                        else
                                val = NULL;
                }
-
 #ifdef DEBUG
                fprintf(stderr, "Setting %s : %s\n",
                        name, val ? val : " removed");
@@ -824,7 +823,7 @@ int fw_parse_script(char *fname, struct env_opts *opts)
                 */
                if (fw_env_write(name, val)) {
                        fprintf(stderr,
-                       "fw_env_write returns with error : %s\n",
+                               "fw_env_write returns with error : %s\n",
                                strerror(errno));
                        ret = -1;
                        break;
@@ -867,13 +866,13 @@ static int flash_bad_block(int fd, uint8_t mtd_type, loff_t blockstart)
                int badblock = ioctl(fd, MEMGETBADBLOCK, &blockstart);
 
                if (badblock < 0) {
-                       perror ("Cannot read bad block mark");
+                       perror("Cannot read bad block mark");
                        return badblock;
                }
 
                if (badblock) {
 #ifdef DEBUG
-                       fprintf (stderr, "Bad block at 0x%llx, skipping\n",
+                       fprintf(stderr, "Bad block at 0x%llx, skipping\n",
                                (unsigned long long)blockstart);
 #endif
                        return badblock;
@@ -888,8 +887,8 @@ static int flash_bad_block(int fd, uint8_t mtd_type, loff_t blockstart)
  * bad blocks but makes sure it stays within ENVSECTORS (dev) starting from
  * the DEVOFFSET (dev) block. On NOR the loop is only run once.
  */
-static int flash_read_buf (int dev, int fd, void *buf, size_t count,
-                          off_t offset)
+static int flash_read_buf(int dev, int fd, void *buf, size_t count,
+                         off_t offset)
 {
        size_t blocklen;        /* erase / write length - one block on NAND,
                                   0 on NOR */
@@ -901,7 +900,7 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count,
                                   MEMGETBADBLOCK needs 64 bits */
        int rc;
 
-       blockstart = (offset / DEVESIZE (dev)) * DEVESIZE (dev);
+       blockstart = (offset / DEVESIZE(dev)) * DEVESIZE(dev);
 
        /* Offset inside a block */
        block_seek = offset - blockstart;
@@ -911,7 +910,7 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count,
                 * NAND: calculate which blocks we are reading. We have
                 * to read one block at a time to skip bad blocks.
                 */
-               blocklen = DEVESIZE (dev);
+               blocklen = DEVESIZE(dev);
 
                /* Limit to one block for the first read */
                if (readlen > blocklen - block_seek)
@@ -923,17 +922,16 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count,
        /* This only runs once on NOR flash */
        while (processed < count) {
                rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
-               if (rc < 0)             /* block test failed */
+               if (rc < 0)     /* block test failed */
                        return -1;
 
                if (blockstart + block_seek + readlen > environment_end(dev)) {
                        /* End of range is reached */
-                       fprintf (stderr,
-                                "Too few good blocks within range\n");
+                       fprintf(stderr, "Too few good blocks within range\n");
                        return -1;
                }
 
-               if (rc) {               /* block is bad */
+               if (rc) {       /* block is bad */
                        blockstart += blocklen;
                        continue;
                }
@@ -942,21 +940,21 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count,
                 * If a block is bad, we retry in the next block at the same
                 * offset - see env/nand.c::writeenv()
                 */
-               lseek (fd, blockstart + block_seek, SEEK_SET);
+               lseek(fd, blockstart + block_seek, SEEK_SET);
 
-               rc = read (fd, buf + processed, readlen);
+               rc = read(fd, buf + processed, readlen);
                if (rc != readlen) {
-                       fprintf (stderr, "Read error on %s: %s\n",
-                                DEVNAME (dev), strerror (errno));
+                       fprintf(stderr, "Read error on %s: %s\n",
+                               DEVNAME(dev), strerror(errno));
                        return -1;
                }
 #ifdef DEBUG
                fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
-                       rc, (unsigned long long) blockstart + block_seek,
+                       rc, (unsigned long long)blockstart + block_seek,
                        DEVNAME(dev));
 #endif
                processed += readlen;
-               readlen = min (blocklen, count - processed);
+               readlen = min(blocklen, count - processed);
                block_seek = 0;
                blockstart += blocklen;
        }
@@ -1018,7 +1016,7 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count)
                 * to the end of the block
                 */
                write_total = ((block_seek + count + blocklen - 1) /
-                                                       blocklen) * blocklen;
+                              blocklen) * blocklen;
        }
 
        /*
@@ -1027,11 +1025,11 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count)
         * block back again.
         */
        if (write_total > count) {
-               data = malloc (erase_len);
+               data = malloc(erase_len);
                if (!data) {
-                       fprintf (stderr,
-                                "Cannot malloc %zu bytes: %s\n",
-                                erase_len, strerror (errno));
+                       fprintf(stderr,
+                               "Cannot malloc %zu bytes: %s\n",
+                               erase_len, strerror(errno));
                        return -1;
                }
 
@@ -1047,13 +1045,13 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count)
                        if (block_seek != 0)
                                fprintf(stderr, " and ");
                        fprintf(stderr, "0x%lx - 0x%lx",
-                               (unsigned long) block_seek + count,
-                               (unsigned long) write_total - 1);
+                               (unsigned long)block_seek + count,
+                               (unsigned long)write_total - 1);
                }
                fprintf(stderr, "\n");
 #endif
                /* Overwrite the old environment */
-               memcpy (data + block_seek, buf, count);
+               memcpy(data + block_seek, buf, count);
        } else {
                /*
                 * We get here, iff offset is block-aligned and count is a
@@ -1077,15 +1075,15 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count)
        /* This only runs once on NOR flash and SPI-dataflash */
        while (processed < write_total) {
                rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
-               if (rc < 0)             /* block test failed */
+               if (rc < 0)     /* block test failed */
                        return rc;
 
                if (blockstart + erasesize > environment_end(dev)) {
-                       fprintf (stderr, "End of range reached, aborting\n");
+                       fprintf(stderr, "End of range reached, aborting\n");
                        return -1;
                }
 
-               if (rc) {               /* block is bad */
+               if (rc) {       /* block is bad */
                        blockstart += blocklen;
                        continue;
                }
@@ -1103,34 +1101,33 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count)
                                }
                }
 
-               if (lseek (fd, blockstart, SEEK_SET) == -1) {
-                       fprintf (stderr,
-                                "Seek error on %s: %s\n",
-                                DEVNAME (dev), strerror (errno));
+               if (lseek(fd, blockstart, SEEK_SET) == -1) {
+                       fprintf(stderr,
+                               "Seek error on %s: %s\n",
+                               DEVNAME(dev), strerror(errno));
                        return -1;
                }
-
 #ifdef DEBUG
                fprintf(stderr, "Write 0x%llx bytes at 0x%llx\n",
-                       (unsigned long long) erasesize,
-                       (unsigned long long) blockstart);
+                       (unsigned long long)erasesize,
+                       (unsigned long long)blockstart);
 #endif
-               if (write (fd, data + processed, erasesize) != erasesize) {
-                       fprintf (stderr, "Write error on %s: %s\n",
-                                DEVNAME (dev), strerror (errno));
+               if (write(fd, data + processed, erasesize) != erasesize) {
+                       fprintf(stderr, "Write error on %s: %s\n",
+                               DEVNAME(dev), strerror(errno));
                        return -1;
                }
 
                if (DEVTYPE(dev) != MTD_ABSENT)
                        ioctl(fd, MEMLOCK, &erase);
 
-               processed  += erasesize;
+               processed += erasesize;
                block_seek = 0;
                blockstart += erasesize;
        }
 
        if (write_total > count)
-               free (data);
+               free(data);
 
        return processed;
 }
@@ -1138,30 +1135,30 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count)
 /*
  * Set obsolete flag at offset - NOR flash only
  */
-static int flash_flag_obsolete (int dev, int fd, off_t offset)
+static int flash_flag_obsolete(int dev, int fd, off_t offset)
 {
        int rc;
        struct erase_info_user erase;
 
-       erase.start  = DEVOFFSET (dev);
-       erase.length = DEVESIZE (dev);
+       erase.start = DEVOFFSET(dev);
+       erase.length = DEVESIZE(dev);
        /* This relies on the fact, that obsolete_flag == 0 */
-       rc = lseek (fd, offset, SEEK_SET);
+       rc = lseek(fd, offset, SEEK_SET);
        if (rc < 0) {
-               fprintf (stderr, "Cannot seek to set the flag on %s \n",
-                        DEVNAME (dev));
+               fprintf(stderr, "Cannot seek to set the flag on %s\n",
+                       DEVNAME(dev));
                return rc;
        }
-       ioctl (fd, MEMUNLOCK, &erase);
-       rc = write (fd, &obsolete_flag, sizeof (obsolete_flag));
-       ioctl (fd, MEMLOCK, &erase);
+       ioctl(fd, MEMUNLOCK, &erase);
+       rc = write(fd, &obsolete_flag, sizeof(obsolete_flag));
+       ioctl(fd, MEMLOCK, &erase);
        if (rc < 0)
-               perror ("Could not set obsolete flag");
+               perror("Could not set obsolete flag");
 
        return rc;
 }
 
-static int flash_write (int fd_current, int fd_target, int dev_target)
+static int flash_write(int fd_current, int fd_target, int dev_target)
 {
        int rc;
 
@@ -1175,14 +1172,14 @@ static int flash_write (int fd_current, int fd_target, int dev_target)
                *environment.flags = active_flag;
                break;
        default:
-               fprintf (stderr, "Unimplemented flash scheme %u \n",
-                        environment.flag_scheme);
+               fprintf(stderr, "Unimplemented flash scheme %u\n",
+                       environment.flag_scheme);
                return -1;
        }
 
 #ifdef DEBUG
        fprintf(stderr, "Writing new environment at 0x%llx on %s\n",
-               DEVOFFSET (dev_target), DEVNAME (dev_target));
+               DEVOFFSET(dev_target), DEVNAME(dev_target));
 #endif
 
        if (IS_UBI(dev_target)) {
@@ -1198,20 +1195,20 @@ static int flash_write (int fd_current, int fd_target, int dev_target)
 
        if (environment.flag_scheme == FLAG_BOOLEAN) {
                /* Have to set obsolete flag */
-               off_t offset = DEVOFFSET (dev_current) +
-                       offsetof (struct env_image_redundant, flags);
+               off_t offset = DEVOFFSET(dev_current) +
+                   offsetof(struct env_image_redundant, flags);
 #ifdef DEBUG
                fprintf(stderr,
                        "Setting obsolete flag in environment at 0x%llx on %s\n",
-                       DEVOFFSET (dev_current), DEVNAME (dev_current));
+                       DEVOFFSET(dev_current), DEVNAME(dev_current));
 #endif
-               flash_flag_obsolete (dev_current, fd_current, offset);
+               flash_flag_obsolete(dev_current, fd_current, offset);
        }
 
        return 0;
 }
 
-static int flash_read (int fd)
+static int flash_read(int fd)
 {
        int rc;
 
@@ -1229,72 +1226,153 @@ static int flash_read (int fd)
        return 0;
 }
 
-static int flash_io (int mode)
+static int flash_open_tempfile(const char **dname, const char **target_temp)
 {
-       int fd_current, fd_target, rc, dev_target;
+       char *dup_name = strdup(DEVNAME(dev_current));
+       char *temp_name = NULL;
+       int rc = -1;
 
-       /* dev_current: fd_current, erase_current */
-       fd_current = open (DEVNAME (dev_current), mode);
-       if (fd_current < 0) {
-               fprintf (stderr,
-                        "Can't open %s: %s\n",
-                        DEVNAME (dev_current), strerror (errno));
+       if (!dup_name)
                return -1;
+
+       *dname = dirname(dup_name);
+       if (!*dname)
+               goto err;
+
+       rc = asprintf(&temp_name, "%s/XXXXXX", *dname);
+       if (rc == -1)
+               goto err;
+
+       rc = mkstemp(temp_name);
+       if (rc == -1) {
+               /* fall back to in place write */
+               fprintf(stderr,
+                       "Can't create %s: %s\n", temp_name, strerror(errno));
+               free(temp_name);
+       } else {
+               *target_temp = temp_name;
+               /* deliberately leak dup_name as dname /might/ point into
+                * it and we need it for our caller
+                */
+               dup_name = NULL;
        }
 
-       if (mode == O_RDWR) {
-               if (HaveRedundEnv) {
-                       /* switch to next partition for writing */
-                       dev_target = !dev_current;
-                       /* dev_target: fd_target, erase_target */
-                       fd_target = open (DEVNAME (dev_target), mode);
-                       if (fd_target < 0) {
-                               fprintf (stderr,
-                                        "Can't open %s: %s\n",
-                                        DEVNAME (dev_target),
-                                        strerror (errno));
-                               rc = -1;
-                               goto exit;
-                       }
-               } else {
-                       dev_target = dev_current;
-                       fd_target = fd_current;
+err:
+       if (dup_name)
+               free(dup_name);
+
+       return rc;
+}
+
+static int flash_io_write(int fd_current)
+{
+       int fd_target = -1, rc, dev_target;
+       const char *dname, *target_temp = NULL;
+
+       if (have_redund_env) {
+               /* switch to next partition for writing */
+               dev_target = !dev_current;
+               /* dev_target: fd_target, erase_target */
+               fd_target = open(DEVNAME(dev_target), O_RDWR);
+               if (fd_target < 0) {
+                       fprintf(stderr,
+                               "Can't open %s: %s\n",
+                               DEVNAME(dev_target), strerror(errno));
+                       rc = -1;
+                       goto exit;
                }
+       } else {
+               struct stat sb;
 
-               rc = flash_write (fd_current, fd_target, dev_target);
+               if (fstat(fd_current, &sb) == 0 && S_ISREG(sb.st_mode)) {
+                       /* if any part of flash_open_tempfile() fails we fall
+                        * back to in-place writes
+                        */
+                       fd_target = flash_open_tempfile(&dname, &target_temp);
+               }
+               dev_target = dev_current;
+               if (fd_target == -1)
+                       fd_target = fd_current;
+       }
+
+       rc = flash_write(fd_current, fd_target, dev_target);
 
-               if (fsync(fd_current) &&
+       if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) {
+               fprintf(stderr,
+                       "fsync failed on %s: %s\n",
+                       DEVNAME(dev_current), strerror(errno));
+       }
+
+       if (fd_current != fd_target) {
+               if (fsync(fd_target) &&
                    !(errno == EINVAL || errno == EROFS)) {
-                       fprintf (stderr,
-                                "fsync failed on %s: %s\n",
-                                DEVNAME (dev_current), strerror (errno));
+                       fprintf(stderr,
+                               "fsync failed on %s: %s\n",
+                               DEVNAME(dev_current), strerror(errno));
                }
 
-               if (HaveRedundEnv) {
-                       if (fsync(fd_target) &&
-                           !(errno == EINVAL || errno == EROFS)) {
-                               fprintf (stderr,
-                                        "fsync failed on %s: %s\n",
-                                        DEVNAME (dev_current), strerror (errno));
-                       }
+               if (close(fd_target)) {
+                       fprintf(stderr,
+                               "I/O error on %s: %s\n",
+                               DEVNAME(dev_target), strerror(errno));
+                       rc = -1;
+               }
 
-                       if (close (fd_target)) {
-                               fprintf (stderr,
-                                       "I/O error on %s: %s\n",
-                                       DEVNAME (dev_target),
-                                       strerror (errno));
+               if (target_temp) {
+                       int dir_fd;
+
+                       dir_fd = open(dname, O_DIRECTORY | O_RDONLY);
+                       if (dir_fd == -1)
+                               fprintf(stderr,
+                                       "Can't open %s: %s\n",
+                                       dname, strerror(errno));
+
+                       if (rename(target_temp, DEVNAME(dev_target))) {
+                               fprintf(stderr,
+                                       "rename failed %s => %s: %s\n",
+                                       target_temp, DEVNAME(dev_target),
+                                       strerror(errno));
                                rc = -1;
                        }
+
+                       if (dir_fd != -1 && fsync(dir_fd))
+                               fprintf(stderr,
+                                       "fsync failed on %s: %s\n",
+                                       dname, strerror(errno));
+
+                       if (dir_fd != -1 && close(dir_fd))
+                               fprintf(stderr,
+                                       "I/O error on %s: %s\n",
+                                       dname, strerror(errno));
                }
+       }
+ exit:
+       return rc;
+}
+
+static int flash_io(int mode)
+{
+       int fd_current, rc;
+
+       /* dev_current: fd_current, erase_current */
+       fd_current = open(DEVNAME(dev_current), mode);
+       if (fd_current < 0) {
+               fprintf(stderr,
+                       "Can't open %s: %s\n",
+                       DEVNAME(dev_current), strerror(errno));
+               return -1;
+       }
+
+       if (mode == O_RDWR) {
+               rc = flash_io_write(fd_current);
        } else {
-               rc = flash_read (fd_current);
+               rc = flash_read(fd_current);
        }
 
-exit:
-       if (close (fd_current)) {
-               fprintf (stderr,
-                        "I/O error on %s: %s\n",
-                        DEVNAME (dev_current), strerror (errno));
+       if (close(fd_current)) {
+               fprintf(stderr,
+                       "I/O error on %s: %s\n",
+                       DEVNAME(dev_current), strerror(errno));
                return -1;
        }
 
@@ -1322,7 +1400,7 @@ int fw_env_open(struct env_opts *opts)
        if (!opts)
                opts = &default_opts;
 
-       if (parse_config(opts))         /* should fill envdevices */
+       if (parse_config(opts)) /* should fill envdevices */
                return -EINVAL;
 
        addr0 = calloc(1, CUR_ENVSIZE);
@@ -1337,16 +1415,16 @@ int fw_env_open(struct env_opts *opts)
        /* read environment from FLASH to local buffer */
        environment.image = addr0;
 
-       if (HaveRedundEnv) {
+       if (have_redund_env) {
                redundant = addr0;
-               environment.crc         = &redundant->crc;
-               environment.flags       = &redundant->flags;
-               environment.data        = redundant->data;
+               environment.crc = &redundant->crc;
+               environment.flags = &redundant->flags;
+               environment.data = redundant->data;
        } else {
                single = addr0;
-               environment.crc         = &single->crc;
-               environment.flags       = NULL;
-               environment.data        = single->data;
+               environment.crc = &single->crc;
+               environment.flags = NULL;
+               environment.data = single->data;
        }
 
        dev_current = 0;
@@ -1355,14 +1433,15 @@ int fw_env_open(struct env_opts *opts)
                goto open_cleanup;
        }
 
-       crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
+       crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE);
 
        crc0_ok = (crc0 == *environment.crc);
-       if (!HaveRedundEnv) {
+       if (!have_redund_env) {
                if (!crc0_ok) {
-                       fprintf (stderr,
+                       fprintf(stderr,
                                "Warning: Bad CRC, using default environment\n");
-                       memcpy(environment.data, default_environment, sizeof default_environment);
+                       memcpy(environment.data, default_environment,
+                              sizeof(default_environment));
                }
        } else {
                flag0 = *environment.flags;
@@ -1406,12 +1485,12 @@ int fw_env_open(struct env_opts *opts)
                           IS_UBI(dev_current) == IS_UBI(!dev_current)) {
                        environment.flag_scheme = FLAG_INCREMENTAL;
                } else {
-                       fprintf (stderr, "Incompatible flash types!\n");
+                       fprintf(stderr, "Incompatible flash types!\n");
                        ret = -EINVAL;
                        goto open_cleanup;
                }
 
-               crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
+               crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE);
 
                crc1_ok = (crc1 == redundant->crc);
                flag1 = redundant->flags;
@@ -1421,10 +1500,10 @@ int fw_env_open(struct env_opts *opts)
                } else if (!crc0_ok && crc1_ok) {
                        dev_current = 1;
                } else if (!crc0_ok && !crc1_ok) {
-                       fprintf (stderr,
+                       fprintf(stderr,
                                "Warning: Bad CRC, using default environment\n");
-                       memcpy (environment.data, default_environment,
-                               sizeof default_environment);
+                       memcpy(environment.data, default_environment,
+                              sizeof(default_environment));
                        dev_current = 0;
                } else {
                        switch (environment.flag_scheme) {
@@ -1451,12 +1530,12 @@ int fw_env_open(struct env_opts *opts)
                                else if ((flag1 == 255 && flag0 == 0) ||
                                         flag0 >= flag1)
                                        dev_current = 0;
-                               else /* flag1 > flag0 */
+                               else    /* flag1 > flag0 */
                                        dev_current = 1;
                                break;
                        default:
-                               fprintf (stderr, "Unknown flag scheme %u \n",
-                                        environment.flag_scheme);
+                               fprintf(stderr, "Unknown flag scheme %u\n",
+                                       environment.flag_scheme);
                                return -1;
                        }
                }
@@ -1467,15 +1546,15 @@ int fw_env_open(struct env_opts *opts)
                 * flags before writing out
                 */
                if (dev_current) {
-                       environment.image       = addr1;
-                       environment.crc         = &redundant->crc;
-                       environment.flags       = &redundant->flags;
-                       environment.data        = redundant->data;
-                       free (addr0);
+                       environment.image = addr1;
+                       environment.crc = &redundant->crc;
+                       environment.flags = &redundant->flags;
+                       environment.data = redundant->data;
+                       free(addr0);
                } else {
-                       environment.image       = addr0;
+                       environment.image = addr0;
                        /* Other pointers are already set */
-                       free (addr1);
+                       free(addr1);
                }
 #ifdef DEBUG
                fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current));
@@ -1483,7 +1562,7 @@ int fw_env_open(struct env_opts *opts)
        }
        return 0;
 
-open_cleanup:
+ open_cleanup:
        if (addr0)
                free(addr0);
 
@@ -1518,15 +1597,13 @@ static int check_device_config(int dev)
        fd = open(DEVNAME(dev), O_RDONLY);
        if (fd < 0) {
                fprintf(stderr,
-                       "Cannot open %s: %s\n",
-                       DEVNAME(dev), strerror(errno));
+                       "Cannot open %s: %s\n", DEVNAME(dev), strerror(errno));
                return -1;
        }
 
        rc = fstat(fd, &st);
        if (rc < 0) {
-               fprintf(stderr, "Cannot stat the file %s\n",
-                       DEVNAME(dev));
+               fprintf(stderr, "Cannot stat the file %s\n", DEVNAME(dev));
                goto err;
        }
 
@@ -1571,14 +1648,16 @@ static int check_device_config(int dev)
                if (DEVOFFSET(dev) < 0) {
                        rc = ioctl(fd, BLKGETSIZE64, &size);
                        if (rc < 0) {
-                               fprintf(stderr, "Could not get block device size on %s\n",
+                               fprintf(stderr,
+                                       "Could not get block device size on %s\n",
                                        DEVNAME(dev));
                                goto err;
                        }
 
                        DEVOFFSET(dev) = DEVOFFSET(dev) + size;
 #ifdef DEBUG
-                       fprintf(stderr, "Calculated device offset 0x%llx on %s\n",
+                       fprintf(stderr,
+                               "Calculated device offset 0x%llx on %s\n",
                                DEVOFFSET(dev), DEVNAME(dev));
 #endif
                }
@@ -1589,18 +1668,20 @@ static int check_device_config(int dev)
                ENVSECTORS(dev) = DIV_ROUND_UP(ENVSIZE(dev), DEVESIZE(dev));
 
        if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
-               fprintf(stderr, "Environment does not start on (erase) block boundary\n");
+               fprintf(stderr,
+                       "Environment does not start on (erase) block boundary\n");
                errno = EINVAL;
                return -1;
        }
 
        if (ENVSIZE(dev) > ENVSECTORS(dev) * DEVESIZE(dev)) {
-               fprintf(stderr, "Environment does not fit into available sectors\n");
+               fprintf(stderr,
+                       "Environment does not fit into available sectors\n");
                errno = EINVAL;
                return -1;
        }
 
-err:
+ err:
        close(fd);
        return rc;
 }
@@ -1620,42 +1701,42 @@ static int parse_config(struct env_opts *opts)
                return -1;
        }
 #else
-       DEVNAME (0) = DEVICE1_NAME;
-       DEVOFFSET (0) = DEVICE1_OFFSET;
-       ENVSIZE (0) = ENV1_SIZE;
+       DEVNAME(0) = DEVICE1_NAME;
+       DEVOFFSET(0) = DEVICE1_OFFSET;
+       ENVSIZE(0) = ENV1_SIZE;
 
        /* Set defaults for DEVESIZE, ENVSECTORS later once we
         * know DEVTYPE
         */
 #ifdef DEVICE1_ESIZE
-       DEVESIZE (0) = DEVICE1_ESIZE;
+       DEVESIZE(0) = DEVICE1_ESIZE;
 #endif
 #ifdef DEVICE1_ENVSECTORS
-       ENVSECTORS (0) = DEVICE1_ENVSECTORS;
+       ENVSECTORS(0) = DEVICE1_ENVSECTORS;
 #endif
 
 #ifdef HAVE_REDUND
-       DEVNAME (1) = DEVICE2_NAME;
-       DEVOFFSET (1) = DEVICE2_OFFSET;
-       ENVSIZE (1) = ENV2_SIZE;
+       DEVNAME(1) = DEVICE2_NAME;
+       DEVOFFSET(1) = DEVICE2_OFFSET;
+       ENVSIZE(1) = ENV2_SIZE;
 
        /* Set defaults for DEVESIZE, ENVSECTORS later once we
         * know DEVTYPE
         */
 #ifdef DEVICE2_ESIZE
-       DEVESIZE (1) = DEVICE2_ESIZE;
+       DEVESIZE(1) = DEVICE2_ESIZE;
 #endif
 #ifdef DEVICE2_ENVSECTORS
-       ENVSECTORS (1) = DEVICE2_ENVSECTORS;
+       ENVSECTORS(1) = DEVICE2_ENVSECTORS;
 #endif
-       HaveRedundEnv = 1;
+       have_redund_env = 1;
 #endif
 #endif
        rc = check_device_config(0);
        if (rc < 0)
                return rc;
 
-       if (HaveRedundEnv) {
+       if (have_redund_env) {
                rc = check_device_config(1);
                if (rc < 0)
                        return rc;
@@ -1668,14 +1749,14 @@ static int parse_config(struct env_opts *opts)
        }
 
        usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
-       if (HaveRedundEnv)
+       if (have_redund_env)
                usable_envsize -= sizeof(char);
 
        return 0;
 }
 
 #if defined(CONFIG_FILE)
-static int get_config (char *fname)
+static int get_config(char *fname)
 {
        FILE *fp;
        int i = 0;
@@ -1683,11 +1764,11 @@ static int get_config (char *fname)
        char dump[128];
        char *devname;
 
-       fp = fopen (fname, "r");
+       fp = fopen(fname, "r");
        if (fp == NULL)
                return -1;
 
-       while (i < 2 && fgets (dump, sizeof (dump), fp)) {
+       while (i < 2 && fgets(dump, sizeof(dump), fp)) {
                /* Skip incomplete conversions and comment strings */
                if (dump[0] == '#')
                        continue;
@@ -1695,9 +1776,7 @@ static int get_config (char *fname)
                rc = sscanf(dump, "%ms %lli %lx %lx %lx",
                            &devname,
                            &DEVOFFSET(i),
-                           &ENVSIZE(i),
-                           &DEVESIZE(i),
-                           &ENVSECTORS(i));
+                           &ENVSIZE(i), &DEVESIZE(i), &ENVSECTORS(i));
 
                if (rc < 3)
                        continue;
@@ -1710,10 +1789,10 @@ static int get_config (char *fname)
 
                i++;
        }
-       fclose (fp);
+       fclose(fp);
 
-       HaveRedundEnv = i - 1;
-       if (!i) {                       /* No valid entries found */
+       have_redund_env = i - 1;
+       if (!i) {               /* No valid entries found */
                errno = EINVAL;
                return -1;
        } else

diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 3ca3b3b4a62f40e60d6d93fa70b2578803fa7ce2..26686ad30f98b8d5e2a39cff820c4a41c559681f 100644 (file)
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1616,6 +1616,10 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
                                  struct image_tool_params *params)
 {
        uint8_t checksum;
+       size_t header_size = kwbimage_header_size(ptr);
+
+       if (header_size > image_size)
+               return -FDT_ERR_BADSTRUCTURE;
 
        if (!main_hdr_checksum_ok(ptr))
                return -FDT_ERR_BADSTRUCTURE;

diff --git a/tools/stm32image.c b/tools/stm32image.c
new file mode 100644 (file)
index 0000000..437e384
--- /dev/null
+++ b/tools/stm32image.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0+        BSD-3-Clause
+ */
+
+#include <image.h>
+#include "imagetool.h"
+
+/* magic ='S' 'T' 'M' 0x32 */
+#define HEADER_MAGIC be32_to_cpu(0x53544D32)
+#define VER_MAJOR_IDX  2
+#define VER_MINOR_IDX  1
+#define VER_VARIANT_IDX        0
+#define HEADER_VERSION_V1      0x1
+/* default option : bit0 => no signature */
+#define HEADER_DEFAULT_OPTION  (cpu_to_le32(0x00000001))
+
+struct stm32_header {
+       uint32_t magic_number;
+       uint32_t image_signature[64 / 4];
+       uint32_t image_checksum;
+       uint8_t  header_version[4];
+       uint32_t image_length;
+       uint32_t image_entry_point;
+       uint32_t reserved1;
+       uint32_t load_address;
+       uint32_t reserved2;
+       uint32_t version_number;
+       uint32_t option_flags;
+       uint32_t ecdsa_algorithm;
+       uint32_t ecdsa_public_key[64 / 4];
+       uint32_t padding[84 / 4];
+};
+
+static struct stm32_header stm32image_header;
+
+static void stm32image_default_header(struct stm32_header *ptr)
+{
+       if (!ptr)
+               return;
+
+       ptr->magic_number = HEADER_MAGIC;
+       ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
+       ptr->option_flags = HEADER_DEFAULT_OPTION;
+       ptr->ecdsa_algorithm = 1;
+}
+
+static uint32_t stm32image_checksum(void *start, uint32_t len)
+{
+       uint32_t csum = 0;
+       uint32_t hdr_len = sizeof(struct stm32_header);
+       uint8_t *p;
+
+       if (len < hdr_len)
+               return 0;
+
+       p = start + hdr_len;
+       len -= hdr_len;
+
+       while (len > 0) {
+               csum += *p;
+               p++;
+               len--;
+       }
+
+       return csum;
+}
+
+static int stm32image_check_image_types(uint8_t type)
+{
+       if (type == IH_TYPE_STM32IMAGE)
+               return EXIT_SUCCESS;
+       return EXIT_FAILURE;
+}
+
+static int stm32image_verify_header(unsigned char *ptr, int image_size,
+                                   struct image_tool_params *params)
+{
+       struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+       int i;
+
+       if (image_size < sizeof(struct stm32_header))
+               return -1;
+       if (stm32hdr->magic_number != HEADER_MAGIC)
+               return -1;
+       if (stm32hdr->header_version[VER_MAJOR_IDX] != HEADER_VERSION_V1)
+               return -1;
+       if (stm32hdr->reserved1 || stm32hdr->reserved2)
+               return -1;
+       for (i = 0; i < (sizeof(stm32hdr->padding) / 4); i++) {
+               if (stm32hdr->padding[i] != 0)
+                       return -1;
+       }
+
+       return 0;
+}
+
+static void stm32image_print_header(const void *ptr)
+{
+       struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+
+       printf("Image Type   : STMicroelectronics STM32 V%d.%d\n",
+              stm32hdr->header_version[VER_MAJOR_IDX],
+              stm32hdr->header_version[VER_MINOR_IDX]);
+       printf("Image Size   : %lu bytes\n",
+              (unsigned long)le32_to_cpu(stm32hdr->image_length));
+       printf("Image Load   : 0x%08x\n",
+              le32_to_cpu(stm32hdr->load_address));
+       printf("Entry Point  : 0x%08x\n",
+              le32_to_cpu(stm32hdr->image_entry_point));
+       printf("Checksum     : 0x%08x\n",
+              le32_to_cpu(stm32hdr->image_checksum));
+       printf("Option     : 0x%08x\n",
+              le32_to_cpu(stm32hdr->option_flags));
+}
+
+static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
+                                 struct image_tool_params *params)
+{
+       struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+
+       stm32image_default_header(stm32hdr);
+
+       stm32hdr->load_address = cpu_to_le32(params->addr);
+       stm32hdr->image_entry_point = cpu_to_le32(params->ep);
+       stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size -
+                                            sizeof(struct stm32_header));
+       stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
+}
+
+/*
+ * stm32image parameters
+ */
+U_BOOT_IMAGE_TYPE(
+       stm32image,
+       "STMicroelectronics STM32MP Image support",
+       sizeof(struct stm32_header),
+       (void *)&stm32image_header,
+       NULL,
+       stm32image_verify_header,
+       stm32image_print_header,
+       stm32image_set_header,
+       NULL,
+       stm32image_check_image_types,
+       NULL,
+       NULL
+);

diff --git a/tools/zynqimage.c b/tools/zynqimage.c
index 021d2d3fc91f0ae515b160b33a56a8872fd5dda2..aa003a7543b65d99fb0fdd8a81db34f5bc9eabb1 100644 (file)
--- a/tools/zynqimage.c
+++ b/tools/zynqimage.c
@@ -147,6 +147,12 @@ static int zynqimage_verify_header(unsigned char *ptr, int image_size,
        if (image_size < sizeof(struct zynq_header))
                return -1;
 
+       if (zynqhdr->__reserved1 != 0)
+               return -1;
+
+       if (zynqhdr->__reserved2 != 0)
+               return -1;
+
        if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
                return -1;
        if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)

diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
index f48ac6dbe5056de5b36a1c99695908bfdeeadb41..a61fb17c40d2adf5ef33f6a16674c49ee8a5463e 100644 (file)
--- a/tools/zynqmpimage.c
+++ b/tools/zynqmpimage.c
@@ -178,7 +178,7 @@ static void zynqmpimage_print_header(const void *ptr)
        struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
        int i;
 
-       printf("Image Type   : Xilinx Zynq Boot Image support\n");
+       printf("Image Type   : Xilinx ZynqMP Boot Image support\n");
        printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
        printf("Image Size   : %lu bytes (%lu bytes packed)\n",
               (unsigned long)le32_to_cpu(zynqhdr->image_size),