return (phys_addr_t)&secondary_boot_code;
 }
 
+void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+       u64 *table = get_spin_tbl_addr();
+       int i;
+
+       for (i = 1; i < CONFIG_MAX_CPUS; i++)
+               table[i * WORDS_PER_SPIN_TABLE_ENTRY +
+                       SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
+}
+
 #ifdef CONFIG_FSL_LSCH3
 void wake_secondary_core_n(int cluster, int core, int cluster_cores)
 {
 
 *      uint64_t entry_addr;
 *      uint64_t status;
 *      uint64_t lpid;
+*      uint64_t os_arch;
 * };
 * we pad this struct to 64 bytes so each entry is in its own cacheline
 * the actual spin table is an array of these structures
 #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
 #define SPIN_TABLE_ELEM_STATUS_IDX     1
 #define SPIN_TABLE_ELEM_LPID_IDX       2
+#define SPIN_TABLE_ELEM_OS_ARCH_IDX    3
 #define WORDS_PER_SPIN_TABLE_ENTRY     8       /* pad to 64 bytes */
 #define SPIN_TABLE_ELEM_SIZE           64
 
 
 #endif
 
 #ifdef CONFIG_ARM64
+__weak void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+}
+
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
 static void switch_to_el1(void)
 {
        if (!fake) {
                do_nonsec_virt_switch();
 
+               update_os_arch_secondary_cores(images->os.arch);
+
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
                armv8_switch_to_el2((u64)images->ft_addr, 0, 0,
                                    (u64)switch_to_el1, ES_TO_AARCH64);