]> git.sur5r.net Git - u-boot/commitdiff
arm: mx6: add support for Compulab cm-fx6 CoM
authorNikita Kiryanov <nikita@compulab.co.il>
Sun, 7 Sep 2014 15:59:29 +0000 (18:59 +0300)
committerStefano Babic <sbabic@denx.de>
Tue, 9 Sep 2014 13:35:43 +0000 (15:35 +0200)
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
arch/arm/Kconfig
board/compulab/cm_fx6/Kconfig [new file with mode: 0644]
board/compulab/cm_fx6/MAINTAINERS [new file with mode: 0644]
board/compulab/cm_fx6/Makefile [new file with mode: 0644]
board/compulab/cm_fx6/cm_fx6.c [new file with mode: 0644]
board/compulab/cm_fx6/common.c [new file with mode: 0644]
board/compulab/cm_fx6/common.h [new file with mode: 0644]
board/compulab/cm_fx6/imximage.cfg [new file with mode: 0644]
board/compulab/cm_fx6/spl.c [new file with mode: 0644]
configs/cm_fx6_defconfig [new file with mode: 0644]
include/configs/cm_fx6.h [new file with mode: 0644]

index 22f0f09af6e96cd7df49c10812d1363c4da7faee..f933123395e71832af236c562f46e56a377b46c0 100644 (file)
@@ -424,6 +424,9 @@ config OMAP54XX
 config RMOBILE
        bool "Renesas ARM SoCs"
 
+config TARGET_CM_FX6
+       bool "Support cm_fx6"
+
 config TARGET_S5P_GONI
        bool "Support s5p_goni"
 
@@ -579,6 +582,7 @@ source "board/cirrus/edb93xx/Kconfig"
 source "board/cm4008/Kconfig"
 source "board/cm41xx/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/creative/xfi3/Kconfig"
 source "board/davedenx/qong/Kconfig"
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
new file mode 100644 (file)
index 0000000..42a8438
--- /dev/null
@@ -0,0 +1,23 @@
+if TARGET_CM_FX6
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_BOARD
+       string
+       default "cm_fx6"
+
+config SYS_VENDOR
+       string
+       default "compulab"
+
+config SYS_SOC
+       string
+       default "mx6"
+
+config SYS_CONFIG_NAME
+       string
+       default "cm_fx6"
+
+endif
diff --git a/board/compulab/cm_fx6/MAINTAINERS b/board/compulab/cm_fx6/MAINTAINERS
new file mode 100644 (file)
index 0000000..5b2623a
--- /dev/null
@@ -0,0 +1,6 @@
+CM_FX6 BOARD
+M:     Nikita Kiryanov <nikita@compulab.co.il>
+S:     Maintained
+F:     board/compulab/cm_fx6/
+F:     include/configs/cm_fx6.h
+F:     configs/cm_fx6_defconfig
diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile
new file mode 100644 (file)
index 0000000..3e5c903
--- /dev/null
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y = common.o cm_fx6.o
+endif
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
new file mode 100644 (file)
index 0000000..b589581
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ * Board functions for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC1_BASE_ADDR},
+       {USDHC2_BASE_ADDR},
+       {USDHC3_BASE_ADDR},
+};
+
+static enum mxc_clock usdhc_clk[3] = {
+       MXC_ESDHC_CLK,
+       MXC_ESDHC2_CLK,
+       MXC_ESDHC3_CLK,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+       int i;
+
+       cm_fx6_set_usdhc_iomux();
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
+               usdhc_cfg[i].max_bus_width = 4;
+               fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               enable_usdhc_clk(1, i);
+       }
+
+       return 0;
+}
+#endif
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: CM-FX6\n");
+       return 0;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+       switch (gd->ram_size) {
+       case 0x10000000: /* DDR_16BIT_256MB */
+               gd->bd->bi_dram[0].size = 0x10000000;
+               gd->bd->bi_dram[1].size = 0;
+               break;
+       case 0x20000000: /* DDR_32BIT_512MB */
+               gd->bd->bi_dram[0].size = 0x20000000;
+               gd->bd->bi_dram[1].size = 0;
+               break;
+       case 0x40000000:
+               if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
+                       gd->bd->bi_dram[0].size = 0x20000000;
+                       gd->bd->bi_dram[1].size = 0x20000000;
+               } else { /* DDR_64BIT_1GB */
+                       gd->bd->bi_dram[0].size = 0x40000000;
+                       gd->bd->bi_dram[1].size = 0;
+               }
+               break;
+       case 0x80000000: /* DDR_64BIT_2GB */
+               gd->bd->bi_dram[0].size = 0x40000000;
+               gd->bd->bi_dram[1].size = 0x40000000;
+               break;
+       case 0xEFF00000: /* DDR_64BIT_4GB */
+               gd->bd->bi_dram[0].size = 0x70000000;
+               gd->bd->bi_dram[1].size = 0x7FF00000;
+               break;
+       }
+}
+
+int dram_init(void)
+{
+       gd->ram_size = imx_ddr_size();
+       switch (gd->ram_size) {
+       case 0x10000000:
+       case 0x20000000:
+       case 0x40000000:
+       case 0x80000000:
+               break;
+       case 0xF0000000:
+               gd->ram_size -= 0x100000;
+               break;
+       default:
+               printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
+               return -1;
+       }
+
+       return 0;
+}
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
new file mode 100644 (file)
index 0000000..1f39679
--- /dev/null
@@ -0,0 +1,84 @@
+/*
+ * Code used by both U-Boot and SPL for Compulab CM-FX6
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc_pads[] = {
+       IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+       IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+       IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+void cm_fx6_set_usdhc_iomux(void)
+{
+       SETUP_IOMUX_PADS(usdhc_pads);
+}
+
+/* CINS bit doesn't work, so always try to access the MMC card */
+int board_mmc_getcd(struct mmc *mmc)
+{
+       return 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+               PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const ecspi_pads[] = {
+       IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+       IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+};
+
+void cm_fx6_set_ecspi_iomux(void)
+{
+       SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+       return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
+}
+#endif
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
new file mode 100644 (file)
index 0000000..347d07b
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+                       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+                       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define CM_FX6_ECSPI_BUS0_CS0  IMX_GPIO_NR(2, 30)
+#define CM_FX6_GREEN_LED       IMX_GPIO_NR(2, 31)
+
+void cm_fx6_set_usdhc_iomux(void);
+void cm_fx6_set_ecspi_iomux(void);
diff --git a/board/compulab/cm_fx6/imximage.cfg b/board/compulab/cm_fx6/imximage.cfg
new file mode 100644 (file)
index 0000000..420947e
--- /dev/null
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM      sd
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
new file mode 100644 (file)
index 0000000..a3abc7b
--- /dev/null
@@ -0,0 +1,355 @@
+/*
+ * SPL specific code for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_config {
+       DDR_16BIT_256MB,
+       DDR_32BIT_512MB,
+       DDR_32BIT_1GB,
+       DDR_64BIT_1GB,
+       DDR_64BIT_2GB,
+       DDR_64BIT_4GB,
+       DDR_UNKNOWN,
+};
+
+/*
+ * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
+ * Freescale QRM, but this is exactly the value used by the automatic
+ * calibration script and it works also in all our tests, so we leave
+ * it as is at this point.
+ */
+#define CM_FX6_DDR_IOMUX_CFG \
+       .dram_sdqs0     = 0x00000038, \
+       .dram_sdqs1     = 0x00000038, \
+       .dram_sdqs2     = 0x00000038, \
+       .dram_sdqs3     = 0x00000038, \
+       .dram_sdqs4     = 0x00000038, \
+       .dram_sdqs5     = 0x00000038, \
+       .dram_sdqs6     = 0x00000038, \
+       .dram_sdqs7     = 0x00000038, \
+       .dram_dqm0      = 0x00000038, \
+       .dram_dqm1      = 0x00000038, \
+       .dram_dqm2      = 0x00000038, \
+       .dram_dqm3      = 0x00000038, \
+       .dram_dqm4      = 0x00000038, \
+       .dram_dqm5      = 0x00000038, \
+       .dram_dqm6      = 0x00000038, \
+       .dram_dqm7      = 0x00000038, \
+       .dram_cas       = 0x00000038, \
+       .dram_ras       = 0x00000038, \
+       .dram_sdclk_0   = 0x00000038, \
+       .dram_sdclk_1   = 0x00000038, \
+       .dram_sdcke0    = 0x00003000, \
+       .dram_sdcke1    = 0x00003000, \
+       .dram_reset     = 0x00000038, \
+       .dram_sdba2     = 0x00000000, \
+       .dram_sdodt0    = 0x00000038, \
+       .dram_sdodt1    = 0x00000038,
+
+#define CM_FX6_GPR_IOMUX_CFG \
+       .grp_b0ds       = 0x00000038, \
+       .grp_b1ds       = 0x00000038, \
+       .grp_b2ds       = 0x00000038, \
+       .grp_b3ds       = 0x00000038, \
+       .grp_b4ds       = 0x00000038, \
+       .grp_b5ds       = 0x00000038, \
+       .grp_b6ds       = 0x00000038, \
+       .grp_b7ds       = 0x00000038, \
+       .grp_addds      = 0x00000038, \
+       .grp_ddrmode_ctl = 0x00020000, \
+       .grp_ddrpke     = 0x00000000, \
+       .grp_ddrmode    = 0x00020000, \
+       .grp_ctlds      = 0x00000038, \
+       .grp_ddr_type   = 0x000C0000,
+
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
+static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
+
+static struct mx6_mmdc_calibration cm_fx6_calib_s = {
+       .p0_mpwldectrl0 = 0x005B0061,
+       .p0_mpwldectrl1 = 0x004F0055,
+       .p0_mpdgctrl0   = 0x0314030C,
+       .p0_mpdgctrl1   = 0x025C0268,
+       .p0_mprddlctl   = 0x42464646,
+       .p0_mpwrdlctl   = 0x36322C34,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
+       .cs1_mirror     = 1,
+       .cs_density     = 16,
+       .bi_on          = 1,
+       .rtt_nom        = 1,
+       .rtt_wr         = 0,
+       .ralat          = 5,
+       .walat          = 1,
+       .mif3_mode      = 3,
+       .rst_to_cke     = 0x23,
+       .sde_to_rst     = 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
+       .mem_speed      = 800,
+       .density        = 4,
+       .rowaddr        = 14,
+       .coladdr        = 10,
+       .pagesz         = 2,
+       .trcd           = 1800,
+       .trcmin         = 5200,
+       .trasmin        = 3600,
+       .SRT            = 0,
+};
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
+{
+       if (reset)
+               ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+       switch (dram_config) {
+       case DDR_16BIT_256MB:
+               cm_fx6_sysinfo_s.dsize = 0;
+               cm_fx6_sysinfo_s.ncs = 1;
+               break;
+       case DDR_32BIT_512MB:
+               cm_fx6_sysinfo_s.dsize = 1;
+               cm_fx6_sysinfo_s.ncs = 1;
+               break;
+       case DDR_32BIT_1GB:
+               cm_fx6_sysinfo_s.dsize = 1;
+               cm_fx6_sysinfo_s.ncs = 2;
+               break;
+       default:
+               puts("Tried to setup invalid DDR configuration\n");
+               hang();
+       }
+
+       mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
+       udelay(100);
+}
+
+static struct mx6_mmdc_calibration cm_fx6_calib_q = {
+       .p0_mpwldectrl0 = 0x00630068,
+       .p0_mpwldectrl1 = 0x0068005D,
+       .p0_mpdgctrl0   = 0x04140428,
+       .p0_mpdgctrl1   = 0x037C037C,
+       .p0_mprddlctl   = 0x3C30303A,
+       .p0_mpwrdlctl   = 0x3A344038,
+       .p1_mpwldectrl0 = 0x0035004C,
+       .p1_mpwldectrl1 = 0x00170026,
+       .p1_mpdgctrl0   = 0x0374037C,
+       .p1_mpdgctrl1   = 0x0350032C,
+       .p1_mprddlctl   = 0x30322A3C,
+       .p1_mpwrdlctl   = 0x48304A3E,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
+       .cs_density     = 16,
+       .cs1_mirror     = 1,
+       .bi_on          = 1,
+       .rtt_nom        = 1,
+       .rtt_wr         = 0,
+       .ralat          = 5,
+       .walat          = 1,
+       .mif3_mode      = 3,
+       .rst_to_cke     = 0x23,
+       .sde_to_rst     = 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
+       .mem_speed      = 1066,
+       .density        = 4,
+       .rowaddr        = 14,
+       .coladdr        = 10,
+       .pagesz         = 2,
+       .trcd           = 1324,
+       .trcmin         = 59500,
+       .trasmin        = 9750,
+       .SRT            = 0,
+};
+
+static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
+{
+       if (reset)
+               ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+       cm_fx6_ddr3_cfg_q.rowaddr = 14;
+       switch (dram_config) {
+       case DDR_16BIT_256MB:
+               cm_fx6_sysinfo_q.dsize = 0;
+               cm_fx6_sysinfo_q.ncs = 1;
+               break;
+       case DDR_32BIT_512MB:
+               cm_fx6_sysinfo_q.dsize = 1;
+               cm_fx6_sysinfo_q.ncs = 1;
+               break;
+       case DDR_64BIT_1GB:
+               cm_fx6_sysinfo_q.dsize = 2;
+               cm_fx6_sysinfo_q.ncs = 1;
+               break;
+       case DDR_64BIT_2GB:
+               cm_fx6_sysinfo_q.dsize = 2;
+               cm_fx6_sysinfo_q.ncs = 2;
+               break;
+       case DDR_64BIT_4GB:
+               cm_fx6_sysinfo_q.dsize = 2;
+               cm_fx6_sysinfo_q.ncs = 2;
+               cm_fx6_ddr3_cfg_q.rowaddr = 15;
+               break;
+       default:
+               puts("Tried to setup invalid DDR configuration\n");
+               hang();
+       }
+
+       mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
+       udelay(100);
+}
+
+static int cm_fx6_spl_dram_init(void)
+{
+       unsigned long bank1_size, bank2_size;
+
+       switch (get_cpu_type()) {
+       case MXC_CPU_MX6SOLO:
+               mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
+
+               spl_mx6s_dram_init(DDR_32BIT_1GB, false);
+               bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+               if (bank1_size == 0x40000000)
+                       return 0;
+
+               if (bank1_size == 0x20000000) {
+                       spl_mx6s_dram_init(DDR_32BIT_512MB, true);
+                       return 0;
+               }
+
+               spl_mx6s_dram_init(DDR_16BIT_256MB, true);
+               bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+               if (bank1_size == 0x10000000)
+                       return 0;
+
+               break;
+       case MXC_CPU_MX6D:
+       case MXC_CPU_MX6Q:
+               mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
+
+               spl_mx6q_dram_init(DDR_64BIT_4GB, false);
+               bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+               if (bank1_size == 0x80000000)
+                       return 0;
+
+               if (bank1_size == 0x40000000) {
+                       bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
+                                                               0x80000000);
+                       if (bank2_size == 0x40000000) {
+                               /* Don't do a full reset here */
+                               spl_mx6q_dram_init(DDR_64BIT_2GB, false);
+                       } else {
+                               spl_mx6q_dram_init(DDR_64BIT_1GB, true);
+                       }
+
+                       return 0;
+               }
+
+               spl_mx6q_dram_init(DDR_32BIT_512MB, true);
+               bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+               if (bank1_size == 0x20000000)
+                       return 0;
+
+               spl_mx6q_dram_init(DDR_16BIT_256MB, true);
+               bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+               if (bank1_size == 0x10000000)
+                       return 0;
+
+               break;
+       }
+
+       return -1;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+       IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+       IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_uart(void)
+{
+       SETUP_IOMUX_PADS(uart4_pads);
+       enable_uart_clk(1);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void cm_fx6_setup_ecspi(void)
+{
+       cm_fx6_set_ecspi_iomux();
+       enable_cspi_clock(1, 0);
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+       gd = &gdata;
+       arch_cpu_init();
+       timer_init();
+       cm_fx6_setup_ecspi();
+       cm_fx6_setup_uart();
+       get_clocks();
+       preloader_console_init();
+       gpio_direction_output(CM_FX6_GREEN_LED, 1);
+       if (cm_fx6_spl_dram_init()) {
+               puts("!!!ERROR!!! DRAM detection failed!!!\n");
+               hang();
+       }
+
+       memset(__bss_start, 0, __bss_end - __bss_start);
+       board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+       u32 boot_device = spl_boot_device();
+
+       if (boot_device == BOOT_DEVICE_SPI)
+               puts("Booting from SPI flash\n");
+       else if (boot_device == BOOT_DEVICE_MMC1)
+               puts("Booting from MMC\n");
+       else
+               puts("Unknown boot device\n");
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+       .esdhc_base = USDHC3_BASE_ADDR,
+       .max_bus_width = 4,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+       cm_fx6_set_usdhc_iomux();
+
+       usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+       return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
new file mode 100644 (file)
index 0000000..50c06f7
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_CM_FX6=y
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644 (file)
index 0000000..15c55be
--- /dev/null
@@ -0,0 +1,192 @@
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/* Machine config */
+#define CONFIG_MX6
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE               4273
+#define CONFIG_SYS_HZ                  1000
+
+/* Display information on boot */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIMESTAMP
+
+/* CMD */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GREPENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM       3
+#define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1                   MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2                   MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS           2
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART4_BASE
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
+
+/* Shell */
+#define CONFIG_SYS_PROMPT      "CM-FX6 # "
+#define CONFIG_SYS_CBSIZE      1024
+#define CONFIG_SYS_MAXARGS     16
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* SPI flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS          0
+#define CONFIG_SF_DEFAULT_CS           0
+#define CONFIG_SF_DEFAULT_SPEED                25000000
+#define CONFIG_SF_DEFAULT_MODE         (SPI_MODE_0)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+#define CONFIG_ENV_OFFSET              (768 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "kernel=uImage-cm-fx6\0" \
+       "autoload=no\0" \
+       "loadaddr=0x10800000\0" \
+       "fdtaddr=0x11000000\0" \
+       "console=ttymxc3,115200\0" \
+       "ethprime=FEC0\0" \
+       "bootscr=boot.scr\0" \
+       "bootm_low=18000000\0" \
+       "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
+       "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
+       "fdtfile=cm-fx6.dtb\0" \
+       "doboot=bootm ${loadaddr}\0" \
+       "loadfdt=false\0" \
+       "setboottypez=setenv kernel zImage-cm-fx6;" \
+               "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
+               "setenv loadfdt true;\0" \
+       "setboottypem=setenv kernel uImage-cm-fx6;" \
+               "setenv doboot bootm ${loadaddr};" \
+               "setenv loadfdt false;\0"\
+       "run_eboot=echo Starting EBOOT ...; "\
+               "mmc dev ${mmcdev} && " \
+               "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
+       "mmcdev=2\0" \
+       "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+       "loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
+       "mmcbootscript=echo Running bootscript from mmc ...; "\
+               "source ${loadaddr}\0" \
+       "mmcargs=setenv bootargs console=${console} " \
+               "root=${mmcroot} " \
+               "${video}\0" \
+       "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+       "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "run doboot\0" \
+       "boot=mmc dev ${mmcdev}; " \
+               "if mmc rescan; then " \
+                       "if run loadmmcbootscript; then " \
+                               "run mmcbootscript;" \
+                       "else " \
+                               "if run mmcloadkernel; then " \
+                                       "if ${loadfdt}; then " \
+                                               "run mmcloadfdt;" \
+                                       "fi;" \
+                                       "run mmcboot;" \
+                               "fi;" \
+                       "fi;" \
+               "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+       "run setboottypem; run boot"
+
+/* SPI */
+#define CONFIG_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_WINBOND
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_LOADADDR                        0x10800000
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+#define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
+#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* misc */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_STACKSIZE                       (128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN                  (2 * 1024 * 1024)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS     800 /* 400 KB */
+
+/* SPL */
+#include "imx6_spl.h"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0x80 /* offset 64 kb */
+#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     (64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+
+#endif /* __CONFIG_CM_FX6_H */