F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
+ARM OWL
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: arch/arm/include/asm/arch-owl/
+F: arch/arm/mach-owl/
+F: board/ucRobotics/
+F: drivers/clk/owl/
+F: drivers/serial/serial_owl.c
+
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@gmail.com>
select BOARD_EARLY_INIT_F
imply MXC_GPIO
+config ARCH_OWL
+ bool "Actions Semi OWL SoCs"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+
config ARCH_QEMU
bool "QEMU Virtual Platform"
select DM
source "arch/arm/mach-orion5x/Kconfig"
+source "arch/arm/mach-owl/Kconfig"
+
source "arch/arm/mach-rmobile/Kconfig"
source "arch/arm/mach-meson/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
+source "board/ucRobotics/bubblegum_96/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
+machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree Source for Bubblegum-96
+//
+// Copyright (C) 2015 Actions Semi Co., Ltd.
+// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+/dts-v1/;
+#include "s900.dtsi"
+
+/ {
+ model = "Bubblegum-96";
+ compatible = "ucrobotics,bubblegum-96", "actions,s900";
+
+ aliases {
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree Source for Actions Semi S900 SoC
+//
+// Copyright (C) 2015 Actions Semi Co., Ltd.
+// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+/dts-v1/;
+#include <dt-bindings/clock/s900_cmu.h>
+
+/ {
+ compatible = "actions,s900";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ losc: losc {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ diff24M: diff24M {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+
+ uart5: serial@e012a000 {
+ u-boot,dm-pre-reloc;
+ compatible = "actions,s900-serial";
+ reg = <0x0 0xe012a000 0x0 0x1000>;
+ clocks = <&cmu CLOCK_UART5>;
+ status = "disabled";
+ };
+
+ cmu: clock-controller@e0160000 {
+ u-boot,dm-pre-reloc;
+ compatible = "actions,s900-cmu";
+ reg = <0x0 0xe0160000 0x0 0x1000>;
+ clocks = <&losc>, <&diff24M>;
+ clock-names = "losc", "diff24M";
+ #clock-cells = <1>;
+ };
+ };
+};
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S900 Clock Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_CLK_S900_H_
+#define _OWL_CLK_S900_H_
+
+#include <clk-uclass.h>
+
+struct owl_clk_priv {
+ phys_addr_t base;
+};
+
+/* BUSCLK register definitions */
+#define CMU_PDBGDIV_8 7
+#define CMU_PDBGDIV_SHIFT 26
+#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
+#define CMU_PERDIV_8 7
+#define CMU_PERDIV_SHIFT 20
+#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
+#define CMU_NOCDIV_2 1
+#define CMU_NOCDIV_SHIFT 19
+#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
+#define CMU_DMMCLK_SRC_APLL 2
+#define CMU_DMMCLK_SRC_SHIFT 10
+#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
+#define CMU_APBCLK_DIV BIT(8)
+#define CMU_NOCCLK_SRC BIT(7)
+#define CMU_AHBCLK_DIV BIT(4)
+#define CMU_CORECLK_MASK 3
+#define CMU_CORECLK_CPLL BIT(1)
+#define CMU_CORECLK_HOSC BIT(0)
+
+/* COREPLL register definitions */
+#define CMU_COREPLL_EN BIT(9)
+#define CMU_COREPLL_HOSC_EN BIT(8)
+#define CMU_COREPLL_OUT (1104 / 24)
+
+/* DEVPLL register definitions */
+#define CMU_DEVPLL_CLK BIT(12)
+#define CMU_DEVPLL_EN BIT(8)
+#define CMU_DEVPLL_OUT (660 / 6)
+
+/* UARTCLK register definitions */
+#define CMU_UARTCLK_SRC_DEVPLL BIT(16)
+
+/* DEVCLKEN1 register definitions */
+#define CMU_DEVCLKEN1_UART5 BIT(21)
+
+#define PLL_STABILITY_WAIT_US 50
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S900 Register Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_REGS_S900_H_
+#define _OWL_REGS_S900_H_
+
+/* CMU registers */
+#define CMU_COREPLL (0x0000)
+#define CMU_DEVPLL (0x0004)
+#define CMU_DDRPLL (0x0008)
+#define CMU_NANDPLL (0x000C)
+#define CMU_DISPLAYPLL (0x0010)
+#define CMU_AUDIOPLL (0x0014)
+#define CMU_TVOUTPLL (0x0018)
+#define CMU_BUSCLK (0x001C)
+#define CMU_SENSORCLK (0x0020)
+#define CMU_LCDCLK (0x0024)
+#define CMU_DSICLK (0x0028)
+#define CMU_CSICLK (0x002C)
+#define CMU_DECLK (0x0030)
+#define CMU_BISPCLK (0x0034)
+#define CMU_IMXCLK (0x0038)
+#define CMU_HDECLK (0x003C)
+#define CMU_VDECLK (0x0040)
+#define CMU_VCECLK (0x0044)
+#define CMU_NANDCCLK (0x004C)
+#define CMU_SD0CLK (0x0050)
+#define CMU_SD1CLK (0x0054)
+#define CMU_SD2CLK (0x0058)
+#define CMU_UART0CLK (0x005C)
+#define CMU_UART1CLK (0x0060)
+#define CMU_UART2CLK (0x0064)
+#define CMU_PWM0CLK (0x0070)
+#define CMU_PWM1CLK (0x0074)
+#define CMU_PWM2CLK (0x0078)
+#define CMU_PWM3CLK (0x007C)
+#define CMU_USBPLL (0x0080)
+#define CMU_ASSISTPLL (0x0084)
+#define CMU_EDPCLK (0x0088)
+#define CMU_GPU3DCLK (0x0090)
+#define CMU_CORECTL (0x009C)
+#define CMU_DEVCLKEN0 (0x00A0)
+#define CMU_DEVCLKEN1 (0x00A4)
+#define CMU_DEVRST0 (0x00A8)
+#define CMU_DEVRST1 (0x00AC)
+#define CMU_UART3CLK (0x00B0)
+#define CMU_UART4CLK (0x00B4)
+#define CMU_UART5CLK (0x00B8)
+#define CMU_UART6CLK (0x00BC)
+#define CMU_TLSCLK (0x00C0)
+#define CMU_SD3CLK (0x00C4)
+#define CMU_PWM4CLK (0x00C8)
+#define CMU_PWM5CLK (0x00CC)
+#define CMU_ANALOGDEBUG (0x00D4)
+#define CMU_TVOUTPLLDEBUG0 (0x00EC)
+#define CMU_TVOUTPLLDEBUG1 (0x00FC)
+
+#endif
--- /dev/null
+if ARCH_OWL
+
+config SYS_SOC
+ default "owl"
+
+choice
+ prompt "Actions Semi OWL SoCs board select"
+ optional
+
+config TARGET_BUBBLEGUM_96
+ bool "96Boards Bubblegum-96"
+ help
+ Support for 96Boards Bubblegum-96. This board complies with
+ 96Board Consumer Edition Specification. Features:
+ - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
+ - 2GiB RAM
+ - 8GiB eMMC, uSD slot
+ - WiFi, Bluetooth and GPS module
+ - 2x Host, 1x Device USB port
+ - HDMI
+ - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
+
+endchoice
+
+source "board/ucRobotics/bubblegum_96/Kconfig"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += sysmap-s900.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi S900 Memory map
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region s900_mem_map[] = {
+ {
+ .virt = 0x0UL, /* DDR */
+ .phys = 0x0UL, /* DDR */
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xE0000000UL, /* Peripheral block */
+ .phys = 0xE0000000UL, /* Peripheral block */
+ .size = 0x08000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = s900_mem_map;
select SPL_OF_TRANSLATE
select SPL_PINCTRL
select SPL_REGMAP
- select SPL_RESET_SUPPORT
+ select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
select SPL_SYSCON
select SPL_DRIVERS_MISC_SUPPORT
--- /dev/null
+if TARGET_BUBBLEGUM_96
+
+config SYS_BOARD
+ default "bubblegum_96"
+
+config SYS_VENDOR
+ default "ucRobotics"
+
+config SYS_SOC
+ default "s900"
+
+config SYS_CONFIG_NAME
+ default "bubblegum_96"
+
+endif
--- /dev/null
+BUBBLEGUM_96 BOARD
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: board/ucRobotics/bubblegum_96/
+F: include/configs/bubblegum_96.h
+F: configs/bubblegum_96_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := bubblegum_96.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bubblegum-96 Boards Support
+ *
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/psci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+static void show_psci_version(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ printf("PSCI: v%ld.%ld\n",
+ PSCI_VERSION_MAJOR(res.a0),
+ PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+ show_psci_version();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
performed before booting. This enables the drivers in post/drivers
as part of an SPL build.
-config SPL_RESET_SUPPORT
+config SPL_DM_RESET
bool "Support reset drivers"
depends on SPL
help
CONFIG_CMD_SF=y
CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD=y
CONFIG_ATCSPI200_SPI=y
CONFIG_TIMER=y
CONFIG_ATCPIT100_TIMER=y
-CONFIG_BOOTP_PREFER_SERVERIP=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_OWL=y
+CONFIG_TARGET_BUBBLEGUM_96=y
+CONFIG_SYS_TEXT_BASE=0x11000000
+CONFIG_IDENT_STRING="\nBubblegum-96"
+CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_ARM_SMCCC=y
+CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="U-Boot => "
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CLK=y
+CONFIG_CLK_OWL=y
+CONFIG_CLK_S900=y
+CONFIG_OWL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 > "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 factory > "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_HELIOS4=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_I2C=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
-CONFIG_AHCI=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SCSI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_PCI=y
-CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_DM_I2C=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PHY=y
-CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR=1
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_GPIO=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PHY=y
-CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
-CONFIG_SECURE_BOOT=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
-# CONFIG_DM_MMC_OPS is not set
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_DM_ETH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
CONFIG_FSL_PFE=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_AHCI_MVEBU=y
-CONFIG_BLOCK_CACHE=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_DM_GPIO=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_AHCI_MVEBU=y
-CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_MISC=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_AHCI_MVEBU=y
-CONFIG_BLOCK_CACHE=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_DM_GPIO=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_AHCI_MVEBU=y
-CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PHY=y
-CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_WOL=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_WOL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
-CONFIG_SYS_THUMB_BUILD=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BLOCK_CACHE=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_DM_GPIO=y
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
-obj-$(CONFIG_SPL_RESET_SUPPORT) += reset/
+obj-$(CONFIG_SPL_DM_RESET) += reset/
obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
source "drivers/clk/at91/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/mvebu/Kconfig"
+source "drivers/clk/owl/Kconfig"
config ICS8N3QV01
bool "Enable ICS8N3QV01 VCXO driver"
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
--- /dev/null
+config CLK_OWL
+ bool "Actions Semi OWL clock drivers"
+ depends on CLK && ARCH_OWL
+ help
+ Enable support for clock managemet unit present in Actions Semi
+ OWL SoCs.
+
+config CLK_S900
+ bool "Actions Semi S900 clock driver"
+ depends on CLK_OWL && ARM64
+ help
+ Enable support for the clocks in Actions Semi S900 SoC.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_S900) += clk_s900.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi S900 clock driver
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch-owl/clk_s900.h>
+#include <asm/arch-owl/regs_s900.h>
+#include <asm/io.h>
+
+#include <dt-bindings/clock/s900_cmu.h>
+
+void owl_clk_init(struct owl_clk_priv *priv)
+{
+ u32 bus_clk = 0, core_pll, dev_pll;
+
+ /* Enable ASSIST_PLL */
+ setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Source HOSC to DEV_CLK */
+ clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
+
+ /* Configure BUS_CLK */
+ bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
+ CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
+ CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
+ writel(bus_clk, priv->base + CMU_BUSCLK);
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Configure CORE_PLL */
+ core_pll = readl(priv->base + CMU_COREPLL);
+ core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
+ writel(core_pll, priv->base + CMU_COREPLL);
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Configure DEV_PLL */
+ dev_pll = readl(priv->base + CMU_DEVPLL);
+ dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
+ writel(dev_pll, priv->base + CMU_DEVPLL);
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Source CORE_PLL for CORE_CLK */
+ clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
+ CMU_CORECLK_CPLL);
+
+ /* Source DEV_PLL for DEV_CLK */
+ setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
+
+ udelay(PLL_STABILITY_WAIT_US);
+}
+
+void owl_uart_clk_enable(struct owl_clk_priv *priv)
+{
+ /* Source HOSC for UART5 interface */
+ clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
+
+ /* Enable UART5 interface clock */
+ setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
+}
+
+void owl_uart_clk_disable(struct owl_clk_priv *priv)
+{
+ /* Disable UART5 interface clock */
+ clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
+}
+
+int owl_clk_enable(struct clk *clk)
+{
+ struct owl_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLOCK_UART5:
+ owl_uart_clk_enable(priv);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+int owl_clk_disable(struct clk *clk)
+{
+ struct owl_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLOCK_UART5:
+ owl_uart_clk_disable(priv);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int owl_clk_probe(struct udevice *dev)
+{
+ struct owl_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* setup necessary clocks */
+ owl_clk_init(priv);
+
+ return 0;
+}
+
+static struct clk_ops owl_clk_ops = {
+ .enable = owl_clk_enable,
+ .disable = owl_clk_disable,
+};
+
+static const struct udevice_id owl_clk_ids[] = {
+ { .compatible = "actions,s900-cmu" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_owl) = {
+ .name = "clk_s900",
+ .id = UCLASS_CLK,
+ .of_match = owl_clk_ids,
+ .ops = &owl_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
+ .probe = owl_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
#include <linux/libfdt.h>
#include <linux/err.h>
#include <malloc.h>
+#include <reset.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int smplsel;
};
+static void socfpga_dwmci_reset(struct udevice *dev)
+{
+ struct reset_ctl_bulk reset_bulk;
+ int ret;
+
+ ret = reset_get_bulk(dev, &reset_bulk);
+ if (ret) {
+ dev_warn(dev, "Can't get reset: %d\n", ret);
+ return;
+ }
+
+ reset_deassert_bulk(&reset_bulk);
+}
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ socfpga_dwmci_reset(dev);
+
#ifdef CONFIG_BLK
dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
host->mmc = &plat->mmc;
#include <miiphy.h>
#include <malloc.h>
#include <pci.h>
+#include <reset.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <linux/kernel.h>
u32 iobase = pdata->iobase;
ulong ioaddr;
int ret;
+ struct reset_ctl_bulk reset_bulk;
#ifdef CONFIG_CLK
int i, err, clock_nb;
}
#endif
+ ret = reset_get_bulk(dev, &reset_bulk);
+ if (ret)
+ dev_warn(dev, "Can't get reset: %d\n", ret);
+ else
+ reset_deassert_bulk(&reset_bulk);
+
#ifdef CONFIG_DM_PCI
/*
* If we are on PCI bus, either directly attached to a PCI root port,
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+config OWL_SERIAL
+ bool "Actions Semi OWL UART"
+ depends on DM_SERIAL && ARCH_OWL
+ help
+ If you have a Actions Semi OWL based board and want to use the on-chip
+ serial port, say Y to this option. If unsure, say N.
+ Single baudrate is supported in current implementation (115200).
+
config PXA_SERIAL
bool "PXA serial port support"
help
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
+obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
#include <dm.h>
#include <errno.h>
#include <ns16550.h>
+#include <reset.h>
#include <serial.h>
#include <watchdog.h>
#include <linux/types.h>
#if defined(CONFIG_ARCH_OMAP2PLUS)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
+
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(ns16550_getfcr(com_port), &com_port->fcr);
if (baud_divisor != -1)
int ns16550_serial_probe(struct udevice *dev)
{
struct NS16550 *const com_port = dev_get_priv(dev);
+ struct reset_ctl_bulk reset_bulk;
+ int ret;
+
+ ret = reset_get_bulk(dev, &reset_bulk);
+ if (!ret)
+ reset_deassert_bulk(&reset_bulk);
com_port->plat = dev_get_platdata(dev);
NS16550_init(com_port, -1);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi OWL SoCs UART driver
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+/* UART Registers */
+#define OWL_UART_CTL (0x0000)
+#define OWL_UART_RXDAT (0x0004)
+#define OWL_UART_TXDAT (0x0008)
+#define OWL_UART_STAT (0x000C)
+
+/* UART_CTL Register Definitions */
+#define OWL_UART_CTL_PRS_NONE GENMASK(6, 4)
+#define OWL_UART_CTL_STPS BIT(2)
+#define OWL_UART_CTL_DWLS 3
+
+/* UART_STAT Register Definitions */
+#define OWL_UART_STAT_TFES BIT(10) /* TX FIFO Empty Status */
+#define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */
+#define OWL_UART_STAT_TFFU BIT(6) /* TX FIFO full Status */
+#define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */
+
+struct owl_serial_priv {
+ phys_addr_t base;
+};
+
+int owl_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ /* Driver supports only fixed baudrate */
+ return 0;
+}
+
+static int owl_serial_getc(struct udevice *dev)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM)
+ return -EAGAIN;
+
+ return (int)(readl(priv->base + OWL_UART_RXDAT));
+}
+
+static int owl_serial_putc(struct udevice *dev, const char ch)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU)
+ return -EAGAIN;
+
+ writel(ch, priv->base + OWL_UART_TXDAT);
+
+ return 0;
+}
+
+static int owl_serial_pending(struct udevice *dev, bool input)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+ unsigned int stat = readl(priv->base + OWL_UART_STAT);
+
+ if (input)
+ return !(stat & OWL_UART_STAT_RFEM);
+ else
+ return !(stat & OWL_UART_STAT_TFES);
+}
+
+static int owl_serial_probe(struct udevice *dev)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ u32 uart_ctl;
+ int ret;
+
+ /* Set data, parity and stop bits */
+ uart_ctl = readl(priv->base + OWL_UART_CTL);
+ uart_ctl &= ~(OWL_UART_CTL_PRS_NONE);
+ uart_ctl &= ~(OWL_UART_CTL_STPS);
+ uart_ctl |= OWL_UART_CTL_DWLS;
+ writel(uart_ctl, priv->base + OWL_UART_CTL);
+
+ /* Enable UART clock */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int owl_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_serial_ops owl_serial_ops = {
+ .putc = owl_serial_putc,
+ .pending = owl_serial_pending,
+ .getc = owl_serial_getc,
+ .setbrg = owl_serial_setbrg,
+};
+
+static const struct udevice_id owl_serial_ids[] = {
+ { .compatible = "actions,s900-serial" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_owl) = {
+ .name = "serial_owl",
+ .id = UCLASS_SERIAL,
+ .of_match = owl_serial_ids,
+ .ofdata_to_platdata = owl_serial_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct owl_serial_priv),
+ .probe = owl_serial_probe,
+ .ops = &owl_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Bubblegum-96
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _BUBBLEGUM_96_H_
+#define _BUGGLEGUM_96_H_
+
+/* SDRAM Definitions */
+#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_SIZE 0x80000000
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (24000000) /* 24MHz */
+
+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)
+
+/* UART Definitions */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_ENV_SIZE 0x2000
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
+#define _DT_BINDINGS_CLOCK_S900_CMU_H_
+
+/* Module Clock ID */
+#define CLOCK_DDRCH1 0
+#define CLOCK_DMAC 1
+#define CLOCK_DDRCH0 2
+#define CLOCK_BROM 3
+#define CLOCK_NANDC0 4
+#define CLOCK_SD0 5
+#define CLOCK_SD1 6
+#define CLOCK_SD2 7
+#define CLOCK_DE 8
+#define CLOCK_LVDS 9
+#define CLOCK_EDP 10
+#define CLOCK_NANDC1 11
+#define CLOCK_DSI 12
+#define CLOCK_CSI0 13
+#define CLOCK_BISP 14
+#define CLOCK_CSI1 15
+#define CLOCK_SD3 16
+#define CLOCK_I2C4 17
+#define CLOCK_GPIO 18
+#define CLOCK_DMM 19
+#define CLOCK_I2STX 20
+#define CLOCK_I2SRX 21
+#define CLOCK_HDMIA 22
+#define CLOCK_SPDIF 23
+#define CLOCK_PCM0 24
+#define CLOCK_VDE 25
+#define CLOCK_VCE 26
+#define CLOCK_HDE 27
+#define CLOCK_SHARESRAM 28
+#define CLOCK_CMU_DDR1 29
+#define CLOCK_GPU3D 30
+#define CLOCK_CMUDDR0 31
+#define CLOCK_SPEED 32
+#define CLOCK_I2C5 33
+#define CLOCK_THERMAL 34
+#define CLOCK_HDMI 35
+#define CLOCK_PWM4 36
+#define CLOCK_PWM5 37
+#define CLOCK_UART0 38
+#define CLOCK_UART1 39
+#define CLOCK_UART2 40
+#define CLOCK_IRC 41
+#define CLOCK_SPI0 42
+#define CLOCK_SPI1 43
+#define CLOCK_SPI2 44
+#define CLOCK_SPI3 45
+#define CLOCK_I2C0 46
+#define CLOCK_I2C1 47
+#define CLOCK_PCM1 48
+#define CLOCK_IMX 49
+#define CLOCK_UART6 50
+#define CLOCK_UART3 51
+#define CLOCK_UART4 52
+#define CLOCK_UART5 53
+#define CLOCK_ETHERNET 54
+#define CLOCK_PWM0 55
+#define CLOCK_PWM1 56
+#define CLOCK_PWM2 57
+#define CLOCK_PWM3 58
+#define CLOCK_TIMER 59
+#define CLOCK_SE 60
+#define CLOCK_HDCP2TX 61
+#define CLOCK_I2C2 62
+#define CLOCK_I2C3 63
+
+#endif
unsigned int count;
};
-#ifdef CONFIG_DM_RESET
+#if CONFIG_IS_ENABLED(DM_RESET)
/**
* reset_get_by_index - Get/request a reset signal by integer index.
*
CONFIG_ARCH_TEGRA
CONFIG_ARCH_USE_BUILTIN_BSWAP
CONFIG_ARC_MMU_VER
-CONFIG_ARIES_M28_V10
CONFIG_ARMADA100
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
CONFIG_RTC_DS3231
CONFIG_RTC_FTRTC010
CONFIG_RTC_IMXDI
-CONFIG_RTC_INTERNAL
CONFIG_RTC_M41T11
CONFIG_RTC_M41T60
CONFIG_RTC_M41T62
CONFIG_RTC_MC146818
CONFIG_RTC_MCFRRTC
CONFIG_RTC_MCP79411
-CONFIG_RTC_MV
CONFIG_RTC_MXS
CONFIG_RTC_PCF8563
CONFIG_RTC_PT7C4338
CONFIG_SYS_USE_NANDFLASH
CONFIG_SYS_USE_NOR
CONFIG_SYS_USE_NORFLASH
-CONFIG_SYS_USE_SERIALFLASH
CONFIG_SYS_USR_EXCEP
CONFIG_SYS_U_BOOT_OFFS
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
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