]> git.sur5r.net Git - u-boot/commitdiff
arndale: Apply Cortex-A15 errata #773022 and #774769
authorIan Campbell <Ian.Campbell@citrix.com>
Tue, 29 Sep 2015 09:27:09 +0000 (10:27 +0100)
committerTom Rini <trini@konsulko.com>
Sun, 11 Oct 2015 21:12:11 +0000 (17:12 -0400)
We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy
userspace.

However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.

Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417
which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
and CPU Errata 773022 and 774769.

This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.

The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no
segfaults.

Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.

I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.

Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
README
arch/arm/cpu/armv7/nonsec_virt.S
include/configs/arndale.h

diff --git a/README b/README
index c22b60b49bc015a86ffeca224850cb11811bad7f..0dc657d0a583739a817f07f52e0f9572b30c8861 100644 (file)
--- a/README
+++ b/README
@@ -681,8 +681,10 @@ The following options need to be configured:
                CONFIG_ARM_ERRATA_742230
                CONFIG_ARM_ERRATA_743622
                CONFIG_ARM_ERRATA_751472
-               CONFIG_ARM_ERRATA_794072
                CONFIG_ARM_ERRATA_761320
+               CONFIG_ARM_ERRATA_773022
+               CONFIG_ARM_ERRATA_774769
+               CONFIG_ARM_ERRATA_794072
 
                If set, the workarounds for these ARM errata are applied early
                during U-Boot startup. Note that these options force the
index 30d81db8b81b398905249b5fff4b0fc218fa6109..31d1c9e348410b137091f0b1c490762438163ac7 100644 (file)
@@ -53,6 +53,20 @@ _secure_monitor:
        bl      psci_arch_init
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_773022
+       mrc     p15, 0, r5, c1, c0, 1
+       orr     r5, r5, #(1 << 1)
+       mcr     p15, 0, r5, c1, c0, 1
+       isb
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_774769
+       mrc     p15, 0, r5, c1, c0, 1
+       orr     r5, r5, #(1 << 25)
+       mcr     p15, 0, r5, c1, c0, 1
+       isb
+#endif
+
        mrc     p15, 0, r5, c1, c1, 0           @ read SCR
        bic     r5, r5, #0x4a                   @ clear IRQ, EA, nET bits
        orr     r5, r5, #0x31                   @ enable NS, AW, FW bits
index 437a7454146c0f69d37e64f4062881af90ece57c..b08f341227543efd4acb5dca78282fd9c8b1661b 100644 (file)
 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
 #define CONFIG_ARM_GIC_BASE_ADDRESS    0x10480000
 
+/* CPU Errata */
+#define CONFIG_ARM_ERRATA_773022
+#define CONFIG_ARM_ERRATA_774769
+
 /* Power */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C