]> git.sur5r.net Git - u-boot/commitdiff
x86: ivybridge: Add a driver for the bd82x6x northbridge
authorSimon Glass <sjg@chromium.org>
Sun, 17 Jan 2016 23:11:15 +0000 (16:11 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sun, 24 Jan 2016 04:08:16 +0000 (12:08 +0800)
Add a driver with an empty probe function where we can move init code in
follow-on patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/x86/cpu/ivybridge/early_init.c
arch/x86/dts/chromebook_link.dts

index 9ca008e345c8637378bb07ba329bf63e6b807346..945ae2dfcd89604de78b5c5fdcc4917ca1ef9ac5 100644 (file)
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
@@ -145,3 +146,20 @@ void sandybridge_early_init(int chipset_type)
 
        sandybridge_setup_graphics(pch_dev, video_dev);
 }
+
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+       return 0;
+}
+
+static const struct udevice_id bd82x6x_northbridge_ids[] = {
+       { .compatible = "intel,bd82x6x-northbridge" },
+       { }
+};
+
+U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
+       .name           = "bd82x6x_northbridge",
+       .id             = UCLASS_NORTHBRIDGE,
+       .of_match       = bd82x6x_northbridge_ids,
+       .probe          = bd82x6x_northbridge_probe,
+};
index f2db8443d2f9ea5b8a1131b85468a267956e9472..e2c722dd95bcc256fa8c1d3318345885fa17ed74 100644 (file)
                ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
                        0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
                        0x01000000 0x0 0x1000 0x1000 0 0xefff>;
+
+               northbridge@0,0 {
+                       reg = <0x00000000 0 0 0 0>;
+                       compatible = "intel,bd82x6x-northbridge";
+                       u-boot,dm-pre-reloc;
+               };
+
                sata {
                        compatible = "intel,pantherpoint-ahci";
                        intel,sata-mode = "ahci";