]> git.sur5r.net Git - u-boot/commitdiff
ARM: DRA7: Consolidate voltage macros across different SoCs
authorAnna, Suman <s-anna@ti.com>
Mon, 23 May 2016 18:32:16 +0000 (13:32 -0500)
committerTom Rini <trini@konsulko.com>
Fri, 3 Jun 2016 01:42:17 +0000 (21:42 -0400)
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.

This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/include/asm/arch-omap5/clock.h
board/ti/am57xx/board.c

index 5db17c41695757bdbd4b83986bbe00fa8475afa9..5b91446a8db4fe4891d9a64579e4ed4bf29155a2 100644 (file)
@@ -365,34 +365,34 @@ struct vcores_data omap5430_volts_es2 = {
 };
 
 struct vcores_data dra752_volts = {
-       .mpu.value      = VDD_MPU_DRA752,
+       .mpu.value      = VDD_MPU_DRA7,
        .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
        .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
        .mpu.pmic       = &tps659038,
        .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-       .eve.value      = VDD_EVE_DRA752,
+       .eve.value      = VDD_EVE_DRA7,
        .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
        .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .eve.addr       = TPS659038_REG_ADDR_SMPS45,
        .eve.pmic       = &tps659038,
        .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-       .gpu.value      = VDD_GPU_DRA752,
+       .gpu.value      = VDD_GPU_DRA7,
        .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
        .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
        .gpu.pmic       = &tps659038,
        .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-       .core.value     = VDD_CORE_DRA752,
+       .core.value     = VDD_CORE_DRA7,
        .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
        .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
        .core.addr      = TPS659038_REG_ADDR_SMPS7,
        .core.pmic      = &tps659038,
 
-       .iva.value      = VDD_IVA_DRA752,
+       .iva.value      = VDD_IVA_DRA7,
        .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
        .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .iva.addr       = TPS659038_REG_ADDR_SMPS8,
@@ -401,14 +401,14 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-       .mpu.value      = VDD_MPU_DRA72x,
+       .mpu.value      = VDD_MPU_DRA7,
        .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
        .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
        .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
        .mpu.pmic       = &tps659038,
        .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-       .core.value     = VDD_CORE_DRA72x,
+       .core.value     = VDD_CORE_DRA7,
        .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
        .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
        .core.addr      = TPS65917_REG_ADDR_SMPS2,
@@ -418,21 +418,21 @@ struct vcores_data dra722_volts = {
         * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
         * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
         */
-       .gpu.value      = VDD_GPU_DRA72x,
+       .gpu.value      = VDD_GPU_DRA7,
        .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
        .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
        .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
        .gpu.pmic       = &tps659038,
        .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-       .eve.value      = VDD_EVE_DRA72x,
+       .eve.value      = VDD_EVE_DRA7,
        .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
        .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
        .eve.addr       = TPS65917_REG_ADDR_SMPS3,
        .eve.pmic       = &tps659038,
        .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-       .iva.value      = VDD_IVA_DRA72x,
+       .iva.value      = VDD_IVA_DRA7,
        .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
        .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
        .iva.addr       = TPS65917_REG_ADDR_SMPS3,
index a850043c8967bcb47b831139d8f4dee3e31aca1a..8c121d6aa54d1cd66ce8efebc5fc50f512375d3e 100644 (file)
 #define VDD_MPU_ES2_LOW 880
 #define VDD_MM_ES2_LOW 880
 
-/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752         1150
-#define VDD_CORE_DRA752                1150
-#define VDD_EVE_DRA752         1060
-#define VDD_GPU_DRA752         1060
-#define VDD_IVA_DRA752         1060
-
-/* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x         1150
-#define VDD_CORE_DRA72x                1150
-#define VDD_EVE_DRA72x         1060
-#define VDD_GPU_DRA72x         1060
-#define VDD_IVA_DRA72x         1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7           1150
+#define VDD_CORE_DRA7          1150
+#define VDD_EVE_DRA7           1060
+#define VDD_GPU_DRA7           1060
+#define VDD_IVA_DRA7           1060
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE      0x4A002000
index 28db532f0c533382a856b9da31e3540a5c958201..da5f499808587ef879b0960e21973ddffe27344f 100644 (file)
@@ -216,34 +216,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 }
 
 struct vcores_data beagle_x15_volts = {
-       .mpu.value              = VDD_MPU_DRA752,
+       .mpu.value              = VDD_MPU_DRA7,
        .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU,
        .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
        .mpu.pmic               = &tps659038,
        .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-       .eve.value              = VDD_EVE_DRA752,
+       .eve.value              = VDD_EVE_DRA7,
        .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,
        .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .eve.addr               = TPS659038_REG_ADDR_SMPS45,
        .eve.pmic               = &tps659038,
        .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 
-       .gpu.value              = VDD_GPU_DRA752,
+       .gpu.value              = VDD_GPU_DRA7,
        .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU,
        .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
        .gpu.pmic               = &tps659038,
        .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 
-       .core.value             = VDD_CORE_DRA752,
+       .core.value             = VDD_CORE_DRA7,
        .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE,
        .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
        .core.addr              = TPS659038_REG_ADDR_SMPS6,
        .core.pmic              = &tps659038,
 
-       .iva.value              = VDD_IVA_DRA752,
+       .iva.value              = VDD_IVA_DRA7,
        .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA,
        .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .iva.addr               = TPS659038_REG_ADDR_SMPS45,