*/
/dts-v1/;
-/include/ "uniphier-ld11.dtsi"
+#include "uniphier-ld11.dtsi"
/ {
model = "UniPhier LD11 Global Board (REF_LD11_GP)";
&usb2 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
*/
/dts-v1/;
-/include/ "uniphier-ld11.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld11.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD11 Reference Board";
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-ld11-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gic: interrupt-controller@5fe00000 {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
};
nand: nand@68000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
*/
/dts-v1/;
-/include/ "uniphier-ld20.dtsi"
+#include "uniphier-ld20.dtsi"
/ {
model = "UniPhier LD20 Global Board (REF_LD20_GP)";
&i2c0 {
status = "okay";
};
+
+&nand {
+ status = "okay";
+};
*/
/dts-v1/;
-/include/ "uniphier-ld20.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld20.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD20 Reference Board";
sdctrl@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-ld20-sd-clock";
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-ld20-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gic: interrupt-controller@5fe00000 {
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
};
usb: usb@65b00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
*/
/dts-v1/;
-/include/ "uniphier-ld4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld4.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD4 Reference Board";
interrupt-controller;
};
- aidet@61830000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@61830000 {
+ compatible = "socionext,uniphier-ld4-aidet";
reg = <0x61830000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
sysctrl@61840000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
+ pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
*/
/dts-v1/;
-/include/ "uniphier-ld6b.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-ld6b.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD6b Reference Board";
* The D-chip (digital chip) is the same as the PXs2 die.
* Reuse the PXs2 device tree with some properties overridden.
*/
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"
/ {
compatible = "socionext,uniphier-ld6b";
*/
&pinctrl {
+ pinctrl_aout: aout_grp {
+ groups = "aout";
+ function = "aout";
+ };
+
pinctrl_emmc: emmc_grp {
groups = "emmc", "emmc_dat8";
function = "emmc";
*/
/dts-v1/;
-/include/ "uniphier-pro4.dtsi"
+#include "uniphier-pro4.dtsi"
/ {
model = "UniPhier Pro4 Ace Board";
*/
/dts-v1/;
-/include/ "uniphier-pro4.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-pro4.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier Pro4 Reference Board";
*/
/dts-v1/;
-/include/ "uniphier-pro4.dtsi"
+#include "uniphier-pro4.dtsi"
/ {
model = "UniPhier Pro4 Sanji Board";
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
timer@60000200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
*/
/dts-v1/;
-/include/ "uniphier-pro5.dtsi"
+#include "uniphier-pro5.dtsi"
/ {
model = "UniPhier Pro5 4KBOX Board";
i2c6 = &i2c6;
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
sdctrl@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
u-boot,dm-pre-reloc;
sd_clk: clock {
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
timer@60000200 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
+ pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
emmc: sdhc@68400000 {
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
*/
/dts-v1/;
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"
/ {
model = "UniPhier PXs2 Gentil Board";
*/
/dts-v1/;
-/include/ "uniphier-pxs2.dtsi"
+#include "uniphier-pxs2.dtsi"
/ {
model = "UniPhier PXs2 Vodka Board";
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
u-boot,dm-pre-reloc;
sd_clk: clock {
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
timer@60000200 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
+ pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+ X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
-/include/ "uniphier-pxs3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-pxs3.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier PXs3 Reference Board";
};
ðsc {
- interrupts = <0 48 4>;
+ interrupts = <0 52 4>;
};
&serial0 {
&i2c0 {
status = "okay";
};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;
/ {
compatible = "socionext,uniphier-pxs3";
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x002>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x003>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+ };
+
+ cluster0_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp-866667000 {
+ opp-hz = /bits/ 64 <866667000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ clock-latency-ns = <300>;
};
};
clock-frequency = <58820000>;
};
+ gpio: gpio@55000000 {
+ compatible = "socionext,uniphier-pxs3-gpio";
+ reg = <0x55000000 0x200>;
+ interrupt-parent = <&aidet>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 0>,
+ <&pinctrl 96 0 0>,
+ <&pinctrl 160 0 0>;
+ gpio-ranges-group-names = "gpio_range0",
+ "gpio_range1",
+ "gpio_range2";
+ };
+
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-pxs3-sd-clock";
emmc: sdhc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
- status = "disabled";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-mmc-highspeed = <2>;
+ cdns,phy-input-delay-mmc-ddr = <3>;
+ cdns,phy-dll-delay-sdclk = <21>;
+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
sd: sdhc@5a400000 {
};
};
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pxs3-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gic: interrupt-controller@5fe00000 {
compatible = "socionext,uniphier-pxs3-reset";
#reset-cells = <1>;
};
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
+ };
+
+ usb0: usb@65b00000 {
+ compatible = "socionext,uniphier-pxs3-dwc3";
+ status = "disabled";
+ reg = <0x65b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ dwc3@65a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65a00000 0x10000>;
+ interrupts = <0 134 4>;
+ dr_mode = "host";
+ tx-fifo-resize;
+ };
+ };
+
+ usb1: usb@65d00000 {
+ compatible = "socionext,uniphier-pxs3-dwc3";
+ status = "disabled";
+ reg = <0x65d00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ dwc3@65c00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65c00000 0x10000>;
+ interrupts = <0 137 4>;
+ dr_mode = "host";
+ tx-fifo-resize;
+ };
};
nand: nand@68000000 {
- compatible = "socionext,denali-nand-v5b";
+ compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
*/
/dts-v1/;
-/include/ "uniphier-sld8.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-sld8.dtsi"
+#include "uniphier-ref-daughter.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier sLD8 Reference Board";
interrupt-controller;
};
- aidet@61830000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet@61830000 {
+ compatible = "socionext,uniphier-sld8-aidet";
reg = <0x61830000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
sysctrl@61840000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
+ pinctrl-0 = <&pinctrl_nand2cs>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
select CPU_V7_HAS_NONSEC
select ARMV7_NONSEC
select ARCH_SUPPORT_PSCI
- imply NAND
choice
prompt "UniPhier SoC select"
struct uniphier_initdata {
unsigned int soc_id;
- bool nand_2cs;
void (*sbc_init)(void);
void (*pll_init)(void);
void (*clk_init)(void);
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{
.soc_id = UNIPHIER_LD4_ID,
- .nand_2cs = true,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
{
.soc_id = UNIPHIER_PRO4_ID,
- .nand_2cs = false,
.sbc_init = uniphier_sbc_init_savepin,
.pll_init = uniphier_pro4_pll_init,
.clk_init = uniphier_pro4_clk_init,
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
{
.soc_id = UNIPHIER_SLD8_ID,
- .nand_2cs = true,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
{
.soc_id = UNIPHIER_PRO5_ID,
- .nand_2cs = true,
.sbc_init = uniphier_sbc_init_savepin,
.clk_init = uniphier_pro5_clk_init,
},
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
{
.soc_id = UNIPHIER_PXS2_ID,
- .nand_2cs = true,
.sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{
.soc_id = UNIPHIER_LD6B_ID,
- .nand_2cs = true,
.sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
{
.soc_id = UNIPHIER_LD11_ID,
- .nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld11_pll_init,
.clk_init = uniphier_ld11_clk_init,
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{
.soc_id = UNIPHIER_LD20_ID,
- .nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld20_pll_init,
.clk_init = uniphier_ld20_clk_init,
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
{
.soc_id = UNIPHIER_PXS3_ID,
- .nand_2cs = false,
.sbc_init = uniphier_pxs2_sbc_init,
.pll_init = uniphier_pxs3_pll_init,
.clk_init = uniphier_pxs3_clk_init,
int board_init(void)
{
const struct uniphier_initdata *initdata;
- int ret;
led_puts("U0");
led_puts("U0");
- if (IS_ENABLED(CONFIG_NAND_DENALI)) {
- ret = uniphier_pin_init(initdata->nand_2cs ?
- "nand2cs_grp" : "nand_grp");
- if (ret)
- pr_err("failed to init NAND pins\n");
- }
-
- led_puts("U1");
-
if (initdata->pll_init)
initdata->pll_init();
- led_puts("U2");
+ led_puts("U1");
if (initdata->clk_init)
initdata->clk_init();
- led_puts("U3");
+ led_puts("U2");
if (initdata->misc_init)
initdata->misc_init();
- led_puts("U4");
+ led_puts("U3");
uniphier_setup_xirq();
- led_puts("U5");
+ led_puts("U4");
support_card_late_init();
if (!base)
return -ENOMEM;
- tmp = readl(base + 8); /* SSCPLLCTRL */
+ tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
writel(tmp, base + 8);
if (!base)
return -ENOMEM;
- tmp = readl(base + 8); /* DSPLLCTRL2 */
+ tmp = readl(base + 4); /* DSPLLCTRL2 */
tmp |= SC_DSPLLCTRL2_K_LD;
- writel(tmp, base + 8);
+ writel(tmp, base + 4);
iounmap(base);
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
+#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
+#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
void uniphier_ld11_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
+#include <linux/delay.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
+#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
+#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
+#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
+#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
+#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
+#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
+#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
+
void uniphier_ld20_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/*
+ * Copyright (C) 2017 Socionext Inc.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/delay.h>
+
#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
+#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
+#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
+#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
+#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
+#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
+#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
+#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
+#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
+#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
void uniphier_pxs3_pll_init(void)
{
+ uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ /* do nothing for SPLL */
+ uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ mdelay(1);
+
+ uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+
+ uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+ uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+ uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
}
/* necessary for ROM boot ?? */
/* system bus output enable */
writel(0x17, PC0CTRL);
+
+ uniphier_pin_init("system_bus_grp"); /* PXs3 */
}
#define SC_BASE_ADDR 0x61840000
-/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
-#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
-#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
-
-/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
-
-/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
-
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
+CONFIG_NAND=y
CONFIG_NAND_DENALI=y
+CONFIG_NAND_DENALI_DT=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
+CONFIG_NAND=y
CONFIG_NAND_DENALI=y
+CONFIG_NAND_DENALI_DT=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
+CONFIG_NAND=y
CONFIG_NAND_DENALI=y
+CONFIG_NAND_DENALI_DT=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_NAND=y
+CONFIG_NAND_DENALI=y
+CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
obj-y += clk-uniphier-core.o
+obj-y += clk-uniphier-sys.o
obj-y += clk-uniphier-mio.o
}
static const struct udevice_id uniphier_clk_match[] = {
+ /* System clock */
+ {
+ .compatible = "socionext,uniphier-ld4-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-clock",
+ .data = (ulong)&uniphier_ld20_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-clock",
+ .data = (ulong)&uniphier_ld20_sys_clk_data,
+ },
+ /* Media I/O clock */
{
.compatible = "socionext,uniphier-ld4-mio-clock",
.data = (ulong)&uniphier_mio_clk_data,
--- /dev/null
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "clk-uniphier.h"
+
+const struct uniphier_clk_gate_data uniphier_pxs2_sys_clk_gate[] = {
+ UNIPHIER_CLK_GATE(8, 0x2104, 10), /* stdmac */
+ UNIPHIER_CLK_GATE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
+ UNIPHIER_CLK_GATE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
+ UNIPHIER_CLK_GATE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
+ UNIPHIER_CLK_GATE(16, 0x2104, 19), /* usb30-phy (PXs2) */
+ UNIPHIER_CLK_GATE(20, 0x2104, 20), /* usb31-phy (PXs2) */
+ UNIPHIER_CLK_END
+};
+
+const struct uniphier_clk_data uniphier_pxs2_sys_clk_data = {
+ .gate = uniphier_pxs2_sys_clk_gate,
+};
+
+const struct uniphier_clk_gate_data uniphier_ld20_sys_clk_gate[] = {
+ UNIPHIER_CLK_GATE(8, 0x210c, 8), /* stdmac */
+ UNIPHIER_CLK_GATE(14, 0x210c, 14), /* usb30 (LD20) */
+ UNIPHIER_CLK_GATE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
+ UNIPHIER_CLK_GATE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
+ UNIPHIER_CLK_END
+};
+
+const struct uniphier_clk_data uniphier_ld20_sys_clk_data = {
+ .gate = uniphier_ld20_sys_clk_gate,
+};
.rates = {(_reg),}, \
}
+extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data;
+extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data;
extern const struct uniphier_clk_data uniphier_mio_clk_data;
#endif /* __CLK_UNIPHIER_H__ */
return 0;
}
}
+
+int ofnode_read_resource_byname(ofnode node, const char *name,
+ struct resource *res)
+{
+ int index;
+
+ index = ofnode_stringlist_search(node, "reg-names", name);
+ if (index < 0)
+ return index;
+
+ return ofnode_read_resource(node, index, res);
+}
{
return ofnode_read_resource(dev_ofnode(dev), index, res);
}
+
+int dev_read_resource_byname(struct udevice *dev, const char *name,
+ struct resource *res)
+{
+ return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
+}
help
Enable support for the Denali NAND controller.
+config NAND_DENALI_DT
+ bool "Support Denali NAND controller as a DT device"
+ depends on NAND_DENALI && OF_CONTROL && DM
+ help
+ Enable the driver for NAND flash on platforms using a Denali NAND
+ controller as a DT device.
+
config SYS_NAND_DENALI_64BIT
bool "Use 64-bit variant of Denali NAND controller"
depends on NAND_DENALI
obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_NAND_DENALI) += denali.o
+obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
static struct nand_ecclayout nand_oob;
-static int denali_init(struct denali_nand_info *denali)
+int denali_init(struct denali_nand_info *denali)
{
struct mtd_info *mtd = nand_to_mtd(&denali->nand);
int ret;
return ret;
}
+#ifndef CONFIG_NAND_DENALI_DT
static int __board_nand_init(void)
{
struct denali_nand_info *denali;
if (__board_nand_init() < 0)
pr_warn("Failed to initialize Denali NAND controller.\n");
}
+#endif
uint32_t max_banks;
};
+int denali_init(struct denali_nand_info *denali);
+
#endif /* __DENALI_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include "denali.h"
+
+static const struct udevice_id denali_nand_dt_ids[] = {
+ {
+ .compatible = "altr,socfpga-denali-nand",
+ },
+ {
+ .compatible = "socionext,uniphier-denali-nand-v5a",
+ },
+ {
+ .compatible = "socionext,uniphier-denali-nand-v5b",
+ },
+ { /* sentinel */ }
+};
+
+static int denali_dt_probe(struct udevice *dev)
+{
+ struct denali_nand_info *denali = dev_get_priv(dev);
+ struct resource res;
+ int ret;
+
+ ret = dev_read_resource_byname(dev, "denali_reg", &res);
+ if (ret)
+ return ret;
+
+ denali->flash_reg = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "nand_data", &res);
+ if (ret)
+ return ret;
+
+ denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res));
+
+ return denali_init(denali);
+}
+
+U_BOOT_DRIVER(denali_nand_dt) = {
+ .name = "denali-nand-dt",
+ .id = UCLASS_MISC,
+ .of_match = denali_nand_dt_ids,
+ .probe = denali_dt_probe,
+ .priv_auto_alloc_size = sizeof(struct denali_nand_info),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(denali_nand_dt),
+ &dev);
+ if (ret && ret != -ENODEV)
+ printf("Failed to initialize Denali NAND controller. (error %d)\n",
+ ret);
+}
UNIPHIER_RESET_END,
};
+static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
+ UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
+ UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
+ UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
+ UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */
+ UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */
+ UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY */
+ UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY */
+ UNIPHIER_RESET_END,
+};
+
/* Media I/O reset data */
#define UNIPHIER_MIO_RESET_SD(id, ch) \
UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
.compatible = "socionext,uniphier-ld20-reset",
.data = (ulong)uniphier_ld20_sys_reset_data,
},
+ {
+ .compatible = "socionext,uniphier-pxs3-reset",
+ .data = (ulong)uniphier_pxs3_sys_reset_data,
+ },
/* Media I/O reset */
{
.compatible = "socionext,uniphier-ld4-mio-reset",
.data = (ulong)uniphier_mio_reset_data,
},
{
- .compatible = "socionext,uniphier-ld20-mio-reset",
+ .compatible = "socionext,uniphier-ld11-sd-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-sd-reset",
+ .data = (ulong)uniphier_mio_reset_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs3-sd-reset",
.data = (ulong)uniphier_mio_reset_data,
},
/* Peripheral reset */
.compatible = "socionext,uniphier-ld20-peri-reset",
.data = (ulong)uniphier_pro4_peri_reset_data,
},
+ {
+ .compatible = "socionext,uniphier-pxs3-peri-reset",
+ .data = (ulong)uniphier_pro4_peri_reset_data,
+ },
{ /* sentinel */ }
};
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
-
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
bool ofnode_pre_reloc(ofnode node);
int ofnode_read_resource(ofnode node, uint index, struct resource *res);
+int ofnode_read_resource_byname(ofnode node, const char *name,
+ struct resource *res);
#endif
/**
* dev_read_resource() - obtain an indexed resource from a device.
*
- * @dev: devuce to examine
+ * @dev: device to examine
* @index index of the resource to retrieve (0 = first)
* @res returns the resource
* @return 0 if ok, negative on error
*/
int dev_read_resource(struct udevice *dev, uint index, struct resource *res);
+/**
+ * dev_read_resource_byname() - obtain a named resource from a device.
+ *
+ * @dev: device to examine
+ * @name: name of the resource to retrieve
+ * @res: returns the resource
+ * @return 0 if ok, negative on error
+ */
+int dev_read_resource_byname(struct udevice *dev, const char *name,
+ struct resource *res);
+
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
static inline int dev_read_u32_default(struct udevice *dev,
return ofnode_read_resource(dev_ofnode(dev), index, res);
}
+static inline int dev_read_resource_byname(struct udevice *dev,
+ const char *name,
+ struct resource *res)
+{
+ return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
+}
+
#endif /* CONFIG_DM_DEV_READ_INLINE */
/**
projects / u-boot / commitdiff