powerpc/t4240qds: fix offset of serdes when checking reference clock

T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 8258ab3805009cd148dd9607a78f5acd556ddef4..dfb370e051b295d64226f203b4be23ed297e9e53 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs {
 #endif
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET   0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET  0xEB000
+#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET  0xEC000
+#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET  0xED000
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET             0xFC000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET         0x100000
@@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_ADDR \

diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index c5161c80b69e10288b69673b67f6c8da3fa71f49..6205fea35e72dc9fbaad6ec18e567997212c7d7d 100644 (file)
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -644,9 +644,10 @@ unsigned long get_board_ddr_clk(void)
 int misc_init_r(void)
 {
        u8 sw;
-       serdes_corenet_t *srds_regs =
-               (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       serdes_corenet_t *srds_regs;
        u32 actual[MAX_SERDES];
+       u32 pllcr0, expected;
        unsigned int i;
 
        sw = QIXIS_READ(brdcfg[2]);
@@ -669,8 +670,9 @@ int misc_init_r(void)
        }
 
        for (i = 0; i < MAX_SERDES; i++) {
-               u32 pllcr0 = srds_regs->bank[i].pllcr0;
-               u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+               srds_regs = srds_base + i * 0x1000;
+               pllcr0 = srds_regs->bank[0].pllcr0;
+               expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
                if (expected != actual[i]) {
                        printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
                               i + 1, serdes_clock_to_string(expected),