struct mxs_dma_desc     *desc;
 };
 
+#if defined(CONFIG_MX23)
+static const unsigned int mxsmmc_id_offset = 1;
+#elif defined(CONFIG_MX28)
+static const unsigned int mxsmmc_id_offset = 0;
+#endif
+
 #define        MXSMMC_MAX_TIMEOUT      10000
 #define MXSMMC_SMALL_TRANSFER  512
 
        priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
                                (data_count << MXS_DMA_DESC_BYTES_OFFSET);
 
-       dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
+       dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset;
        mxs_dma_desc_append(dmach, priv->desc);
        if (mxs_dma_go(dmach)) {
                bounce_buffer_stop(&bbstate);
                }
 
                ctrl0 |= SSP_CTRL0_DATA_XFER;
+
+               reg = data->blocksize * data->blocks;
+#if defined(CONFIG_MX23)
+               ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
+
+               clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
+                       SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
+                       ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
+                       ((ffs(data->blocksize) - 1) <<
+                               SSP_CMD0_BLOCK_SIZE_OFFSET));
+#elif defined(CONFIG_MX28)
+               writel(reg, &ssp_regs->hw_ssp_xfer_size);
+
                reg = ((data->blocks - 1) <<
                        SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
                        ((ffs(data->blocksize) - 1) <<
                        SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
                writel(reg, &ssp_regs->hw_ssp_block_size);
-
-               reg = data->blocksize * data->blocks;
-               writel(reg, &ssp_regs->hw_ssp_xfer_size);
+#endif
        }
 
        /* Kick off the command */
                return -ENOMEM;
        }
 
-       ret = mxs_dma_init_channel(id);
+       ret = mxs_dma_init_channel(id + mxsmmc_id_offset);
        if (ret)
                return ret;