]> git.sur5r.net Git - u-boot/commitdiff
mpc512x: use common code for clock setting for all mpc512x boards
authorAnatolij Gustschin <agust@denx.de>
Fri, 8 Feb 2013 00:03:45 +0000 (00:03 +0000)
committerWolfgang Denk <wd@denx.de>
Sat, 9 Mar 2013 07:22:23 +0000 (08:22 +0100)
Only define enabled clocks in the config file and enable
the clocks in common code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Wolfgang Denk <wd@denx.de>
arch/powerpc/cpu/mpc512x/cpu_init.c
board/davedenx/aria/aria.c
board/esd/mecp5123/mecp5123.c
board/freescale/mpc5121ads/mpc5121ads.c
board/pdm360ng/pdm360ng.c
include/configs/aria.h
include/configs/mecp5123.h
include/configs/mpc5121ads.h
include/configs/pdm360ng.h

index ac2605a53de6827135a893dbcb0eb438f42ba061..2f6a14fa69efab2bf05281de75ee247dd758bd6b 100644 (file)
@@ -180,6 +180,15 @@ void cpu_init_f (volatile immap_t * im)
         * during FLASH chip identification etc.
         */
        setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
+
+       /*
+        * Enable clocks
+        */
+       out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+       out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+       setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
 }
 
 int cpu_init_r (void)
index 04912b8d63b78462aadaa42cf8668d4b346d9b61..229025735826fdbed2b69f8f265aab28210ca4e8 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
-                        CLOCK_SCCR1_LPC_EN |                           \
-                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
-                        CLOCK_SCCR1_PSCFIFO_EN |                       \
-                        CLOCK_SCCR1_DDR_EN |                           \
-                        CLOCK_SCCR1_FEC_EN |                           \
-                        CLOCK_SCCR1_NFC_EN |                           \
-                        CLOCK_SCCR1_PATA_EN |                          \
-                        CLOCK_SCCR1_PCI_EN |                           \
-                        CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_MEM_EN |           \
-                        CLOCK_SCCR2_SPDIF_EN |         \
-                        CLOCK_SCCR2_DIU_EN |           \
-                        CLOCK_SCCR2_I2C_EN)
-
-int board_early_init_f(void)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-       /*
-        * Enable clocks
-        */
-       out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
-       out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
-       setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
-       return 0;
-}
-
 phys_size_t initdram (int board_type)
 {
        return fixed_sdram(NULL, NULL, 0);
index 19e6e1f96b3e7dd071c7268afb5c912ce9bec9a6..e38678fc299deae5edb6e4c6ec8db926f896d78c 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
-                        CLOCK_SCCR1_LPC_EN |                           \
-                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
-                        CLOCK_SCCR1_PSCFIFO_EN |                       \
-                        CLOCK_SCCR1_DDR_EN |                           \
-                        CLOCK_SCCR1_FEC_EN |                           \
-                        CLOCK_SCCR1_NFC_EN |                           \
-                        CLOCK_SCCR1_PCI_EN |                           \
-                        CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_MEM_EN |   \
-                        CLOCK_SCCR2_I2C_EN)
-
 int eeprom_write_enable(unsigned dev_addr, int state)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
@@ -74,15 +60,6 @@ int board_early_init_f(void)
                 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
        sync_law(&im->sysconf.lpbaw);
 
-       /*
-        * Enable clocks
-        */
-       out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
-       out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
-       setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
        /*
         * Configure MSCAN clocks
         */
index 4b58dbcba931823f670c83b9b400336ea60e62eb..33a8aa51847d4e91b6287889349c11f6f9f5e988 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
-                        CLOCK_SCCR1_DDR_EN |                           \
-                        CLOCK_SCCR1_FEC_EN |                           \
-                        CLOCK_SCCR1_LPC_EN |                           \
-                        CLOCK_SCCR1_NFC_EN |                           \
-                        CLOCK_SCCR1_PATA_EN |                          \
-                        CLOCK_SCCR1_PCI_EN |                           \
-                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
-                        CLOCK_SCCR1_PSCFIFO_EN |                       \
-                        CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_DIU_EN |           \
-                        CLOCK_SCCR2_I2C_EN |           \
-                        CLOCK_SCCR2_MEM_EN |           \
-                        CLOCK_SCCR2_SPDIF_EN |         \
-                        CLOCK_SCCR2_USB1_EN |          \
-                        CLOCK_SCCR2_USB2_EN)
-
 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
 
 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
@@ -83,8 +64,6 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
 
 int board_early_init_f(void)
 {
-       volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-
        /*
         * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
         *
@@ -102,16 +81,6 @@ int board_early_init_f(void)
                out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
        }
 #endif
-
-       /*
-        * Enable clocks
-        */
-       out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
-       out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
-       setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
        return 0;
 }
 
index 9a164eeff0a11d453805c2c8fde786be4bf5ce3d..a1f2d5e49935663410ea8491e775c914de43df8e 100644 (file)
@@ -44,37 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
 extern flash_info_t flash_info[];
 ulong flash_get_size (phys_addr_t base, int banknum);
 
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
-                        CLOCK_SCCR1_LPC_EN |                           \
-                        CLOCK_SCCR1_NFC_EN |                           \
-                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
-                        CLOCK_SCCR1_PSCFIFO_EN |                       \
-                        CLOCK_SCCR1_DDR_EN |                           \
-                        CLOCK_SCCR1_FEC_EN |                           \
-                        CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_MEM_EN |           \
-                        CLOCK_SCCR2_SPDIF_EN |         \
-                        CLOCK_SCCR2_DIU_EN |           \
-                        CLOCK_SCCR2_I2C_EN)
-
-int board_early_init_f(void)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-       /*
-        * Enable clocks
-        */
-       out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
-       out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
-       setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
-#endif
-
-       return 0;
-}
-
 sdram_conf_t mddrc_config[] = {
        {
                (512 << 20),    /* 512 MB RAM configuration */
index 6b6e400b5573b56f4a267447fff15281776efe60..b4253996a01b0add87b9eaa5d391e3f0ce7948ee 100644 (file)
@@ -64,7 +64,6 @@
 
 #define CONFIG_SYS_MPC512X_CLKIN       33000000        /* in Hz */
 
-#define CONFIG_BOARD_EARLY_INIT_F              /* call board_early_init_f() */
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_SYS_IMMR                        0x80000000
 #define FSL_ATA_CTRL_DMA_WRITE         0x02000000
 #define FSL_ATA_CTRL_IORDY_EN          0x01000000
 
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
+                        CLOCK_SCCR1_LPC_EN |                           \
+                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
+                        CLOCK_SCCR1_PSCFIFO_EN |                       \
+                        CLOCK_SCCR1_DDR_EN |                           \
+                        CLOCK_SCCR1_FEC_EN |                           \
+                        CLOCK_SCCR1_NFC_EN |                           \
+                        CLOCK_SCCR1_PATA_EN |                          \
+                        CLOCK_SCCR1_PCI_EN |                           \
+                        CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_MEM_EN |           \
+                        CLOCK_SCCR2_SPDIF_EN |         \
+                        CLOCK_SCCR2_DIU_EN |           \
+                        CLOCK_SCCR2_I2C_EN)
+
 #endif /* __CONFIG_H */
index 1e09ff2230b1565954ceb358038965a26994a223..af302573e6782db8edeb550a30cc6c1a6664a923 100644 (file)
 #define CONSOLE_FIFO_RX_SIZE   FIFOC_PSC3_RX_SIZE
 #define CONSOLE_FIFO_RX_ADDR   FIFOC_PSC3_RX_ADDR
 
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
+                        CLOCK_SCCR1_LPC_EN |                           \
+                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
+                        CLOCK_SCCR1_PSCFIFO_EN |                       \
+                        CLOCK_SCCR1_DDR_EN |                           \
+                        CLOCK_SCCR1_FEC_EN |                           \
+                        CLOCK_SCCR1_NFC_EN |                           \
+                        CLOCK_SCCR1_PCI_EN |                           \
+                        CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_MEM_EN |   \
+                        CLOCK_SCCR2_I2C_EN)
+
+
 #define CONFIG_CMDLINE_EDITING 1       /* add command line history     */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
index a64df61fe5c2f2fcecc30dc6af0c1728bad517b7..6e6af62ccad5b7d5ca5a3da7c2ecdd07fa714ade 100644 (file)
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
+                        CLOCK_SCCR1_DDR_EN |                           \
+                        CLOCK_SCCR1_FEC_EN |                           \
+                        CLOCK_SCCR1_LPC_EN |                           \
+                        CLOCK_SCCR1_NFC_EN |                           \
+                        CLOCK_SCCR1_PATA_EN |                          \
+                        CLOCK_SCCR1_PCI_EN |                           \
+                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
+                        CLOCK_SCCR1_PSCFIFO_EN |                       \
+                        CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_DIU_EN |           \
+                        CLOCK_SCCR2_I2C_EN |           \
+                        CLOCK_SCCR2_MEM_EN |           \
+                        CLOCK_SCCR2_SPDIF_EN |         \
+                        CLOCK_SCCR2_USB1_EN |          \
+                        CLOCK_SCCR2_USB2_EN)
+
 /*
  * PCI
  */
index 07731217bcb30dcea45f112e4035b1a37ccdc941..306abcc8e1a4697266b38ef58ef58472901a628f 100644 (file)
@@ -68,7 +68,6 @@
 
 #define CONFIG_SYS_MPC512X_CLKIN       33333333        /* in Hz */
 
-#define CONFIG_BOARD_EARLY_INIT_F      /* call board_early_init_f() */
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_SYS_IMMR                        0x80000000
 #define CONSOLE_FIFO_RX_SIZE   FIFOC_PSC6_RX_SIZE
 #define CONSOLE_FIFO_RX_ADDR   FIFOC_PSC6_RX_ADDR
 
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN        (CLOCK_SCCR1_CFG_EN |                           \
+                        CLOCK_SCCR1_LPC_EN |                           \
+                        CLOCK_SCCR1_NFC_EN |                           \
+                        CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
+                        CLOCK_SCCR1_PSCFIFO_EN |                       \
+                        CLOCK_SCCR1_DDR_EN |                           \
+                        CLOCK_SCCR1_FEC_EN |                           \
+                        CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN        (CLOCK_SCCR2_MEM_EN |           \
+                        CLOCK_SCCR2_SPDIF_EN |         \
+                        CLOCK_SCCR2_DIU_EN |           \
+                        CLOCK_SCCR2_I2C_EN)
+
 /*
  * Used PSC UART devices
  */