sunxi: dram: Respect the DDR3 reset timing requirements

The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.

This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index dc79d1c8ba3e559844937238e4768804d3e15692..a632926fa73a62c24c2a89b17d65772bf13fa86f 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -48,6 +48,11 @@ static void await_completion(u32 *reg, u32 mask)
        }
 }
 
+/*
+ * This performs the external DRAM reset by driving the RESET pin low and
+ * then high again. According to the DDR3 spec, the RESET pin needs to be
+ * kept low for at least 200 us.
+ */
 static void mctl_ddr3_reset(void)
 {
        struct sunxi_dram_reg *dram =
@@ -64,13 +69,13 @@ static void mctl_ddr3_reset(void)
        if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
            CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
                setbits_le32(&dram->mcr, DRAM_MCR_RESET);
-               udelay(2);
+               udelay(200);
                clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
        } else
 #endif
        {
                clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-               udelay(2);
+               udelay(200);
                setbits_le32(&dram->mcr, DRAM_MCR_RESET);
        }
 }