#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
/* MDIO module input frequency */
+#ifdef CONFIG_SOC_K2G
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk))
+#else
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+#endif
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
if (cpu_is_k2hk())
freq = pll_freq_get(DDR3B_PLL);
break;
+ case uart_pll_clk:
+ if (cpu_is_k2g())
+ freq = pll_freq_get(UART_PLL);
+ break;
case sys_clk0_1_clk:
case sys_clk0_clk:
freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
if (argc < 2)
return CMD_RET_USAGE;
- freq = clk_get_rate(sys_clk0_6_clk);
+ freq = CONFIG_SYS_HZ_CLOCK;
addr = simple_strtoul(argv[1], NULL, 16);
#define DEV_SUPPORTED_SPEEDS 0xfff
#define ARM_SUPPORTED_SPEEDS 0xfff
+#define KS2_CLK1_6 sys_clk0_6_clk
+
#endif
CLK(17, sys_clk1_6_clk)\
CLK(18, sys_clk1_12_clk)\
CLK(19, sys_clk2_clk)\
- CLK(20, sys_clk3_clk)
+ CLK(20, sys_clk3_clk)\
+ CLK(21, uart_pll_clk)
#include <asm/types.h>
tetris_clk,
ddr3a_clk,
ddr3b_clk,
+ uart_clk,
ext_clk_count /* number of external clocks */
};
#include <common.h>
#include <asm/arch/clock.h>
+#define SYS_CLK 24000000
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = SYS_CLK,
+ [pa_clk] = SYS_CLK,
+ [tetris_clk] = SYS_CLK,
+ [ddr3a_clk] = SYS_CLK,
+ [uart_clk] = SYS_CLK,
+};
+
static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_CONS_INDEX 1
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2
+#endif
+
/* SPI Configuration */
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
+#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
+#endif
#endif /* __CONFIG_KS2_EVM_H */