nios2: enable device tree control of U-Boot

This patch adds device tree control of U-Boot to nios2 boards.
The example dts is taken from Linux kernel.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/nios2/dts/.gitignore b/arch/nios2/dts/.gitignore
new file mode 100644 (file)
index 0000000..b60ed20
--- /dev/null
+++ b/arch/nios2/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb

diff --git a/arch/nios2/dts/3c120_devboard.dts b/arch/nios2/dts/3c120_devboard.dts
new file mode 100644 (file)
index 0000000..02524ab
--- /dev/null
+++ b/arch/nios2/dts/3c120_devboard.dts
@@ -0,0 +1,153 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This file is generated by sopc2dts.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+       model = "altr,qsys_ghrd_3c120";
+       compatible = "altr,qsys_ghrd_3c120";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu: cpu@0x0 {
+                       device_type = "cpu";
+                       compatible = "altr,nios2-1.0";
+                       reg = <0x00000000>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       clock-frequency = <125000000>;
+                       dcache-line-size = <32>;
+                       icache-line-size = <32>;
+                       dcache-size = <32768>;
+                       icache-size = <32768>;
+                       altr,implementation = "fast";
+                       altr,pid-num-bits = <8>;
+                       altr,tlb-num-ways = <16>;
+                       altr,tlb-num-entries = <128>;
+                       altr,tlb-ptr-sz = <7>;
+                       altr,has-div = <1>;
+                       altr,has-mul = <1>;
+                       altr,reset-addr = <0xc2800000>;
+                       altr,fast-tlb-miss-addr = <0xc7fff400>;
+                       altr,exception-addr = <0xd0000020>;
+                       altr,has-initda = <1>;
+                       altr,has-mmu = <1>;
+               };
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x10000000 0x08000000>,
+                       <0x07fff400 0x00000400>;
+       };
+
+       sopc@0 {
+               device_type = "soc";
+               ranges;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "altr,avalon", "simple-bus";
+               bus-frequency = <125000000>;
+
+               pb_cpu_to_io: bridge@0x8000000 {
+                       compatible = "simple-bus";
+                       reg = <0x08000000 0x00800000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x00002000 0x08002000 0x00002000>,
+                               <0x00004000 0x08004000 0x00000400>,
+                               <0x00004400 0x08004400 0x00000040>,
+                               <0x00004800 0x08004800 0x00000040>,
+                               <0x00004c80 0x08004c80 0x00000020>,
+                               <0x00004d50 0x08004d50 0x00000008>,
+                               <0x00008000 0x08008000 0x00000020>,
+                               <0x00400000 0x08400000 0x00000020>;
+
+                       timer_1ms: timer@0x400000 {
+                               compatible = "altr,timer-1.0";
+                               reg = <0x00400000 0x00000020>;
+                               interrupt-parent = <&cpu>;
+                               interrupts = <11>;
+                               clock-frequency = <125000000>;
+                       };
+
+                       timer_0: timer@0x8000 {
+                               compatible = "altr,timer-1.0";
+                               reg = < 0x00008000 0x00000020 >;
+                               interrupt-parent = < &cpu >;
+                               interrupts = < 5 >;
+                               clock-frequency = < 125000000 >;
+                       };
+
+                       jtag_uart: serial@0x4d50 {
+                               compatible = "altr,juart-1.0";
+                               reg = <0x00004d50 0x00000008>;
+                               interrupt-parent = <&cpu>;
+                               interrupts = <1>;
+                       };
+
+                       tse_mac: ethernet@0x4000 {
+                               compatible = "altr,tse-1.0";
+                               reg = <0x00004000 0x00000400>,
+                                       <0x00004400 0x00000040>,
+                                       <0x00004800 0x00000040>,
+                                       <0x00002000 0x00002000>;
+                               reg-names = "control_port", "rx_csr", "tx_csr", "s1";
+                               interrupt-parent = <&cpu>;
+                               interrupts = <2 3>;
+                               interrupt-names = "rx_irq", "tx_irq";
+                               rx-fifo-depth = <8192>;
+                               tx-fifo-depth = <8192>;
+                               max-frame-size = <1518>;
+                               local-mac-address = [ 00 00 00 00 00 00 ];
+                               phy-mode = "rgmii-id";
+                               phy-handle = <&phy0>;
+                               tse_mac_mdio: mdio {
+                                       compatible = "altr,tse-mdio";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       phy0: ethernet-phy@18 {
+                                               reg = <18>;
+                                               device_type = "ethernet-phy";
+                                       };
+                               };
+                       };
+
+                       uart: serial@0x4c80 {
+                               compatible = "altr,uart-1.0";
+                               reg = <0x00004c80 0x00000020>;
+                               interrupt-parent = <&cpu>;
+                               interrupts = <10>;
+                               current-speed = <115200>;
+                               clock-frequency = <62500000>;
+                       };
+               };
+
+               cfi_flash_64m: flash@0x0 {
+                       compatible = "cfi-flash";
+                       reg = <0x00000000 0x04000000>;
+                       bank-width = <2>;
+                       device-width = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@800000 {
+                               reg = <0x00800000 0x01e00000>;
+                               label = "JFFS2 Filesystem";
+                       };
+               };
+       };
+
+       chosen {
+               bootargs = "debug console=ttyJ0,115200";
+       };
+};

diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile
new file mode 100644 (file)
index 0000000..b40eca9
--- /dev/null
+++ b/arch/nios2/dts/Makefile
@@ -0,0 +1,11 @@
+dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+       @:
+
+clean-files := *.dtb

diff --git a/arch/nios2/dts/include/dt-bindings b/arch/nios2/dts/include/dt-bindings
new file mode 120000 (symlink)
index 0000000..0cecb3d
--- /dev/null
+++ b/arch/nios2/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file

diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig
index f8d282168f6eb7e34a5c11d4e0d27faf7c772ae0..09cc51e1cb264cf569a9119421bfa191516bf298 100644 (file)
--- a/configs/nios2-generic_defconfig
+++ b/configs/nios2-generic_defconfig
@@ -1,5 +1,6 @@
 CONFIG_NIOS2=y
 CONFIG_TARGET_NIOS2_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
@@ -10,4 +11,5 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y