]> git.sur5r.net Git - u-boot/commitdiff
sunxi: Add OrangePi PC 2 initial support
authorAndre Przywara <andre.przywara@arm.com>
Thu, 16 Feb 2017 01:20:29 +0000 (01:20 +0000)
committerJagan Teki <jagan@amarulasolutions.com>
Wed, 5 Apr 2017 09:33:17 +0000 (15:03 +0530)
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.

Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[squash the commits, update the commit message]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
arch/arm/dts/Makefile
arch/arm/dts/sun50i-h5-orangepi-pc2.dts [new file with mode: 0644]
board/sunxi/MAINTAINERS
configs/orangepi_pc2_defconfig [new file with mode: 0644]

index 462c690946cb12e7ed84396c23f899bd5a0c4f22..0286fb3682b2ed7dc08b0ab0d91d989d80bda5fd 100644 (file)
@@ -299,6 +299,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
        sun8i-h3-orangepi-plus.dtb \
        sun8i-h3-orangepi-plus2e.dtb \
        sun8i-h3-nanopi-neo.dtb
+dtb-$(CONFIG_MACH_SUN50I_H5) += \
+       sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
        sun50i-a64-pine64-plus.dtb \
        sun50i-a64-pine64.dtb
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
new file mode 100644 (file)
index 0000000..de60f78
--- /dev/null
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+
+/ {
+       model = "OrangePi PC 2";
+       compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
+
+       cpus {
+               cpu@0 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       enable-method = "psci";
+               };
+               cpu@1 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       enable-method = "psci";
+               };
+               cpu@2 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       enable-method = "psci";
+               };
+               cpu@3 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       enable-method = "psci";
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               reg = <0x40000000 0x40000000>;
+       };
+
+       aliases {
+               serial0 = &uart0;
+               ethernet0 = &emac;
+       };
+
+       soc {
+               reg_vcc3v3: vcc3v3 {
+                       compatible = "regulator-fixed";
+                       regulator-name = "vcc3v3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+               };
+       };
+};
+
+&gic {
+       compatible = "arm,gic-400";
+};
+
+&mmc0 {
+       compatible = "allwinner,sun50i-h5-mmc",
+                    "allwinner,sun50i-a64-mmc",
+                    "allwinner,sun5i-a13-mmc";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+       vmmc-supply = <&reg_vcc3v3>;
+       bus-width = <4>;
+       cd-gpios = <&pio 5 6 0>;
+       cd-inverted;
+       status = "okay";
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins_a>;
+       status = "okay";
+};
+
+&usbphy {
+       status = "okay";
+};
+
+&ohci1 {
+       status = "okay";
+};
+
+&ehci1 {
+       status = "okay";
+};
+
+&emac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_rgmii_pins>;
+       phy-mode = "rgmii";
+       phy = <&phy1>;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};
index 2321b8b08fe9068724b181d3774aeafc21018b7a..3f211293feb65be09be4cee24a1561f7f7ec1af9 100644 (file)
@@ -242,6 +242,11 @@ M: Icenowy Zheng <icenowy@aosc.xyz>
 S:     Maintained
 F:     configs/orangepi_zero_defconfig
 
+ORANGEPI PC 2 BOARD
+M:     Andre Przywara <andre.przywara@arm.com>
+S:     Maintained
+F:     configs/orangepi_pc2_defconfig
+
 R16 EVB PARROT BOARD
 M:     Quentin Schulz <quentin.schulz@free-electrons.com>
 S:     Maintained
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
new file mode 100644 (file)
index 0000000..19a5c2b
--- /dev/null
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_SPL=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y