]> git.sur5r.net Git - u-boot/commitdiff
i2c, davinci: convert driver to new mutlibus/mutliadapter framework
authorVitaly Andrianov <vitalya@ti.com>
Fri, 4 Apr 2014 17:16:52 +0000 (13:16 -0400)
committerTom Rini <trini@ti.com>
Thu, 17 Apr 2014 21:24:38 +0000 (17:24 -0400)
    - add davinci driver to new multibus/multiadpater support
    - adapted all config files, which uses this driver

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
20 files changed:
arch/arm/cpu/arm926ejs/davinci/dm355.c
arch/arm/cpu/arm926ejs/davinci/dm365.c
arch/arm/cpu/arm926ejs/davinci/dm644x.c
arch/arm/cpu/arm926ejs/davinci/dm646x.c
drivers/i2c/Makefile
drivers/i2c/davinci_i2c.c
drivers/i2c/davinci_i2c.h
include/configs/cam_enc_4xx.h
include/configs/da830evm.h
include/configs/da850evm.h
include/configs/davinci_dm355evm.h
include/configs/davinci_dm355leopard.h
include/configs/davinci_dm365evm.h
include/configs/davinci_dm6467evm.h
include/configs/davinci_dvevm.h
include/configs/davinci_schmoogie.h
include/configs/davinci_sffsdr.h
include/configs/davinci_sonata.h
include/configs/ea20.h
include/configs/enbw_cmc.h

index 5f85162b8e00bbf8dc67a282f06f003ff412ab29..f9550a16d34a767fb2c43172830dc35f9c76977b 100644 (file)
@@ -19,7 +19,7 @@ void davinci_enable_uart0(void)
 }
 
 
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
 void davinci_enable_i2c(void)
 {
        lpsc_on(DAVINCI_LPSC_I2C);
index 0af2d0236d835fd01848c574aafb7a6e66b79ffb..f6ca527e74c1cee7f03ad027a456659d904b3dd3 100644 (file)
@@ -12,7 +12,7 @@ void davinci_enable_uart0(void)
        lpsc_on(DAVINCI_LPSC_UART0);
 }
 
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
 void davinci_enable_i2c(void)
 {
        lpsc_on(DAVINCI_LPSC_I2C);
index 788e57840f8bbc1e8701fe87a59f0e56269096e9..c58e271e2811c2931d438257e83065437013dfc0 100644 (file)
@@ -47,7 +47,7 @@ void davinci_enable_emac(void)
 }
 #endif
 
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
 void davinci_enable_i2c(void)
 {
        lpsc_on(DAVINCI_LPSC_I2C);
index 86a508f6a128fb48bccf8bacb3ad3ee6afa5750e..cfea8300def064af0ec54b6435b13be14a27da73 100644 (file)
@@ -18,7 +18,7 @@ void davinci_enable_emac(void)
 }
 #endif
 
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
+#ifdef CONFIG_SYS_I2C_DAVINCI
 void davinci_enable_i2c(void)
 {
        lpsc_on(DAVINCI_DM646X_LPSC_I2C);
index 36d5e5f1a2ee0b5dd2ab10fc7eaf02bcb2149efe..e33586d8a6b6ab9b8faa96b5c50ca8eb8d9e6f1a 100644 (file)
@@ -6,7 +6,6 @@
 #
 
 obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
-obj-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
 obj-$(CONFIG_DW_I2C) += designware_i2c.o
 obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
@@ -16,6 +15,7 @@ obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
 obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
 obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
index 6e5260c4825ea79664d0b26c73bcdaff8321919d..9ca99c4abd0b04d345c8251aef0203a3abc4c082 100644 (file)
@@ -1,8 +1,9 @@
 /*
  * TI DaVinci (TMS320DM644x) I2C driver.
  *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
  * --------------------------------------------------------
  *
  * SPDX-License-Identifier:    GPL-2.0+
 #include <i2c.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/i2c_defs.h>
+#include <asm/io.h>
 #include "davinci_i2c.h"
 
 #define CHECK_NACK() \
        do {\
                if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
-                       REG(I2C_CON) = 0;\
-                       return(1);\
-               }\
+                       REG(&(i2c_base->i2c_con)) = 0;\
+                       return 1;\
+               } \
        } while (0)
 
+static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);
 
-static int wait_for_bus(void)
+static int wait_for_bus(struct i2c_adapter *adap)
 {
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
        int     stat, timeout;
 
-       REG(I2C_STAT) = 0xffff;
+       REG(&(i2c_base->i2c_stat)) = 0xffff;
 
        for (timeout = 0; timeout < 10; timeout++) {
-               if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
-                       REG(I2C_STAT) = 0xffff;
-                       return(0);
+               stat = REG(&(i2c_base->i2c_stat));
+               if (!((stat) & I2C_STAT_BB)) {
+                       REG(&(i2c_base->i2c_stat)) = 0xffff;
+                       return 0;
                }
 
-               REG(I2C_STAT) = stat;
+               REG(&(i2c_base->i2c_stat)) = stat;
                udelay(50000);
        }
 
-       REG(I2C_STAT) = 0xffff;
-       return(1);
+       REG(&(i2c_base->i2c_stat)) = 0xffff;
+       return 1;
 }
 
 
-static int poll_i2c_irq(int mask)
+static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
 {
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
        int     stat, timeout;
 
        for (timeout = 0; timeout < 10; timeout++) {
                udelay(1000);
-               stat = REG(I2C_STAT);
-               if (stat & mask) {
-                       return(stat);
-               }
+               stat = REG(&(i2c_base->i2c_stat));
+               if (stat & mask)
+                       return stat;
        }
 
-       REG(I2C_STAT) = 0xffff;
-       return(stat | I2C_TIMEOUT);
+       REG(&(i2c_base->i2c_stat)) = 0xffff;
+       return stat | I2C_TIMEOUT;
 }
 
-
-void flush_rx(void)
+static void flush_rx(struct i2c_adapter *adap)
 {
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
+
        while (1) {
-               if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
+               if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
                        break;
 
-               REG(I2C_DRR);
-               REG(I2C_STAT) = I2C_STAT_RRDY;
+               REG(&(i2c_base->i2c_drr));
+               REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
                udelay(1000);
        }
 }
 
+static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
+       uint32_t        div, psc;
+
+       psc = 2;
+       /* SCLL + SCLH */
+       div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
+       REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
+       REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
+       REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
+
+       adap->speed     = speed;
+       return 0;
+}
 
-void i2c_init(int speed, int slaveadd)
+static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
-       u_int32_t       div, psc;
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
 
-       if (REG(I2C_CON) & I2C_CON_EN) {
-               REG(I2C_CON) = 0;
-               udelay (50000);
+       if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
+               REG(&(i2c_base->i2c_con)) = 0;
+               udelay(50000);
        }
 
-       psc = 2;
-       div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
-       REG(I2C_PSC) = psc;                     /* 27MHz / (2 + 1) = 9MHz */
-       REG(I2C_SCLL) = (div * 50) / 100;       /* 50% Duty */
-       REG(I2C_SCLH) = div - REG(I2C_SCLL);
+       davinci_i2c_setspeed(adap, speed);
 
-       REG(I2C_OA) = slaveadd;
-       REG(I2C_CNT) = 0;
+       REG(&(i2c_base->i2c_oa)) = slaveadd;
+       REG(&(i2c_base->i2c_cnt)) = 0;
 
        /* Interrupts must be enabled or I2C module won't work */
-       REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
+       REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
                I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
 
        /* Now enable I2C controller (get it out of reset) */
-       REG(I2C_CON) = I2C_CON_EN;
+       REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
 
        udelay(1000);
 }
 
-int i2c_set_bus_speed(unsigned int speed)
-{
-       i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
-       return 0;
-}
-
-int i2c_probe(u_int8_t chip)
+static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 {
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
        int     rc = 1;
 
-       if (chip == REG(I2C_OA)) {
-               return(rc);
-       }
+       if (chip == REG(&(i2c_base->i2c_oa)))
+               return rc;
 
-       REG(I2C_CON) = 0;
-       if (wait_for_bus()) {return(1);}
+       REG(&(i2c_base->i2c_con)) = 0;
+       if (wait_for_bus(adap))
+               return 1;
 
        /* try to read one byte from current (or only) address */
-       REG(I2C_CNT) = 1;
-       REG(I2C_SA) = chip;
-       REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
-       udelay (50000);
+       REG(&(i2c_base->i2c_cnt)) = 1;
+       REG(&(i2c_base->i2c_sa))  = chip;
+       REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+                                    I2C_CON_STP);
+       udelay(50000);
 
-       if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
+       if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
                rc = 0;
-               flush_rx();
-               REG(I2C_STAT) = 0xffff;
+               flush_rx(adap);
+               REG(&(i2c_base->i2c_stat)) = 0xffff;
        } else {
-               REG(I2C_STAT) = 0xffff;
-               REG(I2C_CON) |= I2C_CON_STP;
+               REG(&(i2c_base->i2c_stat)) = 0xffff;
+               REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
                udelay(20000);
-               if (wait_for_bus()) {return(1);}
+               if (wait_for_bus(adap))
+                       return 1;
        }
 
-       flush_rx();
-       REG(I2C_STAT) = 0xffff;
-       REG(I2C_CNT) = 0;
-       return(rc);
+       flush_rx(adap);
+       REG(&(i2c_base->i2c_stat)) = 0xffff;
+       REG(&(i2c_base->i2c_cnt)) = 0;
+       return rc;
 }
 
-
-int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+                               uint32_t addr, int alen, uint8_t *buf, int len)
 {
-       u_int32_t       tmp;
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
+       uint32_t        tmp;
        int             i;
 
        if ((alen < 0) || (alen > 2)) {
-               printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
-               return(1);
+               printf("%s(): bogus address length %x\n", __func__, alen);
+               return 1;
        }
 
-       if (wait_for_bus()) {return(1);}
+       if (wait_for_bus(adap))
+               return 1;
 
        if (alen != 0) {
                /* Start address phase */
                tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
-               REG(I2C_CNT) = alen;
-               REG(I2C_SA) = chip;
-               REG(I2C_CON) = tmp;
+               REG(&(i2c_base->i2c_cnt)) = alen;
+               REG(&(i2c_base->i2c_sa)) = chip;
+               REG(&(i2c_base->i2c_con)) = tmp;
 
-               tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+               tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
 
                CHECK_NACK();
 
                switch (alen) {
-                       case 2:
-                               /* Send address MSByte */
-                               if (tmp & I2C_STAT_XRDY) {
-                                       REG(I2C_DXR) = (addr >> 8) & 0xff;
-                               } else {
-                                       REG(I2C_CON) = 0;
-                                       return(1);
-                               }
-
-                               tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
-                               CHECK_NACK();
-                               /* No break, fall through */
-                       case 1:
-                               /* Send address LSByte */
-                               if (tmp & I2C_STAT_XRDY) {
-                                       REG(I2C_DXR) = addr & 0xff;
-                               } else {
-                                       REG(I2C_CON) = 0;
-                                       return(1);
-                               }
-
-                               tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
-
-                               CHECK_NACK();
-
-                               if (!(tmp & I2C_STAT_ARDY)) {
-                                       REG(I2C_CON) = 0;
-                                       return(1);
-                               }
+               case 2:
+                       /* Send address MSByte */
+                       if (tmp & I2C_STAT_XRDY) {
+                               REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
+                       } else {
+                               REG(&(i2c_base->i2c_con)) = 0;
+                               return 1;
+                       }
+
+                       tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+
+                       CHECK_NACK();
+                       /* No break, fall through */
+               case 1:
+                       /* Send address LSByte */
+                       if (tmp & I2C_STAT_XRDY) {
+                               REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
+                       } else {
+                               REG(&(i2c_base->i2c_con)) = 0;
+                               return 1;
+                       }
+
+                       tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
+                                          I2C_STAT_NACK | I2C_STAT_ARDY);
+
+                       CHECK_NACK();
+
+                       if (!(tmp & I2C_STAT_ARDY)) {
+                               REG(&(i2c_base->i2c_con)) = 0;
+                               return 1;
+                       }
                }
        }
 
        /* Address phase is over, now read 'len' bytes and stop */
        tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
-       REG(I2C_CNT) = len & 0xffff;
-       REG(I2C_SA) = chip;
-       REG(I2C_CON) = tmp;
+       REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
+       REG(&(i2c_base->i2c_sa)) = chip;
+       REG(&(i2c_base->i2c_con)) = tmp;
 
        for (i = 0; i < len; i++) {
-               tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
+               tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
+                                  I2C_STAT_ROVR);
 
                CHECK_NACK();
 
                if (tmp & I2C_STAT_RRDY) {
-                       buf[i] = REG(I2C_DRR);
+                       buf[i] = REG(&(i2c_base->i2c_drr));
                } else {
-                       REG(I2C_CON) = 0;
-                       return(1);
+                       REG(&(i2c_base->i2c_con)) = 0;
+                       return 1;
                }
        }
 
-       tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
+       tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
 
        CHECK_NACK();
 
        if (!(tmp & I2C_STAT_SCD)) {
-               REG(I2C_CON) = 0;
-               return(1);
+               REG(&(i2c_base->i2c_con)) = 0;
+               return 1;
        }
 
-       flush_rx();
-       REG(I2C_STAT) = 0xffff;
-       REG(I2C_CNT) = 0;
-       REG(I2C_CON) = 0;
+       flush_rx(adap);
+       REG(&(i2c_base->i2c_stat)) = 0xffff;
+       REG(&(i2c_base->i2c_cnt)) = 0;
+       REG(&(i2c_base->i2c_con)) = 0;
 
-       return(0);
+       return 0;
 }
 
-
-int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
+static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+                               uint32_t addr, int alen, uint8_t *buf, int len)
 {
-       u_int32_t       tmp;
+       struct i2c_regs *i2c_base = davinci_get_base(adap);
+       uint32_t        tmp;
        int             i;
 
        if ((alen < 0) || (alen > 2)) {
-               printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
-               return(1);
+               printf("%s(): bogus address length %x\n", __func__, alen);
+               return 1;
        }
        if (len < 0) {
-               printf("%s(): bogus length %x\n", __FUNCTION__, len);
-               return(1);
+               printf("%s(): bogus length %x\n", __func__, len);
+               return 1;
        }
 
-       if (wait_for_bus()) {return(1);}
+       if (wait_for_bus(adap))
+               return 1;
 
        /* Start address phase */
-       tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
-       REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
-       REG(I2C_SA) = chip;
-       REG(I2C_CON) = tmp;
+       tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+               I2C_CON_TRX | I2C_CON_STP;
+       REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
+               len & 0xffff : (len & 0xffff) + alen;
+       REG(&(i2c_base->i2c_sa)) = chip;
+       REG(&(i2c_base->i2c_con)) = tmp;
 
        switch (alen) {
-               case 2:
-                       /* Send address MSByte */
-                       tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+       case 2:
+               /* Send address MSByte */
+               tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
 
-                       CHECK_NACK();
+               CHECK_NACK();
 
-                       if (tmp & I2C_STAT_XRDY) {
-                               REG(I2C_DXR) = (addr >> 8) & 0xff;
-                       } else {
-                               REG(I2C_CON) = 0;
-                               return(1);
-                       }
-                       /* No break, fall through */
-               case 1:
-                       /* Send address LSByte */
-                       tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+               if (tmp & I2C_STAT_XRDY) {
+                       REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
+               } else {
+                       REG(&(i2c_base->i2c_con)) = 0;
+                       return 1;
+               }
+               /* No break, fall through */
+       case 1:
+               /* Send address LSByte */
+               tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
 
-                       CHECK_NACK();
+               CHECK_NACK();
 
-                       if (tmp & I2C_STAT_XRDY) {
-                               REG(I2C_DXR) = addr & 0xff;
-                       } else {
-                               REG(I2C_CON) = 0;
-                               return(1);
-                       }
+               if (tmp & I2C_STAT_XRDY) {
+                       REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
+               } else {
+                       REG(&(i2c_base->i2c_con)) = 0;
+                       return 1;
+               }
        }
 
        for (i = 0; i < len; i++) {
-               tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
+               tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
 
                CHECK_NACK();
 
-               if (tmp & I2C_STAT_XRDY) {
-                       REG(I2C_DXR) = buf[i];
-               } else {
-                       return(1);
-               }
+               if (tmp & I2C_STAT_XRDY)
+                       REG(&(i2c_base->i2c_dxr)) = buf[i];
+               else
+                       return 1;
        }
 
-       tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
+       tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
 
        CHECK_NACK();
 
        if (!(tmp & I2C_STAT_SCD)) {
-               REG(I2C_CON) = 0;
-               return(1);
+               REG(&(i2c_base->i2c_con)) = 0;
+               return 1;
        }
 
-       flush_rx();
-       REG(I2C_STAT) = 0xffff;
-       REG(I2C_CNT) = 0;
-       REG(I2C_CON) = 0;
+       flush_rx(adap);
+       REG(&(i2c_base->i2c_stat)) = 0xffff;
+       REG(&(i2c_base->i2c_cnt)) = 0;
+       REG(&(i2c_base->i2c_con)) = 0;
+
+       return 0;
+}
+
+static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
+{
+       switch (adap->hwadapnr) {
+#if I2C_BUS_MAX >= 3
+       case 2:
+               return (struct i2c_regs *)I2C2_BASE;
+#endif
+#if I2C_BUS_MAX >= 2
+       case 1:
+               return (struct i2c_regs *)I2C1_BASE;
+#endif
+       case 0:
+               return (struct i2c_regs *)I2C_BASE;
+
+       default:
+               printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+       }
 
-       return(0);
+       return NULL;
 }
+
+U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
+                        davinci_i2c_read, davinci_i2c_write,
+                        davinci_i2c_setspeed,
+                        CONFIG_SYS_DAVINCI_I2C_SPEED,
+                        CONFIG_SYS_DAVINCI_I2C_SLAVE,
+                        0)
+
+#if I2C_BUS_MAX >= 2
+U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
+                        davinci_i2c_read, davinci_i2c_write,
+                        davinci_i2c_setspeed,
+                        CONFIG_SYS_DAVINCI_I2C_SPEED1,
+                        CONFIG_SYS_DAVINCI_I2C_SLAVE1,
+                        1)
+#endif
+
+#if I2C_BUS_MAX >= 3
+U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
+                        davinci_i2c_read, davinci_i2c_write,
+                        davinci_i2c_setspeed,
+                        CONFIG_SYS_DAVINCI_I2C_SPEED2,
+                        CONFIG_SYS_DAVINCI_I2C_SLAVE2,
+                        2)
+#endif
index 79ff7a3d678a7679d86516e022dfee14005270e8..20d43424b9f99fa9e54ae54acf4e3fd3813db95e 100644 (file)
 #define I2C_WRITE              0
 #define I2C_READ               1
 
-#define        I2C_OA                  (I2C_BASE + 0x00)
-#define I2C_IE                 (I2C_BASE + 0x04)
-#define I2C_STAT               (I2C_BASE + 0x08)
-#define I2C_SCLL               (I2C_BASE + 0x0c)
-#define I2C_SCLH               (I2C_BASE + 0x10)
-#define I2C_CNT                        (I2C_BASE + 0x14)
-#define I2C_DRR                        (I2C_BASE + 0x18)
-#define I2C_SA                 (I2C_BASE + 0x1c)
-#define I2C_DXR                        (I2C_BASE + 0x20)
-#define I2C_CON                        (I2C_BASE + 0x24)
-#define I2C_IV                 (I2C_BASE + 0x28)
-#define I2C_PSC                        (I2C_BASE + 0x30)
+struct i2c_regs {
+       u32     i2c_oa;
+       u32     i2c_ie;
+       u32     i2c_stat;
+       u32     i2c_scll;
+       u32     i2c_sclh;
+       u32     i2c_cnt;
+       u32     i2c_drr;
+       u32     i2c_sa;
+       u32     i2c_dxr;
+       u32     i2c_con;
+       u32     i2c_iv;
+       u32     res_2c;
+       u32     i2c_psc;
+};
 
 /* I2C masks */
 
index 8182a7577bcdc2c26950e528474355810cf1d79d..d1a8ff2a82f0e494534dab5cde0a96d9296aeb22 100644 (file)
 #define CONFIG_RESET_PHY_R
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           400000
-#define CONFIG_SYS_I2C_SLAVE           0x10    /* SMBus host address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE           0x10    /* SMBus host address */
 
 /* NAND: socketed, two chipselects, normally 2 GBytes */
 #define CONFIG_NAND_DAVINCI
index c4cc62ecb41661883f52057228872d3aea4bf885..27171950a6c0e5673193e966a4981166d2475a7a 100644 (file)
 /*
  * I2C Configuration
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           25000 /* 100Kbps won't work, H/W bug */
-#define CONFIG_SYS_I2C_SLAVE           10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED     25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE     10 /* Bogus, master-only in U-Boot */
 
 /*
  * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
index 509fe20d2c2e8c87413cef06204357795c12bcc4..860a11dd2b3e43835bc3c43baf469434f3e6a57d 100644 (file)
 /*
  * I2C Configuration
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           25000
-#define CONFIG_SYS_I2C_SLAVE           10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           25000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 
 /*
index 6382e75b95e9f068bf0ddb77c5356750fca98385..c2e187e3de2826f4cdf0cf8aa67fa9d8a53282eb 100644 (file)
 #define DM9000_DATA                    (CONFIG_DM9000_BASE + 2)
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           400000
-#define CONFIG_SYS_I2C_SLAVE           0x10    /* SMBus host address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE           0x10    /* SMBus host address */
 
 /* NAND: socketed, two chipselects, normally 2 GBytes */
 #define CONFIG_NAND_DAVINCI
index 234bbc0996507c5e81edb8ffc05c971188922a23..5188fdf8785b91efcc5489126753c8dff119ebda 100644 (file)
 #define DM9000_DATA                    (CONFIG_DM9000_BASE + 16)
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           400000
-#define CONFIG_SYS_I2C_SLAVE           0x10
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE           0x10
 
 /* NAND */
 #define CONFIG_NAND_DAVINCI
index b547289d2d0dcaf62c7143b13164ff70ea30a071..c4fccfd39a4593a4a58b5ea484df0e77d3e8ecf5 100644 (file)
 #define CONFIG_NET_RETRY_COUNT 10
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           400000
-#define CONFIG_SYS_I2C_SLAVE           0x10    /* SMBus host address */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE           0x10    /* SMBus host address */
 
 /* NAND: socketed, two chipselects, normally 2 GBytes */
 #define CONFIG_NAND_DAVINCI
index 2132342eb7e102b7ae846db901f1196dab35d1fa..8a3c45334736f66a21c0b93fb2a4382dd4ead799 100644 (file)
@@ -60,10 +60,10 @@ extern unsigned int davinci_arm_clk_get(void);
 #define CONFIG_BAUDRATE                        115200
 
 /* I2C Configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           80000
-#define CONFIG_SYS_I2C_SLAVE           10
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           80000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE           10
 
 /* Network & Ethernet Configuration */
 #define CONFIG_DRIVER_TI_EMAC
index d8fa64600ae41cbafb19c59e6cbff2f57ef6a60b..9b3d0febc01eea814d0d815cd350da1abad4e275 100644 (file)
 /*===================*/
 /* I2C Configuration */
 /*===================*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           80000   /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10        /* Bogus, master-only in U-Boot */
 /*==================================*/
 /* Network & Ethernet Configuration */
 /*==================================*/
index f9a0a76d367a346de5bd9ccb461b6eee5a1d24f4..96c8fe2a4d419c240640c1117fbfadaa5f388734 100644 (file)
 /*===================*/
 /* I2C Configuration */
 /*===================*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           80000   /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
 /*==================================*/
 /* Network & Ethernet Configuration */
 /*==================================*/
index 44449df9cd8a3a830c8c17ad4983e15a27a8ceea..6e07cce766e28ce3c63df02243c062e795bed399 100644 (file)
 #define CONFIG_CONS_INDEX      1               /* use UART0 for console */
 #define CONFIG_BAUDRATE                115200          /* Default baud rate */
 /* I2C Configuration */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           80000   /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
 /* Network & Ethernet Configuration */
 #define CONFIG_DRIVER_TI_EMAC
 #define CONFIG_MII
index ac543f8d94292a95f7c5f7294903d20e45f15288..cd23aaca209b7589e210f22fb9f75f6d3e8964f1 100644 (file)
 /*===================*/
 /* I2C Configuration */
 /*===================*/
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           80000   /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_I2C_SLAVE           10      /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
 /*==================================*/
 /* Network & Ethernet Configuration */
 /*==================================*/
index 58e40ed888d97fd00f5811077824734d3da95423..1d50a37d2fc8be63be197af9a8aebb8defc715f2 100644 (file)
 /*
  * I2C Configuration
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 
 /*
  * Network & Ethernet Configuration
index 03b74a2dabe277c0bb286c7d5a6ccd5867849a83..30ca95f02d5c9a4cf2bf29a840d82899eb54a8c1 100644 (file)
 /*
  * I2C Configuration
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_DAVINCI_I2C
-#define CONFIG_SYS_I2C_SPEED           80000
-#define CONFIG_SYS_I2C_SLAVE           10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED           80000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 #define CONFIG_CMD_I2C