ARM: ls102xa: allow all the peripheral access permission as R/W.

The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 0533a8358013a712022ff54e1aea68e31d9af2e8..5e934da79738a1b62ff289f81b662b0d9dba77b0 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -21,6 +21,7 @@
 
 #define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_SCFG_ADDR               (CONFIG_SYS_IMMR + 0x00570000)

diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
new file mode 100644 (file)
index 0000000..b53f699
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_access {
+       CSU_NS_SUP_R = 0x08,
+       CSU_NS_SUP_W = 0x80,
+       CSU_NS_SUP_RW = 0x88,
+       CSU_NS_USER_R = 0x04,
+       CSU_NS_USER_W = 0x40,
+       CSU_NS_USER_RW = 0x44,
+       CSU_S_SUP_R = 0x02,
+       CSU_S_SUP_W = 0x20,
+       CSU_S_SUP_RW = 0x22,
+       CSU_S_USER_R = 0x01,
+       CSU_S_USER_W = 0x10,
+       CSU_S_USER_RW = 0x11,
+       CSU_ALL_RW = 0xff,
+};
+
+enum csu_cslx_ind {
+       CSU_CSLX_PCIE2_IO = 0,
+       CSU_CSLX_PCIE1_IO,
+       CSU_CSLX_MG2TPR_IP,
+       CSU_CSLX_IFC_MEM,
+       CSU_CSLX_OCRAM,
+       CSU_CSLX_GIC,
+       CSU_CSLX_PCIE1,
+       CSU_CSLX_OCRAM2,
+       CSU_CSLX_QSPI_MEM,
+       CSU_CSLX_PCIE2,
+       CSU_CSLX_SATA,
+       CSU_CSLX_USB3,
+       CSU_CSLX_SERDES = 32,
+       CSU_CSLX_QDMA,
+       CSU_CSLX_LPUART2,
+       CSU_CSLX_LPUART1,
+       CSU_CSLX_LPUART4,
+       CSU_CSLX_LPUART3,
+       CSU_CSLX_LPUART6,
+       CSU_CSLX_LPUART5,
+       CSU_CSLX_DSPI2 = 40,
+       CSU_CSLX_DSPI1,
+       CSU_CSLX_QSPI,
+       CSU_CSLX_ESDHC,
+       CSU_CSLX_2D_ACE,
+       CSU_CSLX_IFC,
+       CSU_CSLX_I2C1,
+       CSU_CSLX_USB2,
+       CSU_CSLX_I2C3,
+       CSU_CSLX_I2C2,
+       CSU_CSLX_DUART2 = 50,
+       CSU_CSLX_DUART1,
+       CSU_CSLX_WDT2,
+       CSU_CSLX_WDT1,
+       CSU_CSLX_EDMA,
+       CSU_CSLX_SYS_CNT,
+       CSU_CSLX_DMA_MUX2,
+       CSU_CSLX_DMA_MUX1,
+       CSU_CSLX_DDR,
+       CSU_CSLX_QUICC,
+       CSU_CSLX_DCFG_CCU_RCPM = 60,
+       CSU_CSLX_SECURE_BOOTROM,
+       CSU_CSLX_SFP,
+       CSU_CSLX_TMU,
+       CSU_CSLX_SECURE_MONITOR,
+       CSU_CSLX_RESERVED0,
+       CSU_CSLX_ETSEC1,
+       CSU_CSLX_SEC5_5,
+       CSU_CSLX_ETSEC3,
+       CSU_CSLX_ETSEC2,
+       CSU_CSLX_GPIO2 = 70,
+       CSU_CSLX_GPIO1,
+       CSU_CSLX_GPIO4,
+       CSU_CSLX_GPIO3,
+       CSU_CSLX_PLATFORM_CONT,
+       CSU_CSLX_CSU,
+       CSU_CSLX_ASRC,
+       CSU_CSLX_SPDIF,
+       CSU_CSLX_FLEXCAN2,
+       CSU_CSLX_FLEXCAN1,
+       CSU_CSLX_FLEXCAN4 = 80,
+       CSU_CSLX_FLEXCAN3,
+       CSU_CSLX_SAI2,
+       CSU_CSLX_SAI1,
+       CSU_CSLX_SAI4,
+       CSU_CSLX_SAI3,
+       CSU_CSLX_FTM2,
+       CSU_CSLX_FTM1,
+       CSU_CSLX_FTM4,
+       CSU_CSLX_FTM3,
+       CSU_CSLX_FTM6 = 90,
+       CSU_CSLX_FTM5,
+       CSU_CSLX_FTM8,
+       CSU_CSLX_FTM7,
+       CSU_CSLX_COP_DCSR,
+       CSU_CSLX_EPU,
+       CSU_CSLX_GDI,
+       CSU_CSLX_DDI,
+       CSU_CSLX_RESERVED1,
+       CSU_CSLX_USB3_PHY = 117,
+       CSU_CSLX_RESERVED2,
+       CSU_CSLX_MAX,
+};
+
+struct csu_ns_dev {
+       unsigned long ind;
+       uint32_t val;
+};
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
+
+#endif

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 9a91b9008a83a5e7b0007a3311ef11b292377bab..148fc41102bf67c22b8c03619360905886d51aae 100644 (file)
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -68,4 +68,6 @@ obj-$(CONFIG_P3041DS) += p_corenet/
 obj-$(CONFIG_P4080DS)  += p_corenet/
 obj-$(CONFIG_P5020DS)  += p_corenet/
 obj-$(CONFIG_P5040DS)  += p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACCESS)        += ns_access.o
 endif

diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
new file mode 100644 (file)
index 0000000..d7de982
--- /dev/null
+++ b/board/freescale/common/ns_access.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+       u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+       u32 *reg;
+       uint32_t val;
+       int i;
+
+       for (i = 0; i < num; i++) {
+               reg = base + ns_dev[i].ind / 2;
+               val = in_be32(reg);
+               if (ns_dev[i].ind % 2 == 0) {
+                       val &= 0x0000ffff;
+                       val |= ns_dev[i].val << 16;
+               } else {
+                       val &= 0xffff0000;
+                       val |= ns_dev[i].val;
+               }
+               out_be32(reg, val);
+       }
+}

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 6c66bd42c30ac0319c40ecdd0f074ccd2ba1d2c9..1679144caa60d2b158314bbaa21f30521d288c9d 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -8,6 +8,7 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/pcie_layerscape.h>
@@ -362,6 +363,92 @@ int misc_init_r(void)
        return 0;
 }
 
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+       { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+       { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+       { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM, CSU_ALL_RW },
+       { CSU_CSLX_GIC, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+       { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+       { CSU_CSLX_PCIE2, CSU_ALL_RW },
+       { CSU_CSLX_SATA, CSU_ALL_RW },
+       { CSU_CSLX_USB3, CSU_ALL_RW },
+       { CSU_CSLX_SERDES, CSU_ALL_RW },
+       { CSU_CSLX_QDMA, CSU_ALL_RW },
+       { CSU_CSLX_LPUART2, CSU_ALL_RW },
+       { CSU_CSLX_LPUART1, CSU_ALL_RW },
+       { CSU_CSLX_LPUART4, CSU_ALL_RW },
+       { CSU_CSLX_LPUART3, CSU_ALL_RW },
+       { CSU_CSLX_LPUART6, CSU_ALL_RW },
+       { CSU_CSLX_LPUART5, CSU_ALL_RW },
+       { CSU_CSLX_DSPI2, CSU_ALL_RW },
+       { CSU_CSLX_DSPI1, CSU_ALL_RW },
+       { CSU_CSLX_QSPI, CSU_ALL_RW },
+       { CSU_CSLX_ESDHC, CSU_ALL_RW },
+       { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+       { CSU_CSLX_IFC, CSU_ALL_RW },
+       { CSU_CSLX_I2C1, CSU_ALL_RW },
+       { CSU_CSLX_USB2, CSU_ALL_RW },
+       { CSU_CSLX_I2C3, CSU_ALL_RW },
+       { CSU_CSLX_I2C2, CSU_ALL_RW },
+       { CSU_CSLX_DUART2, CSU_ALL_RW },
+       { CSU_CSLX_DUART1, CSU_ALL_RW },
+       { CSU_CSLX_WDT2, CSU_ALL_RW },
+       { CSU_CSLX_WDT1, CSU_ALL_RW },
+       { CSU_CSLX_EDMA, CSU_ALL_RW },
+       { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+       { CSU_CSLX_DDR, CSU_ALL_RW },
+       { CSU_CSLX_QUICC, CSU_ALL_RW },
+       { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+       { CSU_CSLX_SFP, CSU_ALL_RW },
+       { CSU_CSLX_TMU, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+       { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO1, CSU_ALL_RW },
+       { CSU_CSLX_GPIO4, CSU_ALL_RW },
+       { CSU_CSLX_GPIO3, CSU_ALL_RW },
+       { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+       { CSU_CSLX_CSU, CSU_ALL_RW },
+       { CSU_CSLX_ASRC, CSU_ALL_RW },
+       { CSU_CSLX_SPDIF, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+       { CSU_CSLX_SAI2, CSU_ALL_RW },
+       { CSU_CSLX_SAI1, CSU_ALL_RW },
+       { CSU_CSLX_SAI4, CSU_ALL_RW },
+       { CSU_CSLX_SAI3, CSU_ALL_RW },
+       { CSU_CSLX_FTM2, CSU_ALL_RW },
+       { CSU_CSLX_FTM1, CSU_ALL_RW },
+       { CSU_CSLX_FTM4, CSU_ALL_RW },
+       { CSU_CSLX_FTM3, CSU_ALL_RW },
+       { CSU_CSLX_FTM6, CSU_ALL_RW },
+       { CSU_CSLX_FTM5, CSU_ALL_RW },
+       { CSU_CSLX_FTM8, CSU_ALL_RW },
+       { CSU_CSLX_FTM7, CSU_ALL_RW },
+       { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+       { CSU_CSLX_EPU, CSU_ALL_RW },
+       { CSU_CSLX_GDI, CSU_ALL_RW },
+       { CSU_CSLX_DDI, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+       { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
 int board_init(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -384,6 +471,10 @@ int board_init(void)
        config_serdes_mux();
 #endif
 
+#ifdef CONFIG_LS102XA_NS_ACCESS
+       enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
 #ifdef CONFIG_U_QE
        u_qe_init();
 #endif

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 5c3a282b303ce3df93379c814dd4b73d7a94e4c0..0e61abaa760e4a06466b5af8ba99bfbeb35d44eb 100644 (file)
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -8,6 +8,7 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/pcie_layerscape.h>
@@ -301,6 +302,92 @@ void board_init_f(ulong dummy)
 }
 #endif
 
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+       { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+       { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+       { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM, CSU_ALL_RW },
+       { CSU_CSLX_GIC, CSU_ALL_RW },
+       { CSU_CSLX_PCIE1, CSU_ALL_RW },
+       { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+       { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+       { CSU_CSLX_PCIE2, CSU_ALL_RW },
+       { CSU_CSLX_SATA, CSU_ALL_RW },
+       { CSU_CSLX_USB3, CSU_ALL_RW },
+       { CSU_CSLX_SERDES, CSU_ALL_RW },
+       { CSU_CSLX_QDMA, CSU_ALL_RW },
+       { CSU_CSLX_LPUART2, CSU_ALL_RW },
+       { CSU_CSLX_LPUART1, CSU_ALL_RW },
+       { CSU_CSLX_LPUART4, CSU_ALL_RW },
+       { CSU_CSLX_LPUART3, CSU_ALL_RW },
+       { CSU_CSLX_LPUART6, CSU_ALL_RW },
+       { CSU_CSLX_LPUART5, CSU_ALL_RW },
+       { CSU_CSLX_DSPI2, CSU_ALL_RW },
+       { CSU_CSLX_DSPI1, CSU_ALL_RW },
+       { CSU_CSLX_QSPI, CSU_ALL_RW },
+       { CSU_CSLX_ESDHC, CSU_ALL_RW },
+       { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+       { CSU_CSLX_IFC, CSU_ALL_RW },
+       { CSU_CSLX_I2C1, CSU_ALL_RW },
+       { CSU_CSLX_USB2, CSU_ALL_RW },
+       { CSU_CSLX_I2C3, CSU_ALL_RW },
+       { CSU_CSLX_I2C2, CSU_ALL_RW },
+       { CSU_CSLX_DUART2, CSU_ALL_RW },
+       { CSU_CSLX_DUART1, CSU_ALL_RW },
+       { CSU_CSLX_WDT2, CSU_ALL_RW },
+       { CSU_CSLX_WDT1, CSU_ALL_RW },
+       { CSU_CSLX_EDMA, CSU_ALL_RW },
+       { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+       { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+       { CSU_CSLX_DDR, CSU_ALL_RW },
+       { CSU_CSLX_QUICC, CSU_ALL_RW },
+       { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+       { CSU_CSLX_SFP, CSU_ALL_RW },
+       { CSU_CSLX_TMU, CSU_ALL_RW },
+       { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+       { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+       { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO2, CSU_ALL_RW },
+       { CSU_CSLX_GPIO1, CSU_ALL_RW },
+       { CSU_CSLX_GPIO4, CSU_ALL_RW },
+       { CSU_CSLX_GPIO3, CSU_ALL_RW },
+       { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+       { CSU_CSLX_CSU, CSU_ALL_RW },
+       { CSU_CSLX_ASRC, CSU_ALL_RW },
+       { CSU_CSLX_SPDIF, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+       { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+       { CSU_CSLX_SAI2, CSU_ALL_RW },
+       { CSU_CSLX_SAI1, CSU_ALL_RW },
+       { CSU_CSLX_SAI4, CSU_ALL_RW },
+       { CSU_CSLX_SAI3, CSU_ALL_RW },
+       { CSU_CSLX_FTM2, CSU_ALL_RW },
+       { CSU_CSLX_FTM1, CSU_ALL_RW },
+       { CSU_CSLX_FTM4, CSU_ALL_RW },
+       { CSU_CSLX_FTM3, CSU_ALL_RW },
+       { CSU_CSLX_FTM6, CSU_ALL_RW },
+       { CSU_CSLX_FTM5, CSU_ALL_RW },
+       { CSU_CSLX_FTM8, CSU_ALL_RW },
+       { CSU_CSLX_FTM7, CSU_ALL_RW },
+       { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+       { CSU_CSLX_EPU, CSU_ALL_RW },
+       { CSU_CSLX_GDI, CSU_ALL_RW },
+       { CSU_CSLX_DDI, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+       { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+       { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
 int board_init(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -320,6 +407,10 @@ int board_init(void)
 #endif
 #endif
 
+#ifdef CONFIG_LS102XA_NS_ACCESS
+       enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
 #ifdef CONFIG_U_QE
        u_qe_init();
 #endif

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 704c3498402e0cc66baa42b12cdb84aaeebbbb96..73918825a57b543e746bf7a819011824d2f2f312 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -496,6 +496,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200
 #define CONFIG_TIMER_CLK_FREQ          12500000
 #define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 809e80f82cdd8bd7205aaa0af348679dd4aaae49..171346b8e1c700563dbf0f0a4911dda3c82f4edb 100644 (file)
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -315,6 +315,7 @@
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200
 #define CONFIG_TIMER_CLK_FREQ          12500000
 #define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR