]> git.sur5r.net Git - u-boot/commitdiff
armv8/ls1043ardb: Add support for >2GB memory
authorShaohui Xie <Shaohui.Xie@freescale.com>
Mon, 23 Nov 2015 07:23:48 +0000 (15:23 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 14 Dec 2015 02:27:29 +0000 (18:27 -0800)
This patch also expose the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/include/asm/arch-fsl-layerscape/config.h
board/freescale/ls1043ardb/ddr.c
board/freescale/ls1043ardb/ls1043ardb.c
include/configs/ls1043a_common.h
include/configs/ls1043ardb.h

index b5a2d28c08f177eaa57917454fe0dc5bad3acb04..7217a87502ea95b34c220512e18ed9a4f228e338 100644 (file)
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
 #define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
index b181579e8e4d31668e4685fa6f117508f8dd107f..249d0565fc5ce3f1a0add741dda644adcdb7c8af 100644 (file)
@@ -187,5 +187,12 @@ phys_size_t initdram(int board_type)
 void dram_init_banksize(void)
 {
        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = gd->ram_size;
+       if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                                         CONFIG_SYS_DDR_BLOCK1_SIZE;
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+       }
 }
index cdd50d6d1877968fc7189e8309af890ab49c6856..4556ea8ad11b73f7a7ebc7e52b4b3ec61ea2ebf1 100644 (file)
@@ -130,6 +130,16 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
+       u64 base[CONFIG_NR_DRAM_BANKS];
+       u64 size[CONFIG_NR_DRAM_BANKS];
+
+       /* fixup DT for the two DDR banks */
+       base[0] = gd->bd->bi_dram[0].start;
+       size[0] = gd->bd->bi_dram[0].size;
+       base[1] = gd->bd->bi_dram[1].start;
+       size[1] = gd->bd->bi_dram[1].size;
+
+       fdt_fixup_memory_banks(blob, base, size, 2);
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
index 6b9856a18f4dc0a0e015b659e93a5dd2eb7c859c..677d28113c1617326522f76f671a891e061af248 100644 (file)
@@ -44,6 +44,7 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 
 #define CPU_RELEASE_ADDR               secondary_boot_func
 
index 7d113a0737ec68ab434ddcb6079c35e13f6e097d..683407499a5dff86af5cd90b2469719eb57d88e7 100644 (file)
@@ -27,7 +27,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
-#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_NR_DRAM_BANKS           2
 
 #define CONFIG_SYS_SPD_BUS_NUM         0