arch/arm: add SEC JR0 offset

Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 0bad0c70b847e1a68fab55d1a1c52cc5634a710c..57b99d4084ef0c666540f1c6e59d5d2ca46c2c12 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -37,8 +37,6 @@
 #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR                        (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR                        (CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_SEC_MON_ADDR                        (CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR                    (CONFIG_SYS_IMMR + 0xe80200)
 
@@ -157,6 +155,13 @@ struct sys_info {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR         \
                (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
+#define CONFIG_SYS_FSL_SEC_OFFSET              0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET              0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
 /* Device Configuration and Pin Control */
 struct ccsr_gur {
        u32     porsr1;         /* POR status 1 */

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b33671f414265f4740224c36d616434b94d8c..65b3357009a5deac414d80b4774aab750784dc68 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -77,8 +77,12 @@
 #define CONFIG_SYS_SFP_ADDR            (CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_ADDR                (CONFIG_SYS_IMMR + 0x07000000)
-#define CONFIG_SYS_FSL_JR0_ADDR                (CONFIG_SYS_IMMR + 0x07010000)
+#define CONFIG_SYS_FSL_SEC_OFFSET              0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET              0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR                (CONFIG_SYS_IMMR + 0x00e90000)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 267bd17727c619c1475f6f924c6fce916a594151..92f30e28aaaca1ebe163f446139fefd93e039e13 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -40,6 +40,7 @@
        (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET              0x00710000
 #define CONFIG_SYS_LS102XA_USB1_OFFSET         0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET                        0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET                        0x01d50000

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3ab04bf998deb66bb7b32a56f500af97eee01352..ac37e4f8e689d37b2748bc580df15fa77db240dd 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -227,8 +227,13 @@
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
 
-#define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET   0
+#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+                                    CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+                                    CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a3106e7e6b43c92e2fb1e301fed25780ed64b1f8..74917f0e69d8bf3c30ec1fa962396ef872294e69 100644 (file)
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -218,10 +218,13 @@
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR     0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR  + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET       0
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+                                        CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
+                                        CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/imx-common/regs-lcdif.h>
 #include <asm/types.h>