uintptr_t       vmr_table_addr;
 
        /* Round monitor address down to the nearest page boundary */
-       dest_addr &= PAGE_ADDR_MASK;
+       dest_addr &= MMU_PAGE_ADDR_MASK;
 
        /* Initialize TLB entry 0 to cover the monitor, and lock it */
        sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
        unsigned int fault_pgno;
        int first, last;
 
-       fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT;
+       fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
        vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
 
        /* Do a binary search through the VM ranges */
                        /* Got it; let's slam it into the TLB */
                        uint32_t tlbelo;
 
-                       tlbelo = vmr->phys & ~PAGE_ADDR_MASK;
-                       tlbelo |= fault_pgno << PAGE_SHIFT;
+                       tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
+                       tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
                        sysreg_write(TLBELO, tlbelo);
                        __builtin_tlbw();
 
 
 
 #include <asm/sysreg.h>
 
-#define PAGE_SHIFT     20
-#define PAGE_SIZE      (1UL << PAGE_SHIFT)
-#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1))
+#define MMU_PAGE_SHIFT 20
+#define MMU_PAGE_SIZE  (1UL << MMU_PAGE_SHIFT)
+#define MMU_PAGE_ADDR_MASK     (~(MMU_PAGE_SIZE - 1))
 
 #define MMU_VMR_CACHE_NONE                                             \
        (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))
 
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
                /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
                /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
-               .virt_pgno      = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
-               .phys           = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
+               .virt_pgno      = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
                /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
 
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
 
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
 
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                | MMU_VMR_CACHE_WRBACK,
        },
 };
 
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
-               .phys           = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
+               .virt_pgno      = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
 
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };