Fix identification on ext2ls help entry.
Patch by Stefan Roese, 14 Oct 2005
+* Add support for TQM834x boards.
+ Cleanup.
+
+* Cleanup for GCC-4.x
+
+* Add documentation for Open Firmware Flat Tree and usage.
+ Patch by Pantelis Antoniou, 13 Oct 2005
+
* Add missing files for Pantelis Antoniou's patch
Patch by Pantelis Antoniou, 04 Sep 2005
#########################################################################
LIST_83xx=" \
- MPC8349ADS \
+ MPC8349ADS TQM834x\
"
MPC8349ADS_config: unconfig
@./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
+TQM834x_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc83xx tqm834x
+
#########################################################################
## MPC85xx Systems
#########################################################################
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
if (!s || strncmp (s, "ELPT860", 7))
printf ("### No HW ID - assuming ELPT860\n");
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
- (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+ SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+ SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- volatile unsigned char *addr = (char *) (info->start[0]);
+ volatile unsigned char *addr = (uchar *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
for (sect = s_first; sect <= s_last; sect++) {
int sector_size = info->size / info->sector_count;
- addr = (char *) (info->start[sect]);
+ addr = (uchar *) (info->start[sect]);
memset ((void *) addr, 0, sector_size);
}
return 0;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (char *) (info->start[sect]);
+ addr = (uchar *) (info->start[sect]);
flash_cmd (info->portwidth, addr, 0, 0x30);
l_sect = sect;
}
/* broken for 2x16: TODO */
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
- volatile unsigned char *addr = (char *) (info->start[0]);
+ volatile unsigned char *addr = (uchar *) (info->start[0]);
ulong start;
int flag, i;
ulong mask;
CHIP_CMD_RST);
/* 1st cycle of word/byte program */
/* write 0x40 to the location to program */
- flash_cmd (info->portwidth, (char *) dest, 0,
+ flash_cmd (info->portwidth, (uchar *) dest, 0,
CHIP_CMD_PROG);
/* 2nd cycle of word/byte program */
/* write the data to the destination address */
static uchar i2c_get_data (uchar * return_data, int len)
{
- unsigned int data, status;
+ unsigned int data, status = 0;
int count = 0;
DP (puts ("i2c_get_data\n"));
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
dev->send = (void *) db64360_eth_transmit;
dev->recv = (void *) db64360_eth_poll;
- dev->priv = (void *) ethernet_private =
- calloc (sizeof (*ethernet_private), 1);
+ ethernet_private = calloc (sizeof (*ethernet_private), 1);
+ dev->priv = (void *) ethernet_private;
+
if (!ethernet_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
/* set pointer to memory for stats data structure etc... */
- ethernet_private->port_private = (void *) port_private =
- calloc (sizeof (*ethernet_private), 1);
+ port_private = calloc (sizeof (*ethernet_private), 1);
+ ethernet_private->port_private = (void *)port_private;
if (!port_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
dev->send = (void *) db64460_eth_transmit;
dev->recv = (void *) db64460_eth_poll;
- dev->priv = (void *) ethernet_private =
- calloc (sizeof (*ethernet_private), 1);
+ ethernet_private = calloc (sizeof (*ethernet_private), 1);
+ dev->priv = (void *)ethernet_private;
if (!ethernet_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
/* set pointer to memory for stats data structure etc... */
- ethernet_private->port_private = (void *) port_private =
- calloc (sizeof (*ethernet_private), 1);
+ port_private = calloc (sizeof (*ethernet_private), 1);
+ ethernet_private->port_private = (void *)port_private;
if (!port_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
- i2c_read (0x54, 0, 1, buff, 128);
- i2c_read (0x54, 128, 1, buff + 128, 128);
+ i2c_read (0x54, 0, 1, (uchar *)buff, 128);
+ i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
/* Retrieve MAC address in buffer (key EA) */
for (cp = buff;;) {
cp += 3;
/* Read MAC address */
for (i = 0; i < 6; i++, cp += 2) {
- enet[i] = aschex_to_byte (cp);
+ enet[i] = aschex_to_byte ((unsigned char *)cp);
}
}
/* Scan to the end of the record */
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
/*
* Final mapping:
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
puts ("Board: RRvision ");
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
- (ulong *)SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*/
int checkboard(void)
{
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
int checkboard(void)
{
sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
get_sys_info(&sysinfo);
int checkboard (void)
{
sys_info_t sysinfo;
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
get_sys_info (&sysinfo);
*/
int checkboard(void)
{
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
uint pvr = get_pvr();
if (pvr == PVR_405GPR_RB) {
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
switch ((*buf) & 0x3) {
case TRY_WORKING:
printf ("found 3 and converted it to 2\n");
- write_flash (buf, (*buf) & 0xFE);
+ write_flash ((char *)buf, (*buf) & 0xFE);
*((unsigned char *)0xFF800000) = 0xF0;
udelay (100);
printf ("buf [%#010x] %#010x\n", buf, (*buf));
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ unsigned char *s = (unsigned char *)getenv ("serial#");
puts ("Board: TTTech C2MON ");
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
- (ulong *)SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE2_PRELIM,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
- unsigned char *s, *e;
+ char *s, *e;
image_header_t *hdr;
time_t timestamp;
struct rtc_time tm;
#define FACTORY_SETTINGS 0xFFFC0000
if ((s = getenv ("ethaddr")) == NULL) {
- e = (unsigned char *) (FACTORY_SETTINGS);
+ e = (char *) (FACTORY_SETTINGS);
if (*(e + 0) != '0'
|| *(e + 1) != '0'
|| *(e + 2) != ':'
{
setenv (Things[thing].envname, Things[thing].dhcpvalue);
}
- return (Things[thing].dhcpvalue);
+ return ((u8 *)(Things[thing].dhcpvalue));
}
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
int misc_init_r (void)
{
revinfo eerev;
- u_char *ptr;
+ char *ptr;
u_int i, l, initSrom, copyNv;
char buf[256];
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
if (strcmp (eerev.magic, "ELTEC") != 0)
{
/* srom is not initialized -> create a default revision info */
- for (i = 0, ptr = (u_char *)&eerev; i < sizeof(revinfo); i++)
+ for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
*ptr++ = 0x00;
strcpy(eerev.magic, "ELTEC");
eerev.revrev[0] = 1;
/* get onboard network iobase */
pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0,
- &onboard_dev.iobase);
+ (unsigned int *)&onboard_dev.iobase);
onboard_dev.iobase &= ~0xf;
source[63] = eepro100_srom_checksum (source);
int i;
/* check revision data */
- eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo, 32);
+ eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
}
/* setup new revision data */
- eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo,
+ eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
32);
}
immap_t *immr = (immap_t *) CFG_IMMR;
/* enable video only on CLUT value */
- if ((penv = getenv ("clut")) != NULL)
- clut = (u_int) simple_strtoul (penv, NULL, 10);
+ if ((penv = (uchar *)getenv ("clut")) != NULL)
+ clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
else
return NULL;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
/*printf ("%s\n", buf); */
/* search for our specific entry */
if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
- setenv ("ethaddr", buf + 19);
+ setenv ("ethaddr", (char *)(buf + 19));
} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
- setenv ("serial#", buf + 15);
+ setenv ("serial#", (char *)(buf + 15));
} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
- setenv ("board_id", buf + 13);
+ setenv ("board_id", (char *)(buf + 13));
}
}
}
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
puts ("Board: ");
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
const unsigned char *fpga;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
/* check the data CRC */
checksum = ntohl(hdr->ih_dcrc);
- if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+ if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
!= checksum) {
printf ("Image %s bad data checksum\n", au_image[i].name);
return -1;
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
printf ("Image %s bad header checksum\n", au_image[i].name);
return -1;
}
*/
if (au_image[i].type != AU_NAND) {
debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
- rc = flash_write(addr, start, nbytes);
+ rc = flash_write((uchar *)addr, start, nbytes);
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
- start, nbytes, &total, addr);
+ start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
#endif
}
* check the dcrc of the copy
*/
if (au_image[i].type != AU_NAND) {
- rc = crc32 (0, (char *)(start + off), ntohl(hdr->ih_size));
+ rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
- start, nbytes, &total, addr);
- rc = crc32 (0, (char *)(addr + off), ntohl(hdr->ih_size));
+ start, nbytes, (size_t *)&total, (uchar *)addr);
+ rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));
#endif
}
if (rc != ntohl(hdr->ih_dcrc)) {
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
int index;
int len;
#endif
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned short ver;
#endif
if (ctermm2()) {
- unsigned char str[4];
+ char str[4];
/*
* Read board-id and save in env-variable
int result;
int i;
unsigned char ow_id[6];
- unsigned char str[32];
+ char str[32];
unsigned char ow_crc;
/*
IPaddr_t ipaddr;
buf = malloc(CFG_ENV_SIZE_2);
- if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
puts("\nError reading backplane EEPROM!\n");
} else {
- crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
if (crc != *(ulong *)buf) {
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
return -1;
int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *buf;
- unsigned char str[32];
+ char str[32];
ulong crc;
if (argc < 2) {
memset(buf, 0, CFG_ENV_SIZE_2);
sprintf(str, "bp_ip=%s", argv[1]);
strcpy(buf+4, str);
- crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
*(ulong *)buf = crc;
- if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
puts("\nError writing backplane EEPROM!\n");
}
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
dev->send = (void *) db64360_eth_transmit;
dev->recv = (void *) db64360_eth_poll;
- dev->priv = (void *) ethernet_private =
+ ethernet_private =
calloc (sizeof (*ethernet_private), 1);
+ dev->priv = (void *) ethernet_private;
if (!ethernet_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
/* set pointer to memory for stats data structure etc... */
- ethernet_private->port_private = (void *) port_private =
+ port_private =
calloc (sizeof (*ethernet_private), 1);
+ ethernet_private->port_private = (void *)port_private;
if (!port_private) {
printf ("%s: %s allocation failure, %s\n",
__FUNCTION__, dev->name,
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
for (i = 0; i < 4; i++) {
pci_read_config_dword (CFG_PCI9054_DEV_FN,
l * 16 + i * 4,
- &val);
+ (unsigned int *)&val);
printf ("%08x ", val);
}
printf ("\n");
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
int fpga;
unsigned short val;
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
{
int index;
int len;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
}
ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+ *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
printf("\nStoring PCI Configuration Regs...\n");
} else {
pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
}
ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+ *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
printf("\nStoring PCI Configuration Regs...\n");
* Rewrite pci config regs (only after soft-reset with magic set)
*/
ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+ if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
puts("Restoring PCI Configurations Regs!\n");
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
for (i=0; i<0x40; i+=4) {
* Rewrite pci config regs (only after soft-reset with magic set)
*/
ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+ if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
puts("Restoring PCI Configurations Regs!\n");
ptr = (unsigned int *)PCI_REGS_ADDR + 1;
for (i=0; i<0x40; i+=4) {
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
void flash_print_info(flash_info_t * info) {
int i;
- uchar *fmt;
+ char *fmt;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *) CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
* Check Bank 0 Memory Size for re-configuration
*
*/
- size_b0 = get_ram_size ((ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
- size_b1 = get_ram_size ((ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
puts ("Board: ");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
* but then only half the real size will be used.]
*/
size_b1 =
- dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+ dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
} else {
*/
/* let the upper layer handle the packet */
- NetReceive (eth_data, eth_len);
+ NetReceive ((uchar *)eth_data, eth_len);
rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
#endif
memcpy(dev->eth_tx_buffer, (char *) p, s);
- tx->buff_pointer = dev->eth_tx_buffer;
+ tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
tx->bytecount_reserved = ((__u16)s) << 16;
/* 31 - own
/* Initialize Rx Side */
for (temp = 0; temp < NR; temp++) {
- p->eth_rx_desc[temp].buff_pointer = p->eth_rx_buffer[temp];
+ p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
/* GT96100 Owner */
dev->send = (void*)gt6426x_eth_transmit;
dev->recv = (void*)gt6426x_eth_poll;
- dev->priv = (void*)p = calloc( sizeof(*p), 1 );
+ p = calloc( sizeof(*p), 1 );
+ dev->priv = (void*)p;
if (!p)
{
printf( "%s: %s allocation failure, %s\n",
volatile struct eth0_tx_desc_struct * next_desc;
/* Note - the following will not work for 64 bit addressing */
volatile unsigned char * buff_pointer;
-} eth0_tx_desc_single __attribute__ ((packed));
+} __attribute__ ((packed)) eth0_tx_desc_single;
typedef struct eth0_rx_desc_struct {
volatile __u32 buff_size_byte_count;
volatile __u32 command_status;
volatile struct eth0_rx_desc_struct * next_desc;
volatile unsigned char * buff_pointer;
-} eth0_rx_desc_single __attribute__ ((packed));
+} __attribute__ ((packed)) eth0_rx_desc_single;
#define NT 20 /* Number of Transmit buffers */
#define NR 20 /* Number of Receive buffers */
int bytes =
hashLength[hashSizeSelector] * sizeof (addrTblEntry);
- tableBase = (unsigned int) realAddrTableBase[port] =
+ realAddrTableBase[port] =
malloc (bytes + 64);
+ tableBase = (unsigned int)realAddrTableBase;
if (!tableBase) {
printf ("%s: alloc memory failed \n", __FUNCTION__);
int
flash_erase (flash_info_t *info, int s_first, int s_last)
{
- volatile unsigned char *addr = (char *)(info->start[0]);
+ volatile unsigned char *addr = (uchar *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
for (sect = s_first; sect<=s_last; sect++) {
int sector_size=info->size/info->sector_count;
- addr = (char *)(info->start[sect]);
+ addr = (uchar *)(info->start[sect]);
memset((void *)addr, 0, sector_size);
}
return 0;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr = (char *)(info->start[sect]);
+ addr = (uchar *)(info->start[sect]);
flash_cmd(info->portwidth,addr,0,0x30);
l_sect = sect;
}
static int
write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile unsigned char *addr = (char *)(info->start[0]);
+ volatile unsigned char *addr = (uchar *)(info->start[0]);
ulong start;
int flag, i;
static uchar
i2c_get_data(uchar* return_data, int len) {
- unsigned int data, status;
+ unsigned int data, status = 0;
int count = 0;
DP(puts("i2c_get_data\n"));
static void
zuma_mbox_setenv(void)
{
- unsigned char *data, buf[32];
+ char *data, buf[32];
unsigned char save = 0;
data = getenv("baudrate");
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s;
- unsigned char buf[64];
+ char *s;
+ char buf[64];
int i;
i = getenv_r ("board_id", buf, sizeof (buf));
int last_stage_init (void)
{
#if !defined(CONFIG_SC)
- unsigned char buf[256];
+ char buf[256];
int i;
/*
#endif
switch (value)
{
- case 0x01:
- case AMD_MANUFACT:
+ case 0x1: /* AMD_MANUFACT */
info->flash_id = FLASH_MAN_AMD;
break;
- case FUJ_MANUFACT:
+ case 0x4: /* FUJ_MANUFACT */
info->flash_id = FLASH_MAN_FUJ;
break;
PrintState ();
#endif
/* printf ("\nChecking bank1..."); */
- size8 = dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
size_b0 = size8;
/* printf ("\nChecking bank2..."); */
size_b1 =
- dram_size (memctl->memc_mbmr, (ulong *) SDRAM_BASE2_PRELIM,
+ dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/*
#if 0
ulong base = (ulong)addr;
#endif
- uchar value;
+ ulong value;
/* Write auto select command: read Manufacturer ID */
#if 0
switch (value)
{
- case AMD_MANUFACT:case 0x01:
+ case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
- setenv ("ethaddr", Rx);
+ setenv ("ethaddr", (char *)Rx);
}
return (0);
}
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
puts ("Board: ");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
offset += sizeof (ulong);
- if (crc32 (crc32 (0, (char *)&hdr, sizeof hdr), data, len) != crc)
+ if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
return (0);
ep->ver = hdr.ver;
char *eval;
ulong lval;
- lval = simple_strtol (val, &eval, 10);
+ lval = simple_strtol ((char *)val, &eval, 10);
if ((uchar *)eval == val || *eval != '\0') {
printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
{
hymod_date_t date;
- uchar *p = val;
+ char *p = (char *)val;
char *ep;
ulong lval;
lval = simple_strtol (p, &ep, 10);
- if ((uchar *)ep == p || *ep++ != '-') {
+ if (ep == p || *ep++ != '-') {
bad_date:
printf ("%s rec (%s) is not a valid date\n", rp->name, val);
return (NULL);
date.year = lval;
lval = simple_strtol (p = ep, &ep, 10);
- if ((uchar *)ep == p || *ep++ != '-' || lval == 0 || lval > 12)
+ if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
goto bad_date;
date.month = lval;
lval = simple_strtol (p = ep, &ep, 10);
- if ((uchar *)ep == p || *ep != '\0' || lval == 0 || lval > 31)
+ if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
goto bad_date;
date.day = lval;
{
uint len;
- if ((len = strlen (val)) > rp->maxlen) {
+ if ((len = strlen ((char *)val)) > rp->maxlen) {
printf ("%s rec (%s) string is too long (%d>%d)\n",
rp->name, val, len, rp->maxlen);
return (NULL);
for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
ulong lval;
- lval = simple_strtol (p, &ep, 10);
+ lval = simple_strtol ((char *)p, &ep, 10);
if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
lval >= 256) {
printf ("%s rec (%s) byte array has invalid uint\n",
eerec_map_t *rp;
for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
- if (strcmp (name, rp->name) == 0)
+ if (strcmp ((char *)name, rp->name) == 0)
break;
if (rp >= &eerec_map[neerecs])
char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver;
int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
- nn = name;
+ nn = (char *)name;
if (*nn == '-') {
override = 0;
return (0);
}
- p = value;
+ p = (char *)value;
q = nv;
while ((c = *p) == ' ' || c == '\t')
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
/* find RAM size */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
value = addr[1]; /* device ID */
- switch (value) {
+ switch ((unsigned long)value) {
case AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
puts ("Board: ");
- i = getenv_r ("serial#", buf, sizeof (buf));
+ i = getenv_r ("serial#", (char *)buf, sizeof (buf));
s = (i > 0) ? buf : NULL;
- if (!s || strncmp (s, "IP860", 5)) {
+ if (!s || strncmp ((char *)s, "IP860", 5)) {
puts ("### No HW ID - assuming IP860");
} else {
for (e = s; *e; ++e) {
* Check SDRAM Memory Size
*/
if (ip860_get_dram_size() == 16)
- size = dram_size (refresh_val | 0x00804114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);
+ size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
else
- size = dram_size (refresh_val | 0x00906114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);
+ size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
udelay (1000);
{
int sn = -1;
- if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
+ if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
sn = cpu_to_le32 (sn);
}
return sn;
{
char mac[6];
- if (!seeprom_read (0xb0, mac, sizeof (mac))) {
+ if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
} else {
{
int sn = -1;
- if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
+ if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
sn = cpu_to_le32 (sn);
}
return sn;
{
char mac[6];
- if (!seeprom_read (0xb0, mac, sizeof (mac))) {
+ if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
} else {
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 =
- dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+ dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
void load_sernum_ethaddr (void)
{
unsigned char *hwi;
- unsigned char *var;
+ char *var;
unsigned char hwi_stack[CFG_HWINFO_SIZE];
- unsigned char *p;
+ char *p;
hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) {
/*
** ethaddr
*/
- var = strstr (hwi_stack, ETHADDR_TOKEN);
+ var = strstr ((char *)hwi_stack, ETHADDR_TOKEN);
if (var) {
var += sizeof (ETHADDR_TOKEN) - 1;
p = strchr (var, '\r');
- if (p < hwi + CFG_HWINFO_SIZE) {
+ if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
*p = '\0';
setenv ("ethaddr", var);
*p = '\r';
/*
** lcd
*/
- var = strstr (hwi_stack, LCD_TOKEN);
+ var = strstr ((char *)hwi_stack, LCD_TOKEN);
if (var) {
var += sizeof (LCD_TOKEN) - 1;
p = strchr (var, '\r');
- if (p < hwi + CFG_HWINFO_SIZE) {
+ if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
*p = '\0';
setenv ("lcd", var);
*p = '\r';
int r = 8, g = 8, b = 4;
int r1, g1, b1;
int n;
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int tft = 0;
immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
}
/* copy bitmap */
- fb = (char *) (fb_info.VmemAddr);
+ fb = (uchar *) (fb_info.VmemAddr);
memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
}
#endif /* CONFIG_KUP4K_LOGO */
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MAMR_8COL,
- (ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
DECLARE_GLOBAL_DATA_PTR;
uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
uchar kbd_init_status = gd->kbd_status >> 8;
uchar kbd_status = gd->kbd_status;
uchar val;
- uchar *str;
+ char *str;
int i;
if (kbd_init_status) {
}
setenv ("keybd", keybd_env);
- str = strdup (key_match (kbd_data)); /* decode keys */
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
#ifdef KEYBD_SET_DEBUGMODE
if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
if ((console_assign (stdout, "lcd") < 0) ||
/* Don't include modifier byte */
memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
- for (; str != NULL; str = (*nxt) ? nxt+1 : nxt) {
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
uchar c;
int k;
- c = (uchar) simple_strtoul (str, (char **) (&nxt), 16);
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
if (str == (uchar *)nxt) { /* invalid character */
break;
***********************************************************************/
static uchar *key_match (uchar *kbd_data)
{
- uchar magic[sizeof (kbd_magic_prefix) + 1];
+ char magic[sizeof (kbd_magic_prefix) + 1];
uchar *suffix;
- uchar *kbd_magic_keys;
+ char *kbd_magic_keys;
/*
* The following string defines the characters that can pe appended
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
- for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix) {
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
#if 0
printf ("### Check magic \"%s\"\n", magic);
#endif
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd_name, cmd ? cmd : "<<NULL>>");
#endif
*kbd_data = *suffix;
- return (cmd);
+ return ((uchar *)cmd);
}
}
#if 0
int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
uchar val;
int i;
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
- return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
+ return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0);
}
#endif /* CONFIG_MODEM_SUPPORT */
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
- return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
+ return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
}
#endif
return rc;
}
-volatile static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
+static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
volatile unsigned long long *addr=(unsigned long long *)dest;
unsigned long long result;
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
if (!s || strncmp (s, "ML2", 9)) {
printf ("### No HW ID - assuming ML2");
#endif
printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
(ulong)src, size);
- if ((rc = flash_write (src, start, size)) != 0) {
+ if ((rc = flash_write ((char *)src, start, size)) != 0) {
puts("ERROR ");
flash_perror(rc);
return (1);
len = sizeof(image_header_t);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts("Bad Header Checksum\n");
return 1;
}
data = ld_addr + sizeof(image_header_t);
len = ntohl(hdr->ih_size);
puts("Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts("Bad Data CRC\n");
return 1;
}
} while(len > off);
name=&name_buf[0];
value=&value_buf[0];
- if(strncmp(name,"baudrate",8)!=0) {
- setenv(name,value);
+ if(strncmp((char *)name,"baudrate",8)!=0) {
+ setenv((char *)name,(char *)value);
}
}
void check_env(void)
{
- unsigned char *s;
+ char *s;
int i=0;
char buf[32];
backup_t back;
char buf[64];
char tmp[16];
char cpustr[16];
- unsigned char *s, *e, bc;
+ char *s, *e, bc;
switch (line_number)
{
case 2:
void isa_sio_loadtable(void)
{
- unsigned char *s = getenv("floppy");
+ char *s = getenv("floppy");
/* setup Floppy device 0*/
isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
/* setup parallel port device 3 */
int checkboard (void)
{
- unsigned char s[50];
+ char s[50];
unsigned char bc, var;
int i;
backup_t *b = (backup_t *) s;
puts ("Board: ");
get_pcbrev_var(&bc,&var);
- i = getenv_r ("serial#", s, 32);
- if ((i == 0) || strncmp (s, BOARD_NAME,sizeof(BOARD_NAME))) {
+ i = getenv_r ("serial#", (char *)s, 32);
+ if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
get_backup_values (b);
if (strncmp (b->signature, "MPL\0", 4) != 0) {
puts ("### No HW ID - assuming " BOARD_NAME);
{
unsigned long stop;
struct rtc_time newtm;
- unsigned char *s;
+ char *s;
mem_test_reloc();
/* write correct LED configuration */
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
{
unsigned char dataout[1];
unsigned char datain[128];
- unsigned long sdram_size;
+ unsigned long sdram_size = 0;
SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
unsigned long memclk;
unsigned long tmemclk = 0;
int checkboard (void)
{
- unsigned char s[50];
+ char s[50];
unsigned char bc;
int i;
backup_t *b = (backup_t *) s;
puts ("Board: ");
- i = getenv_r ("serial#", s, 32);
- if ((i == 0) || strncmp (s, "PIP405", 6)) {
+ i = getenv_r ("serial#", (char *)s, 32);
+ if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
get_backup_values (b);
if (strncmp (b->signature, "MPL\0", 4) != 0) {
puts ("### No HW ID - assuming PIP405");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
- size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE2_PRELIM,
+ size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
- switch (value) {
+ switch ((ulong)value) {
case AMD_ID_F040B:
DEBUGF("Am29F040B\n");
info->flash_id += FLASH_AM040;
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
- test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
if (size < I2155X_VPD_SN_SIZE)
size = I2155X_VPD_SN_SIZE;
for (i = 0; i < (size - 1); i++) {
- i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, &c);
+ i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
if (c == '\0')
break;
string[i] = c;
int res;
if ((ds != 0) && (ds != 0xff)) {
- res = getenv_r ("ethaddr", tmp, sizeof (tmp));
+ res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp));
if (res > 0) {
ss = ((ds >> 4) & 0x0f);
ss += ss < 0x0a ? '0' : ('a' - 10);
tmp[16] = ss;
tmp[17] = '\0';
- setenv ("ethaddr", tmp);
+ setenv ("ethaddr", (char *)tmp);
/* set the led to show the address */
*((unsigned char *) (CFG_LED_BASE + 1)) = ds;
}
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
puts ("Board QUANTUM, Serial No: ");
/* Check Bank 0 Memory Size,
* 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
/*
* Final mapping:
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
+ volatile ulong *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
int misc_init_r (void)
{
- uchar kbd_data[KEYBD_DATALEN];
- uchar keybd_env[2 * KEYBD_DATALEN + 1];
- uchar *str;
+ char kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ char *str;
int i;
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
- i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
+ i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
for (i = 0; i < KEYBD_DATALEN; ++i) {
sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
}
setenv ("keybd", keybd_env);
- str = strdup (key_match (keybd_env)); /* decode keys */
+ str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */
#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
setenv ("preboot", str); /* set or delete definition */
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
- if ((kbd_magic_keys = getenv ("magic_keys")) != NULL) {
+ if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys;
*suffix || suffix == kbd_magic_keys;
++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
#if 0
printf ("### Check magic \"%s\"\n", magic);
#endif
- if ((str = getenv (magic)) != 0) {
+ if ((str = (uchar *)getenv ((char *)magic)) != 0) {
#if 0
printf ("### Compare \"%s\" \"%s\"\n",
kbd_str, str);
#endif
- if (strcmp (kbd_str, str) == 0) {
- sprintf (cmd_name, "%s%c",
+ if (strcmp ((char *)kbd_str, (char *)str) == 0) {
+ sprintf ((char *)cmd_name, "%s%c",
kbd_command_prefix,
*suffix);
- if ((cmd = getenv (cmd_name)) != 0) {
+ if ((cmd = getenv ((char *)cmd_name)) != 0) {
#if 0
printf ("### Set PREBOOT to $(%s): \"%s\"\n",
cmd_name, cmd);
#endif
- return (cmd);
+ return ((uchar *)cmd);
}
}
}
puts ("Keys:");
for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
printf (" %02x", kbd_data[i]);
}
putc ('\n');
- setenv ("keybd", keybd_env);
+ setenv ("keybd", (char *)keybd_env);
return 0;
}
#endif
switch (value)
{
- case 0x01:
- case AMD_MANUFACT:
+ case 0x01: /*AMD_MANUFACT*/
info->flash_id = FLASH_MAN_AMD;
break;
- case FUJ_MANUFACT:
+ case 0x04: /*FUJ_MANUFACT*/
info->flash_id = FLASH_MAN_FUJ;
break;
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
if (!s || strncmp (s, "TQM8", 4)) {
printf ("### No HW ID - assuming RBC823\n");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
* 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
/*
*/
uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
- i2c_read1(i2c_addr, reg, 1, &buf, 1);
+ i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
return(buf);
}
volatile unsigned long brdout_enable_ul; /* Read/Write */
volatile unsigned long brdin_data_ul; /* Read Only */
volatile unsigned long misc_ul; /* Read/Write */
-} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST;
+} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
/* OFEM FPGA */
typedef struct ofem_fpga_regs_s
volatile unsigned long scrmask_ul; /* Read/Write */
volatile unsigned long control_ul; /* Read/Write */
volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
-} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST;
+} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
#endif /* __KAREF_H__ */
volatile unsigned long scrmask_ul; /* Read/Write */
volatile unsigned long control_ul; /* Read/Write */
volatile unsigned long boardinfo_ul; /* Read Only */
-} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST;
+} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
#endif /* __METROBOX_H__ */
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
unsigned char *s;
unsigned char buf[64];
- s = (getenv_r ("serial#", buf, sizeof(buf)) > 0) ? buf : NULL;
+ s = (getenv_r ("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL;
puts ("Board: Siemens CCM");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size = size9;
* Check Bank 0 Memory Size for re-configuration
*
*/
- size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,
+ size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
}
}
- if (checkall && fpga_get_version(fpga, hdr.ih_name) < 0)
+ if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0)
return 1;
/* align length */
}
hdr = (image_header_t *)addr;
- if ((new_id = fpga_get_version(fpga, hdr->ih_name)) == -1)
+ if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1)
return 1;
do_load = 1;
* Check Bank 0 Memory Size for re-configuration
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
- volatile long *base_addr = base;
+ volatile ulong *base_addr = base;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong save2; /* to make test non-destructive */
int checkboard (void)
{
- unsigned char *s, *e;
- unsigned char buf[64];
+ char *s, *e;
+ char buf[64];
int i;
i = getenv_r("serial#", buf, sizeof(buf));
* Check for 32M SDRAM Memory Size
*/
size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
- (ulong *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
+ (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
udelay (1000);
/*
*/
if (size != SDRAM_32M_MAX_SIZE) {
size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
- (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+ (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
}
int checkboard (void)
{
- unsigned char *s, *e;
- unsigned char buf[64];
+ char *s, *e;
+ char buf[64];
int i;
i = getenv_r("serial#", buf, sizeof(buf));
*/
if (size != SDRAM_64M_MAX_SIZE) {
#endif
- size = dram_size (CFG_16M_MBMR, (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+ size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
#if 0
}
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 =
- dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+ dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
+ char *s = getenv("serial#");
int board_type;
if (!s || strncmp(s, "SVM8", 4)) {
/* find RAM size using SDRAM CS0 only */
mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
mpc5xxx_sdram_start(sdram_conf, 0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (test1 > test2) {
mpc5xxx_sdram_start(sdram_conf, 0);
dramsize2 = test1;
/* find RAM size */
mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
mpc5xxx_sdram_start(sdram_conf, 0);
dramsize = test1;
static int i2s_play_wave(unsigned long addr, unsigned long len)
{
unsigned long i;
- unsigned char *wave_file = (char *)addr + 44; /* quick'n dirty: skip
+ unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip
* wav header*/
unsigned char swapped[4];
struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned long reg, val, duration;
- unsigned char *tmp;
+ char *tmp;
unsigned int freq, channel;
unsigned char volume;
int rcode = 1;
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x80000000
+
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <asm-ppc/mmu.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+
+#define IOSYNC asm("eieio")
+#define ISYNC asm("isync")
+#define SYNC asm("sync")
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define DDR_MAX_SIZE_PER_CS 0x20000000
+
+#if defined(DDR_CASLAT_20)
+#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
+#define MODE_CASLAT DDR_MODE_CASLAT_20
+#else
+#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
+#define MODE_CASLAT DDR_MODE_CASLAT_25
+#endif
+
+#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
+ CSCONFIG_COL_BIT_9)
+
+/* Global variable used to store detected number of banks */
+int tqm834x_num_flash_banks;
+
+/* External definitions */
+ulong flash_get_size (ulong base, int banknum);
+extern flash_info_t flash_info[];
+extern long spd_sdram (void);
+
+/* Local functions */
+static int detect_num_flash_banks(void);
+static long int get_ddr_bank_size(short cs, volatile long *base);
+static void set_cs_bounds(short cs, long base, long size);
+static void set_cs_config(short cs, long config);
+static void set_ddr_config(void);
+
+/* Local variable */
+static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+
+/**************************************************************************
+ * Board initialzation after relocation to RAM. Used to detect the number
+ * of Flash banks on TQM834x.
+ */
+int board_early_init_r (void) {
+ /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return 0;
+
+ /* detect the number of Flash banks */
+ return detect_num_flash_banks();
+}
+
+/**************************************************************************
+ * DRAM initalization and size detection
+ */
+long int initdram (int board_type)
+{
+ long bank_size;
+ long size;
+ int cs;
+
+ /* during size detection, set up the max DDRLAW size */
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
+ im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
+
+ /* set CS bounds to maximum size */
+ for(cs = 0; cs < 4; ++cs) {
+ set_cs_bounds(cs,
+ CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+ DDR_MAX_SIZE_PER_CS);
+
+ set_cs_config(cs, INITIAL_CS_CONFIG);
+ }
+
+ /* configure ddr controller */
+ set_ddr_config();
+
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
+ SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR);
+ SYNC;
+
+ /* size detection */
+ debug("\n");
+ size = 0;
+ for(cs = 0; cs < 4; ++cs) {
+ debug("\nDetecting Bank%d\n", cs);
+
+ bank_size = get_ddr_bank_size(cs,
+ (volatile long*)(CFG_DDR_BASE + size));
+ size += bank_size;
+
+ debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
+
+ /* exit if less than one bank */
+ if(size < DDR_MAX_SIZE_PER_CS) break;
+ }
+
+ return size;
+}
+
+/**************************************************************************
+ * checkboard()
+ */
+int checkboard (void)
+{
+ puts("Board: TQM834x\n");
+
+#ifdef CONFIG_PCI
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf("PCI1: disabled\n");
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+
+/* FIXME: No PCI support */
+
+#endif /* CONFIG_PCI */
+
+/**************************************************************************
+ * pci_init_board()
+ */
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+ pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/**************************************************************************
+ *
+ * Local functions
+ *
+ *************************************************************************/
+
+/**************************************************************************
+ * Detect the number of flash banks (1 or 2). Store it in
+ * a global variable tqm834x_num_flash_banks.
+ * Bank detection code based on the Monitor code.
+ */
+static int detect_num_flash_banks(void)
+{
+ typedef unsigned long FLASH_PORT_WIDTH;
+ typedef volatile unsigned long FLASH_PORT_WIDTHV;
+ FPWV *bank1_base;
+ FPWV *bank2_base;
+ FPW bank1_read;
+ FPW bank2_read;
+ ulong bank1_size;
+ ulong bank2_size;
+ ulong total_size;
+
+ tqm834x_num_flash_banks = 2; /* assume two banks */
+
+ /* Get bank 1 and 2 information */
+ bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
+ debug("Bank1 size: %lu\n", bank1_size);
+ bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
+ debug("Bank2 size: %lu\n", bank2_size);
+ total_size = bank1_size + bank2_size;
+
+ if (bank2_size > 0) {
+ /* Seems like we've got bank 2, but maybe it's mirrored 1 */
+
+ /* Set the base addresses */
+ bank1_base = (FPWV *) (CFG_FLASH_BASE);
+ bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
+
+ /* Put bank 2 into CFI command mode and read */
+ bank2_base[0x55] = 0x00980098;
+ IOSYNC;
+ ISYNC;
+ bank2_read = bank2_base[0x10];
+
+ /* Read from bank 1 (it's in read mode) */
+ bank1_read = bank1_base[0x10];
+
+ /* Reset Flash */
+ bank1_base[0] = 0x00F000F0;
+ bank2_base[0] = 0x00F000F0;
+
+ if (bank2_read == bank1_read) {
+ /*
+ * Looks like just one bank, but not sure yet. Let's
+ * read from bank 2 in autosoelect mode.
+ */
+ bank2_base[0x0555] = 0x00AA00AA;
+ bank2_base[0x02AA] = 0x00550055;
+ bank2_base[0x0555] = 0x00900090;
+ IOSYNC;
+ ISYNC;
+ bank2_read = bank2_base[0x10];
+
+ /* Read from bank 1 (it's in read mode) */
+ bank1_read = bank1_base[0x10];
+
+ /* Reset Flash */
+ bank1_base[0] = 0x00F000F0;
+ bank2_base[0] = 0x00F000F0;
+
+ if (bank2_read == bank1_read) {
+ /*
+ * In both CFI command and autoselect modes,
+ * we got the some data reading from Flash.
+ * There is only one mirrored bank.
+ */
+ tqm834x_num_flash_banks = 1;
+ total_size = bank1_size;
+ }
+ }
+ }
+
+ debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
+
+ /* set OR0 and BR0 */
+ im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
+ (-(total_size) & OR_GPCM_AM);
+ im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
+ (BR_MS_GPCM | BR_PS_32 | BR_V);
+
+ return (0);
+}
+
+/*************************************************************************
+ * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
+ */
+static long int get_ddr_bank_size(short cs, volatile long *base)
+{
+ /* This array lists all valid DDR SDRAM configurations, with
+ * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
+ * The last entry has to to have size equal 0 and is igonred during
+ * autodection. Bank sizes must be in increasing order of size
+ */
+ struct {
+ long row;
+ long col;
+ long size;
+ } conf[] = {
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
+ {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
+ {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
+ {0, 0, 0}
+ };
+
+ int i;
+ int detected;
+ long size;
+
+ detected = -1;
+ for(i = 0; conf[i].size != 0; ++i) {
+
+ /* set sdram bank configuration */
+ set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
+
+ debug("Getting RAM size...\n");
+ size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
+
+ if((size == conf[i].size) && (i == detected + 1))
+ detected = i;
+
+ debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
+ conf[i].row,
+ conf[i].col,
+ conf[i].size >> 20,
+ base,
+ size >> 20);
+ }
+
+ if(detected == -1){
+ /* disable empty cs */
+ debug("\nNo valid configurations for CS%d, disabling...\n", cs);
+ set_cs_config(cs, 0);
+ return 0;
+ }
+
+ debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
+ conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
+
+ /* configure cs ro detected params */
+ set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
+ conf[detected].col);
+
+ set_cs_bounds(cs, (long)base, conf[detected].size);
+
+ return(conf[detected].size);
+}
+
+/**************************************************************************
+ * Sets DDR bank CS bounds.
+ */
+static void set_cs_bounds(short cs, long base, long size)
+{
+ debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
+ if(size == 0){
+ im->ddr.csbnds[cs].csbnds = 0x00000000;
+ } else {
+ im->ddr.csbnds[cs].csbnds =
+ ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((base + size - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA);
+ }
+ SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR banks CS configuration.
+ * config == 0x00000000 disables the CS.
+ */
+static void set_cs_config(short cs, long config)
+{
+ debug("Setting config %08x for cs %d\n", config, cs);
+ im->ddr.cs_config[cs] = config;
+ SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR clocks, timings and configuration.
+ */
+static void set_ddr_config(void) {
+ /* clock control */
+ im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+ SYNC;
+
+ /* timing configuration */
+ im->ddr.timing_cfg_1 =
+ (4 << TIMING_CFG1_PRETOACT_SHIFT) |
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
+ (4 << TIMING_CFG1_ACTTORW_SHIFT) |
+ (5 << TIMING_CFG1_REFREC_SHIFT) |
+ (3 << TIMING_CFG1_WRREC_SHIFT) |
+ (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
+ (1 << TIMING_CFG1_WRTORD_SHIFT) |
+ (TIMING_CFG1_CASLAT & TIMING_CASLAT);
+
+ im->ddr.timing_cfg_2 =
+ TIMING_CFG2_CPO_DEF |
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
+ SYNC;
+
+ /* don't enable DDR controller yet */
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR;
+ SYNC;
+
+ /* Set SDRAM mode */
+ im->ddr.sdram_mode =
+ ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
+ SDRAM_MODE_ESD_SHIFT) |
+ ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
+ SDRAM_MODE_SD_SHIFT) |
+ ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
+ MODE_CASLAT);
+ SYNC;
+
+ /* Set fast SDRAM refresh rate */
+ im->ddr.sdram_interval =
+ (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
+ (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
+ SYNC;
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc83xx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
/* set serial# and ethaddr if not yet defined */
if (getenv("serial#") == NULL) {
- setenv ("serial#", serial);
+ setenv ((char *)"serial#", (char *)serial);
}
if (getenv("ethaddr") == NULL) {
- setenv ("ethaddr", ethaddr);
+ setenv ((char *)"ethaddr", (char *)ethaddr);
}
}
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s = getenv ("serial#");
+ char *s = getenv ("serial#");
puts ("Board: ");
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
- size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+ size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
} else {
*/
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
int flag;
ulong status;
int rcode = 0;
- volatile long *addr = (unsigned long *)sector;
+ volatile long *addr = (long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
int flag;
ulong status;
int rcode = 0;
- volatile long *addr = (unsigned long *)sector;
+ volatile long *addr = (long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
xcv_len = len - 14 - fn_len; /* fpga image length */
/* Check for uninitialized FLASH */
- if ((strncmp(buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
+ if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
goto bad_image;
/*
unsigned short stored_crc16, calc_crc16 = 0xffff;
/* Check Eyecatcher */
- if (strncmp(vpd->header.eyecatcher, VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
+ if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
unsigned offset = 0;
if (dev_addr == CFG_DEF_EEPROM_ADDR)
offset += SDRAM_SPD_DATA_SIZE;
case VPD_PID_PID:
if (strlen_ok(packet, MAX_PROD_ID)) {
strncpy(vpdInfo->productId,
- packet->data, packet->size);
+ (char *)(packet->data), packet->size);
}
break;
case VPD_PID_REV:
(strncmp (vpd->productId, "CMM", 3) == 0))) {
char buf[30];
char *eth;
- unsigned char *serial = getenv ("serial#");
- unsigned char *ethaddr = getenv ("ethaddr");
+ char *serial = getenv ("serial#");
+ char *ethaddr = getenv ("ethaddr");
/* Set 'serial#' envvar if serial# isn't set */
if (!serial) {
}
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
- eth = vpd->ethAddrs[0];
+ eth = (char *)(vpd->ethAddrs[0]);
if (ethaddr
&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
/* Now setup ethaddr */
/* initialize the version of the component
*/
- XVersion_FromString(&InstancePtr->Version, "1.00a");
+ XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
/* reset the DMA channel such that it's in a known state and ready
* and indicate the initialization occured with no errors, note that
int
checkboard(void)
{
- uchar tmp[64]; /* long enough for environment variables */
- uchar *s, *e;
+ char tmp[64]; /* long enough for environment variables */
+ char *s, *e;
int i = getenv_r("L", tmp, sizeof (tmp));
if (i < 0) {
RecvFrameLength = PKTSIZE;
Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
if (Result == XST_SUCCESS) {
- NetReceive(etherrxbuff, RecvFrameLength);
+ NetReceive((uchar)etherrxbuff, RecvFrameLength);
return (1);
} else {
return (0);
static void
ip_ml300(uchar * s, uchar * res)
{
- uchar temp[2];
+ char temp[2];
u8 i;
res[0] = 0x00;
for (i = 0; i < 4; i++) {
sprintf(temp, "%02x", atoi(s));
- s = strchr(s, '.') + 1;
- strcat(res, temp);
+ s = (uchar *)strchr((char *)s, '.') + 1;
+ strcat((char *)res, temp);
}
}
change_null(uchar * s)
{
if (s != NULL) {
- change_null(strchr(s + 1, 255));
- *(strchr(s, 255)) = '\0';
+ change_null((uchar *)strchr((char *)s + 1, 255));
+ *(strchr((char *)s, 255)) = '\0';
}
}
void
convert_env(void)
{
- uchar *s; /* pointer to env value */
- uchar temp[20]; /* temp storage for addresses */
+ char *s; /* pointer to env value */
+ char temp[20]; /* temp storage for addresses */
/* E -> ethaddr */
s = getenv("E");
/* I -> ipaddr */
s = getenv("I");
if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi(s), axtoi(s + 2),
- axtoi(s + 4), axtoi(s + 6));
+ sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
+ axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
setenv("ipaddr", temp);
setenv("I", NULL);
}
/* S -> serverip */
s = getenv("S");
if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi(s), axtoi(s + 2),
- axtoi(s + 4), axtoi(s + 6));
+ sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
+ axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
setenv("serverip", temp);
setenv("S", NULL);
}
static void
save_env(void)
{
- uchar eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */
- uchar *s, temp[20];
- uchar ff[] = { 0xff, 0x00 }; /* dummy null value */
+ char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */
+ char *s, temp[20];
+ char ff[] = { 0xff, 0x00 }; /* dummy null value */
u32 len; /* length of env to be written to EEPROM */
eprom[0] = 0x00;
s = getenv("ipaddr");
if (s != NULL) {
strcat(eprom, "I=");
- ip_ml300(s, temp);
+ ip_ml300((uchar *)s, (uchar *)temp);
strcat(eprom, temp);
strcat(eprom, ff);
}
s = getenv("serverip");
if (s != NULL) {
strcat(eprom, "S=");
- ip_ml300(s, temp);
+ ip_ml300((uchar *)s, (uchar *)temp);
strcat(eprom, temp);
strcat(eprom, ff);
}
}
len = strlen(eprom); /* find env length without crc */
- change_null(eprom); /* change 0xff to 0x00 */
+ change_null((uchar *)eprom); /* change 0xff to 0x00 */
/* update EEPROM env values if there is enough space */
- if (update_crc(len, eprom) == 0)
- send(CFG_ENV_OFFSET, eprom, len + 6);
+ if (update_crc(len, (uchar *)eprom) == 0)
+ send(CFG_ENV_OFFSET, (uchar *)eprom, len + 6);
}
/************************************************************************
hdr->ih_hcrc = 0;
len = sizeof (image_header_t);
data = (ulong)hdr;
- if (crc32(0, (char *)data, len) != crc) {
+ if (crc32(0, (uchar *)data, len) != crc) {
puts ("Bad header crc\n");
return 1;
}
len = ntohl(hdr->ih_size);
if (verify) {
- if (crc32(0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32(0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts ("Bad data crc\n");
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_IMLS)
#include <flash.h>
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[]; /* info for FLASH chips */
static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
#endif
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-2);
return 1;
if (verify) {
puts (" Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
SHOW_BOOT_PROGRESS (-3);
return 1;
checksum = hdr->ih_hcrc;
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-11);
do_reset (cmdtp, flag, argc, argv);
if (chunk > CHUNKSZ)
chunk = CHUNKSZ;
- csum = crc32 (csum, (char *)cdata, chunk);
+ csum = crc32 (csum, (uchar *)cdata, chunk);
cdata += chunk;
WATCHDOG_RESET();
}
#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
- csum = crc32 (0, (char *)data, len);
+ csum = crc32 (0, (uchar *)data, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
if (csum != hdr->ih_dcrc) {
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)data, len) != checksum) {
+ if (crc32 (0, (uchar *)data, len) != checksum) {
puts (" Bad Header Checksum\n");
return 1;
}
len = ntohl(hdr->ih_size);
puts (" Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts (" Bad Data CRC\n");
return 1;
}
for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
if (info->flash_id == FLASH_UNKNOWN)
goto next_bank;
- for (j=0; j<CFG_MAX_FLASH_SECT; ++j) {
+ for (j=0; j<info->sector_count; ++j) {
if (!(hdr=(image_header_t *)info->start[j]) ||
(ntohl(hdr->ih_magic) != IH_MAGIC))
checksum = ntohl(header.ih_hcrc);
header.ih_hcrc = 0;
- if (crc32 (0, (char *)&header, sizeof(image_header_t))
+ if (crc32 (0, (uchar *)&header, sizeof(image_header_t))
!= checksum)
goto next_sector;
len = ntohl(hdr->ih_size);
puts (" Verifying Checksum ... ");
- if (crc32 (0, (char *)data, len) != ntohl(hdr->ih_dcrc)) {
+ if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
puts (" Bad Data CRC\n");
}
puts ("OK\n");
cmd ? "read" : "write", curr_device, off, size);
ret = doc_rw(doc_dev_desc + curr_device, cmd, off, size,
- &total, (u_char*)addr);
+ (size_t *)&total, (u_char*)addr);
printf ("%d bytes %s: %s\n", total, cmd ? "read" : "write",
ret ? "ERROR" : "OK");
if (cmd)
ret = doc_read_ecc(this, from, len,
- &n, (u_char*)buf,
- noecc ? NULL : eccbuf);
+ (size_t *)&n, (u_char*)buf,
+ noecc ? (uchar *)NULL : (uchar *)eccbuf);
else
ret = doc_write_ecc(this, from, len,
- &n, (u_char*)buf,
- noecc ? NULL : eccbuf);
+ (size_t *)&n, (u_char*)buf,
+ noecc ? (uchar *)NULL : (uchar *)eccbuf);
if (ret)
break;
/* Check for ANAND header first. Then can whinge if it's found but later
checks fail */
if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize, SECTORSIZE,
- &retlen, buf, NULL))) {
+ (size_t *)&retlen, buf, NULL))) {
static int warncount = 5;
if (warncount) {
/* To be safer with BIOS, also use erase mark as discriminant */
if ((ret = doc_read_oob(nftl->mtd, block * nftl->EraseSize + SECTORSIZE + 8,
- 8, &retlen, (char *)&h1) < 0)) {
+ 8, (size_t *)&retlen, (uchar *)&h1) < 0)) {
#ifdef NFTL_DEBUG
printf("ANAND header found at 0x%x, but OOB data read failed\n",
block * nftl->EraseSize);
/* read one sector for every SECTORSIZE of blocks */
if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize +
i + SECTORSIZE, SECTORSIZE,
- &retlen, buf, (char *)&oob)) < 0) {
+ (size_t *)&retlen, buf, (uchar *)&oob)) < 0) {
puts ("Read of bad sector table failed\n");
return -1;
}
return(1);
}
- if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
+ if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
{
flash_info_t *info;
ulong bank;
+#ifdef CFG_MAX_FLASH_BANKS_DETECT
+ int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
+#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
+#endif
int erased = 0;
int planned;
int rcode = 0;
{
flash_info_t *info;
ulong bank;
+#ifdef CFG_MAX_FLASH_BANKS_DETECT
+ int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT];
+#else
int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS];
+#endif
int protected, i;
int planned;
int rcode;
unsigned int i;
int rc;
- dataptr = fpgadata;
+ dataptr = (unsigned char *)fpgadata;
#if CFG_FPGA_XILINX
/* skip the first bytes of the bitsteam, their meaning is unknown */
*/
do {
printf("%08lx:", addr);
- if(i2c_read(chip, addr, alen, (char *)&data, size) != 0) {
+ if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) {
puts ("\nError reading the chip,\n");
} else {
data = cpu_to_be32(data);
*/
reset_cmd_timeout();
#endif
- if(i2c_write(chip, addr, alen, (char *)&data, size) != 0) {
+ if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) {
puts ("Error writing the chip.\n");
}
#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
SHOW_BOOT_PROGRESS (-1);
return 1;
}
- if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
- (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
+ if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+ (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(image_header_t)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
SHOW_BOOT_PROGRESS (-2);
return 1;
if (rcode == 0) {
iopin.port = port;
iopin.pin = pin;
+ iopin.flag = 0;
switch (cmd) {
case DIR:
if (value)
{
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
/* info for FLASH chips */
- extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ extern flash_info_t flash_info[];
flash_info_t *flash;
int offset_aligned;
u32 end_offset;
if (type == MTD_DEV_TYPE_NOR) {
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
if (num < CFG_MAX_FLASH_BANKS) {
- extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ extern flash_info_t flash_info[];
*size = flash_info[num].size;
return 0;
}
if (addr2info(store_addr)) {
int rc;
- rc = flash_write((uchar *)binbuf,store_addr,binlen);
+ rc = flash_write((char *)binbuf,store_addr,binlen);
if (rc != 0) {
flash_perror (rc);
return (~0);
case 2:
if (strcmp(argv[1],"show") == 0) {
for (i=0; i < (log_size&LOGBUFF_MASK); i++) {
- s = log_buf+((log_start+i)&LOGBUFF_MASK);
+ s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK);
putc (*s);
}
return 0;
}
#endif
puts (" ");
- cp = linebuf;
+ cp = (u_char *)linebuf;
for (i=0; i<linebytes; i++) {
if ((*cp < 0x20) || (*cp > 0x7e))
putc ('.');
puts ("Copy to Flash... ");
- rc = flash_write ((uchar *)addr, dest, count*size);
+ rc = flash_write ((char *)addr, dest, count*size);
if (rc != 0) {
flash_perror (rc);
return (1);
* Look for any and all PHYs. Valid addresses are 0..31.
*/
if (argc >= 3) {
- start = addr; end = addr + 1;
+ start = addrlo; end = addrhi + 1;
} else {
start = 0; end = 32;
}
/* read out-of-band data */
if (cmd & NANDRW_READ) {
ret = nand_read_oob(nand_dev_desc + curr_device,
- off, size, &total,
+ off, size, (size_t *)&total,
(u_char*)addr);
}
else {
ret = nand_write_oob(nand_dev_desc + curr_device,
- off, size, &total,
+ off, size, (size_t *)&total,
(u_char*)addr);
}
return ret;
curr_device, off, size);
ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
- &total, (u_char*)addr);
+ (size_t *)&total, (u_char*)addr);
printf (" %d bytes %s: %s\n", total,
(cmd & NANDRW_READ) ? "read" : "written",
*/
int check_block (struct nand_chip *nand, unsigned long pos)
{
- int retlen;
+ size_t retlen;
uint8_t oob_data;
uint16_t oob_data16[6];
int page0 = pos & (-nand->erasesize);
return 1;
} else {
/* Note - bad block marker can be on first or second page */
- if (nand_read_oob(nand, page0 + badpos, 1, &retlen, &oob_data)
+ if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)
|| oob_data != 0xff
- || nand_read_oob (nand, page1 + badpos, 1, &retlen, &oob_data)
+ || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)
|| oob_data != 0xff)
return 1;
}
if (cmd & NANDRW_READ) {
ret = nand_read_ecc(nand, start,
min(len, eblk + erasesize - start),
- &n, (u_char*)buf, eccbuf);
+ (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
} else {
ret = nand_write_ecc(nand, start,
min(len, eblk + erasesize - start),
- &n, (u_char*)buf, eccbuf);
+ (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
}
if (ret)
l = NAND_JFFS2_OOB16_FSDALEN;
}
- ret = nand_write_oob(nand, ofs + p, l, &n,
+ ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n,
(u_char *)&clean_marker);
/* quit here if write failed */
if (ret)
for (nxt=j; env_get_char(nxt) != '\0'; ++nxt)
;
- k = envmatch(name, j);
+ k = envmatch((uchar *)name, j);
if (k < 0) {
continue;
}
int i, len, oldval;
int console = -1;
uchar *env, *nxt = NULL;
- uchar *name;
+ char *name;
bd_t *bd = gd->bd;
uchar *env_data = env_get_addr(0);
for (env=env_data; *env; env=nxt+1) {
for (nxt=env; *nxt; ++nxt)
;
- if ((oldval = envmatch(name, env-env_data)) >= 0)
+ if ((oldval = envmatch((uchar *)name, env-env_data)) >= 0)
break;
}
if ( (strcmp (name, "serial#") == 0) ||
((strcmp (name, "ethaddr") == 0)
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && (strcmp (env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
+ && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
) ) {
printf ("Can't overwrite \"%s\"\n", name);
* or NULL if not found
*/
-char *getenv (uchar *name)
+char *getenv (char *name)
{
int i, nxt;
return (NULL);
}
}
- if ((val=envmatch(name, i)) < 0)
+ if ((val=envmatch((uchar *)name, i)) < 0)
continue;
- return (env_get_addr(val));
+ return ((char *)env_get_addr(val));
}
return (NULL);
}
-int getenv_r (uchar *name, uchar *buf, unsigned len)
+int getenv_r (char *name, char *buf, unsigned len)
{
int i, nxt;
return (-1);
}
}
- if ((val=envmatch(name, i)) < 0)
+ if ((val=envmatch((uchar *)name, i)) < 0)
continue;
/* found; copy out */
n = 0;
#define MAX_IDENT_FIELDS 4
static uchar *known_cards[] = {
- "ARGOSY PnPIDE D5",
+ (uchar *)"ARGOSY PnPIDE D5",
NULL
};
else
break;
}
- puts (id_str);
+ puts ((char *)id_str);
putc ('\n');
for (card=known_cards; *card; ++card) {
debug ("## Compare against \"%s\"\n", *card);
- if (strcmp(*card, id_str) == 0) { /* found! */
+ if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */
debug ("## CARD FOUND ##\n");
return (1);
}
printf("error reading partinfo\n");
return 1;
}
- if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
- (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
+ if ((strncmp((char *)(info.type), BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+ (strncmp((char *)(info.type), BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(image_header_t)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
return 1;
}
printf("Error with the SPI transaction.\n");
rcode = 1;
} else {
- cp = din;
+ cp = (char *)din;
for(j = 0; j < ((bitlen + 7) / 8); j++) {
printf("%02X", *cp++);
}
if (get_partition_info (stor_dev, part, &info)) {
/* try to boot raw .... */
- strncpy(&info.type[0], BOOT_PART_TYPE, sizeof(BOOT_PART_TYPE));
- strncpy(&info.name[0], "Raw", 4);
+ strncpy((char *)&info.type[0], BOOT_PART_TYPE, sizeof(BOOT_PART_TYPE));
+ strncpy((char *)&info.name[0], "Raw", 4);
info.start=0;
info.blksz=0x200;
info.size=2880;
printf("error reading partinfo...try to boot raw\n");
}
- if ((strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
- (strncmp(info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
+ if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
+ (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
- if (crc32 (0, (char *)hdr, sizeof(image_header_t)) != checksum) {
+ if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
return 1;
}
for (nxt=i; env_get_char(nxt) != '\0'; ++nxt)
;
- lval = env_get_addr(i);
+ lval = (char *)env_get_addr(i);
rval = strchr(lval, '=');
if (rval != NULL) {
vallen = rval - lval;
debug (" %08lX ... %08lX ...",
(ulong)&(flash_addr_new->data),
sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data));
- if ((rc = flash_write(env_ptr->data,
+ if ((rc = flash_write((char *)env_ptr->data,
(ulong)&(flash_addr_new->data),
sizeof(env_ptr->data))) ||
(rc = flash_write((char *)&(env_ptr->crc),
ulong flash_offset;
uchar env_buffer[CFG_ENV_SECT_SIZE];
#else
- uchar *env_buffer = (char *)env_ptr;
+ uchar *env_buffer = (uchar *)env_ptr;
#endif /* CFG_ENV_SECT_SIZE */
int rcode = 0;
return 1;
puts ("Writing to Flash... ");
- rc = flash_write(env_buffer, flash_sect_addr, len);
+ rc = flash_write((char *)env_buffer, flash_sect_addr, len);
if (rc != 0) {
flash_perror (rc);
rcode = 1;
#if !defined(CFG_NO_FLASH)
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
* (only some targets require alignment)
*/
int
-flash_write (uchar *src, ulong addr, ulong cnt)
+flash_write (char *src, ulong addr, ulong cnt)
{
#ifdef CONFIG_SPD823TS
return (ERR_TIMOUT); /* any other error codes are possible as well */
len = info->start[0] + info->size - addr;
if (len > cnt)
len = cnt;
- if ((i = write_buff(info, src, addr, len)) != 0) {
+ if ((i = write_buff(info, (uchar *)src, addr, len)) != 0) {
return (i);
}
cnt -= len;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
/* Local static functions */
-static const fpga_desc * const fpga_get_desc( int devnum );
-static const fpga_desc * const fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
size_t bsize, char *fn );
static int fpga_dev_info( int devnum );
/* fpga_get_desc
* map a device number to a descriptor
*/
-static const fpga_desc * const fpga_get_desc( int devnum )
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum )
{
fpga_desc *desc = (fpga_desc * )NULL;
/* fpga_validate
* generic parameter checking code
*/
-static const fpga_desc * const fpga_validate( int devnum, void *buf,
+static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf,
size_t bsize, char *fn )
{
- const fpga_desc * const desc = fpga_get_desc( devnum );
+ fpga_desc * desc = fpga_get_desc( devnum );
if ( !desc ) {
printf( "%s: Invalid device number %d\n", fn, devnum );
printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
ret_val = altera_info( desc->devdesc );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
#if CONFIG_FPGA & CFG_FPGA_ALTERA
ret_val = altera_reloc( desc, reloc_off );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
/* fpga_count
* Basic interface function to get the current number of devices available.
*/
-const int fpga_count( void )
+int fpga_count( void )
{
return next_desc;
}
int fpga_load( int devnum, void *buf, size_t bsize )
{
int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_validate( devnum, buf, bsize, __FUNCTION__ );
+ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
if ( desc ) {
switch ( desc->devtype ) {
#if CONFIG_FPGA & CFG_FPGA_ALTERA
ret_val = altera_load( desc->devdesc, buf, bsize );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
int fpga_dump( int devnum, void *buf, size_t bsize )
{
int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_validate( devnum, buf, bsize, __FUNCTION__ );
+ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
if ( desc ) {
switch ( desc->devtype ) {
#if CONFIG_FPGA & CFG_FPGA_ALTERA
ret_val = altera_dump( desc->devdesc, buf, bsize );
#else
- fpga_no_sup( __FUNCTION__, "Altera devices" );
+ fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
default:
#endif
/* "globals" within this file */
-static char *ifs;
+static uchar *ifs;
static char map[256];
#ifndef __U_BOOT__
static int fake_mode;
void update_ifs_map(void)
{
/* char *ifs and char map[256] are both globals. */
- ifs = getenv("IFS");
- if (ifs == NULL) ifs=" \t\n";
+ ifs = (uchar *)getenv("IFS");
+ if (ifs == NULL) ifs=(uchar *)" \t\n";
/* Precompute a list of 'flow through' behavior so it can be treated
* quickly up front. Computation is necessary because of IFS.
* Special case handling of IFS == " \t\n" is not implemented.
*/
memset(map,0,sizeof(map)); /* most characters flow through always */
#ifndef __U_BOOT__
- mapset("\\$'\"`", 3); /* never flow through */
- mapset("<>;&|(){}#", 1); /* flow through if quoted */
+ mapset((uchar *)"\\$'\"`", 3); /* never flow through */
+ mapset((uchar *)"<>;&|(){}#", 1); /* flow through if quoted */
#else
- mapset("\\$'\"", 3); /* never flow through */
- mapset(";&|#", 1); /* flow through if quoted */
+ mapset((uchar *)"\\$'\"", 3); /* never flow through */
+ mapset((uchar *)";&|#", 1); /* flow through if quoted */
#endif
mapset(ifs, 2); /* also flow through if quoted */
}
ctx.type = flag;
initialize_context(&ctx);
update_ifs_map();
- if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset(";$&|", 0);
+ if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0);
inp->promptmode=1;
rcode = parse_stream(&temp, &ctx, inp, '\n');
#ifdef __U_BOOT__
}
*buf = 0;
longjmp_on_fault = 0;
- return buf;
+ return (unsigned char *)buf;
}
/* convert the hex array pointed to by buf into binary to be placed in mem
*ptr++ = hexchars[rp->num >> 4];
*ptr++ = hexchars[rp->num & 0xf];
*ptr++ = ':';
- ptr = mem2hex((char *)&rp->val, ptr, 4);
+ ptr = (char *)mem2hex((char *)&rp->val, ptr, 4);
*ptr++ = ';';
}
printf("kgdb: remcomOutBuffer: %s\n", remcomOutBuffer);
#endif
- putpacket(remcomOutBuffer);
+ putpacket((unsigned char *)&remcomOutBuffer);
while (1) {
volatile int errnum;
#endif
/* reply to the request */
- putpacket(remcomOutBuffer);
+ putpacket((unsigned char *)&remcomOutBuffer);
} /* while(1) */
}
buffer[0] = 'O';
mem2hex ((char *)s, &buffer[1], count);
- putpacket(buffer);
+ putpacket((unsigned char *)&buffer);
return 1;
}
static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
{
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
- lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen (s));
+ lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen ((char *)s));
#else
- lcd_drawchars (x, y, s, strlen (s));
+ lcd_drawchars (x, y, s, strlen ((char *)s));
#endif
}
sizeof(bmp_logo_palette)/(sizeof(ushort)));
bmap = &bmp_logo_bitmap[0];
- fb = (char *)(lcd_base + y * lcd_line_length + x);
+ fb = (uchar *)(lcd_base + y * lcd_line_length + x);
if (NBITS(panel_info.vl_bpix) < 12) {
/* Leave room for default color map */
#ifdef CONFIG_MPC823
# ifdef CONFIG_LCD_INFO
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
- lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, info, strlen(info));
+ lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
sprintf (info, "(C) 2004 DENX Software Engineering");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
- info, strlen(info));
+ (uchar *)info, strlen(info));
sprintf (info, " Wolfgang DENK, wd@denx.de");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
- info, strlen(info));
+ (uchar *)info, strlen(info));
# ifdef CONFIG_LCD_INFO_BELOW_LOGO
sprintf (info, "MPC823 CPU at %s MHz",
strmhz(temp, gd->cpu_clk));
gd->ram_size >> 20,
gd->bd->bi_flashsize >> 20 );
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
- info, strlen(info));
+ (uchar *)info, strlen(info));
# endif /* CONFIG_LCD_INFO_BELOW_LOGO */
# endif /* CONFIG_LCD_INFO */
#ifdef CONFIG_MODEM_SUPPORT
debug ("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init);
if (do_mdm_init) {
- uchar *str = strdup(getenv("mdm_cmd"));
+ char *str = strdup(getenv("mdm_cmd"));
setenv ("preboot", str); /* set or delete definition */
if (str != NULL)
free (str);
*/
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
*/
int usb_stor_CB_comdat(ccb *srb, struct us_data *us)
{
- int result;
+ int result = 0;
int dir_in,retry;
unsigned int pipe;
unsigned long status;
USB_STOR_PRINTF("CB_transport: control msg returned %d, direction is %s to go 0x%lx\n",result,dir_in ? "IN" : "OUT",srb->datalen);
if (srb->datalen) {
- result = us_one_transfer(us, pipe, srb->pdata,srb->datalen);
+ result = us_one_transfer(us, pipe, (char *)srb->pdata,srb->datalen);
USB_STOR_PRINTF("CBI attempted to transfer data, result is %d status %lX, len %d\n", result,us->pusb_dev->status,us->pusb_dev->act_len);
if(!(us->pusb_dev->status & USB_ST_NAK_REC))
break;
{
char *ptr;
- ptr=srb->pdata;
+ ptr=(char *)srb->pdata;
memset(&srb->cmd[0],0,12);
srb->cmd[0]=SCSI_REQ_SENSE;
srb->cmd[1]=srb->lun<<5;
srb->cmdlen=12;
ss->transport(srb,ss);
USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]);
- srb->pdata=ptr;
+ srb->pdata=(uchar *)ptr;
return 0;
}
{
int ret_val = FPGA_FAIL; /* assume a failure */
- if (!xilinx_validate (desc, __FUNCTION__)) {
+ if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
{
int ret_val = FPGA_FAIL; /* assume a failure */
- if (!xilinx_validate (desc, __FUNCTION__)) {
+ if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
{
int ret_val = FPGA_FAIL;
- if (xilinx_validate (desc, __FUNCTION__)) {
+ if (xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("Family: \t");
switch (desc->family) {
case Xilinx_Spartan2:
{
int ret_val = FPGA_FAIL; /* assume a failure */
- if (!xilinx_validate (desc, __FUNCTION__)) {
+ if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
* Set individual address filter for unicast address
* and set physical address registers.
*/
- mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
+ mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
/*
* Set multicast address filter
unsigned long ievent;
int frame_length, len = 0;
NBUF *frame;
- char buff[FEC_MAX_PKT_SIZE];
+ uchar buff[FEC_MAX_PKT_SIZE];
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
static int mpc_reg_in(volatile u32 *reg)
{
- return *reg >> 24;
+ int ret = *reg >> 24;
__asm__ __volatile__ ("eieio");
+ return ret;
}
static void mpc_reg_out(volatile u32 *reg, int val, int mask)
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- uchar xaddr[4];
+ char xaddr[4];
struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
int ret = -1;
goto Done;
}
- if (receive_bytes(chip, buf, len)) {
+ if (receive_bytes(chip, (char *)buf, len)) {
printf("i2c_read: receive_bytes failed\n");
goto Done;
}
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- uchar xaddr[4];
+ char xaddr[4];
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
int ret = -1;
goto Done;
}
- if (send_bytes(chip, buf, len)) {
+ if (send_bytes(chip, (char *)buf, len)) {
printf("i2c_write: send_bytes failed\n");
goto Done;
}
uchar i2c_reg_read(uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(chip, reg, 1, &buf, 1);
* Set individual address filter for unicast address
* and set physical address registers.
*/
- mpc8220_fec_set_hwaddr (fec, dev->enetaddr);
+ mpc8220_fec_set_hwaddr (fec, (char *)(dev->enetaddr));
/*
* Set multicast address filter
static int mpc_reg_in (volatile u32 * reg)
{
- return *reg >> 24;
+ int ret;
+ ret = *reg >> 24;
__asm__ __volatile__ ("eieio");
+ return ret;
}
static void mpc_reg_out (volatile u32 * reg, int val, int mask)
goto Done;
}
- if (send_bytes (chip, &xaddr[4 - alen], alen)) {
+ if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) {
printf ("i2c_read: send_bytes failed\n");
goto Done;
}
goto Done;
}
- if (receive_bytes (chip, buf, len)) {
+ if (receive_bytes (chip, (char *)buf, len)) {
printf ("i2c_read: receive_bytes failed\n");
goto Done;
}
goto Done;
}
- if (send_bytes (chip, &xaddr[4 - alen], alen)) {
+ if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) {
printf ("i2c_write: send_bytes failed\n");
goto Done;
}
- if (send_bytes (chip, buf, len)) {
+ if (send_bytes (chip, (char *)buf, len)) {
printf ("i2c_write: send_bytes failed\n");
goto Done;
}
uchar i2c_reg_read (uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read (chip, reg, 1, &buf, 1);
* and looking for an <ACK> back.
*/
udelay (10000);
- return i2c_read (chip, 0, 1, (char *) &tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *) &tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
uchar
i2c_reg_read(uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(chip, reg, 1, &buf, 1);
return -1;
}
- puts("CPU: MPC83xx, ");
+ puts("CPU: MPC83xx, ");
switch(pvr) {
case PVR_8349_REV10:
break;
#include <i2c.h>
#include <asm/i2c.h>
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
#endif
return 0;
} while (get_timer (timeval) < I2C_TIMEOUT);
+
debug("i2c_wait: timed out\n");
+ return -1;
}
static __inline__ int
* and looking for an <ACK> back.
*/
udelay(10000);
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
#include <common.h>
#include <pci.h>
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
#include <asm/i2c.h>
#endif
/*
* Assign PIB PMC slot to desired PCI bus
*/
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
#endif
return -1;
#ifndef CFG_HRCW_HIGH
-# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
+# error "CFG_HRCW_HIGH must be defined in board config file"
#endif /* CFG_HCWD_HIGH */
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
+
# ifndef CONFIG_83XX_CLKIN
-# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
+# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
# endif /* CONFIG_83XX_CLKIN */
# ifdef CONFIG_83XX_PCICLK
-# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
+# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
# endif /* CONFIG_83XX_PCICLK */
-/* PCI Host Mode */
+
+ /* PCI Host Mode */
if (!(im->reset.rcwh & RCWH_PCIHOST)) {
- /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
- /* FIXME: findout if there is a way to issue some warning */
+ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
+ * the im->reset.rcwhr PCI Host Mode is disabled
+ * FIXME: findout if there is a way to issue some warning */
return -2;
}
if (im->clk.spmr & SPMR_CKID) {
- pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
+ /* PCI Clock is half CONFIG_83XX_CLKIN */
+ pci_sync_in = CONFIG_83XX_CLKIN / 2;
}
else {
pci_sync_in = CONFIG_83XX_CLKIN;
}
-#else
+
+#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
+
# ifdef CONFIG_83XX_CLKIN
-# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
+# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
# endif /* CONFIG_83XX_CLKIN */
# ifndef CONFIG_83XX_PCICLK
-# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
+# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
# endif /* CONFIG_83XX_PCICLK */
-/* PCI Agent Mode */
+
+ /* PCI Agent Mode */
if (im->reset.rcwh & RCWH_PCIHOST) {
- /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
+ /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
+ * the im->reset.rcwhr PCI Host Mode is enabled */
return -3;
}
pci_sync_in = CONFIG_83XX_PCICLK;
+
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */
printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000);
- printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
+ debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
- printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
- printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
- printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
- printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
- printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
- printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
-
-#if 0
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- ulong sccr, dfbrg;
- ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
- corecnf_t *cp;
-
- sccr = immap->im_clkrst.car_sccr;
- dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
-
- scmr = immap->im_clkrst.car_scmr;
- corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
- busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
- cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
- plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
- pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
-
- cp = &corecnf_tab[corecnf];
-
- puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
-
- switch (cp->b2c_mult) {
- case _byp:
- puts ("BYPASS");
- break;
+ debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
+ debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
+ debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
+ debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
+ debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
+ debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
- case _off:
- puts ("OFF");
- break;
-
- case _unk:
- puts ("UNKNOWN");
- break;
-
- default:
- printf ("%d%sx",
- cp->b2c_mult / 2,
- (cp->b2c_mult % 2) ? ".5" : "");
- break;
- }
-
- printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
- cp->vco_div, cp->freq_60x, cp->freq_core);
-
- printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
- "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
- pllmf);
-
- printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
- gd->vco_out, gd->scc_clk, gd->brg_clk);
-
- printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
- gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
-
- if (sccr & SCCR_PCI_MODE) {
- uint pci_div;
-
- pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
- ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
-
- printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
- }
- putc ('\n');
-#endif
return 0;
}
* and looking for an <ACK> back.
*/
udelay(10000);
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float
uchar
i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
for (i = 0; i < TEST_NUM; i++) {
for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) {
- packet_fill (txbuf, l);
+ packet_fill ((char *)txbuf, l);
spi_xfer (l);
- if (packet_check (rxbuf, l) < 0) {
+ if (packet_check ((char *)rxbuf, l) < 0) {
goto Done;
}
}
}
}
-static inline void video_drawstring (int xx, int yy, unsigned char *s)
+static inline void video_drawstring (int xx, int yy, char *s)
{
- video_drawchars (xx, yy, s, strlen (s));
+ video_drawchars (xx, yy, (unsigned char *)s, strlen (s));
}
/* Relative to console plotting functions */
static inline void video_putstring (int xx, int yy, unsigned char *s)
{
- video_putchars (xx, yy, s, strlen (s));
+ video_putchars (xx, yy, (unsigned char *)s, strlen ((char *)s));
}
/************************************************************************/
*/
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
int spd_read(uint addr)
{
- char data[2];
+ uchar data[2];
if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
return (int)data[0];
(buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
return (-1);
} /* no DOS Signature at all */
- if(strncmp(&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0)
+ if(strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0)
return DOS_PBR; /* is PBR */
return DOS_MBR; /* Is MBR */
}
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_ATAPI:
- sprintf (info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_SCSI:
- sprintf (info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_USB:
- sprintf (info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_DOC:
- sprintf (info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
default:
- sprintf (info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
break;
}
/* sprintf(info->type, "%d, pt->sys_ind); */
- sprintf (info->type, "U-Boot");
+ sprintf ((char *)info->type, "U-Boot");
return 0;
}
dev_desc->dev, part_num);
return (-1);
}
- if(strncmp(ppr->stand_ident,"CD001",5)!=0) {
+ if(strncmp((char *)ppr->stand_ident,"CD001",5)!=0) {
if(verb)
printf ("** Wrong ISO Ident: %s on %d:%d **\n",
ppr->stand_ident,dev_desc->dev, part_num);
/* the validation entry seems to be ok, now search the "partition" */
entry_num=0;
offset=0x20;
- sprintf (info->type, "U-Boot");
+ sprintf ((char *)info->type, "U-Boot");
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_ATAPI:
- sprintf (info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_SCSI:
- sprintf (info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_USB:
- sprintf (info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
case IF_TYPE_DOC:
- sprintf (info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num);
break;
default:
- sprintf (info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
+ sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num);
break;
}
/* the bootcatalog (including validation Entry) is limited to 2048Bytes
--- /dev/null
+Open Firmware Flat Tree and usage.
+----------------------------------
+
+As part of the ongoing cleanup of the Linux PPC trees, the preferred
+way to pass bootloader and board setup information is the open
+firmware flat tree.
+
+Please take a look at the following email discussion for some
+background.
+
+ http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019408.html
+ http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019362.html
+
+The generated tree is part static and part dynamic.
+
+There is a static part which is compiled in with DTC and a dynamic
+part which is programmatically appended.
+
+You'll need a fairly recent DTC tool, which is available by git at
+
+ rsync://ozlabs.org/dtc/dtc.git
+
+The xxd binary dumper is needed too which I got from
+
+ ftp://ftp.uni-erlangen.de/pub/utilities/etc/xxd-1.10.tar.gz
+
+
+Pantelis Antoniou, 13 Oct 2005
static inline void video_drawstring (int xx, int yy, unsigned char *s)
{
- video_drawchars (xx, yy, s, strlen (s));
+ video_drawchars (xx, yy, s, strlen ((char *)s));
}
/*****************************************************************************/
sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
tm.tm_sec);
video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y, info);
+ VIDEO_INFO_Y, (uchar *)info);
sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
tm.tm_year);
video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, info);
+ VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info);
}
#endif
logo_plot (video_fb_address, VIDEO_COLS, 0, 0);
sprintf (info, " %s", &version_string);
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
+ video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info);
#ifdef CONFIG_CONSOLE_EXTRA_INFO
{
if (*info)
video_drawstring (VIDEO_INFO_X,
VIDEO_INFO_Y + i * VIDEO_FONT_HEIGHT,
- info);
+ (uchar *)info);
}
}
#endif
#define NUM_ERASE_REGIONS 4
+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
+#ifdef CFG_MAX_FLASH_BANKS_DETECT
+static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
+#else
static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
+#endif
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
+ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
ulong tout, char *prompt);
static flash_info_t *flash_get_info(ulong base)
{
int i;
- flash_info_t * info;
+ flash_info_t * info = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
* The following code cannot be run from FLASH!
*
*/
-static ulong flash_get_size (ulong base, int banknum)
+ulong flash_get_size (ulong base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
int i, j;
{
int idx=0;
int card_number = 0;
- int cfrv;
+ unsigned int cfrv;
unsigned char timer;
pci_dev_t devbusfn;
unsigned int iobase;
#ifndef CONFIG_TULIP_FIX_DAVICOM
static void read_hw_addr(struct eth_device *dev, bd_t *bis)
{
- u_short tmp, *p = (short *)(&dev->enetaddr[0]);
+ u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
int i, j = 0;
for (i = 0; i < (ETH_ALEN >> 1); i++) {
if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
return 0;
/*DEBUGOUT("recv: packet len=%d \n", rd->length); */
- NetReceive(packet, le32_to_cpu(rd->length));
+ NetReceive((uchar *)packet, le32_to_cpu(rd->length));
fill_rx(hw);
return 1;
}
{
u32 i, status = 0;
u32 tx_status = 0;
+ vu_long *res = (vu_long *)&tx_status;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
OUTL(dev, TxOn, ChipCmd);
for (i = 0;
- ((vu_long)tx_status = le32_to_cpu(txd.cmdsts)) & DescOwn;
+ (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
i++) {
if (i >= TOUT_LOOP) {
printf
/* get MAC address */
for (i = 0; i < 3; i++) {
u32 data;
- char *mac = &dev->enetaddr[i * 2];
+ char *mac = (char *)&dev->enetaddr[i * 2];
OUTL(dev, i * 2, RxFilterAddr);
data = INL(dev, RxFilterData);
/*
* Setup the PCI device.
*/
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &dev->iobase);
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
dev->iobase &= ~0xf;
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
/*****************************************************************************/
static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id)
{
- unsigned int p, q;
+ unsigned int p = 0;
+ unsigned int q = 0;
long long freq;
register GraphicDevice *pGD = (GraphicDevice *)&smi;
for(i=0;i<MAC_ADDR_LEN;i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
}
- (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
+ regs->macstnaddr1 = *((uint *)(tmpbuf));
tempval = *((uint *)(tmpbuf +4));
- (uint)(regs->macstnaddr2) = tempval;
+ regs->macstnaddr2 = tempval;
/* reset the indices to zero */
rxIdx = 0;
static inline void *memcpy(void *dst, const void *src, unsigned int len)
{
- void * ret = dst;
- while (len-- > 0) *((char *)dst)++ = *((char *)src)++;
- return ret;
+ char *ret = dst;
+ while (len-- > 0) *(ret)++ = *((char *)src)++;
+ return (void *)ret;
}
/* The EEPROM commands include the alway-set leading bit. */
current_tid = id;
PDEBUG ("thread_start: to be stack=0%08x",
(unsigned)lthreads[id].stack);
- setctxsp (<hreads[id].stack[STK_SIZE]);
+ setctxsp ((vu_char *)<hreads[id].stack[STK_SIZE]);
thread_launcher ();
}
/* CPU address space offset calculation macro, struct part_info offset is
* device address space offset, so we need to shift it by a device start address. */
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[];
#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
static int cramfs_read_super (struct part_info *info)
/* no signature found */
return -1;
}
- if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
+ if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset=0;
void rubin_do_decompress(unsigned char *bits, unsigned char *in,
unsigned char *page_out, __u32 destlen)
{
- register char *curr = page_out;
- char *end = page_out + destlen;
+ register char *curr = (char *)page_out;
+ char *end = (char *)(page_out + destlen);
register unsigned long temp;
register unsigned long result;
register unsigned long p;
rec_q <<= 1;
rec_q |= (temp >> (bit++ ^ 7)) & 1;
if (bit > 31) {
+ u32 *p = (u32 *)in;
bit = 0;
- temp = *(++((u32 *) in));
+ temp = *(++p);
+ in = (unsigned char *)p;
}
}
i0 = (bits[i] * p) >> 8;
u32 addr = off;
struct mtdids *id = current_part->dev->id;
- extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+ extern flash_info_t flash_info[];
flash_info_t *flash = &flash_info[id->num];
addr += flash->start[0];
/* length is also the same, so use ascending sort by name
*/
- cmp = strncmp(jNew->name, jOld->name, jNew->nsize);
+ cmp = strncmp((char *)jNew->name, (char *)jOld->name, jNew->nsize);
if (cmp != 0)
return cmp > 0;
struct jffs2_raw_inode *jNode;
u32 totalSize = 0;
u32 latestVersion = 0;
- char *lDest;
- char *src;
+ uchar *lDest;
+ uchar *src;
long ret;
int i;
u32 counter = 0;
#endif
if(dest) {
- src = ((char *) jNode) + sizeof(struct jffs2_raw_inode);
+ src = ((uchar *) jNode) + sizeof(struct jffs2_raw_inode);
/* ignore data behind latest known EOF */
if (jNode->offset > totalSize) {
put_fl_mem(jNode);
continue;
}
- lDest = (char *) (dest + jNode->offset);
+ lDest = (uchar *) (dest + jNode->offset);
#if 0
putLabeledWord("read_inode: src = ", src);
putLabeledWord("read_inode: dest = ", lDest);
jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset);
if ((pino == jDir->pino) && (len == jDir->nsize) &&
(jDir->ino) && /* 0 for unlink */
- (!strncmp(jDir->name, name, len))) { /* a match */
+ (!strncmp((char *)jDir->name, name, len))) { /* a match */
if (jDir->version < version) {
put_fl_mem(jDir);
continue;
if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */
st->st_mtime = 1;
- ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */
+ ctime_r((time_t *)&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */
if ((p = strchr(s,'\n')) != NULL) *p = '\0';
if ((p = strchr(s,'\r')) != NULL) *p = '\0';
if(!d || !i) return -1;
- strncpy(fname, d->name, d->nsize);
+ strncpy(fname, (char *)d->name, d->nsize);
fname[d->nsize] = '\0';
memset(&st,0,sizeof(st));
putnstr(src, jNode->dsize);
putstr("\r\n");
#endif
- strncpy(tmp, src, jNode->dsize);
+ strncpy(tmp, (char *)src, jNode->dsize);
tmp[jNode->dsize] = '\0';
put_fl_mem(jNode);
break;
# define __arch_swab16(x) ld_le16(&x)
# define __arch_swab32(x) ld_le32(&x)
#else
-static __inline__ __const__ __u16 ___arch__swab16(__u16 value)
+static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value)
{
__u16 result;
return result;
}
-static __inline__ __const__ __u32 ___arch__swab32(__u32 value)
+static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value)
{
__u32 result;
#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
#endif
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
/*
* MPC8349 have two i2c bus
*/
typedef struct ddr_cs_bnds{
u32 csbnds;
#define CSBNDS_SA 0x00FF0000
-#define CSBNDS_SA_SHIFT 16
+#define CSBNDS_SA_SHIFT 8
#define CSBNDS_EA 0x000000FF
-#define CSBNDS_EA_SHIFT 0
+#define CSBNDS_EA_SHIFT 24
u8 res0[4];
} ddr_cs_bnds_t;
#define TIMING_CFG1_ACTTOACT_SHIFT 4
#define TIMING_CFG1_WRTORD 0x00000007
#define TIMING_CFG1_WRTORD_SHIFT 0
+#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO 0x0F000000
#define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
+#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
u32 sdram_cfg; /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_8_BE 0x00040000
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
u8 res2[4];
u32 sdram_mode; /**< SDRAM Mode Configuration */
#define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0
+#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
+#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
+#define DDR_MODE_WEAK 0x0002 /* weak drivers */
+#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
+#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
+#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
+#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
+#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
+#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
+#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
+#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
+#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG 0x0000 /* select mode register */
u8 res3[8];
u32 sdram_interval; /**< SDRAM Interval Configuration */
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
u8 res9[8];
u32 sdram_clk_cntl;
+#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
+
u8 res4[0xCCC];
u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
/* crc, base, loop, mtest */
#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */
#define CFG_CMD_ENV 0x00000100ULL /* saveenv */
-#define CFG_CMD_KGDB 0x00000200ULL /* kgdb */
+#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */
#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */
#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */
#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */
/* common/cmd_nvedit.c */
int env_init (void);
void env_relocate (void);
-char *getenv (uchar *);
-int getenv_r (uchar *name, uchar *buf, unsigned len);
+char *getenv (char *);
+int getenv_r (char *name, char *buf, unsigned len);
int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
void inline setenv (char *, char *);
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TQM8349 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC834X 1 /* MPC834X specific */
+#define CONFIG_TQM834X 1 /* TQM834X board specific */
+
+/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+#define CFG_IMMRBAR 0xff400000
+
+/* System clock. Primary input clock when in PCI host mode */
+#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
+
+/*
+ * Local Bus LCRR
+ * LCRR: DLL bypass, Clock divider is 8
+ *
+ * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
+ *
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+
+/* board pre init: do not call, nothing to do */
+#undef CONFIG_BOARD_EARLY_INIT_F
+
+/* detect the number of flash banks */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
+#define CFG_MEMTEST_END 0x00100000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */
+
+/* buffered writes in the AMD chip set is not supported yet */
+#undef CFG_FLASH_USE_BUFFER_WRITE
+
+/*
+ * FLASH bank number detection
+ */
+
+/*
+ * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
+ * banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
+ * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * should be made sufficiently large to accomodate the number of banks that
+ * might acutally be detected. Since most (all?) Flash related functions use
+ * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
+ * defined as tqm834x_num_flash_banks.
+ */
+#define CFG_MAX_FLASH_BANKS_DETECT 2
+#ifndef __ASSEMBLY__
+extern int tqm834x_num_flash_banks;
+#endif
+#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
+
+#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
+
+/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \
+ BR_MS_GPCM | BR_PS_32 | BR_V)
+
+/* FLASH timing (0x0000_0c54) */
+#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+ OR_GPCM_SCY_5 | OR_GPCM_TRLX)
+
+#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
+
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+
+#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+
+/* disable remaining mappings */
+#define CFG_BR1_PRELIM 0x00000000
+#define CFG_OR1_PRELIM 0x00000000
+#define CFG_LBLAWBAR1_PRELIM 0x00000000
+#define CFG_LBLAWAR1_PRELIM 0x00000000
+
+#define CFG_BR2_PRELIM 0x00000000
+#define CFG_OR2_PRELIM 0x00000000
+#define CFG_LBLAWBAR2_PRELIM 0x00000000
+#define CFG_LBLAWAR2_PRELIM 0x00000000
+
+#define CFG_BR3_PRELIM 0x00000000
+#define CFG_OR3_PRELIM 0x00000000
+#define CFG_LBLAWBAR3_PRELIM 0x00000000
+#define CFG_LBLAWAR3_PRELIM 0x00000000
+
+#define CFG_BR4_PRELIM 0x00000000
+#define CFG_OR4_PRELIM 0x00000000
+#define CFG_LBLAWBAR4_PRELIM 0x00000000
+#define CFG_LBLAWAR4_PRELIM 0x00000000
+
+#define CFG_BR5_PRELIM 0x00000000
+#define CFG_OR5_PRELIM 0x00000000
+#define CFG_LBLAWBAR5_PRELIM 0x00000000
+#define CFG_LBLAWAR5_PRELIM 0x00000000
+
+#define CFG_BR6_PRELIM 0x00000000
+#define CFG_OR6_PRELIM 0x00000000
+#define CFG_LBLAWBAR6_PRELIM 0x00000000
+#define CFG_LBLAWAR6_PRELIM 0x00000000
+
+#define CFG_BR7_PRELIM 0x00000000
+#define CFG_OR7_PRELIM 0x00000000
+#define CFG_LBLAWBAR7_PRELIM 0x00000000
+#define CFG_LBLAWAR7_PRELIM 0x00000000
+
+/*
+ * Monitor config
+ */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
+#define CFG_I2C_SLAVE 0x7F /* slave address */
+#define CFG_I2C_OFFSET 0x3000
+
+/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
+#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_MII
+
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC83XX_TSEC2 1
+#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#define CFG_PCI2_MEM_BASE 0xA0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe3000000
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/* Common commands */
+#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
+ | CFG_CMD_PING | CFG_CMD_EEPROM \
+ | CFG_CMD_MII | CFG_CMD_JFFS2
+
+#if defined(CFG_RAMBOOT)
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_TQM8349_COMMON) \
+ & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_TQM8349_COMMON) \
+ & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#endif
+
+#else /* CFG_RAMBOOT */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_TQM8349_COMMON)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_TQM8349_COMMON)
+#endif
+
+#endif /* CFG_RAMBOOT */
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_1X1 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_VCO_1X2 |\
+ HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_64_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_32_BIT_PCI |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_TSEC1M_IN_GMII |\
+ HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* i-cache and d-cache disabled */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID2 0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
+#endif
+
+#define CONFIG_IPADDR 192.168.205.1
+
+#define CONFIG_HOSTNAME tqm8349
+#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=tqm83xx\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "bootfile=/tftpboot/tqm83xx/uImage\0" \
+ "kernel_addr=80060000\0" \
+ "ramdisk_addr=80160000\0" \
+ "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
+ "update=protect off 80000000 8003ffff; " \
+ "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM834x-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
+ "1m(kernel),2m(initrd),"\
+ "-(user);"\
+
+#endif /* __CONFIG_H */
/* common/flash.c */
extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
-extern int flash_write (uchar *, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
extern flash_info_t *addr2info (ulong);
extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
/* root function definitions */
extern void fpga_init( ulong reloc_off );
extern int fpga_add( fpga_type devtype, void *desc );
-extern const int fpga_count( void );
+extern int fpga_count( void );
extern int fpga_load( int devnum, void *buf, size_t bsize );
extern int fpga_dump( int devnum, void *buf, size_t bsize );
extern int fpga_info( int devnum );
#endif /* OPTIMIZE */
-static __inline__ __const__ __u16 __fswab16(__u16 x)
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
{
return __arch__swab16(x);
}
__arch__swab16s(addr);
}
-static __inline__ __const__ __u32 __fswab32(__u32 x)
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
{
return __arch__swab32(x);
}
}
#ifdef __BYTEORDER_HAS_U64__
-static __inline__ __const__ __u64 __fswab64(__u64 x)
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
{
# ifdef __SWAB_64_THRU_32__
__u32 h = x >> 32;
#define BR6 0x5030
#define BR7 0x5038
-#define BR_BA 0xFFFF8000
-#define BR_BA_SHIFT 15
-#define BR_PS 0x00001800
-#define BR_PS_SHIFT 11
-#define BR_DECC 0x00000600
-#define BR_DECC_SHIFT 9
-#define BR_WP 0x00000100
-#define BR_WP_SHIFT 8
-#define BR_MSEL 0x000000E0
-#define BR_MSEL_SHIFT 5
-#define BR_V 0x00000001
-#define BR_V_SHIFT 0
-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#define OR0 0x5004
#define OR1 0x500C
#define OR6 0x5034
#define OR7 0x503C
-#define OR_GPCM_AM 0xFFFF8000
-#define OR_GPCM_AM_SHIFT 15
-#define OR_GPCM_BCTLD 0x00001000
-#define OR_GPCM_BCTLD_SHIFT 12
-#define OR_GPCM_CSNT 0x00000800
-#define OR_GPCM_CSNT_SHIFT 11
-#define OR_GPCM_ACS 0x00000600
-#define OR_GPCM_ACS_SHIFT 9
-#define OR_GPCM_XACS 0x00000100
-#define OR_GPCM_XACS_SHIFT 8
-#define OR_GPCM_SCY 0x000000F0
-#define OR_GPCM_SCY_SHIFT 4
-#define OR_GPCM_SETA 0x00000008
-#define OR_GPCM_SETA_SHIFT 3
-#define OR_GPCM_TRLX 0x00000004
-#define OR_GPCM_TRLX_SHIFT 2
-#define OR_GPCM_EHTR 0x00000002
-#define OR_GPCM_EHTR_SHIFT 1
-#define OR_GPCM_EAD 0x00000001
-#define OR_GPCM_EAD_SHIFT 0
+#define OR_GPCM_AM 0xFFFF8000
+#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_BCTLD 0x00001000
+#define OR_GPCM_BCTLD_SHIFT 12
+#define OR_GPCM_CSNT 0x00000800
+#define OR_GPCM_CSNT_SHIFT 11
+#define OR_GPCM_ACS 0x00000600
+#define OR_GPCM_ACS_SHIFT 9
+#define OR_GPCM_ACS_0b10 0x00000400
+#define OR_GPCM_ACS_0b11 0x00000600
+#define OR_GPCM_XACS 0x00000100
+#define OR_GPCM_XACS_SHIFT 8
+#define OR_GPCM_SCY 0x000000F0
+#define OR_GPCM_SCY_SHIFT 4
+#define OR_GPCM_SCY_1 0x00000010
+#define OR_GPCM_SCY_2 0x00000020
+#define OR_GPCM_SCY_3 0x00000030
+#define OR_GPCM_SCY_4 0x00000040
+#define OR_GPCM_SCY_5 0x00000050
+#define OR_GPCM_SCY_6 0x00000060
+#define OR_GPCM_SCY_7 0x00000070
+#define OR_GPCM_SCY_8 0x00000080
+#define OR_GPCM_SCY_9 0x00000090
+#define OR_GPCM_SCY_10 0x000000a0
+#define OR_GPCM_SCY_11 0x000000b0
+#define OR_GPCM_SCY_12 0x000000c0
+#define OR_GPCM_SCY_13 0x000000d0
+#define OR_GPCM_SCY_14 0x000000e0
+#define OR_GPCM_SCY_15 0x000000f0
+#define OR_GPCM_SETA 0x00000008
+#define OR_GPCM_SETA_SHIFT 3
+#define OR_GPCM_TRLX 0x00000004
+#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_EHTR 0x00000002
+#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EAD 0x00000001
+#define OR_GPCM_EAD_SHIFT 0
#define OR_UPM_AM 0xFFFF8000
#define OR_UPM_AM_SHIFT 15
extern ushort getenv_VLAN(char *);
/* copy a filename (allow for "..." notation, limit length) */
-extern void copy_filename (uchar *dst, uchar *src, int size);
+extern void copy_filename (char *dst, char *src, int size);
/**********************************************************************/
static int init_baudrate (void)
{
- uchar tmp[64]; /* long enough for environment variables */
+ char tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->baudrate = (i > 0)
/*
* reserve protected RAM
*/
- i = getenv_r ("pram", tmp, sizeof (tmp));
- reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM;
+ i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
+ reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
addr -= (reg << 10); /* size is in kB */
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CFG_EXTBDINFO
- strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
- strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
+ strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
+ strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
#endif
- sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
- setenv ("mem", memsz);
+ sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
+ setenv ("mem", (char *)memsz);
}
#endif
#ifdef CONFIG_MODEM_SUPPORT
/* called from main loop (common/main.c) */
+/* 'inline' - We have to do it fast */
+static inline void mdm_readline(char *buf, int bufsiz)
+{
+ char c;
+ char *p;
+ int n;
+
+ n = 0;
+ p = buf;
+ for(;;) {
+ c = serial_getc();
+
+ /* dbg("(%c)", c); */
+
+ switch(c) {
+ case '\r':
+ break;
+ case '\n':
+ *p = '\0';
+ return;
+
+ default:
+ if(n++ > bufsiz) {
+ *p = '\0';
+ return; /* sanity check */
+ }
+ *p = c;
+ p++;
+ break;
+ }
+ }
+}
+
+
+
extern void dbg(const char *fmt, ...);
int mdm_init (void)
{
char *init_str;
int i;
extern char console_buffer[];
- static inline void mdm_readline(char *buf, int bufsiz);
extern void enable_putc(void);
extern int hwflow_onoff(int);
return 0;
}
-/* 'inline' - We have to do it fast */
-static inline void mdm_readline(char *buf, int bufsiz)
-{
- char c;
- char *p;
- int n;
-
- n = 0;
- p = buf;
- for(;;) {
- c = serial_getc();
-
- /* dbg("(%c)", c); */
-
- switch(c) {
- case '\r':
- break;
- case '\n':
- *p = '\0';
- return;
-
- default:
- if(n++ > bufsiz) {
- *p = '\0';
- return; /* sanity check */
- }
- *p = c;
- p++;
- break;
- }
- }
-}
#endif
#if 0 /* We could use plain global data, but the resulting code is bigger */
/* Retrieve extended information (we must parse the vendor area) */
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- BootpVendorProcess(&bp->bp_vend[4], len);
+ BootpVendorProcess((uchar *)&bp->bp_vend[4], len);
NetSetTimeout(0, (thand_f *)0);
u8 *x;
#endif
#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME)
- uchar *hostname;
+ char *hostname;
#endif
*e++ = 99; /* RFC1048 Magic Cookie */
unsigned char bi_enetaddr[6];
int reg;
char *e,*s;
- uchar tmp[64];
+ char tmp[64];
ulong tst1, tst2, sum, m_mask, m_value = 0;
if (BootpTry ==0) {
/* Request additional information from the BOOTP/DHCP server */
#if (CONFIG_COMMANDS & CFG_CMD_DHCP)
- ext_len = DhcpExtended(bp->bp_vend, DHCP_DISCOVER, 0, 0);
+ ext_len = DhcpExtended((u8 *)bp->bp_vend, DHCP_DISCOVER, 0, 0);
#else
- ext_len = BootpExtended(bp->bp_vend);
+ ext_len = BootpExtended((u8 *)bp->bp_vend);
#endif /* CFG_CMD_DHCP */
/*
* Copy options from OFFER packet if present
*/
NetCopyIP(&OfferedIP, &bp->bp_yiaddr);
- extlen = DhcpExtended(bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
+ extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen;
iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
dhcp_state = REQUESTING;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- DhcpOptionsProcess(&bp->bp_vend[4]);
+ DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
BootpCopyNetParams(bp); /* Store net params from reply */
case REQUESTING:
debug ("DHCP State: REQUESTING\n");
- if ( DhcpMessageType(bp->bp_vend) == DHCP_ACK ) {
+ if ( DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK ) {
char *s;
if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
- DhcpOptionsProcess(&bp->bp_vend[4]);
+ DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
BootpCopyNetParams(bp); /* Store net params from reply */
dhcp_state = BOUND;
puts ("DHCP client bound to address ");
int eth_initialize(bd_t *bis)
{
- unsigned char enetvar[32], env_enetaddr[6];
+ char enetvar[32], env_enetaddr[6];
int i, eth_number = 0;
char *tmp, *end;
int odd;
ulong result = 0;
ushort leftover;
+ ushort *p;
if (len > 0) {
odd = 1 & (ulong)buff;
buff++;
}
while (len > 1) {
- result += *((const ushort *)buff)++;
+ p = (ushort *)buff;
+ result += *p++;
+ buff = (uchar *)p;
if (result & 0x80000000)
result = (result & 0xFFFF) + (result >> 16);
len -= 2;
ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
}
-void copy_filename (uchar *dst, uchar *src, int size)
+void copy_filename (char *dst, char *src, int size)
{
if (*src && (*src == '"')) {
++src;
static char *tftp_filename;
#ifdef CFG_DIRECT_FLASH_TFTP
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[];
#endif
static __inline__ void
}
if (rc) { /* Flash is destination for this packet */
- rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);
+ rc = flash_write ((char *)src, (ulong)(load_addr+offset), len);
if (rc) {
flash_perror (rc);
NetState = NETLOOP_FAIL;
static int memory_post_dataline(unsigned long long * pmem)
{
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
int i;
unsigned int hi, lo, pathi, patlo;
int ret = 0;
if (ret == 0)
- ret = memory_post_dataline ((long long *)start);
+ ret = memory_post_dataline ((unsigned long long *)start);
WATCHDOG_RESET ();
if (ret == 0)
- ret = memory_post_addrline ((long *)start, (long *)start, size);
+ ret = memory_post_addrline ((ulong *)start, (ulong *)start, size);
WATCHDOG_RESET ();
if (ret == 0)
- ret = memory_post_addrline ((long *)(start + size - 8),
- (long *)start, size);
+ ret = memory_post_addrline ((ulong *)(start + size - 8),
+ (ulong *)start, size);
WATCHDOG_RESET ();
if (ret == 0)
ret = memory_post_test1 (start, size, 0x00000000);
#include <common.h>
#include <flash.h>
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
#endif
/*---------------------------------------------------------------------*/
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[];
static ulong flash_get_size (ulong addr, flash_info_t *info);
static int flash_get_offsets (ulong base, flash_info_t *info);